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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
ba395927 KA |
20 | */ |
21 | ||
22 | #ifndef _INTEL_IOMMU_H_ | |
23 | #define _INTEL_IOMMU_H_ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/msi.h> | |
f661197e | 27 | #include <linux/sysdev.h> |
ba395927 KA |
28 | #include "iova.h" |
29 | #include <linux/io.h> | |
30 | ||
f661197e DM |
31 | /* |
32 | * We need a fixed PAGE_SIZE of 4K irrespective of | |
33 | * arch PAGE_SIZE for IOMMU page tables. | |
34 | */ | |
35 | #define PAGE_SHIFT_4K (12) | |
36 | #define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K) | |
37 | #define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K) | |
38 | #define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K) | |
39 | ||
40 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K) | |
41 | #define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK) | |
42 | #define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK) | |
43 | ||
ba395927 KA |
44 | /* |
45 | * Intel IOMMU register specification per version 1.0 public spec. | |
46 | */ | |
47 | ||
48 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ | |
49 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
50 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
51 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
52 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
53 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
54 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
55 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
56 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
57 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
58 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
59 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
60 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
61 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
62 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
63 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
64 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
65 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
66 | ||
67 | #define OFFSET_STRIDE (9) | |
68 | /* | |
69 | #define dmar_readl(dmar, reg) readl(dmar + reg) | |
70 | #define dmar_readq(dmar, reg) ({ \ | |
71 | u32 lo, hi; \ | |
72 | lo = readl(dmar + reg); \ | |
73 | hi = readl(dmar + reg + 4); \ | |
74 | (((u64) hi) << 32) + lo; }) | |
75 | */ | |
4fe05bbc | 76 | static inline u64 dmar_readq(void __iomem *addr) |
ba395927 KA |
77 | { |
78 | u32 lo, hi; | |
79 | lo = readl(addr); | |
80 | hi = readl(addr + 4); | |
81 | return (((u64) hi) << 32) + lo; | |
82 | } | |
83 | ||
84 | static inline void dmar_writeq(void __iomem *addr, u64 val) | |
85 | { | |
86 | writel((u32)val, addr); | |
87 | writel((u32)(val >> 32), addr + 4); | |
88 | } | |
89 | ||
90 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
91 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
92 | ||
93 | /* | |
94 | * Decoding Capability Register | |
95 | */ | |
96 | #define cap_read_drain(c) (((c) >> 55) & 1) | |
97 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
98 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
99 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
100 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
101 | ||
102 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
103 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
104 | * OFFSET_STRIDE) + 21) | |
105 | ||
106 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
107 | #define cap_max_fault_reg_offset(c) \ | |
108 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
109 | ||
110 | #define cap_zlr(c) (((c) >> 22) & 1) | |
111 | #define cap_isoch(c) (((c) >> 23) & 1) | |
112 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
113 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
114 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
115 | #define cap_phmr(c) (((c) >> 6) & 1) | |
116 | #define cap_plmr(c) (((c) >> 5) & 1) | |
117 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
118 | #define cap_afl(c) (((c) >> 3) & 1) | |
119 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
120 | /* | |
121 | * Extended Capability Register | |
122 | */ | |
123 | ||
124 | #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) | |
125 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) | |
126 | #define ecap_max_iotlb_offset(e) \ | |
127 | (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) | |
128 | #define ecap_coherent(e) ((e) & 0x1) | |
129 | ||
130 | ||
131 | /* IOTLB_REG */ | |
132 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) | |
133 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
134 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
135 | #define DMA_TLB_IIRG(type) ((type >> 60) & 7) | |
136 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 7) | |
137 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) | |
138 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
139 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
140 | #define DMA_TLB_IVT (((u64)1) << 63) | |
141 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
142 | #define DMA_TLB_MAX_SIZE (0x3f) | |
143 | ||
f8bab735 | 144 | /* PMEN_REG */ |
145 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
146 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
147 | ||
ba395927 KA |
148 | /* GCMD_REG */ |
149 | #define DMA_GCMD_TE (((u32)1) << 31) | |
150 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
151 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
152 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
153 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
154 | ||
155 | /* GSTS_REG */ | |
156 | #define DMA_GSTS_TES (((u32)1) << 31) | |
157 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
158 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
159 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
160 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
161 | ||
162 | /* CCMD_REG */ | |
163 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
164 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
165 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
166 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
167 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
168 | #define DMA_CCMD_MASK_NOBIT 0 | |
169 | #define DMA_CCMD_MASK_1BIT 1 | |
170 | #define DMA_CCMD_MASK_2BIT 2 | |
171 | #define DMA_CCMD_MASK_3BIT 3 | |
172 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
173 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
174 | ||
175 | /* FECTL_REG */ | |
176 | #define DMA_FECTL_IM (((u32)1) << 31) | |
177 | ||
178 | /* FSTS_REG */ | |
179 | #define DMA_FSTS_PPF ((u32)2) | |
180 | #define DMA_FSTS_PFO ((u32)1) | |
181 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) | |
182 | ||
183 | /* FRCD_REG, 32 bits access */ | |
184 | #define DMA_FRCD_F (((u32)1) << 31) | |
185 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
186 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
187 | #define dma_frcd_source_id(c) (c & 0xffff) | |
188 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ | |
189 | ||
190 | /* | |
191 | * 0: Present | |
192 | * 1-11: Reserved | |
193 | * 12-63: Context Ptr (12 - (haw-1)) | |
194 | * 64-127: Reserved | |
195 | */ | |
196 | struct root_entry { | |
197 | u64 val; | |
198 | u64 rsvd1; | |
199 | }; | |
200 | #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry)) | |
201 | static inline bool root_present(struct root_entry *root) | |
202 | { | |
203 | return (root->val & 1); | |
204 | } | |
205 | static inline void set_root_present(struct root_entry *root) | |
206 | { | |
207 | root->val |= 1; | |
208 | } | |
209 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
210 | { | |
211 | root->val |= value & PAGE_MASK_4K; | |
212 | } | |
213 | ||
214 | struct context_entry; | |
215 | static inline struct context_entry * | |
216 | get_context_addr_from_root(struct root_entry *root) | |
217 | { | |
218 | return (struct context_entry *) | |
219 | (root_present(root)?phys_to_virt( | |
220 | root->val & PAGE_MASK_4K): | |
221 | NULL); | |
222 | } | |
223 | ||
224 | /* | |
225 | * low 64 bits: | |
226 | * 0: present | |
227 | * 1: fault processing disable | |
228 | * 2-3: translation type | |
229 | * 12-63: address space root | |
230 | * high 64 bits: | |
231 | * 0-2: address width | |
232 | * 3-6: aval | |
233 | * 8-23: domain id | |
234 | */ | |
235 | struct context_entry { | |
236 | u64 lo; | |
237 | u64 hi; | |
238 | }; | |
239 | #define context_present(c) ((c).lo & 1) | |
240 | #define context_fault_disable(c) (((c).lo >> 1) & 1) | |
241 | #define context_translation_type(c) (((c).lo >> 2) & 3) | |
242 | #define context_address_root(c) ((c).lo & PAGE_MASK_4K) | |
243 | #define context_address_width(c) ((c).hi & 7) | |
244 | #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1)) | |
245 | ||
246 | #define context_set_present(c) do {(c).lo |= 1;} while (0) | |
247 | #define context_set_fault_enable(c) \ | |
248 | do {(c).lo &= (((u64)-1) << 2) | 1;} while (0) | |
249 | #define context_set_translation_type(c, val) \ | |
250 | do { \ | |
251 | (c).lo &= (((u64)-1) << 4) | 3; \ | |
252 | (c).lo |= ((val) & 3) << 2; \ | |
253 | } while (0) | |
254 | #define CONTEXT_TT_MULTI_LEVEL 0 | |
255 | #define context_set_address_root(c, val) \ | |
256 | do {(c).lo |= (val) & PAGE_MASK_4K;} while (0) | |
257 | #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0) | |
258 | #define context_set_domain_id(c, val) \ | |
259 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) | |
260 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) | |
261 | ||
262 | /* | |
263 | * 0: readable | |
264 | * 1: writable | |
265 | * 2-6: reserved | |
266 | * 7: super page | |
267 | * 8-11: available | |
268 | * 12-63: Host physcial address | |
269 | */ | |
270 | struct dma_pte { | |
271 | u64 val; | |
272 | }; | |
273 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | |
274 | ||
275 | #define DMA_PTE_READ (1) | |
276 | #define DMA_PTE_WRITE (2) | |
277 | ||
278 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | |
279 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | |
280 | #define dma_set_pte_prot(p, prot) \ | |
281 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | |
282 | #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K) | |
283 | #define dma_set_pte_addr(p, addr) do {\ | |
284 | (p).val |= ((addr) & PAGE_MASK_4K); } while (0) | |
285 | #define dma_pte_present(p) (((p).val & 3) != 0) | |
286 | ||
287 | struct intel_iommu; | |
288 | ||
289 | struct dmar_domain { | |
290 | int id; /* domain id */ | |
291 | struct intel_iommu *iommu; /* back pointer to owning iommu */ | |
292 | ||
293 | struct list_head devices; /* all devices' list */ | |
294 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
295 | ||
296 | struct dma_pte *pgd; /* virtual address */ | |
297 | spinlock_t mapping_lock; /* page table lock */ | |
298 | int gaw; /* max guest address width */ | |
299 | ||
300 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
301 | int agaw; | |
302 | ||
303 | #define DOMAIN_FLAG_MULTIPLE_DEVICES 1 | |
304 | int flags; | |
305 | }; | |
306 | ||
307 | /* PCI domain-device relationship */ | |
308 | struct device_domain_info { | |
309 | struct list_head link; /* link to domain siblings */ | |
310 | struct list_head global; /* link to global list */ | |
311 | u8 bus; /* PCI bus numer */ | |
312 | u8 devfn; /* PCI devfn number */ | |
313 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
314 | struct dmar_domain *domain; /* pointer to domain */ | |
315 | }; | |
316 | ||
317 | extern int init_dmars(void); | |
318 | ||
319 | struct intel_iommu { | |
320 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
321 | u64 cap; | |
322 | u64 ecap; | |
323 | unsigned long *domain_ids; /* bitmap of domains */ | |
324 | struct dmar_domain **domains; /* ptr to domains */ | |
325 | int seg; | |
326 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ | |
327 | spinlock_t lock; /* protect context, domain ids */ | |
328 | spinlock_t register_lock; /* protect register handling */ | |
329 | struct root_entry *root_entry; /* virtual address */ | |
330 | ||
331 | unsigned int irq; | |
332 | unsigned char name[7]; /* Device Name */ | |
333 | struct msi_msg saved_msg; | |
334 | struct sys_device sysdev; | |
335 | }; | |
336 | ||
e820482c KA |
337 | #ifndef CONFIG_DMAR_GFX_WA |
338 | static inline void iommu_prepare_gfx_mapping(void) | |
339 | { | |
340 | return; | |
341 | } | |
342 | #endif /* !CONFIG_DMAR_GFX_WA */ | |
343 | ||
ba395927 | 344 | #endif |