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intel-iommu: Create new iommu_domain_identity_map() function
[linux-2.6-block.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
ba395927 40#include <asm/cacheflush.h>
46a7fa27 41#include <asm/iommu.h>
ba395927
KA		 42#include "pci.h"
43
5b6985ce
FY		 44#define ROOT_SIZE VTD_PAGE_SIZE
45#define CONTEXT_SIZE VTD_PAGE_SIZE
46
ba395927
KA		 47#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50#define IOAPIC_RANGE_START (0xfee00000)
51#define IOAPIC_RANGE_END (0xfeefffff)
52#define IOVA_START_ADDR (0x1000)
53
54#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
4ed0d3e6
FY		 56#define MAX_AGAW_WIDTH 64
57
ba395927
KA		 58#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59
f27be03b 60#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 61#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 62#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 63
fd18de50
DW		 64#ifndef PHYSICAL_PAGE_MASK
65#define PHYSICAL_PAGE_MASK PAGE_MASK
66#endif
67
d9630fe9
WH		 68/* global iommu list, set NULL for ignored DMAR units */
69static struct intel_iommu **g_iommus;
70
9af88143
DW		 71static int rwbf_quirk;
72
46b08e1a
MM		 73/*
74 * 0: Present
75 * 1-11: Reserved
76 * 12-63: Context Ptr (12 - (haw-1))
77 * 64-127: Reserved
78 */
79struct root_entry {
80 u64 val;
81 u64 rsvd1;
82};
83#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
84static inline bool root_present(struct root_entry *root)
85{
86 return (root->val & 1);
87}
88static inline void set_root_present(struct root_entry *root)
89{
90 root->val |= 1;
91}
92static inline void set_root_value(struct root_entry *root, unsigned long value)
93{
94 root->val |= value & VTD_PAGE_MASK;
95}
96
97static inline struct context_entry *
98get_context_addr_from_root(struct root_entry *root)
99{
100 return (struct context_entry *)
101 (root_present(root)?phys_to_virt(
102 root->val & VTD_PAGE_MASK) :
103 NULL);
104}
105
7a8fc25e
MM		 106/*
107 * low 64 bits:
108 * 0: present
109 * 1: fault processing disable
110 * 2-3: translation type
111 * 12-63: address space root
112 * high 64 bits:
113 * 0-2: address width
114 * 3-6: aval
115 * 8-23: domain id
116 */
117struct context_entry {
118 u64 lo;
119 u64 hi;
120};
c07e7d21
MM		 121
122static inline bool context_present(struct context_entry *context)
123{
124 return (context->lo & 1);
125}
126static inline void context_set_present(struct context_entry *context)
127{
128 context->lo |= 1;
129}
130
131static inline void context_set_fault_enable(struct context_entry *context)
132{
133 context->lo &= (((u64)-1) << 2) | 1;
134}
135
c07e7d21
MM		 136static inline void context_set_translation_type(struct context_entry *context,
137 unsigned long value)
138{
139 context->lo &= (((u64)-1) << 4) | 3;
140 context->lo |= (value & 3) << 2;
141}
142
143static inline void context_set_address_root(struct context_entry *context,
144 unsigned long value)
145{
146 context->lo |= value & VTD_PAGE_MASK;
147}
148
149static inline void context_set_address_width(struct context_entry *context,
150 unsigned long value)
151{
152 context->hi |= value & 7;
153}
154
155static inline void context_set_domain_id(struct context_entry *context,
156 unsigned long value)
157{
158 context->hi |= (value & ((1 << 16) - 1)) << 8;
159}
160
161static inline void context_clear_entry(struct context_entry *context)
162{
163 context->lo = 0;
164 context->hi = 0;
165}
7a8fc25e 166
622ba12a
MM		 167/*
168 * 0: readable
169 * 1: writable
170 * 2-6: reserved
171 * 7: super page
9cf06697
SY		 172 * 8-10: available
173 * 11: snoop behavior
622ba12a
MM		 174 * 12-63: Host physcial address
175 */
176struct dma_pte {
177 u64 val;
178};
622ba12a 179
19c239ce
MM		 180static inline void dma_clear_pte(struct dma_pte *pte)
181{
182 pte->val = 0;
183}
184
185static inline void dma_set_pte_readable(struct dma_pte *pte)
186{
187 pte->val |= DMA_PTE_READ;
188}
189
190static inline void dma_set_pte_writable(struct dma_pte *pte)
191{
192 pte->val |= DMA_PTE_WRITE;
193}
194
9cf06697
SY		 195static inline void dma_set_pte_snp(struct dma_pte *pte)
196{
197 pte->val |= DMA_PTE_SNP;
198}
199
19c239ce
MM		 200static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
201{
202 pte->val = (pte->val & ~3) | (prot & 3);
203}
204
205static inline u64 dma_pte_addr(struct dma_pte *pte)
206{
207 return (pte->val & VTD_PAGE_MASK);
208}
209
210static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
211{
212 pte->val |= (addr & VTD_PAGE_MASK);
213}
214
215static inline bool dma_pte_present(struct dma_pte *pte)
216{
217 return (pte->val & 3) != 0;
218}
622ba12a 219
2c2e2c38
FY		 220/*
221 * This domain is a statically identity mapping domain.
222 * 1. This domain creats a static 1:1 mapping to all usable memory.
223 * 2. It maps to each iommu if successful.
224 * 3. Each iommu mapps to this domain if successful.
225 */
226struct dmar_domain *si_domain;
227
3b5410e7 228/* devices under the same p2p bridge are owned in one domain */
cdc7b837 229#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 230
1ce28feb
WH		 231/* domain represents a virtual machine, more than one devices
232 * across iommus may be owned in one domain, e.g. kvm guest.
233 */
234#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
235
2c2e2c38
FY		 236/* si_domain contains mulitple devices */
237#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
238
99126f7c
MM		 239struct dmar_domain {
240 int id; /* domain id */
8c11e798 241 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 242
243 struct list_head devices; /* all devices' list */
244 struct iova_domain iovad; /* iova's that belong to this domain */
245
246 struct dma_pte *pgd; /* virtual address */
247 spinlock_t mapping_lock; /* page table lock */
248 int gaw; /* max guest address width */
249
250 /* adjusted guest address width, 0 is level 2 30-bit */
251 int agaw;
252
3b5410e7 253 int flags; /* flags to find out type of domain */
8e604097
WH		 254
255 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 256 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 257 int iommu_count; /* reference count of iommu */
258 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 259 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 260};
261
a647dacb
MM		 262/* PCI domain-device relationship */
263struct device_domain_info {
264 struct list_head link; /* link to domain siblings */
265 struct list_head global; /* link to global list */
276dbf99
DW		 266 int segment; /* PCI domain */
267 u8 bus; /* PCI bus number */
a647dacb
MM		 268 u8 devfn; /* PCI devfn number */
269 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 270 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 271 struct dmar_domain *domain; /* pointer to domain */
272};
273
5e0d2a6f 274static void flush_unmaps_timeout(unsigned long data);
275
276DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
277
80b20dd8 278#define HIGH_WATER_MARK 250
279struct deferred_flush_tables {
280 int next;
281 struct iova *iova[HIGH_WATER_MARK];
282 struct dmar_domain *domain[HIGH_WATER_MARK];
283};
284
285static struct deferred_flush_tables *deferred_flush;
286
5e0d2a6f 287/* bitmap for indexing intel_iommus */
5e0d2a6f 288static int g_num_of_iommus;
289
290static DEFINE_SPINLOCK(async_umap_flush_lock);
291static LIST_HEAD(unmaps_to_do);
292
293static int timer_on;
294static long list_size;
5e0d2a6f 295
ba395927
KA		 296static void domain_remove_dev_info(struct dmar_domain *domain);
297
0cd5c3c8
KM		 298#ifdef CONFIG_DMAR_DEFAULT_ON
299int dmar_disabled = 0;
300#else
301int dmar_disabled = 1;
302#endif /*CONFIG_DMAR_DEFAULT_ON*/
303
ba395927 304static int __initdata dmar_map_gfx = 1;
7d3b03ce 305static int dmar_forcedac;
5e0d2a6f 306static int intel_iommu_strict;
ba395927
KA		 307
308#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
309static DEFINE_SPINLOCK(device_domain_lock);
310static LIST_HEAD(device_domain_list);
311
a8bcbb0d
JR		 312static struct iommu_ops intel_iommu_ops;
313
ba395927
KA		 314static int __init intel_iommu_setup(char *str)
315{
316 if (!str)
317 return -EINVAL;
318 while (*str) {
0cd5c3c8
KM		 319 if (!strncmp(str, "on", 2)) {
320 dmar_disabled = 0;
321 printk(KERN_INFO "Intel-IOMMU: enabled\n");
322 } else if (!strncmp(str, "off", 3)) {
ba395927 323 dmar_disabled = 1;
0cd5c3c8 324 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 325 } else if (!strncmp(str, "igfx_off", 8)) {
326 dmar_map_gfx = 0;
327 printk(KERN_INFO
328 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 329 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 330 printk(KERN_INFO
7d3b03ce
KA		 331 "Intel-IOMMU: Forcing DAC for PCI devices\n");
332 dmar_forcedac = 1;
5e0d2a6f 333 } else if (!strncmp(str, "strict", 6)) {
334 printk(KERN_INFO
335 "Intel-IOMMU: disable batched IOTLB flush\n");
336 intel_iommu_strict = 1;
ba395927
KA		 337 }
338
339 str += strcspn(str, ",");
340 while (*str == ',')
341 str++;
342 }
343 return 0;
344}
345__setup("intel_iommu=", intel_iommu_setup);
346
347static struct kmem_cache *iommu_domain_cache;
348static struct kmem_cache *iommu_devinfo_cache;
349static struct kmem_cache *iommu_iova_cache;
350
eb3fa7cb
KA		 351static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
352{
353 unsigned int flags;
354 void *vaddr;
355
356 /* trying to avoid low memory issues */
357 flags = current->flags & PF_MEMALLOC;
358 current->flags |= PF_MEMALLOC;
359 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
360 current->flags &= (~PF_MEMALLOC | flags);
361 return vaddr;
362}
363
364
ba395927
KA		 365static inline void *alloc_pgtable_page(void)
366{
eb3fa7cb
KA		 367 unsigned int flags;
368 void *vaddr;
369
370 /* trying to avoid low memory issues */
371 flags = current->flags & PF_MEMALLOC;
372 current->flags |= PF_MEMALLOC;
373 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
374 current->flags &= (~PF_MEMALLOC | flags);
375 return vaddr;
ba395927
KA		 376}
377
378static inline void free_pgtable_page(void *vaddr)
379{
380 free_page((unsigned long)vaddr);
381}
382
383static inline void *alloc_domain_mem(void)
384{
eb3fa7cb 385 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 386}
387
38717946 388static void free_domain_mem(void *vaddr)
ba395927
KA		 389{
390 kmem_cache_free(iommu_domain_cache, vaddr);
391}
392
393static inline void * alloc_devinfo_mem(void)
394{
eb3fa7cb 395 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 396}
397
398static inline void free_devinfo_mem(void *vaddr)
399{
400 kmem_cache_free(iommu_devinfo_cache, vaddr);
401}
402
403struct iova *alloc_iova_mem(void)
404{
eb3fa7cb 405 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 406}
407
408void free_iova_mem(struct iova *iova)
409{
410 kmem_cache_free(iommu_iova_cache, iova);
411}
412
1b573683
WH		 413
414static inline int width_to_agaw(int width);
415
4ed0d3e6 416static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 417{
418 unsigned long sagaw;
419 int agaw = -1;
420
421 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 422 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 423 agaw >= 0; agaw--) {
424 if (test_bit(agaw, &sagaw))
425 break;
426 }
427
428 return agaw;
429}
430
4ed0d3e6
FY		 431/*
432 * Calculate max SAGAW for each iommu.
433 */
434int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
435{
436 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
437}
438
439/*
440 * calculate agaw for each iommu.
441 * "SAGAW" may be different across iommus, use a default agaw, and
442 * get a supported less agaw for iommus that don't support the default agaw.
443 */
444int iommu_calculate_agaw(struct intel_iommu *iommu)
445{
446 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
447}
448
2c2e2c38 449/* This functionin only returns single iommu in a domain */
8c11e798
WH		 450static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
451{
452 int iommu_id;
453
2c2e2c38 454 /* si_domain and vm domain should not get here. */
1ce28feb 455 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 456 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 457
8c11e798
WH		 458 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
459 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
460 return NULL;
461
462 return g_iommus[iommu_id];
463}
464
8e604097
WH		 465static void domain_update_iommu_coherency(struct dmar_domain *domain)
466{
467 int i;
468
469 domain->iommu_coherency = 1;
470
471 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
472 for (; i < g_num_of_iommus; ) {
473 if (!ecap_coherent(g_iommus[i]->ecap)) {
474 domain->iommu_coherency = 0;
475 break;
476 }
477 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
478 }
479}
480
58c610bd
SY		 481static void domain_update_iommu_snooping(struct dmar_domain *domain)
482{
483 int i;
484
485 domain->iommu_snooping = 1;
486
487 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
488 for (; i < g_num_of_iommus; ) {
489 if (!ecap_sc_support(g_iommus[i]->ecap)) {
490 domain->iommu_snooping = 0;
491 break;
492 }
493 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
494 }
495}
496
497/* Some capabilities may be different across iommus */
498static void domain_update_iommu_cap(struct dmar_domain *domain)
499{
500 domain_update_iommu_coherency(domain);
501 domain_update_iommu_snooping(domain);
502}
503
276dbf99 504static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 505{
506 struct dmar_drhd_unit *drhd = NULL;
507 int i;
508
509 for_each_drhd_unit(drhd) {
510 if (drhd->ignored)
511 continue;
276dbf99
DW		 512 if (segment != drhd->segment)
513 continue;
c7151a8d 514
924b6231 515 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 516 if (drhd->devices[i] &&
517 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 518 drhd->devices[i]->devfn == devfn)
519 return drhd->iommu;
4958c5dc
DW		 520 if (drhd->devices[i] &&
521 drhd->devices[i]->subordinate &&
924b6231
DW		 522 drhd->devices[i]->subordinate->number <= bus &&
523 drhd->devices[i]->subordinate->subordinate >= bus)
524 return drhd->iommu;
525 }
c7151a8d
WH		 526
527 if (drhd->include_all)
528 return drhd->iommu;
529 }
530
531 return NULL;
532}
533
5331fe6f
WH		 534static void domain_flush_cache(struct dmar_domain *domain,
535 void *addr, int size)
536{
537 if (!domain->iommu_coherency)
538 clflush_cache_range(addr, size);
539}
540
ba395927
KA		 541/* Gets context entry for a given bus and devfn */
542static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
543 u8 bus, u8 devfn)
544{
545 struct root_entry *root;
546 struct context_entry *context;
547 unsigned long phy_addr;
548 unsigned long flags;
549
550 spin_lock_irqsave(&iommu->lock, flags);
551 root = &iommu->root_entry[bus];
552 context = get_context_addr_from_root(root);
553 if (!context) {
554 context = (struct context_entry *)alloc_pgtable_page();
555 if (!context) {
556 spin_unlock_irqrestore(&iommu->lock, flags);
557 return NULL;
558 }
5b6985ce 559 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 560 phy_addr = virt_to_phys((void *)context);
561 set_root_value(root, phy_addr);
562 set_root_present(root);
563 __iommu_flush_cache(iommu, root, sizeof(*root));
564 }
565 spin_unlock_irqrestore(&iommu->lock, flags);
566 return &context[devfn];
567}
568
569static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
570{
571 struct root_entry *root;
572 struct context_entry *context;
573 int ret;
574 unsigned long flags;
575
576 spin_lock_irqsave(&iommu->lock, flags);
577 root = &iommu->root_entry[bus];
578 context = get_context_addr_from_root(root);
579 if (!context) {
580 ret = 0;
581 goto out;
582 }
c07e7d21 583 ret = context_present(&context[devfn]);
ba395927
KA		 584out:
585 spin_unlock_irqrestore(&iommu->lock, flags);
586 return ret;
587}
588
589static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
590{
591 struct root_entry *root;
592 struct context_entry *context;
593 unsigned long flags;
594
595 spin_lock_irqsave(&iommu->lock, flags);
596 root = &iommu->root_entry[bus];
597 context = get_context_addr_from_root(root);
598 if (context) {
c07e7d21 599 context_clear_entry(&context[devfn]);
ba395927
KA		 600 __iommu_flush_cache(iommu, &context[devfn], \
601 sizeof(*context));
602 }
603 spin_unlock_irqrestore(&iommu->lock, flags);
604}
605
606static void free_context_table(struct intel_iommu *iommu)
607{
608 struct root_entry *root;
609 int i;
610 unsigned long flags;
611 struct context_entry *context;
612
613 spin_lock_irqsave(&iommu->lock, flags);
614 if (!iommu->root_entry) {
615 goto out;
616 }
617 for (i = 0; i < ROOT_ENTRY_NR; i++) {
618 root = &iommu->root_entry[i];
619 context = get_context_addr_from_root(root);
620 if (context)
621 free_pgtable_page(context);
622 }
623 free_pgtable_page(iommu->root_entry);
624 iommu->root_entry = NULL;
625out:
626 spin_unlock_irqrestore(&iommu->lock, flags);
627}
628
629/* page table handling */
630#define LEVEL_STRIDE (9)
631#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
632
633static inline int agaw_to_level(int agaw)
634{
635 return agaw + 2;
636}
637
638static inline int agaw_to_width(int agaw)
639{
640 return 30 + agaw * LEVEL_STRIDE;
641
642}
643
644static inline int width_to_agaw(int width)
645{
646 return (width - 30) / LEVEL_STRIDE;
647}
648
649static inline unsigned int level_to_offset_bits(int level)
650{
651 return (12 + (level - 1) * LEVEL_STRIDE);
652}
653
654static inline int address_level_offset(u64 addr, int level)
655{
656 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
657}
658
659static inline u64 level_mask(int level)
660{
661 return ((u64)-1 << level_to_offset_bits(level));
662}
663
664static inline u64 level_size(int level)
665{
666 return ((u64)1 << level_to_offset_bits(level));
667}
668
669static inline u64 align_to_level(u64 addr, int level)
670{
671 return ((addr + level_size(level) - 1) & level_mask(level));
672}
673
674static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
675{
676 int addr_width = agaw_to_width(domain->agaw);
677 struct dma_pte *parent, *pte = NULL;
678 int level = agaw_to_level(domain->agaw);
679 int offset;
680 unsigned long flags;
681
682 BUG_ON(!domain->pgd);
683
684 addr &= (((u64)1) << addr_width) - 1;
685 parent = domain->pgd;
686
687 spin_lock_irqsave(&domain->mapping_lock, flags);
688 while (level > 0) {
689 void *tmp_page;
690
691 offset = address_level_offset(addr, level);
692 pte = &parent[offset];
693 if (level == 1)
694 break;
695
19c239ce 696 if (!dma_pte_present(pte)) {
ba395927
KA		 697 tmp_page = alloc_pgtable_page();
698
699 if (!tmp_page) {
700 spin_unlock_irqrestore(&domain->mapping_lock,
701 flags);
702 return NULL;
703 }
5331fe6f 704 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
19c239ce 705 dma_set_pte_addr(pte, virt_to_phys(tmp_page));
ba395927
KA		 706 /*
707 * high level table always sets r/w, last level page
708 * table control read/write
709 */
19c239ce
MM		 710 dma_set_pte_readable(pte);
711 dma_set_pte_writable(pte);
5331fe6f 712 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927 713 }
19c239ce 714 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 715 level--;
716 }
717
718 spin_unlock_irqrestore(&domain->mapping_lock, flags);
719 return pte;
720}
721
722/* return address's pte at specific level */
723static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
724 int level)
725{
726 struct dma_pte *parent, *pte = NULL;
727 int total = agaw_to_level(domain->agaw);
728 int offset;
729
730 parent = domain->pgd;
731 while (level <= total) {
732 offset = address_level_offset(addr, total);
733 pte = &parent[offset];
734 if (level == total)
735 return pte;
736
19c239ce 737 if (!dma_pte_present(pte))
ba395927 738 break;
19c239ce 739 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 740 total--;
741 }
742 return NULL;
743}
744
745/* clear one page's page table */
746static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
747{
748 struct dma_pte *pte = NULL;
749
750 /* get last level pte */
751 pte = dma_addr_level_pte(domain, addr, 1);
752
753 if (pte) {
19c239ce 754 dma_clear_pte(pte);
5331fe6f 755 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927
KA		 756 }
757}
758
759/* clear last level pte, a tlb flush should be followed */
760static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
761{
762 int addr_width = agaw_to_width(domain->agaw);
afeeb7ce 763 int npages;
ba395927
KA		 764
765 start &= (((u64)1) << addr_width) - 1;
766 end &= (((u64)1) << addr_width) - 1;
767 /* in case it's partial page */
31d3568d
FY		 768 start &= PAGE_MASK;
769 end = PAGE_ALIGN(end);
afeeb7ce 770 npages = (end - start) / VTD_PAGE_SIZE;
ba395927
KA		 771
772 /* we don't need lock here, nobody else touches the iova range */
afeeb7ce 773 while (npages--) {
ba395927 774 dma_pte_clear_one(domain, start);
5b6985ce 775 start += VTD_PAGE_SIZE;
ba395927
KA		 776 }
777}
778
779/* free page table pages. last level pte should already be cleared */
780static void dma_pte_free_pagetable(struct dmar_domain *domain,
781 u64 start, u64 end)
782{
783 int addr_width = agaw_to_width(domain->agaw);
784 struct dma_pte *pte;
785 int total = agaw_to_level(domain->agaw);
786 int level;
787 u64 tmp;
788
789 start &= (((u64)1) << addr_width) - 1;
790 end &= (((u64)1) << addr_width) - 1;
791
792 /* we don't need lock here, nobody else touches the iova range */
793 level = 2;
794 while (level <= total) {
795 tmp = align_to_level(start, level);
796 if (tmp >= end || (tmp + level_size(level) > end))
797 return;
798
799 while (tmp < end) {
800 pte = dma_addr_level_pte(domain, tmp, level);
801 if (pte) {
802 free_pgtable_page(
19c239ce
MM		 803 phys_to_virt(dma_pte_addr(pte)));
804 dma_clear_pte(pte);
5331fe6f 805 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927
KA		 806 }
807 tmp += level_size(level);
808 }
809 level++;
810 }
811 /* free pgd */
812 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
813 free_pgtable_page(domain->pgd);
814 domain->pgd = NULL;
815 }
816}
817
818/* iommu handling */
819static int iommu_alloc_root_entry(struct intel_iommu *iommu)
820{
821 struct root_entry *root;
822 unsigned long flags;
823
824 root = (struct root_entry *)alloc_pgtable_page();
825 if (!root)
826 return -ENOMEM;
827
5b6985ce 828 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 829
830 spin_lock_irqsave(&iommu->lock, flags);
831 iommu->root_entry = root;
832 spin_unlock_irqrestore(&iommu->lock, flags);
833
834 return 0;
835}
836
ba395927
KA		 837static void iommu_set_root_entry(struct intel_iommu *iommu)
838{
839 void *addr;
c416daa9 840 u32 sts;
ba395927
KA		 841 unsigned long flag;
842
843 addr = iommu->root_entry;
844
845 spin_lock_irqsave(&iommu->register_lock, flag);
846 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
847
c416daa9 848 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 849
850 /* Make sure hardware complete it */
851 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 852 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 853
854 spin_unlock_irqrestore(&iommu->register_lock, flag);
855}
856
857static void iommu_flush_write_buffer(struct intel_iommu *iommu)
858{
859 u32 val;
860 unsigned long flag;
861
9af88143 862 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 863 return;
ba395927
KA		 864
865 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 866 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 867
868 /* Make sure hardware complete it */
869 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 870 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 871
872 spin_unlock_irqrestore(&iommu->register_lock, flag);
873}
874
875/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 876static void __iommu_flush_context(struct intel_iommu *iommu,
877 u16 did, u16 source_id, u8 function_mask,
878 u64 type)
ba395927
KA		 879{
880 u64 val = 0;
881 unsigned long flag;
882
ba395927
KA		 883 switch (type) {
884 case DMA_CCMD_GLOBAL_INVL:
885 val = DMA_CCMD_GLOBAL_INVL;
886 break;
887 case DMA_CCMD_DOMAIN_INVL:
888 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
889 break;
890 case DMA_CCMD_DEVICE_INVL:
891 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
892 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
893 break;
894 default:
895 BUG();
896 }
897 val |= DMA_CCMD_ICC;
898
899 spin_lock_irqsave(&iommu->register_lock, flag);
900 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
901
902 /* Make sure hardware complete it */
903 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
904 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
905
906 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 907}
908
ba395927 909/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 910static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
911 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 912{
913 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
914 u64 val = 0, val_iva = 0;
915 unsigned long flag;
916
ba395927
KA		 917 switch (type) {
918 case DMA_TLB_GLOBAL_FLUSH:
919 /* global flush doesn't need set IVA_REG */
920 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
921 break;
922 case DMA_TLB_DSI_FLUSH:
923 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
924 break;
925 case DMA_TLB_PSI_FLUSH:
926 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
927 /* Note: always flush non-leaf currently */
928 val_iva = size_order | addr;
929 break;
930 default:
931 BUG();
932 }
933 /* Note: set drain read/write */
934#if 0
935 /*
936 * This is probably to be super secure.. Looks like we can
937 * ignore it without any impact.
938 */
939 if (cap_read_drain(iommu->cap))
940 val |= DMA_TLB_READ_DRAIN;
941#endif
942 if (cap_write_drain(iommu->cap))
943 val |= DMA_TLB_WRITE_DRAIN;
944
945 spin_lock_irqsave(&iommu->register_lock, flag);
946 /* Note: Only uses first TLB reg currently */
947 if (val_iva)
948 dmar_writeq(iommu->reg + tlb_offset, val_iva);
949 dmar_writeq(iommu->reg + tlb_offset + 8, val);
950
951 /* Make sure hardware complete it */
952 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
953 dmar_readq, (!(val & DMA_TLB_IVT)), val);
954
955 spin_unlock_irqrestore(&iommu->register_lock, flag);
956
957 /* check IOTLB invalidation granularity */
958 if (DMA_TLB_IAIG(val) == 0)
959 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
960 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
961 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 962 (unsigned long long)DMA_TLB_IIRG(type),
963 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 964}
965
93a23a72
YZ		 966static struct device_domain_info *iommu_support_dev_iotlb(
967 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
968{
969 int found = 0;
970 unsigned long flags;
971 struct device_domain_info *info;
972 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
973
974 if (!ecap_dev_iotlb_support(iommu->ecap))
975 return NULL;
976
977 if (!iommu->qi)
978 return NULL;
979
980 spin_lock_irqsave(&device_domain_lock, flags);
981 list_for_each_entry(info, &domain->devices, link)
982 if (info->bus == bus && info->devfn == devfn) {
983 found = 1;
984 break;
985 }
986 spin_unlock_irqrestore(&device_domain_lock, flags);
987
988 if (!found || !info->dev)
989 return NULL;
990
991 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
992 return NULL;
993
994 if (!dmar_find_matched_atsr_unit(info->dev))
995 return NULL;
996
997 info->iommu = iommu;
998
999 return info;
1000}
1001
1002static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1003{
93a23a72
YZ		 1004 if (!info)
1005 return;
1006
1007 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1008}
1009
1010static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1011{
1012 if (!info->dev || !pci_ats_enabled(info->dev))
1013 return;
1014
1015 pci_disable_ats(info->dev);
1016}
1017
1018static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1019 u64 addr, unsigned mask)
1020{
1021 u16 sid, qdep;
1022 unsigned long flags;
1023 struct device_domain_info *info;
1024
1025 spin_lock_irqsave(&device_domain_lock, flags);
1026 list_for_each_entry(info, &domain->devices, link) {
1027 if (!info->dev || !pci_ats_enabled(info->dev))
1028 continue;
1029
1030 sid = info->bus << 8 | info->devfn;
1031 qdep = pci_ats_queue_depth(info->dev);
1032 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1033 }
1034 spin_unlock_irqrestore(&device_domain_lock, flags);
1035}
1036
1f0ef2aa
DW		 1037static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1038 u64 addr, unsigned int pages)
ba395927 1039{
9dd2fe89 1040 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
ba395927 1041
5b6985ce 1042 BUG_ON(addr & (~VTD_PAGE_MASK));
ba395927
KA		 1043 BUG_ON(pages == 0);
1044
ba395927 1045 /*
9dd2fe89
YZ		 1046 * Fallback to domain selective flush if no PSI support or the size is
1047 * too big.
ba395927
KA		 1048 * PSI requires page size to be 2 ^ x, and the base address is naturally
1049 * aligned to the size
1050 */
9dd2fe89
YZ		 1051 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1052 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1053 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1054 else
1055 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1056 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1057
1058 /*
1059 * In caching mode, domain ID 0 is reserved for non-present to present
1060 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1061 */
1062 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1063 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1064}
1065
f8bab735 1066static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1067{
1068 u32 pmen;
1069 unsigned long flags;
1070
1071 spin_lock_irqsave(&iommu->register_lock, flags);
1072 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1073 pmen &= ~DMA_PMEN_EPM;
1074 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1075
1076 /* wait for the protected region status bit to clear */
1077 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1078 readl, !(pmen & DMA_PMEN_PRS), pmen);
1079
1080 spin_unlock_irqrestore(&iommu->register_lock, flags);
1081}
1082
ba395927
KA		 1083static int iommu_enable_translation(struct intel_iommu *iommu)
1084{
1085 u32 sts;
1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1089 iommu->gcmd |= DMA_GCMD_TE;
1090 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1091
1092 /* Make sure hardware complete it */
1093 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1094 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1095
ba395927
KA		 1096 spin_unlock_irqrestore(&iommu->register_lock, flags);
1097 return 0;
1098}
1099
1100static int iommu_disable_translation(struct intel_iommu *iommu)
1101{
1102 u32 sts;
1103 unsigned long flag;
1104
1105 spin_lock_irqsave(&iommu->register_lock, flag);
1106 iommu->gcmd &= ~DMA_GCMD_TE;
1107 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1108
1109 /* Make sure hardware complete it */
1110 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1111 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1112
1113 spin_unlock_irqrestore(&iommu->register_lock, flag);
1114 return 0;
1115}
1116
3460a6d9 1117
ba395927
KA		 1118static int iommu_init_domains(struct intel_iommu *iommu)
1119{
1120 unsigned long ndomains;
1121 unsigned long nlongs;
1122
1123 ndomains = cap_ndoms(iommu->cap);
1124 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1125 nlongs = BITS_TO_LONGS(ndomains);
1126
1127 /* TBD: there might be 64K domains,
1128 * consider other allocation for future chip
1129 */
1130 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1131 if (!iommu->domain_ids) {
1132 printk(KERN_ERR "Allocating domain id array failed\n");
1133 return -ENOMEM;
1134 }
1135 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1136 GFP_KERNEL);
1137 if (!iommu->domains) {
1138 printk(KERN_ERR "Allocating domain array failed\n");
1139 kfree(iommu->domain_ids);
1140 return -ENOMEM;
1141 }
1142
e61d98d8
SS		 1143 spin_lock_init(&iommu->lock);
1144
ba395927
KA		 1145 /*
1146 * if Caching mode is set, then invalid translations are tagged
1147 * with domainid 0. Hence we need to pre-allocate it.
1148 */
1149 if (cap_caching_mode(iommu->cap))
1150 set_bit(0, iommu->domain_ids);
1151 return 0;
1152}
ba395927 1153
ba395927
KA		 1154
1155static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1156static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1157
1158void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1159{
1160 struct dmar_domain *domain;
1161 int i;
c7151a8d 1162 unsigned long flags;
ba395927 1163
ba395927
KA		 1164 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1165 for (; i < cap_ndoms(iommu->cap); ) {
1166 domain = iommu->domains[i];
1167 clear_bit(i, iommu->domain_ids);
c7151a8d
WH		 1168
1169 spin_lock_irqsave(&domain->iommu_lock, flags);
5e98c4b1
WH		 1170 if (--domain->iommu_count == 0) {
1171 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1172 vm_domain_exit(domain);
1173 else
1174 domain_exit(domain);
1175 }
c7151a8d
WH		 1176 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1177
ba395927
KA		 1178 i = find_next_bit(iommu->domain_ids,
1179 cap_ndoms(iommu->cap), i+1);
1180 }
1181
1182 if (iommu->gcmd & DMA_GCMD_TE)
1183 iommu_disable_translation(iommu);
1184
1185 if (iommu->irq) {
1186 set_irq_data(iommu->irq, NULL);
1187 /* This will mask the irq */
1188 free_irq(iommu->irq, iommu);
1189 destroy_irq(iommu->irq);
1190 }
1191
1192 kfree(iommu->domains);
1193 kfree(iommu->domain_ids);
1194
d9630fe9
WH		 1195 g_iommus[iommu->seq_id] = NULL;
1196
1197 /* if all iommus are freed, free g_iommus */
1198 for (i = 0; i < g_num_of_iommus; i++) {
1199 if (g_iommus[i])
1200 break;
1201 }
1202
1203 if (i == g_num_of_iommus)
1204 kfree(g_iommus);
1205
ba395927
KA		 1206 /* free context mapping */
1207 free_context_table(iommu);
ba395927
KA		 1208}
1209
2c2e2c38 1210static struct dmar_domain *alloc_domain(void)
ba395927 1211{
ba395927 1212 struct dmar_domain *domain;
ba395927
KA		 1213
1214 domain = alloc_domain_mem();
1215 if (!domain)
1216 return NULL;
1217
2c2e2c38
FY		 1218 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1219 domain->flags = 0;
1220
1221 return domain;
1222}
1223
1224static int iommu_attach_domain(struct dmar_domain *domain,
1225 struct intel_iommu *iommu)
1226{
1227 int num;
1228 unsigned long ndomains;
1229 unsigned long flags;
1230
ba395927
KA		 1231 ndomains = cap_ndoms(iommu->cap);
1232
1233 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1234
ba395927
KA		 1235 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1236 if (num >= ndomains) {
1237 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1238 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1239 return -ENOMEM;
ba395927
KA		 1240 }
1241
ba395927 1242 domain->id = num;
2c2e2c38 1243 set_bit(num, iommu->domain_ids);
8c11e798 1244 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1245 iommu->domains[num] = domain;
1246 spin_unlock_irqrestore(&iommu->lock, flags);
1247
2c2e2c38 1248 return 0;
ba395927
KA		 1249}
1250
2c2e2c38
FY		 1251static void iommu_detach_domain(struct dmar_domain *domain,
1252 struct intel_iommu *iommu)
ba395927
KA		 1253{
1254 unsigned long flags;
2c2e2c38
FY		 1255 int num, ndomains;
1256 int found = 0;
ba395927 1257
8c11e798 1258 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1259 ndomains = cap_ndoms(iommu->cap);
1260 num = find_first_bit(iommu->domain_ids, ndomains);
1261 for (; num < ndomains; ) {
1262 if (iommu->domains[num] == domain) {
1263 found = 1;
1264 break;
1265 }
1266 num = find_next_bit(iommu->domain_ids,
1267 cap_ndoms(iommu->cap), num+1);
1268 }
1269
1270 if (found) {
1271 clear_bit(num, iommu->domain_ids);
1272 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1273 iommu->domains[num] = NULL;
1274 }
8c11e798 1275 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1276}
1277
1278static struct iova_domain reserved_iova_list;
8a443df4
MG		 1279static struct lock_class_key reserved_alloc_key;
1280static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1281
1282static void dmar_init_reserved_ranges(void)
1283{
1284 struct pci_dev *pdev = NULL;
1285 struct iova *iova;
1286 int i;
1287 u64 addr, size;
1288
f661197e 1289 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1290
8a443df4
MG		 1291 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1292 &reserved_alloc_key);
1293 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1294 &reserved_rbtree_key);
1295
ba395927
KA		 1296 /* IOAPIC ranges shouldn't be accessed by DMA */
1297 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1298 IOVA_PFN(IOAPIC_RANGE_END));
1299 if (!iova)
1300 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1301
1302 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1303 for_each_pci_dev(pdev) {
1304 struct resource *r;
1305
1306 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1307 r = &pdev->resource[i];
1308 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1309 continue;
1310 addr = r->start;
fd18de50 1311 addr &= PHYSICAL_PAGE_MASK;
ba395927 1312 size = r->end - addr;
5b6985ce 1313 size = PAGE_ALIGN(size);
ba395927
KA		 1314 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1315 IOVA_PFN(size + addr) - 1);
1316 if (!iova)
1317 printk(KERN_ERR "Reserve iova failed\n");
1318 }
1319 }
1320
1321}
1322
1323static void domain_reserve_special_ranges(struct dmar_domain *domain)
1324{
1325 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1326}
1327
1328static inline int guestwidth_to_adjustwidth(int gaw)
1329{
1330 int agaw;
1331 int r = (gaw - 12) % 9;
1332
1333 if (r == 0)
1334 agaw = gaw;
1335 else
1336 agaw = gaw + 9 - r;
1337 if (agaw > 64)
1338 agaw = 64;
1339 return agaw;
1340}
1341
1342static int domain_init(struct dmar_domain *domain, int guest_width)
1343{
1344 struct intel_iommu *iommu;
1345 int adjust_width, agaw;
1346 unsigned long sagaw;
1347
f661197e 1348 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927 1349 spin_lock_init(&domain->mapping_lock);
c7151a8d 1350 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1351
1352 domain_reserve_special_ranges(domain);
1353
1354 /* calculate AGAW */
8c11e798 1355 iommu = domain_get_iommu(domain);
ba395927
KA		 1356 if (guest_width > cap_mgaw(iommu->cap))
1357 guest_width = cap_mgaw(iommu->cap);
1358 domain->gaw = guest_width;
1359 adjust_width = guestwidth_to_adjustwidth(guest_width);
1360 agaw = width_to_agaw(adjust_width);
1361 sagaw = cap_sagaw(iommu->cap);
1362 if (!test_bit(agaw, &sagaw)) {
1363 /* hardware doesn't support it, choose a bigger one */
1364 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1365 agaw = find_next_bit(&sagaw, 5, agaw);
1366 if (agaw >= 5)
1367 return -ENODEV;
1368 }
1369 domain->agaw = agaw;
1370 INIT_LIST_HEAD(&domain->devices);
1371
8e604097
WH		 1372 if (ecap_coherent(iommu->ecap))
1373 domain->iommu_coherency = 1;
1374 else
1375 domain->iommu_coherency = 0;
1376
58c610bd
SY		 1377 if (ecap_sc_support(iommu->ecap))
1378 domain->iommu_snooping = 1;
1379 else
1380 domain->iommu_snooping = 0;
1381
c7151a8d
WH		 1382 domain->iommu_count = 1;
1383
ba395927
KA		 1384 /* always allocate the top pgd */
1385 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1386 if (!domain->pgd)
1387 return -ENOMEM;
5b6985ce 1388 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1389 return 0;
1390}
1391
1392static void domain_exit(struct dmar_domain *domain)
1393{
2c2e2c38
FY		 1394 struct dmar_drhd_unit *drhd;
1395 struct intel_iommu *iommu;
ba395927
KA		 1396 u64 end;
1397
1398 /* Domain 0 is reserved, so dont process it */
1399 if (!domain)
1400 return;
1401
1402 domain_remove_dev_info(domain);
1403 /* destroy iovas */
1404 put_iova_domain(&domain->iovad);
1405 end = DOMAIN_MAX_ADDR(domain->gaw);
5b6985ce 1406 end = end & (~PAGE_MASK);
ba395927
KA		 1407
1408 /* clear ptes */
1409 dma_pte_clear_range(domain, 0, end);
1410
1411 /* free page tables */
1412 dma_pte_free_pagetable(domain, 0, end);
1413
2c2e2c38
FY		 1414 for_each_active_iommu(iommu, drhd)
1415 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1416 iommu_detach_domain(domain, iommu);
1417
ba395927
KA		 1418 free_domain_mem(domain);
1419}
1420
4ed0d3e6
FY		 1421static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1422 u8 bus, u8 devfn, int translation)
ba395927
KA		 1423{
1424 struct context_entry *context;
ba395927 1425 unsigned long flags;
5331fe6f 1426 struct intel_iommu *iommu;
ea6606b0
WH		 1427 struct dma_pte *pgd;
1428 unsigned long num;
1429 unsigned long ndomains;
1430 int id;
1431 int agaw;
93a23a72 1432 struct device_domain_info *info = NULL;
ba395927
KA		 1433
1434 pr_debug("Set context mapping for %02x:%02x.%d\n",
1435 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1436
ba395927 1437 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1438 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1439 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1440
276dbf99 1441 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1442 if (!iommu)
1443 return -ENODEV;
1444
ba395927
KA		 1445 context = device_to_context_entry(iommu, bus, devfn);
1446 if (!context)
1447 return -ENOMEM;
1448 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1449 if (context_present(context)) {
ba395927
KA		 1450 spin_unlock_irqrestore(&iommu->lock, flags);
1451 return 0;
1452 }
1453
ea6606b0
WH		 1454 id = domain->id;
1455 pgd = domain->pgd;
1456
2c2e2c38
FY		 1457 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1458 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1459 int found = 0;
1460
1461 /* find an available domain id for this device in iommu */
1462 ndomains = cap_ndoms(iommu->cap);
1463 num = find_first_bit(iommu->domain_ids, ndomains);
1464 for (; num < ndomains; ) {
1465 if (iommu->domains[num] == domain) {
1466 id = num;
1467 found = 1;
1468 break;
1469 }
1470 num = find_next_bit(iommu->domain_ids,
1471 cap_ndoms(iommu->cap), num+1);
1472 }
1473
1474 if (found == 0) {
1475 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1476 if (num >= ndomains) {
1477 spin_unlock_irqrestore(&iommu->lock, flags);
1478 printk(KERN_ERR "IOMMU: no free domain ids\n");
1479 return -EFAULT;
1480 }
1481
1482 set_bit(num, iommu->domain_ids);
2c2e2c38 1483 set_bit(iommu->seq_id, &domain->iommu_bmp);
ea6606b0
WH		 1484 iommu->domains[num] = domain;
1485 id = num;
1486 }
1487
1488 /* Skip top levels of page tables for
1489 * iommu which has less agaw than default.
1490 */
1491 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1492 pgd = phys_to_virt(dma_pte_addr(pgd));
1493 if (!dma_pte_present(pgd)) {
1494 spin_unlock_irqrestore(&iommu->lock, flags);
1495 return -ENOMEM;
1496 }
1497 }
1498 }
1499
1500 context_set_domain_id(context, id);
4ed0d3e6 1501
93a23a72
YZ		 1502 if (translation != CONTEXT_TT_PASS_THROUGH) {
1503 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1504 translation = info ? CONTEXT_TT_DEV_IOTLB :
1505 CONTEXT_TT_MULTI_LEVEL;
1506 }
4ed0d3e6
FY		 1507 /*
1508 * In pass through mode, AW must be programmed to indicate the largest
1509 * AGAW value supported by hardware. And ASR is ignored by hardware.
1510 */
93a23a72 1511 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1512 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1513 else {
1514 context_set_address_root(context, virt_to_phys(pgd));
1515 context_set_address_width(context, iommu->agaw);
1516 }
4ed0d3e6
FY		 1517
1518 context_set_translation_type(context, translation);
c07e7d21
MM		 1519 context_set_fault_enable(context);
1520 context_set_present(context);
5331fe6f 1521 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1522
4c25a2c1
DW		 1523 /*
1524 * It's a non-present to present mapping. If hardware doesn't cache
1525 * non-present entry we only need to flush the write-buffer. If the
1526 * _does_ cache non-present entries, then it does so in the special
1527 * domain #0, which we have to flush:
1528 */
1529 if (cap_caching_mode(iommu->cap)) {
1530 iommu->flush.flush_context(iommu, 0,
1531 (((u16)bus) << 8) | devfn,
1532 DMA_CCMD_MASK_NOBIT,
1533 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1534 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1535 } else {
ba395927 1536 iommu_flush_write_buffer(iommu);
4c25a2c1 1537 }
93a23a72 1538 iommu_enable_dev_iotlb(info);
ba395927 1539 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1540
1541 spin_lock_irqsave(&domain->iommu_lock, flags);
1542 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1543 domain->iommu_count++;
58c610bd 1544 domain_update_iommu_cap(domain);
c7151a8d
WH		 1545 }
1546 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1547 return 0;
1548}
1549
1550static int
4ed0d3e6
FY		 1551domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1552 int translation)
ba395927
KA		 1553{
1554 int ret;
1555 struct pci_dev *tmp, *parent;
1556
276dbf99 1557 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1558 pdev->bus->number, pdev->devfn,
1559 translation);
ba395927
KA		 1560 if (ret)
1561 return ret;
1562
1563 /* dependent device mapping */
1564 tmp = pci_find_upstream_pcie_bridge(pdev);
1565 if (!tmp)
1566 return 0;
1567 /* Secondary interface's bus number and devfn 0 */
1568 parent = pdev->bus->self;
1569 while (parent != tmp) {
276dbf99
DW		 1570 ret = domain_context_mapping_one(domain,
1571 pci_domain_nr(parent->bus),
1572 parent->bus->number,
4ed0d3e6 1573 parent->devfn, translation);
ba395927
KA		 1574 if (ret)
1575 return ret;
1576 parent = parent->bus->self;
1577 }
1578 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1579 return domain_context_mapping_one(domain,
276dbf99 1580 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1581 tmp->subordinate->number, 0,
1582 translation);
ba395927
KA		 1583 else /* this is a legacy PCI bridge */
1584 return domain_context_mapping_one(domain,
276dbf99
DW		 1585 pci_domain_nr(tmp->bus),
1586 tmp->bus->number,
4ed0d3e6
FY		 1587 tmp->devfn,
1588 translation);
ba395927
KA		 1589}
1590
5331fe6f 1591static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1592{
1593 int ret;
1594 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1595 struct intel_iommu *iommu;
1596
276dbf99
DW		 1597 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1598 pdev->devfn);
5331fe6f
WH		 1599 if (!iommu)
1600 return -ENODEV;
ba395927 1601
276dbf99 1602 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1603 if (!ret)
1604 return ret;
1605 /* dependent device mapping */
1606 tmp = pci_find_upstream_pcie_bridge(pdev);
1607 if (!tmp)
1608 return ret;
1609 /* Secondary interface's bus number and devfn 0 */
1610 parent = pdev->bus->self;
1611 while (parent != tmp) {
8c11e798 1612 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1613 parent->devfn);
ba395927
KA		 1614 if (!ret)
1615 return ret;
1616 parent = parent->bus->self;
1617 }
1618 if (tmp->is_pcie)
276dbf99
DW		 1619 return device_context_mapped(iommu, tmp->subordinate->number,
1620 0);
ba395927 1621 else
276dbf99
DW		 1622 return device_context_mapped(iommu, tmp->bus->number,
1623 tmp->devfn);
ba395927
KA		 1624}
1625
1626static int
1627domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1628 u64 hpa, size_t size, int prot)
1629{
1630 u64 start_pfn, end_pfn;
1631 struct dma_pte *pte;
1632 int index;
5b6985ce
FY		 1633 int addr_width = agaw_to_width(domain->agaw);
1634
1635 hpa &= (((u64)1) << addr_width) - 1;
ba395927
KA		 1636
1637 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1638 return -EINVAL;
5b6985ce
FY		 1639 iova &= PAGE_MASK;
1640 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1641 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
ba395927
KA		 1642 index = 0;
1643 while (start_pfn < end_pfn) {
5b6985ce 1644 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
ba395927
KA		 1645 if (!pte)
1646 return -ENOMEM;
1647 /* We don't need lock here, nobody else
1648 * touches the iova range
1649 */
19c239ce
MM		 1650 BUG_ON(dma_pte_addr(pte));
1651 dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
1652 dma_set_pte_prot(pte, prot);
9cf06697
SY		 1653 if (prot & DMA_PTE_SNP)
1654 dma_set_pte_snp(pte);
5331fe6f 1655 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927
KA		 1656 start_pfn++;
1657 index++;
1658 }
1659 return 0;
1660}
1661
c7151a8d 1662static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1663{
c7151a8d
WH		 1664 if (!iommu)
1665 return;
8c11e798
WH		 1666
1667 clear_context_table(iommu, bus, devfn);
1668 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1669 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1670 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1671}
1672
1673static void domain_remove_dev_info(struct dmar_domain *domain)
1674{
1675 struct device_domain_info *info;
1676 unsigned long flags;
c7151a8d 1677 struct intel_iommu *iommu;
ba395927
KA		 1678
1679 spin_lock_irqsave(&device_domain_lock, flags);
1680 while (!list_empty(&domain->devices)) {
1681 info = list_entry(domain->devices.next,
1682 struct device_domain_info, link);
1683 list_del(&info->link);
1684 list_del(&info->global);
1685 if (info->dev)
358dd8ac 1686 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1687 spin_unlock_irqrestore(&device_domain_lock, flags);
1688
93a23a72 1689 iommu_disable_dev_iotlb(info);
276dbf99 1690 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1691 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1692 free_devinfo_mem(info);
1693
1694 spin_lock_irqsave(&device_domain_lock, flags);
1695 }
1696 spin_unlock_irqrestore(&device_domain_lock, flags);
1697}
1698
1699/*
1700 * find_domain
358dd8ac 1701 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1702 */
38717946 1703static struct dmar_domain *
ba395927
KA		 1704find_domain(struct pci_dev *pdev)
1705{
1706 struct device_domain_info *info;
1707
1708 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1709 info = pdev->dev.archdata.iommu;
ba395927
KA		 1710 if (info)
1711 return info->domain;
1712 return NULL;
1713}
1714
ba395927
KA		 1715/* domain is initialized */
1716static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1717{
1718 struct dmar_domain *domain, *found = NULL;
1719 struct intel_iommu *iommu;
1720 struct dmar_drhd_unit *drhd;
1721 struct device_domain_info *info, *tmp;
1722 struct pci_dev *dev_tmp;
1723 unsigned long flags;
1724 int bus = 0, devfn = 0;
276dbf99 1725 int segment;
2c2e2c38 1726 int ret;
ba395927
KA		 1727
1728 domain = find_domain(pdev);
1729 if (domain)
1730 return domain;
1731
276dbf99
DW		 1732 segment = pci_domain_nr(pdev->bus);
1733
ba395927
KA		 1734 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1735 if (dev_tmp) {
1736 if (dev_tmp->is_pcie) {
1737 bus = dev_tmp->subordinate->number;
1738 devfn = 0;
1739 } else {
1740 bus = dev_tmp->bus->number;
1741 devfn = dev_tmp->devfn;
1742 }
1743 spin_lock_irqsave(&device_domain_lock, flags);
1744 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1745 if (info->segment == segment &&
1746 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1747 found = info->domain;
1748 break;
1749 }
1750 }
1751 spin_unlock_irqrestore(&device_domain_lock, flags);
1752 /* pcie-pci bridge already has a domain, uses it */
1753 if (found) {
1754 domain = found;
1755 goto found_domain;
1756 }
1757 }
1758
2c2e2c38
FY		 1759 domain = alloc_domain();
1760 if (!domain)
1761 goto error;
1762
ba395927
KA		 1763 /* Allocate new domain for the device */
1764 drhd = dmar_find_matched_drhd_unit(pdev);
1765 if (!drhd) {
1766 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1767 pci_name(pdev));
1768 return NULL;
1769 }
1770 iommu = drhd->iommu;
1771
2c2e2c38
FY		 1772 ret = iommu_attach_domain(domain, iommu);
1773 if (ret) {
1774 domain_exit(domain);
ba395927 1775 goto error;
2c2e2c38 1776 }
ba395927
KA		 1777
1778 if (domain_init(domain, gaw)) {
1779 domain_exit(domain);
1780 goto error;
1781 }
1782
1783 /* register pcie-to-pci device */
1784 if (dev_tmp) {
1785 info = alloc_devinfo_mem();
1786 if (!info) {
1787 domain_exit(domain);
1788 goto error;
1789 }
276dbf99 1790 info->segment = segment;
ba395927
KA		 1791 info->bus = bus;
1792 info->devfn = devfn;
1793 info->dev = NULL;
1794 info->domain = domain;
1795 /* This domain is shared by devices under p2p bridge */
3b5410e7 1796 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1797
1798 /* pcie-to-pci bridge already has a domain, uses it */
1799 found = NULL;
1800 spin_lock_irqsave(&device_domain_lock, flags);
1801 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1802 if (tmp->segment == segment &&
1803 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1804 found = tmp->domain;
1805 break;
1806 }
1807 }
1808 if (found) {
1809 free_devinfo_mem(info);
1810 domain_exit(domain);
1811 domain = found;
1812 } else {
1813 list_add(&info->link, &domain->devices);
1814 list_add(&info->global, &device_domain_list);
1815 }
1816 spin_unlock_irqrestore(&device_domain_lock, flags);
1817 }
1818
1819found_domain:
1820 info = alloc_devinfo_mem();
1821 if (!info)
1822 goto error;
276dbf99 1823 info->segment = segment;
ba395927
KA		 1824 info->bus = pdev->bus->number;
1825 info->devfn = pdev->devfn;
1826 info->dev = pdev;
1827 info->domain = domain;
1828 spin_lock_irqsave(&device_domain_lock, flags);
1829 /* somebody is fast */
1830 found = find_domain(pdev);
1831 if (found != NULL) {
1832 spin_unlock_irqrestore(&device_domain_lock, flags);
1833 if (found != domain) {
1834 domain_exit(domain);
1835 domain = found;
1836 }
1837 free_devinfo_mem(info);
1838 return domain;
1839 }
1840 list_add(&info->link, &domain->devices);
1841 list_add(&info->global, &device_domain_list);
358dd8ac 1842 pdev->dev.archdata.iommu = info;
ba395927
KA		 1843 spin_unlock_irqrestore(&device_domain_lock, flags);
1844 return domain;
1845error:
1846 /* recheck it here, maybe others set it */
1847 return find_domain(pdev);
1848}
1849
2c2e2c38
FY		 1850static int iommu_identity_mapping;
1851
b213203e
DW		 1852static int iommu_domain_identity_map(struct dmar_domain *domain,
1853 unsigned long long start,
1854 unsigned long long end)
ba395927 1855{
ba395927 1856 unsigned long size;
5b6985ce 1857 unsigned long long base;
ba395927
KA		 1858
1859 /* The address might not be aligned */
5b6985ce 1860 base = start & PAGE_MASK;
ba395927 1861 size = end - base;
5b6985ce 1862 size = PAGE_ALIGN(size);
ba395927
KA		 1863 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1864 IOVA_PFN(base + size) - 1)) {
1865 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1866 return -ENOMEM;
ba395927
KA		 1867 }
1868
b213203e
DW		 1869 pr_debug("Mapping reserved region %lx@%llx for domain %d\n",
1870 size, base, domain->id);
ba395927
KA		 1871 /*
1872 * RMRR range might have overlap with physical memory range,
1873 * clear it first
1874 */
1875 dma_pte_clear_range(domain, base, base + size);
1876
b213203e
DW		 1877 return domain_page_mapping(domain, base, base, size,
1878 DMA_PTE_READ|DMA_PTE_WRITE);
1879}
1880
1881static int iommu_prepare_identity_map(struct pci_dev *pdev,
1882 unsigned long long start,
1883 unsigned long long end)
1884{
1885 struct dmar_domain *domain;
1886 int ret;
1887
1888 printk(KERN_INFO
1889 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1890 pci_name(pdev), start, end);
1891
1892 if (iommu_identity_mapping)
1893 domain = si_domain;
1894 else
1895 /* page table init */
1896 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1897 if (!domain)
1898 return -ENOMEM;
1899
1900 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 1901 if (ret)
1902 goto error;
1903
1904 /* context entry init */
4ed0d3e6 1905 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 1906 if (ret)
1907 goto error;
1908
1909 return 0;
1910
1911 error:
ba395927
KA		 1912 domain_exit(domain);
1913 return ret;
ba395927
KA		 1914}
1915
1916static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1917 struct pci_dev *pdev)
1918{
358dd8ac 1919 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 1920 return 0;
1921 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1922 rmrr->end_address + 1);
1923}
1924
d52d53b8
YL		 1925struct iommu_prepare_data {
1926 struct pci_dev *pdev;
1927 int ret;
1928};
1929
1930static int __init iommu_prepare_work_fn(unsigned long start_pfn,
1931 unsigned long end_pfn, void *datax)
1932{
1933 struct iommu_prepare_data *data;
1934
1935 data = (struct iommu_prepare_data *)datax;
1936
1937 data->ret = iommu_prepare_identity_map(data->pdev,
1938 start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
1939 return data->ret;
1940
1941}
1942
1943static int __init iommu_prepare_with_active_regions(struct pci_dev *pdev)
1944{
1945 int nid;
1946 struct iommu_prepare_data data;
1947
1948 data.pdev = pdev;
1949 data.ret = 0;
1950
1951 for_each_online_node(nid) {
1952 work_with_active_regions(nid, iommu_prepare_work_fn, &data);
1953 if (data.ret)
1954 return data.ret;
1955 }
1956 return data.ret;
1957}
1958
7e25a242 1959#ifdef CONFIG_DMAR_GFX_WA
e820482c
KA		 1960static void __init iommu_prepare_gfx_mapping(void)
1961{
1962 struct pci_dev *pdev = NULL;
e820482c
KA		 1963 int ret;
1964
1965 for_each_pci_dev(pdev) {
358dd8ac 1966 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO ||
e820482c
KA		 1967 !IS_GFX_DEVICE(pdev))
1968 continue;
1969 printk(KERN_INFO "IOMMU: gfx device %s 1-1 mapping\n",
1970 pci_name(pdev));
d52d53b8
YL		 1971 ret = iommu_prepare_with_active_regions(pdev);
1972 if (ret)
1973 printk(KERN_ERR "IOMMU: mapping reserved region failed\n");
e820482c
KA		 1974 }
1975}
2abd7e16
MM		 1976#else /* !CONFIG_DMAR_GFX_WA */
1977static inline void iommu_prepare_gfx_mapping(void)
1978{
1979 return;
1980}
e820482c
KA		 1981#endif
1982
49a0429e
KA		 1983#ifdef CONFIG_DMAR_FLOPPY_WA
1984static inline void iommu_prepare_isa(void)
1985{
1986 struct pci_dev *pdev;
1987 int ret;
1988
1989 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1990 if (!pdev)
1991 return;
1992
1993 printk(KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
1994 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1995
1996 if (ret)
1c35b8e5 1997 printk(KERN_ERR "IOMMU: Failed to create 0-64M identity map, "
49a0429e
KA		 1998 "floppy might not work\n");
1999
2000}
2001#else
2002static inline void iommu_prepare_isa(void)
2003{
2004 return;
2005}
2006#endif /* !CONFIG_DMAR_FLPY_WA */
2007
4ed0d3e6
FY		 2008/* Initialize each context entry as pass through.*/
2009static int __init init_context_pass_through(void)
2010{
2011 struct pci_dev *pdev = NULL;
2012 struct dmar_domain *domain;
2013 int ret;
2014
2015 for_each_pci_dev(pdev) {
2016 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2017 ret = domain_context_mapping(domain, pdev,
2018 CONTEXT_TT_PASS_THROUGH);
2019 if (ret)
2020 return ret;
2021 }
2022 return 0;
2023}
2024
2c2e2c38
FY		 2025static int md_domain_init(struct dmar_domain *domain, int guest_width);
2026static int si_domain_init(void)
2027{
2028 struct dmar_drhd_unit *drhd;
2029 struct intel_iommu *iommu;
2030 int ret = 0;
2031
2032 si_domain = alloc_domain();
2033 if (!si_domain)
2034 return -EFAULT;
2035
2036
2037 for_each_active_iommu(iommu, drhd) {
2038 ret = iommu_attach_domain(si_domain, iommu);
2039 if (ret) {
2040 domain_exit(si_domain);
2041 return -EFAULT;
2042 }
2043 }
2044
2045 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2046 domain_exit(si_domain);
2047 return -EFAULT;
2048 }
2049
2050 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2051
2052 return 0;
2053}
2054
2055static void domain_remove_one_dev_info(struct dmar_domain *domain,
2056 struct pci_dev *pdev);
2057static int identity_mapping(struct pci_dev *pdev)
2058{
2059 struct device_domain_info *info;
2060
2061 if (likely(!iommu_identity_mapping))
2062 return 0;
2063
2064
2065 list_for_each_entry(info, &si_domain->devices, link)
2066 if (info->dev == pdev)
2067 return 1;
2068 return 0;
2069}
2070
2071static int domain_add_dev_info(struct dmar_domain *domain,
2072 struct pci_dev *pdev)
2073{
2074 struct device_domain_info *info;
2075 unsigned long flags;
2076
2077 info = alloc_devinfo_mem();
2078 if (!info)
2079 return -ENOMEM;
2080
2081 info->segment = pci_domain_nr(pdev->bus);
2082 info->bus = pdev->bus->number;
2083 info->devfn = pdev->devfn;
2084 info->dev = pdev;
2085 info->domain = domain;
2086
2087 spin_lock_irqsave(&device_domain_lock, flags);
2088 list_add(&info->link, &domain->devices);
2089 list_add(&info->global, &device_domain_list);
2090 pdev->dev.archdata.iommu = info;
2091 spin_unlock_irqrestore(&device_domain_lock, flags);
2092
2093 return 0;
2094}
2095
2096static int iommu_prepare_static_identity_mapping(void)
2097{
2c2e2c38
FY		 2098 struct pci_dev *pdev = NULL;
2099 int ret;
2100
2101 ret = si_domain_init();
2102 if (ret)
2103 return -EFAULT;
2104
2105 printk(KERN_INFO "IOMMU: Setting identity map:\n");
2106 for_each_pci_dev(pdev) {
7e25a242
CW		 2107 ret = iommu_prepare_with_active_regions(pdev);
2108 if (ret) {
2109 printk(KERN_INFO "1:1 mapping to one domain failed.\n");
2110 return -EFAULT;
2c2e2c38
FY		 2111 }
2112 ret = domain_add_dev_info(si_domain, pdev);
2113 if (ret)
2114 return ret;
2115 }
2116
2117 return 0;
2118}
2119
2120int __init init_dmars(void)
ba395927
KA		 2121{
2122 struct dmar_drhd_unit *drhd;
2123 struct dmar_rmrr_unit *rmrr;
2124 struct pci_dev *pdev;
2125 struct intel_iommu *iommu;
9d783ba0 2126 int i, ret;
4ed0d3e6 2127 int pass_through = 1;
ba395927 2128
2c2e2c38
FY		 2129 /*
2130 * In case pass through can not be enabled, iommu tries to use identity
2131 * mapping.
2132 */
2133 if (iommu_pass_through)
2134 iommu_identity_mapping = 1;
2135
ba395927
KA		 2136 /*
2137 * for each drhd
2138 * allocate root
2139 * initialize and program root entry to not present
2140 * endfor
2141 */
2142 for_each_drhd_unit(drhd) {
5e0d2a6f 2143 g_num_of_iommus++;
2144 /*
2145 * lock not needed as this is only incremented in the single
2146 * threaded kernel __init code path all other access are read
2147 * only
2148 */
2149 }
2150
d9630fe9
WH		 2151 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2152 GFP_KERNEL);
2153 if (!g_iommus) {
2154 printk(KERN_ERR "Allocating global iommu array failed\n");
2155 ret = -ENOMEM;
2156 goto error;
2157 }
2158
80b20dd8 2159 deferred_flush = kzalloc(g_num_of_iommus *
2160 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2161 if (!deferred_flush) {
d9630fe9 2162 kfree(g_iommus);
5e0d2a6f 2163 ret = -ENOMEM;
2164 goto error;
2165 }
2166
5e0d2a6f 2167 for_each_drhd_unit(drhd) {
2168 if (drhd->ignored)
2169 continue;
1886e8a9
SS		 2170
2171 iommu = drhd->iommu;
d9630fe9 2172 g_iommus[iommu->seq_id] = iommu;
ba395927 2173
e61d98d8
SS		 2174 ret = iommu_init_domains(iommu);
2175 if (ret)
2176 goto error;
2177
ba395927
KA		 2178 /*
2179 * TBD:
2180 * we could share the same root & context tables
2181 * amoung all IOMMU's. Need to Split it later.
2182 */
2183 ret = iommu_alloc_root_entry(iommu);
2184 if (ret) {
2185 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2186 goto error;
2187 }
4ed0d3e6
FY		 2188 if (!ecap_pass_through(iommu->ecap))
2189 pass_through = 0;
ba395927 2190 }
4ed0d3e6
FY		 2191 if (iommu_pass_through)
2192 if (!pass_through) {
2193 printk(KERN_INFO
2194 "Pass Through is not supported by hardware.\n");
2195 iommu_pass_through = 0;
2196 }
ba395927 2197
1531a6a6
SS		 2198 /*
2199 * Start from the sane iommu hardware state.
2200 */
a77b67d4
YS		 2201 for_each_drhd_unit(drhd) {
2202 if (drhd->ignored)
2203 continue;
2204
2205 iommu = drhd->iommu;
1531a6a6
SS		 2206
2207 /*
2208 * If the queued invalidation is already initialized by us
2209 * (for example, while enabling interrupt-remapping) then
2210 * we got the things already rolling from a sane state.
2211 */
2212 if (iommu->qi)
2213 continue;
2214
2215 /*
2216 * Clear any previous faults.
2217 */
2218 dmar_fault(-1, iommu);
2219 /*
2220 * Disable queued invalidation if supported and already enabled
2221 * before OS handover.
2222 */
2223 dmar_disable_qi(iommu);
2224 }
2225
2226 for_each_drhd_unit(drhd) {
2227 if (drhd->ignored)
2228 continue;
2229
2230 iommu = drhd->iommu;
2231
a77b67d4
YS		 2232 if (dmar_enable_qi(iommu)) {
2233 /*
2234 * Queued Invalidate not enabled, use Register Based
2235 * Invalidate
2236 */
2237 iommu->flush.flush_context = __iommu_flush_context;
2238 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2239 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2240 "invalidation\n",
2241 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2242 } else {
2243 iommu->flush.flush_context = qi_flush_context;
2244 iommu->flush.flush_iotlb = qi_flush_iotlb;
2245 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2246 "invalidation\n",
2247 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2248 }
2249 }
2250
ba395927 2251 /*
4ed0d3e6
FY		 2252 * If pass through is set and enabled, context entries of all pci
2253 * devices are intialized by pass through translation type.
ba395927 2254 */
4ed0d3e6
FY		 2255 if (iommu_pass_through) {
2256 ret = init_context_pass_through();
2257 if (ret) {
2258 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2259 iommu_pass_through = 0;
ba395927
KA		 2260 }
2261 }
2262
ba395927 2263 /*
4ed0d3e6 2264 * If pass through is not set or not enabled, setup context entries for
2c2e2c38
FY		 2265 * identity mappings for rmrr, gfx, and isa and may fall back to static
2266 * identity mapping if iommu_identity_mapping is set.
ba395927 2267 */
4ed0d3e6 2268 if (!iommu_pass_through) {
2c2e2c38
FY		 2269 if (iommu_identity_mapping)
2270 iommu_prepare_static_identity_mapping();
4ed0d3e6
FY		 2271 /*
2272 * For each rmrr
2273 * for each dev attached to rmrr
2274 * do
2275 * locate drhd for dev, alloc domain for dev
2276 * allocate free domain
2277 * allocate page table entries for rmrr
2278 * if context not allocated for bus
2279 * allocate and init context
2280 * set present in root table for this bus
2281 * init context with domain, translation etc
2282 * endfor
2283 * endfor
2284 */
2c2e2c38 2285 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
4ed0d3e6
FY		 2286 for_each_rmrr_units(rmrr) {
2287 for (i = 0; i < rmrr->devices_cnt; i++) {
2288 pdev = rmrr->devices[i];
2289 /*
2290 * some BIOS lists non-exist devices in DMAR
2291 * table.
2292 */
2293 if (!pdev)
2294 continue;
2295 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2296 if (ret)
2297 printk(KERN_ERR
ba395927 2298 "IOMMU: mapping reserved region failed\n");
4ed0d3e6 2299 }
ba395927 2300 }
ba395927 2301
4ed0d3e6 2302 iommu_prepare_gfx_mapping();
e820482c 2303
4ed0d3e6
FY		 2304 iommu_prepare_isa();
2305 }
49a0429e 2306
ba395927
KA		 2307 /*
2308 * for each drhd
2309 * enable fault log
2310 * global invalidate context cache
2311 * global invalidate iotlb
2312 * enable translation
2313 */
2314 for_each_drhd_unit(drhd) {
2315 if (drhd->ignored)
2316 continue;
2317 iommu = drhd->iommu;
ba395927
KA		 2318
2319 iommu_flush_write_buffer(iommu);
2320
3460a6d9
KA		 2321 ret = dmar_set_interrupt(iommu);
2322 if (ret)
2323 goto error;
2324
ba395927
KA		 2325 iommu_set_root_entry(iommu);
2326
4c25a2c1 2327 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2328 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2329 iommu_disable_protect_mem_regions(iommu);
2330
ba395927
KA		 2331 ret = iommu_enable_translation(iommu);
2332 if (ret)
2333 goto error;
2334 }
2335
2336 return 0;
2337error:
2338 for_each_drhd_unit(drhd) {
2339 if (drhd->ignored)
2340 continue;
2341 iommu = drhd->iommu;
2342 free_iommu(iommu);
2343 }
d9630fe9 2344 kfree(g_iommus);
ba395927
KA		 2345 return ret;
2346}
2347
2348static inline u64 aligned_size(u64 host_addr, size_t size)
2349{
2350 u64 addr;
5b6985ce
FY		 2351 addr = (host_addr & (~PAGE_MASK)) + size;
2352 return PAGE_ALIGN(addr);
ba395927
KA		 2353}
2354
2355struct iova *
f76aec76 2356iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
ba395927 2357{
ba395927
KA		 2358 struct iova *piova;
2359
2360 /* Make sure it's in range */
ba395927 2361 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
f76aec76 2362 if (!size || (IOVA_START_ADDR + size > end))
ba395927
KA		 2363 return NULL;
2364
2365 piova = alloc_iova(&domain->iovad,
5b6985ce 2366 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
ba395927
KA		 2367 return piova;
2368}
2369
f76aec76
KA		 2370static struct iova *
2371__intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
bb9e6d65 2372 size_t size, u64 dma_mask)
ba395927 2373{
ba395927 2374 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2375 struct iova *iova = NULL;
ba395927 2376
284901a9 2377 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
bb9e6d65
FT		 2378 iova = iommu_alloc_iova(domain, size, dma_mask);
2379 else {
ba395927
KA		 2380 /*
2381 * First try to allocate an io virtual address in
284901a9 2382 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2383 * from higher range
ba395927 2384 */
284901a9 2385 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
ba395927 2386 if (!iova)
bb9e6d65 2387 iova = iommu_alloc_iova(domain, size, dma_mask);
ba395927
KA		 2388 }
2389
2390 if (!iova) {
2391 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
f76aec76
KA		 2392 return NULL;
2393 }
2394
2395 return iova;
2396}
2397
2398static struct dmar_domain *
2399get_valid_domain_for_dev(struct pci_dev *pdev)
2400{
2401 struct dmar_domain *domain;
2402 int ret;
2403
2404 domain = get_domain_for_dev(pdev,
2405 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2406 if (!domain) {
2407 printk(KERN_ERR
2408 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2409 return NULL;
ba395927
KA		 2410 }
2411
2412 /* make sure context mapping is ok */
5331fe6f 2413 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2414 ret = domain_context_mapping(domain, pdev,
2415 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2416 if (ret) {
2417 printk(KERN_ERR
2418 "Domain context map for %s failed",
2419 pci_name(pdev));
4fe05bbc 2420 return NULL;
f76aec76 2421 }
ba395927
KA		 2422 }
2423
f76aec76
KA		 2424 return domain;
2425}
2426
2c2e2c38
FY		 2427static int iommu_dummy(struct pci_dev *pdev)
2428{
2429 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2430}
2431
2432/* Check if the pdev needs to go through non-identity map and unmap process.*/
2433static int iommu_no_mapping(struct pci_dev *pdev)
2434{
2435 int found;
2436
2437 if (!iommu_identity_mapping)
2438 return iommu_dummy(pdev);
2439
2440 found = identity_mapping(pdev);
2441 if (found) {
2442 if (pdev->dma_mask > DMA_BIT_MASK(32))
2443 return 1;
2444 else {
2445 /*
2446 * 32 bit DMA is removed from si_domain and fall back
2447 * to non-identity mapping.
2448 */
2449 domain_remove_one_dev_info(si_domain, pdev);
2450 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2451 pci_name(pdev));
2452 return 0;
2453 }
2454 } else {
2455 /*
2456 * In case of a detached 64 bit DMA device from vm, the device
2457 * is put into si_domain for identity mapping.
2458 */
2459 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2460 int ret;
2461 ret = domain_add_dev_info(si_domain, pdev);
2462 if (!ret) {
2463 printk(KERN_INFO "64bit %s uses identity mapping\n",
2464 pci_name(pdev));
2465 return 1;
2466 }
2467 }
2468 }
2469
2470 return iommu_dummy(pdev);
2471}
2472
bb9e6d65
FT		 2473static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2474 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2475{
2476 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2477 struct dmar_domain *domain;
5b6985ce 2478 phys_addr_t start_paddr;
f76aec76
KA		 2479 struct iova *iova;
2480 int prot = 0;
6865f0d1 2481 int ret;
8c11e798 2482 struct intel_iommu *iommu;
f76aec76
KA		 2483
2484 BUG_ON(dir == DMA_NONE);
2c2e2c38
FY		 2485
2486 if (iommu_no_mapping(pdev))
6865f0d1 2487 return paddr;
f76aec76
KA		 2488
2489 domain = get_valid_domain_for_dev(pdev);
2490 if (!domain)
2491 return 0;
2492
8c11e798 2493 iommu = domain_get_iommu(domain);
6865f0d1 2494 size = aligned_size((u64)paddr, size);
f76aec76 2495
bb9e6d65 2496 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
f76aec76
KA		 2497 if (!iova)
2498 goto error;
2499
5b6985ce 2500 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
f76aec76 2501
ba395927
KA		 2502 /*
2503 * Check if DMAR supports zero-length reads on write only
2504 * mappings..
2505 */
2506 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2507 !cap_zlr(iommu->cap))
ba395927
KA		 2508 prot |= DMA_PTE_READ;
2509 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2510 prot |= DMA_PTE_WRITE;
2511 /*
6865f0d1 2512 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2513 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2514 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2515 * is not a big problem
2516 */
6865f0d1 2517 ret = domain_page_mapping(domain, start_paddr,
fd18de50
DW		 2518 ((u64)paddr) & PHYSICAL_PAGE_MASK,
2519 size, prot);
ba395927
KA		 2520 if (ret)
2521 goto error;
2522
1f0ef2aa
DW		 2523 /* it's a non-present to present mapping. Only flush if caching mode */
2524 if (cap_caching_mode(iommu->cap))
2525 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2526 size >> VTD_PAGE_SHIFT);
2527 else
8c11e798 2528 iommu_flush_write_buffer(iommu);
f76aec76 2529
5b6985ce 2530 return start_paddr + ((u64)paddr & (~PAGE_MASK));
ba395927 2531
ba395927 2532error:
f76aec76
KA		 2533 if (iova)
2534 __free_iova(&domain->iovad, iova);
4cf2e75d 2535 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2536 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2537 return 0;
2538}
2539
ffbbef5c
FT		 2540static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2541 unsigned long offset, size_t size,
2542 enum dma_data_direction dir,
2543 struct dma_attrs *attrs)
bb9e6d65 2544{
ffbbef5c
FT		 2545 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2546 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2547}
2548
5e0d2a6f 2549static void flush_unmaps(void)
2550{
80b20dd8 2551 int i, j;
5e0d2a6f 2552
5e0d2a6f 2553 timer_on = 0;
2554
2555 /* just flush them all */
2556 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2557 struct intel_iommu *iommu = g_iommus[i];
2558 if (!iommu)
2559 continue;
c42d9f32 2560
9dd2fe89
YZ		 2561 if (!deferred_flush[i].next)
2562 continue;
2563
2564 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2565 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2566 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2567 unsigned long mask;
2568 struct iova *iova = deferred_flush[i].iova[j];
2569
2570 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2571 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2572 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2573 iova->pfn_lo << PAGE_SHIFT, mask);
2574 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2575 }
9dd2fe89 2576 deferred_flush[i].next = 0;
5e0d2a6f 2577 }
2578
5e0d2a6f 2579 list_size = 0;
5e0d2a6f 2580}
2581
2582static void flush_unmaps_timeout(unsigned long data)
2583{
80b20dd8 2584 unsigned long flags;
2585
2586 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2587 flush_unmaps();
80b20dd8 2588 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2589}
2590
2591static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2592{
2593 unsigned long flags;
80b20dd8 2594 int next, iommu_id;
8c11e798 2595 struct intel_iommu *iommu;
5e0d2a6f 2596
2597 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2598 if (list_size == HIGH_WATER_MARK)
2599 flush_unmaps();
2600
8c11e798
WH		 2601 iommu = domain_get_iommu(dom);
2602 iommu_id = iommu->seq_id;
c42d9f32 2603
80b20dd8 2604 next = deferred_flush[iommu_id].next;
2605 deferred_flush[iommu_id].domain[next] = dom;
2606 deferred_flush[iommu_id].iova[next] = iova;
2607 deferred_flush[iommu_id].next++;
5e0d2a6f 2608
2609 if (!timer_on) {
2610 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2611 timer_on = 1;
2612 }
2613 list_size++;
2614 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2615}
2616
ffbbef5c
FT		 2617static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2618 size_t size, enum dma_data_direction dir,
2619 struct dma_attrs *attrs)
ba395927 2620{
ba395927 2621 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76
KA		 2622 struct dmar_domain *domain;
2623 unsigned long start_addr;
ba395927 2624 struct iova *iova;
8c11e798 2625 struct intel_iommu *iommu;
ba395927 2626
2c2e2c38 2627 if (iommu_no_mapping(pdev))
f76aec76 2628 return;
2c2e2c38 2629
ba395927
KA		 2630 domain = find_domain(pdev);
2631 BUG_ON(!domain);
2632
8c11e798
WH		 2633 iommu = domain_get_iommu(domain);
2634
ba395927 2635 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
f76aec76 2636 if (!iova)
ba395927 2637 return;
ba395927 2638
5b6985ce 2639 start_addr = iova->pfn_lo << PAGE_SHIFT;
f76aec76 2640 size = aligned_size((u64)dev_addr, size);
ba395927 2641
4cf2e75d 2642 pr_debug("Device %s unmapping: %zx@%llx\n",
5b6985ce 2643 pci_name(pdev), size, (unsigned long long)start_addr);
ba395927 2644
f76aec76
KA		 2645 /* clear the whole page */
2646 dma_pte_clear_range(domain, start_addr, start_addr + size);
2647 /* free page tables */
2648 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
5e0d2a6f 2649 if (intel_iommu_strict) {
1f0ef2aa
DW		 2650 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2651 size >> VTD_PAGE_SHIFT);
5e0d2a6f 2652 /* free iova */
2653 __free_iova(&domain->iovad, iova);
2654 } else {
2655 add_unmap(domain, iova);
2656 /*
2657 * queue up the release of the unmap to save the 1/6th of the
2658 * cpu used up by the iotlb flush operation...
2659 */
5e0d2a6f 2660 }
ba395927
KA		 2661}
2662
d7ab5c46
FT		 2663static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2664 int dir)
ffbbef5c
FT		 2665{
2666 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2667}
2668
d7ab5c46
FT		 2669static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2670 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2671{
2672 void *vaddr;
2673 int order;
2674
5b6985ce 2675 size = PAGE_ALIGN(size);
ba395927
KA		 2676 order = get_order(size);
2677 flags &= ~(GFP_DMA | GFP_DMA32);
2678
2679 vaddr = (void *)__get_free_pages(flags, order);
2680 if (!vaddr)
2681 return NULL;
2682 memset(vaddr, 0, size);
2683
bb9e6d65
FT		 2684 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2685 DMA_BIDIRECTIONAL,
2686 hwdev->coherent_dma_mask);
ba395927
KA		 2687 if (*dma_handle)
2688 return vaddr;
2689 free_pages((unsigned long)vaddr, order);
2690 return NULL;
2691}
2692
d7ab5c46
FT		 2693static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2694 dma_addr_t dma_handle)
ba395927
KA		 2695{
2696 int order;
2697
5b6985ce 2698 size = PAGE_ALIGN(size);
ba395927
KA		 2699 order = get_order(size);
2700
2701 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2702 free_pages((unsigned long)vaddr, order);
2703}
2704
d7ab5c46
FT		 2705static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2706 int nelems, enum dma_data_direction dir,
2707 struct dma_attrs *attrs)
ba395927
KA		 2708{
2709 int i;
2710 struct pci_dev *pdev = to_pci_dev(hwdev);
2711 struct dmar_domain *domain;
f76aec76
KA		 2712 unsigned long start_addr;
2713 struct iova *iova;
2714 size_t size = 0;
4cf2e75d 2715 phys_addr_t addr;
c03ab37c 2716 struct scatterlist *sg;
8c11e798 2717 struct intel_iommu *iommu;
ba395927 2718
2c2e2c38 2719 if (iommu_no_mapping(pdev))
ba395927
KA		 2720 return;
2721
2722 domain = find_domain(pdev);
8c11e798
WH		 2723 BUG_ON(!domain);
2724
2725 iommu = domain_get_iommu(domain);
ba395927 2726
c03ab37c 2727 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
f76aec76
KA		 2728 if (!iova)
2729 return;
c03ab37c 2730 for_each_sg(sglist, sg, nelems, i) {
4cf2e75d 2731 addr = page_to_phys(sg_page(sg)) + sg->offset;
f76aec76
KA		 2732 size += aligned_size((u64)addr, sg->length);
2733 }
2734
5b6985ce 2735 start_addr = iova->pfn_lo << PAGE_SHIFT;
f76aec76
KA		 2736
2737 /* clear the whole page */
2738 dma_pte_clear_range(domain, start_addr, start_addr + size);
2739 /* free page tables */
2740 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2741
1f0ef2aa
DW		 2742 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2743 size >> VTD_PAGE_SHIFT);
f76aec76
KA		 2744
2745 /* free iova */
2746 __free_iova(&domain->iovad, iova);
ba395927
KA		 2747}
2748
ba395927 2749static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2750 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2751{
2752 int i;
c03ab37c 2753 struct scatterlist *sg;
ba395927 2754
c03ab37c 2755 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2756 BUG_ON(!sg_page(sg));
4cf2e75d 2757 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2758 sg->dma_length = sg->length;
ba395927
KA		 2759 }
2760 return nelems;
2761}
2762
d7ab5c46
FT		 2763static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2764 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2765{
4cf2e75d 2766 phys_addr_t addr;
ba395927 2767 int i;
ba395927
KA		 2768 struct pci_dev *pdev = to_pci_dev(hwdev);
2769 struct dmar_domain *domain;
f76aec76
KA		 2770 size_t size = 0;
2771 int prot = 0;
2772 size_t offset = 0;
2773 struct iova *iova = NULL;
2774 int ret;
c03ab37c 2775 struct scatterlist *sg;
f76aec76 2776 unsigned long start_addr;
8c11e798 2777 struct intel_iommu *iommu;
ba395927
KA		 2778
2779 BUG_ON(dir == DMA_NONE);
2c2e2c38 2780 if (iommu_no_mapping(pdev))
c03ab37c 2781 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2782
f76aec76
KA		 2783 domain = get_valid_domain_for_dev(pdev);
2784 if (!domain)
2785 return 0;
2786
8c11e798
WH		 2787 iommu = domain_get_iommu(domain);
2788
c03ab37c 2789 for_each_sg(sglist, sg, nelems, i) {
4cf2e75d 2790 addr = page_to_phys(sg_page(sg)) + sg->offset;
f76aec76
KA		 2791 size += aligned_size((u64)addr, sg->length);
2792 }
2793
bb9e6d65 2794 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
f76aec76 2795 if (!iova) {
c03ab37c 2796 sglist->dma_length = 0;
f76aec76
KA		 2797 return 0;
2798 }
2799
2800 /*
2801 * Check if DMAR supports zero-length reads on write only
2802 * mappings..
2803 */
2804 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2805 !cap_zlr(iommu->cap))
f76aec76
KA		 2806 prot |= DMA_PTE_READ;
2807 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2808 prot |= DMA_PTE_WRITE;
2809
5b6985ce 2810 start_addr = iova->pfn_lo << PAGE_SHIFT;
f76aec76 2811 offset = 0;
c03ab37c 2812 for_each_sg(sglist, sg, nelems, i) {
4cf2e75d 2813 addr = page_to_phys(sg_page(sg)) + sg->offset;
f76aec76
KA		 2814 size = aligned_size((u64)addr, sg->length);
2815 ret = domain_page_mapping(domain, start_addr + offset,
fd18de50
DW		 2816 ((u64)addr) & PHYSICAL_PAGE_MASK,
2817 size, prot);
f76aec76
KA		 2818 if (ret) {
2819 /* clear the page */
2820 dma_pte_clear_range(domain, start_addr,
2821 start_addr + offset);
2822 /* free page tables */
2823 dma_pte_free_pagetable(domain, start_addr,
2824 start_addr + offset);
2825 /* free iova */
2826 __free_iova(&domain->iovad, iova);
ba395927
KA		 2827 return 0;
2828 }
f76aec76 2829 sg->dma_address = start_addr + offset +
5b6985ce 2830 ((u64)addr & (~PAGE_MASK));
ba395927 2831 sg->dma_length = sg->length;
f76aec76 2832 offset += size;
ba395927
KA		 2833 }
2834
1f0ef2aa
DW		 2835 /* it's a non-present to present mapping. Only flush if caching mode */
2836 if (cap_caching_mode(iommu->cap))
2837 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2838 offset >> VTD_PAGE_SHIFT);
2839 else
8c11e798 2840 iommu_flush_write_buffer(iommu);
1f0ef2aa 2841
ba395927
KA		 2842 return nelems;
2843}
2844
dfb805e8
FT		 2845static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2846{
2847 return !dma_addr;
2848}
2849
160c1d8e 2850struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2851 .alloc_coherent = intel_alloc_coherent,
2852 .free_coherent = intel_free_coherent,
ba395927
KA		 2853 .map_sg = intel_map_sg,
2854 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2855 .map_page = intel_map_page,
2856 .unmap_page = intel_unmap_page,
dfb805e8 2857 .mapping_error = intel_mapping_error,
ba395927
KA		 2858};
2859
2860static inline int iommu_domain_cache_init(void)
2861{
2862 int ret = 0;
2863
2864 iommu_domain_cache = kmem_cache_create("iommu_domain",
2865 sizeof(struct dmar_domain),
2866 0,
2867 SLAB_HWCACHE_ALIGN,
2868
2869 NULL);
2870 if (!iommu_domain_cache) {
2871 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2872 ret = -ENOMEM;
2873 }
2874
2875 return ret;
2876}
2877
2878static inline int iommu_devinfo_cache_init(void)
2879{
2880 int ret = 0;
2881
2882 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2883 sizeof(struct device_domain_info),
2884 0,
2885 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2886 NULL);
2887 if (!iommu_devinfo_cache) {
2888 printk(KERN_ERR "Couldn't create devinfo cache\n");
2889 ret = -ENOMEM;
2890 }
2891
2892 return ret;
2893}
2894
2895static inline int iommu_iova_cache_init(void)
2896{
2897 int ret = 0;
2898
2899 iommu_iova_cache = kmem_cache_create("iommu_iova",
2900 sizeof(struct iova),
2901 0,
2902 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2903 NULL);
2904 if (!iommu_iova_cache) {
2905 printk(KERN_ERR "Couldn't create iova cache\n");
2906 ret = -ENOMEM;
2907 }
2908
2909 return ret;
2910}
2911
2912static int __init iommu_init_mempool(void)
2913{
2914 int ret;
2915 ret = iommu_iova_cache_init();
2916 if (ret)
2917 return ret;
2918
2919 ret = iommu_domain_cache_init();
2920 if (ret)
2921 goto domain_error;
2922
2923 ret = iommu_devinfo_cache_init();
2924 if (!ret)
2925 return ret;
2926
2927 kmem_cache_destroy(iommu_domain_cache);
2928domain_error:
2929 kmem_cache_destroy(iommu_iova_cache);
2930
2931 return -ENOMEM;
2932}
2933
2934static void __init iommu_exit_mempool(void)
2935{
2936 kmem_cache_destroy(iommu_devinfo_cache);
2937 kmem_cache_destroy(iommu_domain_cache);
2938 kmem_cache_destroy(iommu_iova_cache);
2939
2940}
2941
ba395927
KA		 2942static void __init init_no_remapping_devices(void)
2943{
2944 struct dmar_drhd_unit *drhd;
2945
2946 for_each_drhd_unit(drhd) {
2947 if (!drhd->include_all) {
2948 int i;
2949 for (i = 0; i < drhd->devices_cnt; i++)
2950 if (drhd->devices[i] != NULL)
2951 break;
2952 /* ignore DMAR unit if no pci devices exist */
2953 if (i == drhd->devices_cnt)
2954 drhd->ignored = 1;
2955 }
2956 }
2957
2958 if (dmar_map_gfx)
2959 return;
2960
2961 for_each_drhd_unit(drhd) {
2962 int i;
2963 if (drhd->ignored || drhd->include_all)
2964 continue;
2965
2966 for (i = 0; i < drhd->devices_cnt; i++)
2967 if (drhd->devices[i] &&
2968 !IS_GFX_DEVICE(drhd->devices[i]))
2969 break;
2970
2971 if (i < drhd->devices_cnt)
2972 continue;
2973
2974 /* bypass IOMMU if it is just for gfx devices */
2975 drhd->ignored = 1;
2976 for (i = 0; i < drhd->devices_cnt; i++) {
2977 if (!drhd->devices[i])
2978 continue;
358dd8ac 2979 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 2980 }
2981 }
2982}
2983
f59c7b69
FY		 2984#ifdef CONFIG_SUSPEND
2985static int init_iommu_hw(void)
2986{
2987 struct dmar_drhd_unit *drhd;
2988 struct intel_iommu *iommu = NULL;
2989
2990 for_each_active_iommu(iommu, drhd)
2991 if (iommu->qi)
2992 dmar_reenable_qi(iommu);
2993
2994 for_each_active_iommu(iommu, drhd) {
2995 iommu_flush_write_buffer(iommu);
2996
2997 iommu_set_root_entry(iommu);
2998
2999 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3000 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3001 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3002 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3003 iommu_disable_protect_mem_regions(iommu);
3004 iommu_enable_translation(iommu);
3005 }
3006
3007 return 0;
3008}
3009
3010static void iommu_flush_all(void)
3011{
3012 struct dmar_drhd_unit *drhd;
3013 struct intel_iommu *iommu;
3014
3015 for_each_active_iommu(iommu, drhd) {
3016 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3017 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3018 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3019 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3020 }
3021}
3022
3023static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3024{
3025 struct dmar_drhd_unit *drhd;
3026 struct intel_iommu *iommu = NULL;
3027 unsigned long flag;
3028
3029 for_each_active_iommu(iommu, drhd) {
3030 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3031 GFP_ATOMIC);
3032 if (!iommu->iommu_state)
3033 goto nomem;
3034 }
3035
3036 iommu_flush_all();
3037
3038 for_each_active_iommu(iommu, drhd) {
3039 iommu_disable_translation(iommu);
3040
3041 spin_lock_irqsave(&iommu->register_lock, flag);
3042
3043 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3044 readl(iommu->reg + DMAR_FECTL_REG);
3045 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3046 readl(iommu->reg + DMAR_FEDATA_REG);
3047 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3048 readl(iommu->reg + DMAR_FEADDR_REG);
3049 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3050 readl(iommu->reg + DMAR_FEUADDR_REG);
3051
3052 spin_unlock_irqrestore(&iommu->register_lock, flag);
3053 }
3054 return 0;
3055
3056nomem:
3057 for_each_active_iommu(iommu, drhd)
3058 kfree(iommu->iommu_state);
3059
3060 return -ENOMEM;
3061}
3062
3063static int iommu_resume(struct sys_device *dev)
3064{
3065 struct dmar_drhd_unit *drhd;
3066 struct intel_iommu *iommu = NULL;
3067 unsigned long flag;
3068
3069 if (init_iommu_hw()) {
3070 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3071 return -EIO;
3072 }
3073
3074 for_each_active_iommu(iommu, drhd) {
3075
3076 spin_lock_irqsave(&iommu->register_lock, flag);
3077
3078 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3079 iommu->reg + DMAR_FECTL_REG);
3080 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3081 iommu->reg + DMAR_FEDATA_REG);
3082 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3083 iommu->reg + DMAR_FEADDR_REG);
3084 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3085 iommu->reg + DMAR_FEUADDR_REG);
3086
3087 spin_unlock_irqrestore(&iommu->register_lock, flag);
3088 }
3089
3090 for_each_active_iommu(iommu, drhd)
3091 kfree(iommu->iommu_state);
3092
3093 return 0;
3094}
3095
3096static struct sysdev_class iommu_sysclass = {
3097 .name = "iommu",
3098 .resume = iommu_resume,
3099 .suspend = iommu_suspend,
3100};
3101
3102static struct sys_device device_iommu = {
3103 .cls = &iommu_sysclass,
3104};
3105
3106static int __init init_iommu_sysfs(void)
3107{
3108 int error;
3109
3110 error = sysdev_class_register(&iommu_sysclass);
3111 if (error)
3112 return error;
3113
3114 error = sysdev_register(&device_iommu);
3115 if (error)
3116 sysdev_class_unregister(&iommu_sysclass);
3117
3118 return error;
3119}
3120
3121#else
3122static int __init init_iommu_sysfs(void)
3123{
3124 return 0;
3125}
3126#endif /* CONFIG_PM */
3127
ba395927
KA		 3128int __init intel_iommu_init(void)
3129{
3130 int ret = 0;
3131
ba395927
KA		 3132 if (dmar_table_init())
3133 return -ENODEV;
3134
1886e8a9
SS		 3135 if (dmar_dev_scope_init())
3136 return -ENODEV;
3137
2ae21010
SS		 3138 /*
3139 * Check the need for DMA-remapping initialization now.
3140 * Above initialization will also be used by Interrupt-remapping.
3141 */
4ed0d3e6 3142 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2ae21010
SS		 3143 return -ENODEV;
3144
ba395927
KA		 3145 iommu_init_mempool();
3146 dmar_init_reserved_ranges();
3147
3148 init_no_remapping_devices();
3149
3150 ret = init_dmars();
3151 if (ret) {
3152 printk(KERN_ERR "IOMMU: dmar init failed\n");
3153 put_iova_domain(&reserved_iova_list);
3154 iommu_exit_mempool();
3155 return ret;
3156 }
3157 printk(KERN_INFO
3158 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3159
5e0d2a6f 3160 init_timer(&unmap_timer);
ba395927 3161 force_iommu = 1;
4ed0d3e6
FY		 3162
3163 if (!iommu_pass_through) {
3164 printk(KERN_INFO
3165 "Multi-level page-table translation for DMAR.\n");
3166 dma_ops = &intel_dma_ops;
3167 } else
3168 printk(KERN_INFO
3169 "DMAR: Pass through translation for DMAR.\n");
3170
f59c7b69 3171 init_iommu_sysfs();
a8bcbb0d
JR		 3172
3173 register_iommu(&intel_iommu_ops);
3174
ba395927
KA		 3175 return 0;
3176}
e820482c 3177
3199aa6b
HW		 3178static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3179 struct pci_dev *pdev)
3180{
3181 struct pci_dev *tmp, *parent;
3182
3183 if (!iommu || !pdev)
3184 return;
3185
3186 /* dependent device detach */
3187 tmp = pci_find_upstream_pcie_bridge(pdev);
3188 /* Secondary interface's bus number and devfn 0 */
3189 if (tmp) {
3190 parent = pdev->bus->self;
3191 while (parent != tmp) {
3192 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3193 parent->devfn);
3199aa6b
HW		 3194 parent = parent->bus->self;
3195 }
3196 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3197 iommu_detach_dev(iommu,
3198 tmp->subordinate->number, 0);
3199 else /* this is a legacy PCI bridge */
276dbf99
DW		 3200 iommu_detach_dev(iommu, tmp->bus->number,
3201 tmp->devfn);
3199aa6b
HW		 3202 }
3203}
3204
2c2e2c38 3205static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3206 struct pci_dev *pdev)
3207{
3208 struct device_domain_info *info;
3209 struct intel_iommu *iommu;
3210 unsigned long flags;
3211 int found = 0;
3212 struct list_head *entry, *tmp;
3213
276dbf99
DW		 3214 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3215 pdev->devfn);
c7151a8d
WH		 3216 if (!iommu)
3217 return;
3218
3219 spin_lock_irqsave(&device_domain_lock, flags);
3220 list_for_each_safe(entry, tmp, &domain->devices) {
3221 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3222 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3223 if (info->bus == pdev->bus->number &&
3224 info->devfn == pdev->devfn) {
3225 list_del(&info->link);
3226 list_del(&info->global);
3227 if (info->dev)
3228 info->dev->dev.archdata.iommu = NULL;
3229 spin_unlock_irqrestore(&device_domain_lock, flags);
3230
93a23a72 3231 iommu_disable_dev_iotlb(info);
c7151a8d 3232 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3233 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3234 free_devinfo_mem(info);
3235
3236 spin_lock_irqsave(&device_domain_lock, flags);
3237
3238 if (found)
3239 break;
3240 else
3241 continue;
3242 }
3243
3244 /* if there is no other devices under the same iommu
3245 * owned by this domain, clear this iommu in iommu_bmp
3246 * update iommu count and coherency
3247 */
276dbf99
DW		 3248 if (iommu == device_to_iommu(info->segment, info->bus,
3249 info->devfn))
c7151a8d
WH		 3250 found = 1;
3251 }
3252
3253 if (found == 0) {
3254 unsigned long tmp_flags;
3255 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3256 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3257 domain->iommu_count--;
58c610bd 3258 domain_update_iommu_cap(domain);
c7151a8d
WH		 3259 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3260 }
3261
3262 spin_unlock_irqrestore(&device_domain_lock, flags);
3263}
3264
3265static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3266{
3267 struct device_domain_info *info;
3268 struct intel_iommu *iommu;
3269 unsigned long flags1, flags2;
3270
3271 spin_lock_irqsave(&device_domain_lock, flags1);
3272 while (!list_empty(&domain->devices)) {
3273 info = list_entry(domain->devices.next,
3274 struct device_domain_info, link);
3275 list_del(&info->link);
3276 list_del(&info->global);
3277 if (info->dev)
3278 info->dev->dev.archdata.iommu = NULL;
3279
3280 spin_unlock_irqrestore(&device_domain_lock, flags1);
3281
93a23a72 3282 iommu_disable_dev_iotlb(info);
276dbf99 3283 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3284 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3285 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3286
3287 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3288 * and capabilities
c7151a8d
WH		 3289 */
3290 spin_lock_irqsave(&domain->iommu_lock, flags2);
3291 if (test_and_clear_bit(iommu->seq_id,
3292 &domain->iommu_bmp)) {
3293 domain->iommu_count--;
58c610bd 3294 domain_update_iommu_cap(domain);
c7151a8d
WH		 3295 }
3296 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3297
3298 free_devinfo_mem(info);
3299 spin_lock_irqsave(&device_domain_lock, flags1);
3300 }
3301 spin_unlock_irqrestore(&device_domain_lock, flags1);
3302}
3303
5e98c4b1
WH		 3304/* domain id for virtual machine, it won't be set in context */
3305static unsigned long vm_domid;
3306
fe40f1e0
WH		 3307static int vm_domain_min_agaw(struct dmar_domain *domain)
3308{
3309 int i;
3310 int min_agaw = domain->agaw;
3311
3312 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3313 for (; i < g_num_of_iommus; ) {
3314 if (min_agaw > g_iommus[i]->agaw)
3315 min_agaw = g_iommus[i]->agaw;
3316
3317 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3318 }
3319
3320 return min_agaw;
3321}
3322
5e98c4b1
WH		 3323static struct dmar_domain *iommu_alloc_vm_domain(void)
3324{
3325 struct dmar_domain *domain;
3326
3327 domain = alloc_domain_mem();
3328 if (!domain)
3329 return NULL;
3330
3331 domain->id = vm_domid++;
3332 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3333 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3334
3335 return domain;
3336}
3337
2c2e2c38 3338static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3339{
3340 int adjust_width;
3341
3342 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3343 spin_lock_init(&domain->mapping_lock);
3344 spin_lock_init(&domain->iommu_lock);
3345
3346 domain_reserve_special_ranges(domain);
3347
3348 /* calculate AGAW */
3349 domain->gaw = guest_width;
3350 adjust_width = guestwidth_to_adjustwidth(guest_width);
3351 domain->agaw = width_to_agaw(adjust_width);
3352
3353 INIT_LIST_HEAD(&domain->devices);
3354
3355 domain->iommu_count = 0;
3356 domain->iommu_coherency = 0;
fe40f1e0 3357 domain->max_addr = 0;
5e98c4b1
WH		 3358
3359 /* always allocate the top pgd */
3360 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3361 if (!domain->pgd)
3362 return -ENOMEM;
3363 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3364 return 0;
3365}
3366
3367static void iommu_free_vm_domain(struct dmar_domain *domain)
3368{
3369 unsigned long flags;
3370 struct dmar_drhd_unit *drhd;
3371 struct intel_iommu *iommu;
3372 unsigned long i;
3373 unsigned long ndomains;
3374
3375 for_each_drhd_unit(drhd) {
3376 if (drhd->ignored)
3377 continue;
3378 iommu = drhd->iommu;
3379
3380 ndomains = cap_ndoms(iommu->cap);
3381 i = find_first_bit(iommu->domain_ids, ndomains);
3382 for (; i < ndomains; ) {
3383 if (iommu->domains[i] == domain) {
3384 spin_lock_irqsave(&iommu->lock, flags);
3385 clear_bit(i, iommu->domain_ids);
3386 iommu->domains[i] = NULL;
3387 spin_unlock_irqrestore(&iommu->lock, flags);
3388 break;
3389 }
3390 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3391 }
3392 }
3393}
3394
3395static void vm_domain_exit(struct dmar_domain *domain)
3396{
3397 u64 end;
3398
3399 /* Domain 0 is reserved, so dont process it */
3400 if (!domain)
3401 return;
3402
3403 vm_domain_remove_all_dev_info(domain);
3404 /* destroy iovas */
3405 put_iova_domain(&domain->iovad);
3406 end = DOMAIN_MAX_ADDR(domain->gaw);
3407 end = end & (~VTD_PAGE_MASK);
3408
3409 /* clear ptes */
3410 dma_pte_clear_range(domain, 0, end);
3411
3412 /* free page tables */
3413 dma_pte_free_pagetable(domain, 0, end);
3414
3415 iommu_free_vm_domain(domain);
3416 free_domain_mem(domain);
3417}
3418
5d450806 3419static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3420{
5d450806 3421 struct dmar_domain *dmar_domain;
38717946 3422
5d450806
JR		 3423 dmar_domain = iommu_alloc_vm_domain();
3424 if (!dmar_domain) {
38717946 3425 printk(KERN_ERR
5d450806
JR		 3426 "intel_iommu_domain_init: dmar_domain == NULL\n");
3427 return -ENOMEM;
38717946 3428 }
2c2e2c38 3429 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3430 printk(KERN_ERR
5d450806
JR		 3431 "intel_iommu_domain_init() failed\n");
3432 vm_domain_exit(dmar_domain);
3433 return -ENOMEM;
38717946 3434 }
5d450806 3435 domain->priv = dmar_domain;
faa3d6f5 3436
5d450806 3437 return 0;
38717946 3438}
38717946 3439
5d450806 3440static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3441{
5d450806
JR		 3442 struct dmar_domain *dmar_domain = domain->priv;
3443
3444 domain->priv = NULL;
3445 vm_domain_exit(dmar_domain);
38717946 3446}
38717946 3447
4c5478c9
JR		 3448static int intel_iommu_attach_device(struct iommu_domain *domain,
3449 struct device *dev)
38717946 3450{
4c5478c9
JR		 3451 struct dmar_domain *dmar_domain = domain->priv;
3452 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3453 struct intel_iommu *iommu;
3454 int addr_width;
3455 u64 end;
faa3d6f5
WH		 3456 int ret;
3457
3458 /* normally pdev is not mapped */
3459 if (unlikely(domain_context_mapped(pdev))) {
3460 struct dmar_domain *old_domain;
3461
3462 old_domain = find_domain(pdev);
3463 if (old_domain) {
2c2e2c38
FY		 3464 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3465 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3466 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3467 else
3468 domain_remove_dev_info(old_domain);
3469 }
3470 }
3471
276dbf99
DW		 3472 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3473 pdev->devfn);
fe40f1e0
WH		 3474 if (!iommu)
3475 return -ENODEV;
3476
3477 /* check if this iommu agaw is sufficient for max mapped address */
3478 addr_width = agaw_to_width(iommu->agaw);
3479 end = DOMAIN_MAX_ADDR(addr_width);
3480 end = end & VTD_PAGE_MASK;
4c5478c9 3481 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3482 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3483 "sufficient for the mapped address (%llx)\n",
4c5478c9 3484 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3485 return -EFAULT;
3486 }
3487
2c2e2c38 3488 ret = domain_add_dev_info(dmar_domain, pdev);
faa3d6f5
WH		 3489 if (ret)
3490 return ret;
3491
93a23a72 3492 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
faa3d6f5 3493 return ret;
38717946 3494}
38717946 3495
4c5478c9
JR		 3496static void intel_iommu_detach_device(struct iommu_domain *domain,
3497 struct device *dev)
38717946 3498{
4c5478c9
JR		 3499 struct dmar_domain *dmar_domain = domain->priv;
3500 struct pci_dev *pdev = to_pci_dev(dev);
3501
2c2e2c38 3502 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3503}
c7151a8d 3504
dde57a21
JR		 3505static int intel_iommu_map_range(struct iommu_domain *domain,
3506 unsigned long iova, phys_addr_t hpa,
3507 size_t size, int iommu_prot)
faa3d6f5 3508{
dde57a21 3509 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3510 u64 max_addr;
3511 int addr_width;
dde57a21 3512 int prot = 0;
faa3d6f5 3513 int ret;
fe40f1e0 3514
dde57a21
JR		 3515 if (iommu_prot & IOMMU_READ)
3516 prot |= DMA_PTE_READ;
3517 if (iommu_prot & IOMMU_WRITE)
3518 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3519 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3520 prot |= DMA_PTE_SNP;
dde57a21 3521
fe40f1e0 3522 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
dde57a21 3523 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3524 int min_agaw;
3525 u64 end;
3526
3527 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3528 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3529 addr_width = agaw_to_width(min_agaw);
3530 end = DOMAIN_MAX_ADDR(addr_width);
3531 end = end & VTD_PAGE_MASK;
3532 if (end < max_addr) {
3533 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3534 "sufficient for the mapped address (%llx)\n",
3535 __func__, min_agaw, max_addr);
3536 return -EFAULT;
3537 }
dde57a21 3538 dmar_domain->max_addr = max_addr;
fe40f1e0
WH		 3539 }
3540
dde57a21 3541 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
faa3d6f5 3542 return ret;
38717946 3543}
38717946 3544
dde57a21
JR		 3545static void intel_iommu_unmap_range(struct iommu_domain *domain,
3546 unsigned long iova, size_t size)
38717946 3547{
dde57a21 3548 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5
WH		 3549 dma_addr_t base;
3550
3551 /* The address might not be aligned */
3552 base = iova & VTD_PAGE_MASK;
3553 size = VTD_PAGE_ALIGN(size);
dde57a21 3554 dma_pte_clear_range(dmar_domain, base, base + size);
fe40f1e0 3555
dde57a21
JR		 3556 if (dmar_domain->max_addr == base + size)
3557 dmar_domain->max_addr = base;
38717946 3558}
38717946 3559
d14d6577
JR		 3560static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3561 unsigned long iova)
38717946 3562{
d14d6577 3563 struct dmar_domain *dmar_domain = domain->priv;
38717946 3564 struct dma_pte *pte;
faa3d6f5 3565 u64 phys = 0;
38717946 3566
d14d6577 3567 pte = addr_to_dma_pte(dmar_domain, iova);
38717946 3568 if (pte)
faa3d6f5 3569 phys = dma_pte_addr(pte);
38717946 3570
faa3d6f5 3571 return phys;
38717946 3572}
a8bcbb0d 3573
dbb9fd86
SY		 3574static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3575 unsigned long cap)
3576{
3577 struct dmar_domain *dmar_domain = domain->priv;
3578
3579 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3580 return dmar_domain->iommu_snooping;
3581
3582 return 0;
3583}
3584
a8bcbb0d
JR		 3585static struct iommu_ops intel_iommu_ops = {
3586 .domain_init = intel_iommu_domain_init,
3587 .domain_destroy = intel_iommu_domain_destroy,
3588 .attach_dev = intel_iommu_attach_device,
3589 .detach_dev = intel_iommu_detach_device,
3590 .map = intel_iommu_map_range,
3591 .unmap = intel_iommu_unmap_range,
3592 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3593 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3594};
9af88143
DW		 3595
3596static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3597{
3598 /*
3599 * Mobile 4 Series Chipset neglects to set RWBF capability,
3600 * but needs it:
3601 */
3602 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3603 rwbf_quirk = 1;
3604}
3605
3606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
Linux 6.x block layer and io_uring tree(s)