[linux-2.6-block.git] / drivers / pci / hotplug / shpchp.h

/*
 * Standard Hot Plug Controller Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
 *
 */
#ifndef _SHPCHP_H
#define _SHPCHP_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/pci_hotplug.h>
#include <linux/delay.h>
#include <linux/sched.h>	/* signal_pending(), struct timer_list */
#include <linux/mutex.h>
#include <linux/workqueue.h>

#if !defined(MODULE)
	#define MY_NAME	"shpchp"
#else
	#define MY_NAME	THIS_MODULE->name
#endif

extern int shpchp_poll_mode;
extern int shpchp_poll_time;
extern int shpchp_debug;
extern struct workqueue_struct *shpchp_wq;
extern struct workqueue_struct *shpchp_ordered_wq;

#define dbg(format, arg...)						\
do {									\
	if (shpchp_debug)						\
		printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg);	\
} while (0)
#define err(format, arg...)						\
	printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
#define info(format, arg...)						\
	printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
#define warn(format, arg...)						\
	printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)

#define ctrl_dbg(ctrl, format, arg...)					\
	do {								\
		if (shpchp_debug)					\
			dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,	\
					format, ## arg);		\
	} while (0)
#define ctrl_err(ctrl, format, arg...)					\
	dev_err(&ctrl->pci_dev->dev, format, ## arg)
#define ctrl_info(ctrl, format, arg...)					\
	dev_info(&ctrl->pci_dev->dev, format, ## arg)
#define ctrl_warn(ctrl, format, arg...)					\
	dev_warn(&ctrl->pci_dev->dev, format, ## arg)


#define SLOT_NAME_SIZE 10
struct slot {
	u8 bus;
	u8 device;
	u16 status;
	u32 number;
	u8 is_a_board;
	u8 state;
	u8 presence_save;
	u8 pwr_save;
	struct controller *ctrl;
	struct hpc_ops *hpc_ops;
	struct hotplug_slot *hotplug_slot;
	struct list_head	slot_list;
	struct delayed_work work;	/* work for button event */
	struct mutex lock;
	u8 hp_slot;
};

struct event_info {
	u32 event_type;
	struct slot *p_slot;
	struct work_struct work;
};

struct controller {
	struct mutex crit_sect;		/* critical section mutex */
	struct mutex cmd_lock;		/* command lock */
	int num_slots;			/* Number of slots on ctlr */
	int slot_num_inc;		/* 1 or -1 */
	struct pci_dev *pci_dev;
	struct list_head slot_list;
	struct hpc_ops *hpc_ops;
	wait_queue_head_t queue;	/* sleep & wake process */
	u8 slot_device_offset;
	u32 pcix_misc2_reg;	/* for amd pogo errata */
	u32 first_slot;		/* First physical slot number */
	u32 cap_offset;
	unsigned long mmio_base;
	unsigned long mmio_size;
	void __iomem *creg;
	struct timer_list poll_timer;
};

/* Define AMD SHPC ID  */
#define PCI_DEVICE_ID_AMD_GOLAM_7450	0x7450
#define PCI_DEVICE_ID_AMD_POGO_7458	0x7458

/* AMD PCI-X bridge registers */
#define PCIX_MEM_BASE_LIMIT_OFFSET	0x1C
#define PCIX_MISCII_OFFSET		0x48
#define PCIX_MISC_BRIDGE_ERRORS_OFFSET	0x80

/* AMD PCIX_MISCII masks and offsets */
#define PERRNONFATALENABLE_MASK		0x00040000
#define PERRFATALENABLE_MASK		0x00080000
#define PERRFLOODENABLE_MASK		0x00100000
#define SERRNONFATALENABLE_MASK		0x00200000
#define SERRFATALENABLE_MASK		0x00400000

/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
#define PERR_OBSERVED_MASK		0x00000001

/* AMD PCIX_MEM_BASE_LIMIT masks */
#define RSE_MASK			0x40000000

#define INT_BUTTON_IGNORE		0
#define INT_PRESENCE_ON			1
#define INT_PRESENCE_OFF		2
#define INT_SWITCH_CLOSE		3
#define INT_SWITCH_OPEN			4
#define INT_POWER_FAULT			5
#define INT_POWER_FAULT_CLEAR		6
#define INT_BUTTON_PRESS		7
#define INT_BUTTON_RELEASE		8
#define INT_BUTTON_CANCEL		9

#define STATIC_STATE			0
#define BLINKINGON_STATE		1
#define BLINKINGOFF_STATE		2
#define POWERON_STATE			3
#define POWEROFF_STATE			4

/* Error messages */
#define INTERLOCK_OPEN			0x00000002
#define ADD_NOT_SUPPORTED		0x00000003
#define CARD_FUNCTIONING		0x00000005
#define ADAPTER_NOT_SAME		0x00000006
#define NO_ADAPTER_PRESENT		0x00000009
#define NOT_ENOUGH_RESOURCES		0x0000000B
#define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
#define WRONG_BUS_FREQUENCY		0x0000000D
#define POWER_FAILURE			0x0000000E

extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
extern void shpchp_remove_ctrl_files(struct controller *ctrl);
extern int shpchp_sysfs_enable_slot(struct slot *slot);
extern int shpchp_sysfs_disable_slot(struct slot *slot);
extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
extern int shpchp_configure_device(struct slot *p_slot);
extern int shpchp_unconfigure_device(struct slot *p_slot);
extern void cleanup_slots(struct controller *ctrl);
extern void shpchp_queue_pushbutton_work(struct work_struct *work);
extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev);

static inline const char *slot_name(struct slot *slot)
{
	return hotplug_slot_name(slot->hotplug_slot);
}

#ifdef CONFIG_ACPI
#include <linux/pci-acpi.h>
static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
{
	u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
	return acpi_get_hp_hw_control_from_firmware(dev, flags);
}
#else
#define get_hp_hw_control_from_firmware(dev) (0)
#endif

struct ctrl_reg {
	volatile u32 base_offset;
	volatile u32 slot_avail1;
	volatile u32 slot_avail2;
	volatile u32 slot_config;
	volatile u16 sec_bus_config;
	volatile u8  msi_ctrl;
	volatile u8  prog_interface;
	volatile u16 cmd;
	volatile u16 cmd_status;
	volatile u32 intr_loc;
	volatile u32 serr_loc;
	volatile u32 serr_intr_enable;
	volatile u32 slot1;
} __attribute__ ((packed));

/* offsets to the controller registers based on the above structure layout */
enum ctrl_offsets {
	BASE_OFFSET 	 = offsetof(struct ctrl_reg, base_offset),
	SLOT_AVAIL1 	 = offsetof(struct ctrl_reg, slot_avail1),
	SLOT_AVAIL2	 = offsetof(struct ctrl_reg, slot_avail2),
	SLOT_CONFIG 	 = offsetof(struct ctrl_reg, slot_config),
	SEC_BUS_CONFIG	 = offsetof(struct ctrl_reg, sec_bus_config),
	MSI_CTRL	 = offsetof(struct ctrl_reg, msi_ctrl),
	PROG_INTERFACE 	 = offsetof(struct ctrl_reg, prog_interface),
	CMD		 = offsetof(struct ctrl_reg, cmd),
	CMD_STATUS	 = offsetof(struct ctrl_reg, cmd_status),
	INTR_LOC	 = offsetof(struct ctrl_reg, intr_loc),
	SERR_LOC	 = offsetof(struct ctrl_reg, serr_loc),
	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	SLOT1		 = offsetof(struct ctrl_reg, slot1),
};

static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
{
	return hotplug_slot->private;
}

static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
{
	struct slot *slot;

	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
		if (slot->device == device)
			return slot;
	}

	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
	return NULL;
}

static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;

	/* save MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;

	/* clear SERR/PERR enable bits */
	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;
	u32 pcix_bridge_errors_reg;
	u32 pcix_mem_base_reg;
	u8  perr_set;
	u8  rse_set;

	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	if (perr_set) {
		ctrl_dbg(p_slot->ctrl,
			 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
			 perr_set);

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	}

	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	rse_set = pcix_mem_base_reg & RSE_MASK;
	if (rse_set) {
		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	}
	/* restore MiscII register */
	pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );

	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
		pcix_misc2_temp |= SERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
		pcix_misc2_temp |= PERRFLOODENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
		pcix_misc2_temp |= PERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

struct hpc_ops {
	int (*power_on_slot)(struct slot *slot);
	int (*slot_enable)(struct slot *slot);
	int (*slot_disable)(struct slot *slot);
	int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
	int (*get_power_status)(struct slot *slot, u8 *status);
	int (*get_attention_status)(struct slot *slot, u8 *status);
	int (*set_attention_status)(struct slot *slot, u8 status);
	int (*get_latch_status)(struct slot *slot, u8 *status);
	int (*get_adapter_status)(struct slot *slot, u8 *status);
	int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
	int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
	int (*get_prog_int)(struct slot *slot, u8 *prog_int);
	int (*query_power_fault)(struct slot *slot);
	void (*green_led_on)(struct slot *slot);
	void (*green_led_off)(struct slot *slot);
	void (*green_led_blink)(struct slot *slot);
	void (*release_ctlr)(struct controller *ctrl);
	int (*check_cmd_status)(struct controller *ctrl);
};

#endif				/* _SHPCHP_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Standard Hot Plug Controller Driver
	3	*
	4	* Copyright (C) 1995,2001 Compaq Computer Corporation
	5	* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
	6	* Copyright (C) 2001 IBM
	7	* Copyright (C) 2003-2004 Intel Corporation
	8	*
	9	* All rights reserved.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or (at
	14	* your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	19	* NON INFRINGEMENT. See the GNU General Public License for more
	20	* details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
8cf4c195	26	* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4 LT	27	*
	28	*/
	29	#ifndef _SHPCHP_H
	30	#define _SHPCHP_H
	31
	32	#include <linux/types.h>
	33	#include <linux/pci.h>
7a54f25c	34	#include <linux/pci_hotplug.h>
1da177e4	35	#include <linux/delay.h>
4e57b681	36	#include <linux/sched.h> /* signal_pending(), struct timer_list */
6aa4cdd0	37	#include <linux/mutex.h>
e24dcbef	38	#include <linux/workqueue.h>
4e57b681	39
1da177e4 LT	40	#if !defined(MODULE)
	41	#define MY_NAME "shpchp"
	42	#else
	43	#define MY_NAME THIS_MODULE->name
	44	#endif
	45
	46	extern int shpchp_poll_mode;
	47	extern int shpchp_poll_time;
	48	extern int shpchp_debug;
f7391f53	49	extern struct workqueue_struct *shpchp_wq;
e24dcbef	50	extern struct workqueue_struct *shpchp_ordered_wq;
1da177e4	51
8352e04e	52	#define dbg(format, arg...) \
1c35b8e5 FS	53	do { \
	54	if (shpchp_debug) \
	55	printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
	56	} while (0)
8352e04e KK	57	#define err(format, arg...) \
	58	printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
	59	#define info(format, arg...) \
	60	printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
	61	#define warn(format, arg...) \
	62	printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
1da177e4	63
f98ca311 TI	64	#define ctrl_dbg(ctrl, format, arg...) \
	65	do { \
	66	if (shpchp_debug) \
1c35b8e5	67	dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
f98ca311 TI	68	format, ## arg); \
	69	} while (0)
	70	#define ctrl_err(ctrl, format, arg...) \
	71	dev_err(&ctrl->pci_dev->dev, format, ## arg)
	72	#define ctrl_info(ctrl, format, arg...) \
	73	dev_info(&ctrl->pci_dev->dev, format, ## arg)
	74	#define ctrl_warn(ctrl, format, arg...) \
	75	dev_warn(&ctrl->pci_dev->dev, format, ## arg)
	76
	77
bbe779db	78	#define SLOT_NAME_SIZE 10
1da177e4	79	struct slot {
1da177e4 LT	80	u8 bus;
1da177e4 LT	81	u8 device;
2178bfad	82	u16 status;
1da177e4 LT	83	u32 number;
1da177e4 LT	84	u8 is_a_board;
1da177e4	85	u8 state;
1da177e4	86	u8 presence_save;
2178bfad	87	u8 pwr_save;
1da177e4 LT	88	struct controller *ctrl;
	89	struct hpc_ops *hpc_ops;
	90	struct hotplug_slot *hotplug_slot;
	91	struct list_head slot_list;
c4028958	92	struct delayed_work work; /* work for button event */
a246fa4e	93	struct mutex lock;
66f17055	94	u8 hp_slot;
1da177e4 LT	95	};
1da177e4 LT	96
1da177e4 LT	97	struct event_info {
1da177e4 LT	98	u32 event_type;
f7391f53 KK	99	struct slot *p_slot;
f7391f53 KK	100	struct work_struct work;
1da177e4 LT	101	};
	102
	103	struct controller {
6aa4cdd0	104	struct mutex crit_sect; /* critical section mutex */
d29aadda	105	struct mutex cmd_lock; /* command lock */
1da177e4 LT	106	int num_slots; /* Number of slots on ctlr */
1da177e4 LT	107	int slot_num_inc; /* 1 or -1 */
1da177e4	108	struct pci_dev *pci_dev;
5b1a960d	109	struct list_head slot_list;
1da177e4 LT	110	struct hpc_ops *hpc_ops;
1da177e4 LT	111	wait_queue_head_t queue; /* sleep & wake process */
1da177e4	112	u8 slot_device_offset;
53044f35	113	u32 pcix_misc2_reg; /* for amd pogo errata */
1da177e4	114	u32 first_slot; /* First physical slot number */
0455986c KK	115	u32 cap_offset;
	116	unsigned long mmio_base;
	117	unsigned long mmio_size;
0abe68ce KK	118	void __iomem *creg;
0abe68ce KK	119	struct timer_list poll_timer;
1da177e4 LT	120	};
1da177e4 LT	121
1da177e4	122	/* Define AMD SHPC ID */
9f593e30	123	#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
53044f35 KD	124	#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
53044f35 KD	125
45e829ea	126	/* AMD PCI-X bridge registers */
53044f35 KD	127	#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
	128	#define PCIX_MISCII_OFFSET 0x48
	129	#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
	130
	131	/* AMD PCIX_MISCII masks and offsets */
	132	#define PERRNONFATALENABLE_MASK 0x00040000
	133	#define PERRFATALENABLE_MASK 0x00080000
	134	#define PERRFLOODENABLE_MASK 0x00100000
	135	#define SERRNONFATALENABLE_MASK 0x00200000
	136	#define SERRFATALENABLE_MASK 0x00400000
	137
	138	/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
	139	#define PERR_OBSERVED_MASK 0x00000001
	140
	141	/* AMD PCIX_MEM_BASE_LIMIT masks */
	142	#define RSE_MASK 0x40000000
1da177e4 LT	143
	144	#define INT_BUTTON_IGNORE 0
	145	#define INT_PRESENCE_ON 1
	146	#define INT_PRESENCE_OFF 2
	147	#define INT_SWITCH_CLOSE 3
	148	#define INT_SWITCH_OPEN 4
	149	#define INT_POWER_FAULT 5
	150	#define INT_POWER_FAULT_CLEAR 6
	151	#define INT_BUTTON_PRESS 7
	152	#define INT_BUTTON_RELEASE 8
	153	#define INT_BUTTON_CANCEL 9
	154
	155	#define STATIC_STATE 0
	156	#define BLINKINGON_STATE 1
	157	#define BLINKINGOFF_STATE 2
	158	#define POWERON_STATE 3
	159	#define POWEROFF_STATE 4
	160
1da177e4 LT	161	/* Error messages */
	162	#define INTERLOCK_OPEN 0x00000002
	163	#define ADD_NOT_SUPPORTED 0x00000003
	164	#define CARD_FUNCTIONING 0x00000005
	165	#define ADAPTER_NOT_SAME 0x00000006
	166	#define NO_ADAPTER_PRESENT 0x00000009
	167	#define NOT_ENOUGH_RESOURCES 0x0000000B
	168	#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
	169	#define WRONG_BUS_FREQUENCY 0x0000000D
	170	#define POWER_FAILURE 0x0000000E
	171
e1b95dc6	172	extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
8352e04e KK	173	extern void shpchp_remove_ctrl_files(struct controller *ctrl);
	174	extern int shpchp_sysfs_enable_slot(struct slot *slot);
	175	extern int shpchp_sysfs_disable_slot(struct slot *slot);
0abe68ce KK	176	extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
	177	extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
	178	extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
	179	extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
8352e04e KK	180	extern int shpchp_configure_device(struct slot *p_slot);
	181	extern int shpchp_unconfigure_device(struct slot *p_slot);
	182	extern void cleanup_slots(struct controller *ctrl);
e325e1f0	183	extern void shpchp_queue_pushbutton_work(struct work_struct *work);
8352e04e	184	extern int shpc_init( struct controller ctrl, struct pci_dev pdev);
783c49fc	185
66f17055 AC	186	static inline const char slot_name(struct slot slot)
	187	{
	188	return hotplug_slot_name(slot->hotplug_slot);
	189	}
	190
783c49fc	191	#ifdef CONFIG_ACPI
ac9c052d	192	#include <linux/pci-acpi.h>
ac9c052d KK	193	static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
	194	{
	195	u32 flags = OSC_SHPC_NATIVE_HP_CONTROL;
	196	return acpi_get_hp_hw_control_from_firmware(dev, flags);
	197	}
783c49fc	198	#else
ac9c052d	199	#define get_hp_hw_control_from_firmware(dev) (0)
783c49fc KA	200	#endif
783c49fc KA	201
1da177e4 LT	202	struct ctrl_reg {
	203	volatile u32 base_offset;
	204	volatile u32 slot_avail1;
	205	volatile u32 slot_avail2;
	206	volatile u32 slot_config;
	207	volatile u16 sec_bus_config;
	208	volatile u8 msi_ctrl;
	209	volatile u8 prog_interface;
	210	volatile u16 cmd;
	211	volatile u16 cmd_status;
	212	volatile u32 intr_loc;
	213	volatile u32 serr_loc;
	214	volatile u32 serr_intr_enable;
	215	volatile u32 slot1;
1da177e4 LT	216	} __attribute__ ((packed));
	217
	218	/* offsets to the controller registers based on the above structure layout */
	219	enum ctrl_offsets {
8352e04e KK	220	BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
	221	SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
	222	SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
	223	SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
	224	SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
	225	MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
	226	PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
	227	CMD = offsetof(struct ctrl_reg, cmd),
	228	CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
	229	INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
	230	SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
	231	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	232	SLOT1 = offsetof(struct ctrl_reg, slot1),
1da177e4	233	};
1da177e4	234
8352e04e	235	static inline struct slot get_slot(struct hotplug_slot hotplug_slot)
9f593e30	236	{
8352e04e	237	return hotplug_slot->private;
1da177e4 LT	238	}
1da177e4 LT	239
8352e04e	240	static inline struct slot shpchp_find_slot(struct controller ctrl, u8 device)
1da177e4	241	{
5b1a960d	242	struct slot *slot;
1da177e4	243
5b1a960d KK	244	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
	245	if (slot->device == device)
	246	return slot;
1da177e4 LT	247	}
1da177e4 LT	248
be7bce25	249	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
5b1a960d	250	return NULL;
1da177e4 LT	251	}
1da177e4 LT	252
53044f35 KD	253	static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
	254	{
	255	u32 pcix_misc2_temp;
	256
	257	/* save MiscII register */
	258	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
	259
	260	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
	261
	262	/* clear SERR/PERR enable bits */
	263	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	264	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	265	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	266	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	267	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	268	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	269	}
	270
	271	static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
	272	{
	273	u32 pcix_misc2_temp;
	274	u32 pcix_bridge_errors_reg;
	275	u32 pcix_mem_base_reg;
	276	u8 perr_set;
	277	u8 rse_set;
	278
	279	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	280	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	281	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	282	if (perr_set) {
f98ca311	283	ctrl_dbg(p_slot->ctrl,
be7bce25 TI	284	"Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
be7bce25 TI	285	perr_set);
53044f35 KD	286
	287	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	288	}
	289
	290	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	291	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	292	rse_set = pcix_mem_base_reg & RSE_MASK;
	293	if (rse_set) {
be7bce25	294	ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
53044f35 KD	295
	296	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	297	}
	298	/* restore MiscII register */
	299	pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
	300
	301	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
	302	pcix_misc2_temp \|= SERRFATALENABLE_MASK;
	303	else
	304	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	305
	306	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
	307	pcix_misc2_temp \|= SERRNONFATALENABLE_MASK;
	308	else
	309	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	310
	311	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
	312	pcix_misc2_temp \|= PERRFLOODENABLE_MASK;
	313	else
	314	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	315
	316	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
	317	pcix_misc2_temp \|= PERRFATALENABLE_MASK;
	318	else
	319	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	320
	321	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
	322	pcix_misc2_temp \|= PERRNONFATALENABLE_MASK;
	323	else
	324	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	325	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	326	}
	327
1da177e4	328	struct hpc_ops {
8352e04e KK	329	int (power_on_slot)(struct slot slot);
	330	int (slot_enable)(struct slot slot);
	331	int (slot_disable)(struct slot slot);
	332	int (set_bus_speed_mode)(struct slot slot, enum pci_bus_speed speed);
	333	int (get_power_status)(struct slot slot, u8 *status);
	334	int (get_attention_status)(struct slot slot, u8 *status);
	335	int (set_attention_status)(struct slot slot, u8 status);
	336	int (get_latch_status)(struct slot slot, u8 *status);
	337	int (get_adapter_status)(struct slot slot, u8 *status);
8352e04e KK	338	int (get_adapter_speed)(struct slot slot, enum pci_bus_speed *speed);
	339	int (get_mode1_ECC_cap)(struct slot slot, u8 *mode);
	340	int (get_prog_int)(struct slot slot, u8 *prog_int);
	341	int (query_power_fault)(struct slot slot);
	342	void (green_led_on)(struct slot slot);
	343	void (green_led_off)(struct slot slot);
	344	void (green_led_blink)(struct slot slot);
	345	void (release_ctlr)(struct controller ctrl);
	346	int (check_cmd_status)(struct controller ctrl);
1da177e4 LT	347	};
	348
	349	#endif /* _SHPCHP_H */