[linux-2.6-block.git] / drivers / pci / hotplug / shpchp.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Standard Hot Plug Controller Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
 *
 */
#ifndef _SHPCHP_H
#define _SHPCHP_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/pci_hotplug.h>
#include <linux/delay.h>
#include <linux/sched/signal.h>	/* signal_pending(), struct timer_list */
#include <linux/mutex.h>
#include <linux/workqueue.h>

#if !defined(MODULE)
	#define MY_NAME	"shpchp"
#else
	#define MY_NAME	THIS_MODULE->name
#endif

extern bool shpchp_poll_mode;
extern int shpchp_poll_time;
extern bool shpchp_debug;

#define dbg(format, arg...)						\
do {									\
	if (shpchp_debug)						\
		printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg);	\
} while (0)
#define err(format, arg...)						\
	printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
#define info(format, arg...)						\
	printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
#define warn(format, arg...)						\
	printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)

#define ctrl_dbg(ctrl, format, arg...)					\
	do {								\
		if (shpchp_debug)					\
			pci_printk(KERN_DEBUG, ctrl->pci_dev,		\
					format, ## arg);		\
	} while (0)
#define ctrl_err(ctrl, format, arg...)					\
	pci_err(ctrl->pci_dev, format, ## arg)
#define ctrl_info(ctrl, format, arg...)					\
	pci_info(ctrl->pci_dev, format, ## arg)
#define ctrl_warn(ctrl, format, arg...)					\
	pci_warn(ctrl->pci_dev, format, ## arg)


#define SLOT_NAME_SIZE 10
struct slot {
	u8 bus;
	u8 device;
	u16 status;
	u32 number;
	u8 is_a_board;
	u8 state;
	u8 attention_save;
	u8 presence_save;
	u8 latch_save;
	u8 pwr_save;
	struct controller *ctrl;
	const struct hpc_ops *hpc_ops;
	struct hotplug_slot hotplug_slot;
	struct list_head	slot_list;
	struct delayed_work work;	/* work for button event */
	struct mutex lock;
	struct workqueue_struct *wq;
	u8 hp_slot;
};

struct event_info {
	u32 event_type;
	struct slot *p_slot;
	struct work_struct work;
};

struct controller {
	struct mutex crit_sect;		/* critical section mutex */
	struct mutex cmd_lock;		/* command lock */
	int num_slots;			/* Number of slots on ctlr */
	int slot_num_inc;		/* 1 or -1 */
	struct pci_dev *pci_dev;
	struct list_head slot_list;
	const struct hpc_ops *hpc_ops;
	wait_queue_head_t queue;	/* sleep & wake process */
	u8 slot_device_offset;
	u32 pcix_misc2_reg;	/* for amd pogo errata */
	u32 first_slot;		/* First physical slot number */
	u32 cap_offset;
	unsigned long mmio_base;
	unsigned long mmio_size;
	void __iomem *creg;
	struct timer_list poll_timer;
};

/* Define AMD SHPC ID  */
#define PCI_DEVICE_ID_AMD_POGO_7458	0x7458

/* AMD PCI-X bridge registers */
#define PCIX_MEM_BASE_LIMIT_OFFSET	0x1C
#define PCIX_MISCII_OFFSET		0x48
#define PCIX_MISC_BRIDGE_ERRORS_OFFSET	0x80

/* AMD PCIX_MISCII masks and offsets */
#define PERRNONFATALENABLE_MASK		0x00040000
#define PERRFATALENABLE_MASK		0x00080000
#define PERRFLOODENABLE_MASK		0x00100000
#define SERRNONFATALENABLE_MASK		0x00200000
#define SERRFATALENABLE_MASK		0x00400000

/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
#define PERR_OBSERVED_MASK		0x00000001

/* AMD PCIX_MEM_BASE_LIMIT masks */
#define RSE_MASK			0x40000000

#define INT_BUTTON_IGNORE		0
#define INT_PRESENCE_ON			1
#define INT_PRESENCE_OFF		2
#define INT_SWITCH_CLOSE		3
#define INT_SWITCH_OPEN			4
#define INT_POWER_FAULT			5
#define INT_POWER_FAULT_CLEAR		6
#define INT_BUTTON_PRESS		7
#define INT_BUTTON_RELEASE		8
#define INT_BUTTON_CANCEL		9

#define STATIC_STATE			0
#define BLINKINGON_STATE		1
#define BLINKINGOFF_STATE		2
#define POWERON_STATE			3
#define POWEROFF_STATE			4

/* Error messages */
#define INTERLOCK_OPEN			0x00000002
#define ADD_NOT_SUPPORTED		0x00000003
#define CARD_FUNCTIONING		0x00000005
#define ADAPTER_NOT_SAME		0x00000006
#define NO_ADAPTER_PRESENT		0x00000009
#define NOT_ENOUGH_RESOURCES		0x0000000B
#define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
#define WRONG_BUS_FREQUENCY		0x0000000D
#define POWER_FAILURE			0x0000000E

int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
void shpchp_remove_ctrl_files(struct controller *ctrl);
int shpchp_sysfs_enable_slot(struct slot *slot);
int shpchp_sysfs_disable_slot(struct slot *slot);
u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
int shpchp_configure_device(struct slot *p_slot);
int shpchp_unconfigure_device(struct slot *p_slot);
void cleanup_slots(struct controller *ctrl);
void shpchp_queue_pushbutton_work(struct work_struct *work);
int shpc_init(struct controller *ctrl, struct pci_dev *pdev);

static inline const char *slot_name(struct slot *slot)
{
	return hotplug_slot_name(&slot->hotplug_slot);
}

struct ctrl_reg {
	volatile u32 base_offset;
	volatile u32 slot_avail1;
	volatile u32 slot_avail2;
	volatile u32 slot_config;
	volatile u16 sec_bus_config;
	volatile u8  msi_ctrl;
	volatile u8  prog_interface;
	volatile u16 cmd;
	volatile u16 cmd_status;
	volatile u32 intr_loc;
	volatile u32 serr_loc;
	volatile u32 serr_intr_enable;
	volatile u32 slot1;
} __attribute__ ((packed));

/* offsets to the controller registers based on the above structure layout */
enum ctrl_offsets {
	BASE_OFFSET	 = offsetof(struct ctrl_reg, base_offset),
	SLOT_AVAIL1	 = offsetof(struct ctrl_reg, slot_avail1),
	SLOT_AVAIL2	 = offsetof(struct ctrl_reg, slot_avail2),
	SLOT_CONFIG	 = offsetof(struct ctrl_reg, slot_config),
	SEC_BUS_CONFIG	 = offsetof(struct ctrl_reg, sec_bus_config),
	MSI_CTRL	 = offsetof(struct ctrl_reg, msi_ctrl),
	PROG_INTERFACE	 = offsetof(struct ctrl_reg, prog_interface),
	CMD		 = offsetof(struct ctrl_reg, cmd),
	CMD_STATUS	 = offsetof(struct ctrl_reg, cmd_status),
	INTR_LOC	 = offsetof(struct ctrl_reg, intr_loc),
	SERR_LOC	 = offsetof(struct ctrl_reg, serr_loc),
	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	SLOT1		 = offsetof(struct ctrl_reg, slot1),
};

static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
{
	return container_of(hotplug_slot, struct slot, hotplug_slot);
}

static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
{
	struct slot *slot;

	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
		if (slot->device == device)
			return slot;
	}

	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
	return NULL;
}

static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;

	/* save MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;

	/* clear SERR/PERR enable bits */
	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;
	u32 pcix_bridge_errors_reg;
	u32 pcix_mem_base_reg;
	u8  perr_set;
	u8  rse_set;

	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	if (perr_set) {
		ctrl_dbg(p_slot->ctrl,
			 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
			 perr_set);

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	}

	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	rse_set = pcix_mem_base_reg & RSE_MASK;
	if (rse_set) {
		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	}
	/* restore MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
		pcix_misc2_temp |= SERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
		pcix_misc2_temp |= PERRFLOODENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
		pcix_misc2_temp |= PERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

struct hpc_ops {
	int (*power_on_slot)(struct slot *slot);
	int (*slot_enable)(struct slot *slot);
	int (*slot_disable)(struct slot *slot);
	int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
	int (*get_power_status)(struct slot *slot, u8 *status);
	int (*get_attention_status)(struct slot *slot, u8 *status);
	int (*set_attention_status)(struct slot *slot, u8 status);
	int (*get_latch_status)(struct slot *slot, u8 *status);
	int (*get_adapter_status)(struct slot *slot, u8 *status);
	int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
	int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
	int (*get_prog_int)(struct slot *slot, u8 *prog_int);
	int (*query_power_fault)(struct slot *slot);
	void (*green_led_on)(struct slot *slot);
	void (*green_led_off)(struct slot *slot);
	void (*green_led_blink)(struct slot *slot);
	void (*release_ctlr)(struct controller *ctrl);
	int (*check_cmd_status)(struct controller *ctrl);
};

#endif				/* _SHPCHP_H */
Commit	Line	Data
736759ef	1	/* SPDX-License-Identifier: GPL-2.0+ */
1da177e4 LT	2	/*
	3	* Standard Hot Plug Controller Driver
	4	*
	5	* Copyright (C) 1995,2001 Compaq Computer Corporation
	6	* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
	7	* Copyright (C) 2001 IBM
	8	* Copyright (C) 2003-2004 Intel Corporation
	9	*
	10	* All rights reserved.
	11	*
8cf4c195	12	* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4 LT	13	*
	14	*/
	15	#ifndef _SHPCHP_H
	16	#define _SHPCHP_H
	17
	18	#include <linux/types.h>
	19	#include <linux/pci.h>
7a54f25c	20	#include <linux/pci_hotplug.h>
1da177e4	21	#include <linux/delay.h>
174cd4b1	22	#include <linux/sched/signal.h> /* signal_pending(), struct timer_list */
6aa4cdd0	23	#include <linux/mutex.h>
e24dcbef	24	#include <linux/workqueue.h>
4e57b681	25
1da177e4 LT	26	#if !defined(MODULE)
	27	#define MY_NAME "shpchp"
	28	#else
	29	#define MY_NAME THIS_MODULE->name
	30	#endif
	31
90ab5ee9	32	extern bool shpchp_poll_mode;
1da177e4	33	extern int shpchp_poll_time;
90ab5ee9	34	extern bool shpchp_debug;
1da177e4	35
8352e04e	36	#define dbg(format, arg...) \
1c35b8e5 FS	37	do { \
1c35b8e5 FS	38	if (shpchp_debug) \
ff3ce480	39	printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
1c35b8e5	40	} while (0)
8352e04e	41	#define err(format, arg...) \
ff3ce480	42	printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
8352e04e	43	#define info(format, arg...) \
ff3ce480	44	printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
8352e04e	45	#define warn(format, arg...) \
ff3ce480	46	printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
1da177e4	47
f98ca311 TI	48	#define ctrl_dbg(ctrl, format, arg...) \
	49	do { \
	50	if (shpchp_debug) \
7506dc79	51	pci_printk(KERN_DEBUG, ctrl->pci_dev, \
f98ca311 TI	52	format, ## arg); \
	53	} while (0)
	54	#define ctrl_err(ctrl, format, arg...) \
7506dc79	55	pci_err(ctrl->pci_dev, format, ## arg)
f98ca311	56	#define ctrl_info(ctrl, format, arg...) \
7506dc79	57	pci_info(ctrl->pci_dev, format, ## arg)
f98ca311	58	#define ctrl_warn(ctrl, format, arg...) \
7506dc79	59	pci_warn(ctrl->pci_dev, format, ## arg)
f98ca311 TI	60
f98ca311 TI	61
bbe779db	62	#define SLOT_NAME_SIZE 10
1da177e4	63	struct slot {
1da177e4 LT	64	u8 bus;
1da177e4 LT	65	u8 device;
2178bfad	66	u16 status;
1da177e4 LT	67	u32 number;
1da177e4 LT	68	u8 is_a_board;
1da177e4	69	u8 state;
a7da2161	70	u8 attention_save;
1da177e4	71	u8 presence_save;
a7da2161	72	u8 latch_save;
2178bfad	73	u8 pwr_save;
1da177e4	74	struct controller *ctrl;
bd790082	75	const struct hpc_ops *hpc_ops;
125450f8	76	struct hotplug_slot hotplug_slot;
1da177e4	77	struct list_head slot_list;
c4028958	78	struct delayed_work work; /* work for button event */
a246fa4e	79	struct mutex lock;
f652e7d2	80	struct workqueue_struct *wq;
66f17055	81	u8 hp_slot;
1da177e4 LT	82	};
1da177e4 LT	83
1da177e4 LT	84	struct event_info {
1da177e4 LT	85	u32 event_type;
f7391f53 KK	86	struct slot *p_slot;
f7391f53 KK	87	struct work_struct work;
1da177e4 LT	88	};
	89
	90	struct controller {
6aa4cdd0	91	struct mutex crit_sect; /* critical section mutex */
d29aadda	92	struct mutex cmd_lock; /* command lock */
1da177e4 LT	93	int num_slots; /* Number of slots on ctlr */
1da177e4 LT	94	int slot_num_inc; /* 1 or -1 */
1da177e4	95	struct pci_dev *pci_dev;
5b1a960d	96	struct list_head slot_list;
bd790082	97	const struct hpc_ops *hpc_ops;
1da177e4	98	wait_queue_head_t queue; /* sleep & wake process */
1da177e4	99	u8 slot_device_offset;
53044f35	100	u32 pcix_misc2_reg; /* for amd pogo errata */
1da177e4	101	u32 first_slot; /* First physical slot number */
0455986c KK	102	u32 cap_offset;
	103	unsigned long mmio_base;
	104	unsigned long mmio_size;
0abe68ce KK	105	void __iomem *creg;
0abe68ce KK	106	struct timer_list poll_timer;
1da177e4 LT	107	};
1da177e4 LT	108
1da177e4	109	/* Define AMD SHPC ID */
53044f35 KD	110	#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
53044f35 KD	111
45e829ea	112	/* AMD PCI-X bridge registers */
53044f35 KD	113	#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
	114	#define PCIX_MISCII_OFFSET 0x48
	115	#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
	116
	117	/* AMD PCIX_MISCII masks and offsets */
	118	#define PERRNONFATALENABLE_MASK 0x00040000
	119	#define PERRFATALENABLE_MASK 0x00080000
	120	#define PERRFLOODENABLE_MASK 0x00100000
	121	#define SERRNONFATALENABLE_MASK 0x00200000
	122	#define SERRFATALENABLE_MASK 0x00400000
	123
	124	/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
	125	#define PERR_OBSERVED_MASK 0x00000001
	126
	127	/* AMD PCIX_MEM_BASE_LIMIT masks */
	128	#define RSE_MASK 0x40000000
1da177e4 LT	129
	130	#define INT_BUTTON_IGNORE 0
	131	#define INT_PRESENCE_ON 1
	132	#define INT_PRESENCE_OFF 2
	133	#define INT_SWITCH_CLOSE 3
	134	#define INT_SWITCH_OPEN 4
	135	#define INT_POWER_FAULT 5
	136	#define INT_POWER_FAULT_CLEAR 6
	137	#define INT_BUTTON_PRESS 7
	138	#define INT_BUTTON_RELEASE 8
	139	#define INT_BUTTON_CANCEL 9
	140
	141	#define STATIC_STATE 0
	142	#define BLINKINGON_STATE 1
	143	#define BLINKINGOFF_STATE 2
	144	#define POWERON_STATE 3
	145	#define POWEROFF_STATE 4
	146
1da177e4 LT	147	/* Error messages */
	148	#define INTERLOCK_OPEN 0x00000002
	149	#define ADD_NOT_SUPPORTED 0x00000003
	150	#define CARD_FUNCTIONING 0x00000005
	151	#define ADAPTER_NOT_SAME 0x00000006
	152	#define NO_ADAPTER_PRESENT 0x00000009
	153	#define NOT_ENOUGH_RESOURCES 0x0000000B
	154	#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
	155	#define WRONG_BUS_FREQUENCY 0x0000000D
	156	#define POWER_FAILURE 0x0000000E
	157
f39d5b72 BH	158	int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
	159	void shpchp_remove_ctrl_files(struct controller *ctrl);
	160	int shpchp_sysfs_enable_slot(struct slot *slot);
	161	int shpchp_sysfs_disable_slot(struct slot *slot);
	162	u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
	163	u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
	164	u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
	165	u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
	166	int shpchp_configure_device(struct slot *p_slot);
	167	int shpchp_unconfigure_device(struct slot *p_slot);
	168	void cleanup_slots(struct controller *ctrl);
	169	void shpchp_queue_pushbutton_work(struct work_struct *work);
3c78bc61	170	int shpc_init(struct controller ctrl, struct pci_dev pdev);
783c49fc	171
66f17055 AC	172	static inline const char slot_name(struct slot slot)
66f17055 AC	173	{
125450f8	174	return hotplug_slot_name(&slot->hotplug_slot);
66f17055 AC	175	}
66f17055 AC	176
1da177e4 LT	177	struct ctrl_reg {
	178	volatile u32 base_offset;
	179	volatile u32 slot_avail1;
	180	volatile u32 slot_avail2;
	181	volatile u32 slot_config;
	182	volatile u16 sec_bus_config;
	183	volatile u8 msi_ctrl;
	184	volatile u8 prog_interface;
	185	volatile u16 cmd;
	186	volatile u16 cmd_status;
	187	volatile u32 intr_loc;
	188	volatile u32 serr_loc;
	189	volatile u32 serr_intr_enable;
	190	volatile u32 slot1;
1da177e4 LT	191	} __attribute__ ((packed));
	192
	193	/* offsets to the controller registers based on the above structure layout */
	194	enum ctrl_offsets {
f7625980 BH	195	BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
f7625980 BH	196	SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
8352e04e	197	SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
f7625980	198	SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
8352e04e KK	199	SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
8352e04e KK	200	MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
f7625980	201	PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
8352e04e KK	202	CMD = offsetof(struct ctrl_reg, cmd),
	203	CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
	204	INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
	205	SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
	206	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	207	SLOT1 = offsetof(struct ctrl_reg, slot1),
1da177e4	208	};
1da177e4	209
8352e04e	210	static inline struct slot get_slot(struct hotplug_slot hotplug_slot)
9f593e30	211	{
125450f8	212	return container_of(hotplug_slot, struct slot, hotplug_slot);
1da177e4 LT	213	}
1da177e4 LT	214
8352e04e	215	static inline struct slot shpchp_find_slot(struct controller ctrl, u8 device)
1da177e4	216	{
5b1a960d	217	struct slot *slot;
1da177e4	218
5b1a960d KK	219	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
	220	if (slot->device == device)
	221	return slot;
1da177e4 LT	222	}
1da177e4 LT	223
be7bce25	224	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
5b1a960d	225	return NULL;
1da177e4 LT	226	}
1da177e4 LT	227
53044f35 KD	228	static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
	229	{
	230	u32 pcix_misc2_temp;
	231
	232	/* save MiscII register */
	233	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
	234
	235	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
	236
	237	/* clear SERR/PERR enable bits */
	238	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	239	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	240	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	241	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	242	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	243	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	244	}
	245
	246	static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
	247	{
	248	u32 pcix_misc2_temp;
	249	u32 pcix_bridge_errors_reg;
	250	u32 pcix_mem_base_reg;
	251	u8 perr_set;
	252	u8 rse_set;
	253
	254	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	255	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	256	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	257	if (perr_set) {
f98ca311	258	ctrl_dbg(p_slot->ctrl,
be7bce25 TI	259	"Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
be7bce25 TI	260	perr_set);
53044f35 KD	261
	262	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	263	}
	264
	265	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	266	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	267	rse_set = pcix_mem_base_reg & RSE_MASK;
	268	if (rse_set) {
be7bce25	269	ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
53044f35 KD	270
	271	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	272	}
	273	/* restore MiscII register */
ff3ce480	274	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
53044f35 KD	275
	276	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
	277	pcix_misc2_temp \|= SERRFATALENABLE_MASK;
	278	else
	279	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	280
	281	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
	282	pcix_misc2_temp \|= SERRNONFATALENABLE_MASK;
	283	else
	284	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	285
	286	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
	287	pcix_misc2_temp \|= PERRFLOODENABLE_MASK;
	288	else
	289	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	290
	291	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
	292	pcix_misc2_temp \|= PERRFATALENABLE_MASK;
	293	else
	294	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	295
	296	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
	297	pcix_misc2_temp \|= PERRNONFATALENABLE_MASK;
	298	else
	299	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	300	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	301	}
	302
1da177e4	303	struct hpc_ops {
8352e04e KK	304	int (power_on_slot)(struct slot slot);
	305	int (slot_enable)(struct slot slot);
	306	int (slot_disable)(struct slot slot);
	307	int (set_bus_speed_mode)(struct slot slot, enum pci_bus_speed speed);
	308	int (get_power_status)(struct slot slot, u8 *status);
	309	int (get_attention_status)(struct slot slot, u8 *status);
	310	int (set_attention_status)(struct slot slot, u8 status);
	311	int (get_latch_status)(struct slot slot, u8 *status);
	312	int (get_adapter_status)(struct slot slot, u8 *status);
8352e04e KK	313	int (get_adapter_speed)(struct slot slot, enum pci_bus_speed *speed);
	314	int (get_mode1_ECC_cap)(struct slot slot, u8 *mode);
	315	int (get_prog_int)(struct slot slot, u8 *prog_int);
	316	int (query_power_fault)(struct slot slot);
	317	void (green_led_on)(struct slot slot);
	318	void (green_led_off)(struct slot slot);
	319	void (green_led_blink)(struct slot slot);
	320	void (release_ctlr)(struct controller ctrl);
	321	int (check_cmd_status)(struct controller ctrl);
1da177e4 LT	322	};
	323
	324	#endif /* _SHPCHP_H */