[linux-2.6-block.git] / drivers / pci / hotplug / pciehp_pci.c

/*
 * PCI Express Hot Plug Controller Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM Corp.
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include "../pci.h"
#include "pciehp.h"

static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
{
	u16 pci_cmd, pci_bctl;

	if (hpp->revision > 1) {
		printk(KERN_WARNING "%s: Rev.%d type0 record not supported\n",
		       __FUNCTION__, hpp->revision);
		return;
	}

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
	pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
	if (hpp->enable_serr)
		pci_cmd |= PCI_COMMAND_SERR;
	else
		pci_cmd &= ~PCI_COMMAND_SERR;
	if (hpp->enable_perr)
		pci_cmd |= PCI_COMMAND_PARITY;
	else
		pci_cmd &= ~PCI_COMMAND_PARITY;
	pci_write_config_word(dev, PCI_COMMAND, pci_cmd);

	/* Program bridge control value */
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
				      hpp->latency_timer);
		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
		if (hpp->enable_serr)
			pci_bctl |= PCI_BRIDGE_CTL_SERR;
		else
			pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
		if (hpp->enable_perr)
			pci_bctl |= PCI_BRIDGE_CTL_PARITY;
		else
			pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
	}
}

static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
{
	int pos;
	u16 reg16;
	u32 reg32;

	if (hpp->revision > 1) {
		printk(KERN_WARNING "%s: Rev.%d type2 record not supported\n",
		       __FUNCTION__, hpp->revision);
		return;
	}

	/* Find PCI Express capability */
	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
	if (!pos)
		return;

	/* Initialize Device Control Register */
	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
	reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);

	/* Initialize Link Control Register */
	if (dev->subordinate) {
		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16);
		reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
			| hpp->pci_exp_lnkctl_or;
		pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
	}

	/* Find Advanced Error Reporting Enhanced Capability */
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	if (!pos)
		return;

	/* Initialize Uncorrectable Error Mask Register */
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
	reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);

	/* Initialize Uncorrectable Error Severity Register */
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
	reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);

	/* Initialize Correctable Error Mask Register */
	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
	reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);

	/* Initialize Advanced Error Capabilities and Control Register */
	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
	reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
	pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);

	/*
	 * FIXME: The following two registers are not supported yet.
	 *
	 *   o Secondary Uncorrectable Error Severity Register
	 *   o Secondary Uncorrectable Error Mask Register
	 */
}

static void program_fw_provided_values(struct pci_dev *dev)
{
	struct pci_dev *cdev;
	struct hotplug_params hpp;

	/* Program hpp values for this device */
	if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
			(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
			(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
		return;

	if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
		printk(KERN_WARNING "%s: Could not get hotplug parameters\n",
		       __FUNCTION__);
		return;
	}

	if (hpp.t2)
		program_hpp_type2(dev, hpp.t2);
	if (hpp.t0)
		program_hpp_type0(dev, hpp.t0);

	/* Program child devices */
	if (dev->subordinate) {
		list_for_each_entry(cdev, &dev->subordinate->devices,
				    bus_list)
			program_fw_provided_values(cdev);
	}
}

static int __ref pciehp_add_bridge(struct pci_dev *dev)
{
	struct pci_bus *parent = dev->bus;
	int pass, busnr, start = parent->secondary;
	int end = parent->subordinate;

	for (busnr = start; busnr <= end; busnr++) {
		if (!pci_find_bus(pci_domain_nr(parent), busnr))
			break;
	}
	if (busnr-- > end) {
		err("No bus number available for hot-added bridge %s\n",
				pci_name(dev));
		return -1;
	}
	for (pass = 0; pass < 2; pass++)
		busnr = pci_scan_bridge(parent, dev, busnr, pass);
	if (!dev->subordinate)
		return -1;
	pci_bus_size_bridges(dev->subordinate);
	pci_bus_assign_resources(parent);
	pci_enable_bridges(parent);
	pci_bus_add_devices(parent);
	return 0;
}

int pciehp_configure_device(struct slot *p_slot)
{
	struct pci_dev *dev;
	struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
	int num, fn;

	dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
	if (dev) {
		err("Device %s already exists at %x:%x, cannot hot-add\n",
				pci_name(dev), p_slot->bus, p_slot->device);
		pci_dev_put(dev);
		return -EINVAL;
	}

	num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
	if (num == 0) {
		err("No new device found\n");
		return -ENODEV;
	}

	for (fn = 0; fn < 8; fn++) {
		dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
		if (!dev)
			continue;
		if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
			err("Cannot hot-add display device %s\n",
					pci_name(dev));
			pci_dev_put(dev);
			continue;
		}
		if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
				(dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
			pciehp_add_bridge(dev);
		}
		program_fw_provided_values(dev);
		pci_dev_put(dev);
	}

	pci_bus_assign_resources(parent);
	pci_bus_add_devices(parent);
	return 0;
}

int pciehp_unconfigure_device(struct slot *p_slot)
{
	int ret, rc = 0;
	int j;
	u8 bctl = 0;
	u8 presence = 0;
	struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
	u16 command;

	dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
				p_slot->device);
	ret = p_slot->hpc_ops->get_adapter_status(p_slot, &presence);
	if (ret)
		presence = 0;

	for (j = 0; j < 8; j++) {
		struct pci_dev* temp = pci_get_slot(parent,
				(p_slot->device << 3) | j);
		if (!temp)
			continue;
		if ((temp->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
			err("Cannot remove display device %s\n",
					pci_name(temp));
			pci_dev_put(temp);
			continue;
		}
		if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
			pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
			if (bctl & PCI_BRIDGE_CTL_VGA) {
				err("Cannot remove display device %s\n",
				    pci_name(temp));
				pci_dev_put(temp);
				continue;
			}
		}
		pci_remove_bus_device(temp);
		/*
		 * Ensure that no new Requests will be generated from
		 * the device.
		 */
		if (presence) {
			pci_read_config_word(temp, PCI_COMMAND, &command);
			command &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
			command |= PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(temp, PCI_COMMAND, command);
		}
		pci_dev_put(temp);
	}
	/*
	 * Some PCI Express root ports require fixup after hot-plug operation.
	 */
	if (pcie_mch_quirk)
		pci_fixup_device(pci_fixup_final, p_slot->ctrl->pci_dev);

	return rc;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* PCI Express Hot Plug Controller Driver
	3	*
	4	* Copyright (C) 1995,2001 Compaq Computer Corporation
	5	* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
	6	* Copyright (C) 2001 IBM Corp.
	7	* Copyright (C) 2003-2004 Intel Corporation
	8	*
	9	* All rights reserved.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or (at
	14	* your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	19	* NON INFRINGEMENT. See the GNU General Public License for more
	20	* details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
8cf4c195	26	* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
1da177e4 LT	27	*
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/types.h>
1da177e4 LT	33	#include <linux/pci.h>
	34	#include "../pci.h"
	35	#include "pciehp.h"
1da177e4	36
40abb96c KK	37	static void program_hpp_type0(struct pci_dev dev, struct hpp_type0 hpp)
	38	{
	39	u16 pci_cmd, pci_bctl;
	40
	41	if (hpp->revision > 1) {
	42	printk(KERN_WARNING "%s: Rev.%d type0 record not supported\n",
	43	__FUNCTION__, hpp->revision);
	44	return;
	45	}
	46
	47	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
	48	pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
	49	pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
	50	if (hpp->enable_serr)
	51	pci_cmd \|= PCI_COMMAND_SERR;
	52	else
	53	pci_cmd &= ~PCI_COMMAND_SERR;
	54	if (hpp->enable_perr)
	55	pci_cmd \|= PCI_COMMAND_PARITY;
	56	else
	57	pci_cmd &= ~PCI_COMMAND_PARITY;
	58	pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
	59
	60	/* Program bridge control value */
	61	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	62	pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
	63	hpp->latency_timer);
	64	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
	65	if (hpp->enable_serr)
	66	pci_bctl \|= PCI_BRIDGE_CTL_SERR;
	67	else
	68	pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
	69	if (hpp->enable_perr)
	70	pci_bctl \|= PCI_BRIDGE_CTL_PARITY;
	71	else
	72	pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
	73	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
	74	}
	75	}
	76
	77	static void program_hpp_type2(struct pci_dev dev, struct hpp_type2 hpp)
	78	{
	79	int pos;
	80	u16 reg16;
	81	u32 reg32;
	82
	83	if (hpp->revision > 1) {
	84	printk(KERN_WARNING "%s: Rev.%d type2 record not supported\n",
	85	__FUNCTION__, hpp->revision);
	86	return;
	87	}
	88
	89	/* Find PCI Express capability */
	90	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
	91	if (!pos)
	92	return;
	93
	94	/* Initialize Device Control Register */
	95	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
	96	reg16 = (reg16 & hpp->pci_exp_devctl_and) \| hpp->pci_exp_devctl_or;
	97	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
	98
	99	/* Initialize Link Control Register */
	100	if (dev->subordinate) {
101	pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16);
102	reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
103	\| hpp->pci_exp_lnkctl_or;
104	pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
105	}
106
107	/* Find Advanced Error Reporting Enhanced Capability */
9515930e	108	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
40abb96c KK	109	if (!pos)
	110	return;
	111
	112	/* Initialize Uncorrectable Error Mask Register */
	113	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
	114	reg32 = (reg32 & hpp->unc_err_mask_and) \| hpp->unc_err_mask_or;
	115	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
	116
	117	/* Initialize Uncorrectable Error Severity Register */
	118	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
	119	reg32 = (reg32 & hpp->unc_err_sever_and) \| hpp->unc_err_sever_or;
	120	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
	121
	122	/* Initialize Correctable Error Mask Register */
	123	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
	124	reg32 = (reg32 & hpp->cor_err_mask_and) \| hpp->cor_err_mask_or;
	125	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
	126
	127	/* Initialize Advanced Error Capabilities and Control Register */
	128	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
	129	reg32 = (reg32 & hpp->adv_err_cap_and) \| hpp->adv_err_cap_or;
	130	pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
	131
	132	/*
	133	* FIXME: The following two registers are not supported yet.
	134	*
	135	* o Secondary Uncorrectable Error Severity Register
	136	* o Secondary Uncorrectable Error Mask Register
	137	*/
	138	}
	139
	140	static void program_fw_provided_values(struct pci_dev *dev)
	141	{
	142	struct pci_dev *cdev;
	143	struct hotplug_params hpp;
	144
	145	/* Program hpp values for this device */
	146	if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL \|\|
	147	(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
	148	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
	149	return;
	150
	151	if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
	152	printk(KERN_WARNING "%s: Could not get hotplug parameters\n",
	153	__FUNCTION__);
	154	return;
	155	}
	156
	157	if (hpp.t2)
	158	program_hpp_type2(dev, hpp.t2);
	159	if (hpp.t0)
	160	program_hpp_type0(dev, hpp.t0);
	161
	162	/* Program child devices */
	163	if (dev->subordinate) {
	164	list_for_each_entry(cdev, &dev->subordinate->devices,
	165	bus_list)
	166	program_fw_provided_values(cdev);
	167	}
	168	}
	169
0ab2b57f	170	static int __ref pciehp_add_bridge(struct pci_dev *dev)
0eb3bcfd RS	171	{
	172	struct pci_bus *parent = dev->bus;
	173	int pass, busnr, start = parent->secondary;
	174	int end = parent->subordinate;
	175
	176	for (busnr = start; busnr <= end; busnr++) {
	177	if (!pci_find_bus(pci_domain_nr(parent), busnr))
	178	break;
	179	}
	180	if (busnr-- > end) {
	181	err("No bus number available for hot-added bridge %s\n",
	182	pci_name(dev));
	183	return -1;
	184	}
	185	for (pass = 0; pass < 2; pass++)
	186	busnr = pci_scan_bridge(parent, dev, busnr, pass);
	187	if (!dev->subordinate)
	188	return -1;
	189	pci_bus_size_bridges(dev->subordinate);
	190	pci_bus_assign_resources(parent);
	191	pci_enable_bridges(parent);
	192	pci_bus_add_devices(parent);
	193	return 0;
	194	}
1da177e4	195
71b720c0	196	int pciehp_configure_device(struct slot *p_slot)
1da177e4	197	{
71b720c0	198	struct pci_dev *dev;
	199	struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
	200	int num, fn;
	201
56bfada3	202	dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
71b720c0	203	if (dev) {
	204	err("Device %s already exists at %x:%x, cannot hot-add\n",
	205	pci_name(dev), p_slot->bus, p_slot->device);
56bfada3	206	pci_dev_put(dev);
71b720c0	207	return -EINVAL;
1da177e4 LT	208	}
1da177e4 LT	209
71b720c0	210	num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
	211	if (num == 0) {
	212	err("No new device found\n");
	213	return -ENODEV;
	214	}
1da177e4	215
71b720c0	216	for (fn = 0; fn < 8; fn++) {
0eb3bcfd RS	217	dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
0eb3bcfd RS	218	if (!dev)
71b720c0	219	continue;
	220	if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
	221	err("Cannot hot-add display device %s\n",
	222	pci_name(dev));
6e33706b	223	pci_dev_put(dev);
71b720c0	224	continue;
	225	}
	226	if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) \|\|
	227	(dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
0eb3bcfd	228	pciehp_add_bridge(dev);
71b720c0	229	}
40abb96c	230	program_fw_provided_values(dev);
6e33706b	231	pci_dev_put(dev);
1da177e4 LT	232	}
1da177e4 LT	233
71b720c0	234	pci_bus_assign_resources(parent);
71b720c0	235	pci_bus_add_devices(parent);
1da177e4 LT	236	return 0;
	237	}
	238
ca22a5e4	239	int pciehp_unconfigure_device(struct slot *p_slot)
1da177e4	240	{
1cf53d5d	241	int ret, rc = 0;
1da177e4	242	int j;
ca22a5e4	243	u8 bctl = 0;
1cf53d5d	244	u8 presence = 0;
56bfada3	245	struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
2326e2b9	246	u16 command;
1da177e4	247
ca22a5e4	248	dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
ca22a5e4	249	p_slot->device);
2326e2b9 KK	250	ret = p_slot->hpc_ops->get_adapter_status(p_slot, &presence);
	251	if (ret)
	252	presence = 0;
1da177e4	253
f07234b6	254	for (j = 0; j < 8; j++) {
56bfada3	255	struct pci_dev* temp = pci_get_slot(parent,
ca22a5e4	256	(p_slot->device << 3) \| j);
	257	if (!temp)
	258	continue;
	259	if ((temp->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
	260	err("Cannot remove display device %s\n",
	261	pci_name(temp));
56bfada3	262	pci_dev_put(temp);
ca22a5e4	263	continue;
ca22a5e4	264	}
2326e2b9 KK	265	if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
	266	pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
	267	if (bctl & PCI_BRIDGE_CTL_VGA) {
	268	err("Cannot remove display device %s\n",
	269	pci_name(temp));
	270	pci_dev_put(temp);
	271	continue;
ca22a5e4	272	}
1da177e4	273	}
ca22a5e4	274	pci_remove_bus_device(temp);
2326e2b9 KK	275	/*
	276	* Ensure that no new Requests will be generated from
	277	* the device.
	278	*/
	279	if (presence) {
	280	pci_read_config_word(temp, PCI_COMMAND, &command);
	281	command &= ~(PCI_COMMAND_MASTER \| PCI_COMMAND_SERR);
	282	command \|= PCI_COMMAND_INTX_DISABLE;
	283	pci_write_config_word(temp, PCI_COMMAND, command);
	284	}
56bfada3	285	pci_dev_put(temp);
1da177e4	286	}
9fe81645	287	/*
1da177e4 LT	288	* Some PCI Express root ports require fixup after hot-plug operation.
1da177e4 LT	289	*/
9fe81645	290	if (pcie_mch_quirk)
ca22a5e4	291	pci_fixup_device(pci_fixup_final, p_slot->ctrl->pci_dev);
9fe81645	292
1da177e4 LT	293	return rc;
1da177e4 LT	294	}