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[PATCH] PCI: kzalloc() conversion in drivers/pci
[linux-2.6-block.git] / drivers / pci / hotplug / pciehp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
de25968c
TS		 33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
1da177e4 36#include <linux/pci.h>
5d1b8c9e
AM		 37#include <linux/interrupt.h>
38
1da177e4
LT		 39#include "../pci.h"
40#include "pciehp.h"
41
42#ifdef DEBUG
43#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49/* Redefine this flagword to set debug level */
50#define DEBUG_LEVEL DBG_K_STANDARD
51
52#define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
53
54#define DBG_PRINT( dbg_flags, args... ) \
55 do { \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
57 { \
58 int len; \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
63 } \
64 } while (0)
65
66#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
68#else
69#define DEFINE_DBG_BUFFER
70#define DBG_ENTER_ROUTINE
71#define DBG_LEAVE_ROUTINE
72#endif /* DEBUG */
73
74struct ctrl_reg {
75 u8 cap_id;
76 u8 nxt_ptr;
77 u16 cap_reg;
78 u32 dev_cap;
79 u16 dev_ctrl;
80 u16 dev_status;
81 u32 lnk_cap;
82 u16 lnk_ctrl;
83 u16 lnk_status;
84 u32 slot_cap;
85 u16 slot_ctrl;
86 u16 slot_status;
87 u16 root_ctrl;
88 u16 rsvp;
89 u32 root_status;
90} __attribute__ ((packed));
91
92/* offsets to the controller registers based on the above structure layout */
93enum ctrl_offsets {
94 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
95 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
96 CAPREG = offsetof(struct ctrl_reg, cap_reg),
97 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
98 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
99 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
100 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
101 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
102 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
103 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
104 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
105 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
106 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
107 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
108};
109static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
110
8b245e45
DS		 111#define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
112#define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
113#define CAP_REG(cb) ( cb + CAPREG )
114#define DEV_CAP(cb) ( cb + DEVCAP )
115#define DEV_CTRL(cb) ( cb + DEVCTRL )
116#define DEV_STATUS(cb) ( cb + DEVSTATUS )
117#define LNK_CAP(cb) ( cb + LNKCAP )
118#define LNK_CTRL(cb) ( cb + LNKCTRL )
119#define LNK_STATUS(cb) ( cb + LNKSTATUS )
120#define SLOT_CAP(cb) ( cb + SLOTCAP )
121#define SLOT_CTRL(cb) ( cb + SLOTCTRL )
122#define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
123#define ROOT_CTRL(cb) ( cb + ROOTCTRL )
124#define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
1da177e4
LT		 125
126#define hp_register_read_word(pdev, reg , value) \
127 pci_read_config_word(pdev, reg, &value)
128
129#define hp_register_read_dword(pdev, reg , value) \
130 pci_read_config_dword(pdev, reg, &value)
131
132#define hp_register_write_word(pdev, reg , value) \
133 pci_write_config_word(pdev, reg, value)
134
135#define hp_register_dwrite_word(pdev, reg , value) \
136 pci_write_config_dword(pdev, reg, value)
137
138/* Field definitions in PCI Express Capabilities Register */
139#define CAP_VER 0x000F
140#define DEV_PORT_TYPE 0x00F0
141#define SLOT_IMPL 0x0100
142#define MSG_NUM 0x3E00
143
144/* Device or Port Type */
145#define NAT_ENDPT 0x00
146#define LEG_ENDPT 0x01
147#define ROOT_PORT 0x04
148#define UP_STREAM 0x05
149#define DN_STREAM 0x06
150#define PCIE_PCI_BRDG 0x07
151#define PCI_PCIE_BRDG 0x10
152
153/* Field definitions in Device Capabilities Register */
154#define DATTN_BUTTN_PRSN 0x1000
155#define DATTN_LED_PRSN 0x2000
156#define DPWR_LED_PRSN 0x4000
157
158/* Field definitions in Link Capabilities Register */
159#define MAX_LNK_SPEED 0x000F
160#define MAX_LNK_WIDTH 0x03F0
161
162/* Link Width Encoding */
163#define LNK_X1 0x01
164#define LNK_X2 0x02
165#define LNK_X4 0x04
166#define LNK_X8 0x08
167#define LNK_X12 0x0C
168#define LNK_X16 0x10
169#define LNK_X32 0x20
170
171/*Field definitions of Link Status Register */
172#define LNK_SPEED 0x000F
173#define NEG_LINK_WD 0x03F0
174#define LNK_TRN_ERR 0x0400
175#define LNK_TRN 0x0800
176#define SLOT_CLK_CONF 0x1000
177
178/* Field definitions in Slot Capabilities Register */
179#define ATTN_BUTTN_PRSN 0x00000001
180#define PWR_CTRL_PRSN 0x00000002
181#define MRL_SENS_PRSN 0x00000004
182#define ATTN_LED_PRSN 0x00000008
183#define PWR_LED_PRSN 0x00000010
184#define HP_SUPR_RM_SUP 0x00000020
185#define HP_CAP 0x00000040
186#define SLOT_PWR_VALUE 0x000003F8
187#define SLOT_PWR_LIMIT 0x00000C00
188#define PSN 0xFFF80000 /* PSN: Physical Slot Number */
189
190/* Field definitions in Slot Control Register */
191#define ATTN_BUTTN_ENABLE 0x0001
192#define PWR_FAULT_DETECT_ENABLE 0x0002
193#define MRL_DETECT_ENABLE 0x0004
194#define PRSN_DETECT_ENABLE 0x0008
195#define CMD_CMPL_INTR_ENABLE 0x0010
196#define HP_INTR_ENABLE 0x0020
197#define ATTN_LED_CTRL 0x00C0
198#define PWR_LED_CTRL 0x0300
199#define PWR_CTRL 0x0400
200
201/* Attention indicator and Power indicator states */
202#define LED_ON 0x01
203#define LED_BLINK 0x10
204#define LED_OFF 0x11
205
206/* Power Control Command */
207#define POWER_ON 0
208#define POWER_OFF 0x0400
209
210/* Field definitions in Slot Status Register */
211#define ATTN_BUTTN_PRESSED 0x0001
212#define PWR_FAULT_DETECTED 0x0002
213#define MRL_SENS_CHANGED 0x0004
214#define PRSN_DETECT_CHANGED 0x0008
215#define CMD_COMPLETED 0x0010
216#define MRL_STATE 0x0020
217#define PRSN_STATE 0x0040
218
1da177e4
LT		 219static spinlock_t hpc_event_lock;
220
221DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
222static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
223static int ctlr_seq_num = 0; /* Controller sequence # */
224static spinlock_t list_lock;
225
226static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
227
228static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
229
230/* This is the interrupt polling timeout function. */
231static void int_poll_timeout(unsigned long lphp_ctlr)
232{
233 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
234
235 DBG_ENTER_ROUTINE
236
237 if ( !php_ctlr ) {
238 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
239 return;
240 }
241
242 /* Poll for interrupt events. regs == NULL => polling */
243 pcie_isr( 0, (void *)php_ctlr, NULL );
244
245 init_timer(&php_ctlr->int_poll_timer);
246
247 if (!pciehp_poll_time)
248 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
249
250 start_int_poll_timer(php_ctlr, pciehp_poll_time);
251
252 return;
253}
254
255/* This function starts the interrupt polling timer. */
256static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
257{
258 if (!php_ctlr) {
259 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
260 return;
261 }
262
263 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
264 seconds = 2; /* Clamp to sane value */
265
266 php_ctlr->int_poll_timer.function = &int_poll_timeout;
267 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
268 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
269 add_timer(&php_ctlr->int_poll_timer);
270
271 return;
272}
273
274static int pcie_write_cmd(struct slot *slot, u16 cmd)
275{
276 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
277 int retval = 0;
278 u16 slot_status;
279
280 DBG_ENTER_ROUTINE
281
1da177e4
LT		 282 if (!php_ctlr) {
283 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
284 return -1;
285 }
286
8b245e45 287 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 288 if (retval) {
289 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
290 return retval;
291 }
1da177e4
LT		 292
293 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
294 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
295 the next command according to spec. Just print out the error message */
296 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
297 }
298
8b245e45 299 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
1da177e4
LT		 300 if (retval) {
301 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
302 return retval;
303 }
1da177e4
LT		 304
305 DBG_LEAVE_ROUTINE
306 return retval;
307}
308
309static int hpc_check_lnk_status(struct controller *ctrl)
310{
311 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
312 u16 lnk_status;
313 int retval = 0;
314
315 DBG_ENTER_ROUTINE
316
317 if (!php_ctlr) {
318 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
319 return -1;
320 }
321
8b245e45 322 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
1da177e4
LT		 323
324 if (retval) {
325 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
326 return retval;
327 }
328
329 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
330 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
331 !(lnk_status & NEG_LINK_WD)) {
332 err("%s : Link Training Error occurs \n", __FUNCTION__);
333 retval = -1;
334 return retval;
335 }
336
337 DBG_LEAVE_ROUTINE
338 return retval;
339}
340
341
342static int hpc_get_attention_status(struct slot *slot, u8 *status)
343{
344 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
345 u16 slot_ctrl;
346 u8 atten_led_state;
347 int retval = 0;
348
349 DBG_ENTER_ROUTINE
350
351 if (!php_ctlr) {
352 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
353 return -1;
354 }
355
8b245e45 356 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 357
358 if (retval) {
359 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
360 return retval;
361 }
362
8b245e45 363 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 364
365 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
366
367 switch (atten_led_state) {
368 case 0:
369 *status = 0xFF; /* Reserved */
370 break;
371 case 1:
372 *status = 1; /* On */
373 break;
374 case 2:
375 *status = 2; /* Blink */
376 break;
377 case 3:
378 *status = 0; /* Off */
379 break;
380 default:
381 *status = 0xFF;
382 break;
383 }
384
385 DBG_LEAVE_ROUTINE
386 return 0;
387}
388
389static int hpc_get_power_status(struct slot * slot, u8 *status)
390{
391 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
392 u16 slot_ctrl;
393 u8 pwr_state;
394 int retval = 0;
395
396 DBG_ENTER_ROUTINE
397
398 if (!php_ctlr) {
399 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
400 return -1;
401 }
402
8b245e45 403 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 404
405 if (retval) {
406 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
407 return retval;
408 }
8b245e45 409 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 410
411 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
412
413 switch (pwr_state) {
414 case 0:
415 *status = 1;
416 break;
417 case 1:
418 *status = 0;
419 break;
420 default:
421 *status = 0xFF;
422 break;
423 }
424
425 DBG_LEAVE_ROUTINE
426 return retval;
427}
428
429
430static int hpc_get_latch_status(struct slot *slot, u8 *status)
431{
432 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
433 u16 slot_status;
434 int retval = 0;
435
436 DBG_ENTER_ROUTINE
437
438 if (!php_ctlr) {
439 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
440 return -1;
441 }
442
8b245e45 443 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 444
445 if (retval) {
446 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
447 return retval;
448 }
449
450 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
451
452 DBG_LEAVE_ROUTINE
453 return 0;
454}
455
456static int hpc_get_adapter_status(struct slot *slot, u8 *status)
457{
458 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
459 u16 slot_status;
460 u8 card_state;
461 int retval = 0;
462
463 DBG_ENTER_ROUTINE
464
465 if (!php_ctlr) {
466 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
467 return -1;
468 }
469
8b245e45 470 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 471
472 if (retval) {
473 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
474 return retval;
475 }
476 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
477 *status = (card_state == 1) ? 1 : 0;
478
479 DBG_LEAVE_ROUTINE
480 return 0;
481}
482
483static int hpc_query_power_fault(struct slot * slot)
484{
485 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
486 u16 slot_status;
487 u8 pwr_fault;
488 int retval = 0;
1da177e4
LT		 489
490 DBG_ENTER_ROUTINE
491
492 if (!php_ctlr) {
493 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
494 return -1;
495 }
496
8b245e45 497 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 498
499 if (retval) {
8239def1 500 err("%s : Cannot check for power fault\n", __FUNCTION__);
1da177e4
LT		 501 return retval;
502 }
503 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
1da177e4
LT		 504
505 DBG_LEAVE_ROUTINE
8239def1 506 return pwr_fault;
1da177e4
LT		 507}
508
509static int hpc_set_attention_status(struct slot *slot, u8 value)
510{
511 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
512 u16 slot_cmd = 0;
513 u16 slot_ctrl;
514 int rc = 0;
515
1a9ed1bf 516 DBG_ENTER_ROUTINE
517
1da177e4
LT		 518 if (!php_ctlr) {
519 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
520 return -1;
521 }
522
523 if (slot->hp_slot >= php_ctlr->num_slots) {
524 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
525 return -1;
526 }
8b245e45 527 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 528
529 if (rc) {
530 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
531 return rc;
532 }
1da177e4
LT		 533
534 switch (value) {
535 case 0 : /* turn off */
536 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
537 break;
538 case 1: /* turn on */
539 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
540 break;
541 case 2: /* turn blink */
542 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
543 break;
544 default:
545 return -1;
546 }
547 if (!pciehp_poll_mode)
548 slot_cmd = slot_cmd | HP_INTR_ENABLE;
549
550 pcie_write_cmd(slot, slot_cmd);
8b245e45 551 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4 552
1a9ed1bf 553 DBG_LEAVE_ROUTINE
1da177e4
LT		 554 return rc;
555}
556
557
558static void hpc_set_green_led_on(struct slot *slot)
559{
560 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
561 u16 slot_cmd;
562 u16 slot_ctrl;
563 int rc = 0;
564
1a9ed1bf 565 DBG_ENTER_ROUTINE
566
1da177e4
LT		 567 if (!php_ctlr) {
568 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
569 return ;
570 }
571
572 if (slot->hp_slot >= php_ctlr->num_slots) {
573 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
574 return ;
575 }
576
8b245e45 577 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 578
579 if (rc) {
580 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
581 return;
582 }
1da177e4
LT		 583 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
584 if (!pciehp_poll_mode)
585 slot_cmd = slot_cmd | HP_INTR_ENABLE;
586
587 pcie_write_cmd(slot, slot_cmd);
588
8b245e45 589 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1a9ed1bf 590 DBG_LEAVE_ROUTINE
1da177e4
LT		 591 return;
592}
593
594static void hpc_set_green_led_off(struct slot *slot)
595{
596 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
597 u16 slot_cmd;
598 u16 slot_ctrl;
599 int rc = 0;
600
1a9ed1bf 601 DBG_ENTER_ROUTINE
602
1da177e4
LT		 603 if (!php_ctlr) {
604 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
605 return ;
606 }
607
608 if (slot->hp_slot >= php_ctlr->num_slots) {
609 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
610 return ;
611 }
612
8b245e45 613 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 614
615 if (rc) {
616 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
617 return;
618 }
1da177e4
LT		 619
620 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
621
622 if (!pciehp_poll_mode)
623 slot_cmd = slot_cmd | HP_INTR_ENABLE;
624 pcie_write_cmd(slot, slot_cmd);
8b245e45 625 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4 626
1a9ed1bf 627 DBG_LEAVE_ROUTINE
1da177e4
LT		 628 return;
629}
630
631static void hpc_set_green_led_blink(struct slot *slot)
632{
633 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
634 u16 slot_cmd;
635 u16 slot_ctrl;
636 int rc = 0;
637
1a9ed1bf 638 DBG_ENTER_ROUTINE
639
1da177e4
LT		 640 if (!php_ctlr) {
641 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
642 return ;
643 }
644
645 if (slot->hp_slot >= php_ctlr->num_slots) {
646 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
647 return ;
648 }
649
8b245e45 650 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 651
652 if (rc) {
653 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
654 return;
655 }
1da177e4
LT		 656
657 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
658
659 if (!pciehp_poll_mode)
660 slot_cmd = slot_cmd | HP_INTR_ENABLE;
661 pcie_write_cmd(slot, slot_cmd);
662
8b245e45 663 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1a9ed1bf 664 DBG_LEAVE_ROUTINE
1da177e4
LT		 665 return;
666}
667
668int pcie_get_ctlr_slot_config(struct controller *ctrl,
669 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
670 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
671 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
672 u8 *ctrlcap)
673{
674 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
675 u32 slot_cap;
676 int rc = 0;
677
678 DBG_ENTER_ROUTINE
679
680 if (!php_ctlr) {
681 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
682 return -1;
683 }
684
685 *first_device_num = 0;
686 *num_ctlr_slots = 1;
687
8b245e45 688 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 689
690 if (rc) {
691 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
692 return -1;
693 }
694
695 *physical_slot_num = slot_cap >> 19;
696 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
697
698 *ctrlcap = slot_cap & 0x0000007f;
699
700 DBG_LEAVE_ROUTINE
701 return 0;
702}
703
704static void hpc_release_ctlr(struct controller *ctrl)
705{
706 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
707 struct php_ctlr_state_s *p, *p_prev;
708
709 DBG_ENTER_ROUTINE
710
711 if (!php_ctlr) {
712 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
713 return ;
714 }
715
716 if (pciehp_poll_mode) {
717 del_timer(&php_ctlr->int_poll_timer);
718 } else {
719 if (php_ctlr->irq) {
720 free_irq(php_ctlr->irq, ctrl);
721 php_ctlr->irq = 0;
722 if (!pcie_mch_quirk)
723 pci_disable_msi(php_ctlr->pci_dev);
724 }
725 }
726 if (php_ctlr->pci_dev)
727 php_ctlr->pci_dev = NULL;
728
729 spin_lock(&list_lock);
730 p = php_ctlr_list_head;
731 p_prev = NULL;
732 while (p) {
733 if (p == php_ctlr) {
734 if (p_prev)
735 p_prev->pnext = p->pnext;
736 else
737 php_ctlr_list_head = p->pnext;
738 break;
739 } else {
740 p_prev = p;
741 p = p->pnext;
742 }
743 }
744 spin_unlock(&list_lock);
745
746 kfree(php_ctlr);
747
748 DBG_LEAVE_ROUTINE
749
750}
751
752static int hpc_power_on_slot(struct slot * slot)
753{
754 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
755 u16 slot_cmd;
5a49f203 756 u16 slot_ctrl, slot_status;
1da177e4
LT		 757
758 int retval = 0;
759
760 DBG_ENTER_ROUTINE
1da177e4
LT		 761
762 if (!php_ctlr) {
763 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
764 return -1;
765 }
766
767 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
768 if (slot->hp_slot >= php_ctlr->num_slots) {
769 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
770 return -1;
771 }
772
5a49f203
RS		 773 /* Clear sticky power-fault bit from previous power failures */
774 hp_register_read_word(php_ctlr->pci_dev,
775 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
776 slot_status &= PWR_FAULT_DETECTED;
777 if (slot_status)
778 hp_register_write_word(php_ctlr->pci_dev,
779 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
780
8b245e45 781 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 782
783 if (retval) {
784 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
785 return retval;
786 }
1da177e4
LT		 787
788 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
789
c7ab337f 790 /* Enable detection that we turned off at slot power-off time */
1da177e4 791 if (!pciehp_poll_mode)
c7ab337f
TS		 792 slot_cmd = slot_cmd |
793 PWR_FAULT_DETECT_ENABLE |
794 MRL_DETECT_ENABLE |
795 PRSN_DETECT_ENABLE |
796 HP_INTR_ENABLE;
1da177e4
LT		 797
798 retval = pcie_write_cmd(slot, slot_cmd);
799
800 if (retval) {
801 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
802 return -1;
803 }
8b245e45 804 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4
LT		 805
806 DBG_LEAVE_ROUTINE
807
808 return retval;
809}
810
811static int hpc_power_off_slot(struct slot * slot)
812{
813 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
814 u16 slot_cmd;
815 u16 slot_ctrl;
816
817 int retval = 0;
818
819 DBG_ENTER_ROUTINE
1da177e4
LT		 820
821 if (!php_ctlr) {
822 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
823 return -1;
824 }
825
826 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
827 slot->hp_slot = 0;
828 if (slot->hp_slot >= php_ctlr->num_slots) {
829 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
830 return -1;
831 }
8b245e45 832 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 833
834 if (retval) {
835 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
836 return retval;
837 }
1da177e4
LT		 838
839 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
840
c7ab337f
TS		 841 /*
842 * If we get MRL or presence detect interrupts now, the isr
843 * will notice the sticky power-fault bit too and issue power
844 * indicator change commands. This will lead to an endless loop
845 * of command completions, since the power-fault bit remains on
846 * till the slot is powered on again.
847 */
1da177e4 848 if (!pciehp_poll_mode)
c7ab337f
TS		 849 slot_cmd = (slot_cmd &
850 ~PWR_FAULT_DETECT_ENABLE &
851 ~MRL_DETECT_ENABLE &
852 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
1da177e4
LT		 853
854 retval = pcie_write_cmd(slot, slot_cmd);
855
856 if (retval) {
857 err("%s: Write command failed!\n", __FUNCTION__);
858 return -1;
859 }
8b245e45 860 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4
LT		 861
862 DBG_LEAVE_ROUTINE
863
864 return retval;
865}
866
867static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
868{
869 struct controller *ctrl = NULL;
870 struct php_ctlr_state_s *php_ctlr;
871 u8 schedule_flag = 0;
872 u16 slot_status, intr_detect, intr_loc;
873 u16 temp_word;
874 int hp_slot = 0; /* only 1 slot per PCI Express port */
875 int rc = 0;
876
877 if (!dev_id)
878 return IRQ_NONE;
879
880 if (!pciehp_poll_mode) {
881 ctrl = dev_id;
882 php_ctlr = ctrl->hpc_ctlr_handle;
883 } else {
884 php_ctlr = dev_id;
885 ctrl = (struct controller *)php_ctlr->callback_instance_id;
886 }
887
888 if (!ctrl) {
889 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
890 return IRQ_NONE;
891 }
892
893 if (!php_ctlr) {
894 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
895 return IRQ_NONE;
896 }
897
8b245e45 898 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 899 if (rc) {
900 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
901 return IRQ_NONE;
902 }
903
904 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
905 PRSN_DETECT_CHANGED | CMD_COMPLETED );
906
907 intr_loc = slot_status & intr_detect;
908
909 /* Check to see if it was our interrupt */
910 if ( !intr_loc )
911 return IRQ_NONE;
912
913 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
914 /* Mask Hot-plug Interrupt Enable */
915 if (!pciehp_poll_mode) {
8b245e45 916 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 917 if (rc) {
918 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
919 return IRQ_NONE;
920 }
921
1da177e4
LT		 922 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
923 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
924
8b245e45 925 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 926 if (rc) {
927 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
928 return IRQ_NONE;
929 }
1da177e4 930
8b245e45 931 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 932 if (rc) {
933 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
934 return IRQ_NONE;
935 }
936 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
937
938 /* Clear command complete interrupt caused by this write */
939 temp_word = 0x1f;
8b245e45 940 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 941 if (rc) {
942 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
943 return IRQ_NONE;
944 }
1da177e4
LT		 945 }
946
947 if (intr_loc & CMD_COMPLETED) {
948 /*
949 * Command Complete Interrupt Pending
950 */
1da177e4
LT		 951 wake_up_interruptible(&ctrl->queue);
952 }
953
954 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
955 schedule_flag += php_ctlr->switch_change_callback(
956 hp_slot, php_ctlr->callback_instance_id);
957 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
958 schedule_flag += php_ctlr->attention_button_callback(
959 hp_slot, php_ctlr->callback_instance_id);
960 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
961 schedule_flag += php_ctlr->presence_change_callback(
962 hp_slot , php_ctlr->callback_instance_id);
963 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
964 schedule_flag += php_ctlr->power_fault_callback(
965 hp_slot, php_ctlr->callback_instance_id);
966
967 /* Clear all events after serving them */
968 temp_word = 0x1F;
8b245e45 969 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 970 if (rc) {
971 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
972 return IRQ_NONE;
973 }
974 /* Unmask Hot-plug Interrupt Enable */
975 if (!pciehp_poll_mode) {
8b245e45 976 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 977 if (rc) {
978 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
979 return IRQ_NONE;
980 }
981
982 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
1da177e4
LT		 983 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
984
8b245e45 985 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 986 if (rc) {
987 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
988 return IRQ_NONE;
989 }
1da177e4 990
8b245e45 991 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 992 if (rc) {
993 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
994 return IRQ_NONE;
995 }
1da177e4
LT		 996
997 /* Clear command complete interrupt caused by this write */
998 temp_word = 0x1F;
8b245e45 999 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 1000 if (rc) {
1001 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1002 return IRQ_NONE;
1003 }
1004 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1005 }
1006
1007 return IRQ_HANDLED;
1008}
1009
1010static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1011{
1012 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1013 enum pcie_link_speed lnk_speed;
1014 u32 lnk_cap;
1015 int retval = 0;
1016
1017 DBG_ENTER_ROUTINE
1018
1019 if (!php_ctlr) {
1020 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1021 return -1;
1022 }
1023
1024 if (slot->hp_slot >= php_ctlr->num_slots) {
1025 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1026 return -1;
1027 }
1028
8b245e45 1029 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1da177e4
LT		 1030
1031 if (retval) {
1032 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1033 return retval;
1034 }
1035
1036 switch (lnk_cap & 0x000F) {
1037 case 1:
1038 lnk_speed = PCIE_2PT5GB;
1039 break;
1040 default:
1041 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1042 break;
1043 }
1044
1045 *value = lnk_speed;
1046 dbg("Max link speed = %d\n", lnk_speed);
1047 DBG_LEAVE_ROUTINE
1048 return retval;
1049}
1050
1051static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1052{
1053 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1054 enum pcie_link_width lnk_wdth;
1055 u32 lnk_cap;
1056 int retval = 0;
1057
1058 DBG_ENTER_ROUTINE
1059
1060 if (!php_ctlr) {
1061 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1062 return -1;
1063 }
1064
1065 if (slot->hp_slot >= php_ctlr->num_slots) {
1066 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1067 return -1;
1068 }
1069
8b245e45 1070 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1da177e4
LT		 1071
1072 if (retval) {
1073 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1074 return retval;
1075 }
1076
1077 switch ((lnk_cap & 0x03F0) >> 4){
1078 case 0:
1079 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1080 break;
1081 case 1:
1082 lnk_wdth = PCIE_LNK_X1;
1083 break;
1084 case 2:
1085 lnk_wdth = PCIE_LNK_X2;
1086 break;
1087 case 4:
1088 lnk_wdth = PCIE_LNK_X4;
1089 break;
1090 case 8:
1091 lnk_wdth = PCIE_LNK_X8;
1092 break;
1093 case 12:
1094 lnk_wdth = PCIE_LNK_X12;
1095 break;
1096 case 16:
1097 lnk_wdth = PCIE_LNK_X16;
1098 break;
1099 case 32:
1100 lnk_wdth = PCIE_LNK_X32;
1101 break;
1102 default:
1103 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1104 break;
1105 }
1106
1107 *value = lnk_wdth;
1108 dbg("Max link width = %d\n", lnk_wdth);
1109 DBG_LEAVE_ROUTINE
1110 return retval;
1111}
1112
1113static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1114{
1115 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1116 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1117 int retval = 0;
1118 u16 lnk_status;
1119
1120 DBG_ENTER_ROUTINE
1121
1122 if (!php_ctlr) {
1123 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1124 return -1;
1125 }
1126
1127 if (slot->hp_slot >= php_ctlr->num_slots) {
1128 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1129 return -1;
1130 }
1131
8b245e45 1132 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1da177e4
LT		 1133
1134 if (retval) {
1135 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1136 return retval;
1137 }
1138
1139 switch (lnk_status & 0x0F) {
1140 case 1:
1141 lnk_speed = PCIE_2PT5GB;
1142 break;
1143 default:
1144 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1145 break;
1146 }
1147
1148 *value = lnk_speed;
1149 dbg("Current link speed = %d\n", lnk_speed);
1150 DBG_LEAVE_ROUTINE
1151 return retval;
1152}
1153
1154static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1155{
1156 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1157 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1158 int retval = 0;
1159 u16 lnk_status;
1160
1161 DBG_ENTER_ROUTINE
1162
1163 if (!php_ctlr) {
1164 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1165 return -1;
1166 }
1167
1168 if (slot->hp_slot >= php_ctlr->num_slots) {
1169 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1170 return -1;
1171 }
1172
8b245e45 1173 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1da177e4
LT		 1174
1175 if (retval) {
1176 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1177 return retval;
1178 }
1179
1180 switch ((lnk_status & 0x03F0) >> 4){
1181 case 0:
1182 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1183 break;
1184 case 1:
1185 lnk_wdth = PCIE_LNK_X1;
1186 break;
1187 case 2:
1188 lnk_wdth = PCIE_LNK_X2;
1189 break;
1190 case 4:
1191 lnk_wdth = PCIE_LNK_X4;
1192 break;
1193 case 8:
1194 lnk_wdth = PCIE_LNK_X8;
1195 break;
1196 case 12:
1197 lnk_wdth = PCIE_LNK_X12;
1198 break;
1199 case 16:
1200 lnk_wdth = PCIE_LNK_X16;
1201 break;
1202 case 32:
1203 lnk_wdth = PCIE_LNK_X32;
1204 break;
1205 default:
1206 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1207 break;
1208 }
1209
1210 *value = lnk_wdth;
1211 dbg("Current link width = %d\n", lnk_wdth);
1212 DBG_LEAVE_ROUTINE
1213 return retval;
1214}
1215
1216static struct hpc_ops pciehp_hpc_ops = {
1217 .power_on_slot = hpc_power_on_slot,
1218 .power_off_slot = hpc_power_off_slot,
1219 .set_attention_status = hpc_set_attention_status,
1220 .get_power_status = hpc_get_power_status,
1221 .get_attention_status = hpc_get_attention_status,
1222 .get_latch_status = hpc_get_latch_status,
1223 .get_adapter_status = hpc_get_adapter_status,
1224
1225 .get_max_bus_speed = hpc_get_max_lnk_speed,
1226 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1227 .get_max_lnk_width = hpc_get_max_lnk_width,
1228 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1229
1230 .query_power_fault = hpc_query_power_fault,
1231 .green_led_on = hpc_set_green_led_on,
1232 .green_led_off = hpc_set_green_led_off,
1233 .green_led_blink = hpc_set_green_led_blink,
1234
1235 .release_ctlr = hpc_release_ctlr,
1236 .check_lnk_status = hpc_check_lnk_status,
1237};
1238
ed6cbcf2 1239int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1da177e4
LT		 1240{
1241 struct php_ctlr_state_s *php_ctlr, *p;
1242 void *instance_id = ctrl;
1243 int rc;
1244 static int first = 1;
1245 u16 temp_word;
1246 u16 cap_reg;
1247 u16 intr_enable = 0;
1248 u32 slot_cap;
1249 int cap_base, saved_cap_base;
1250 u16 slot_status, slot_ctrl;
1251 struct pci_dev *pdev;
1252
1253 DBG_ENTER_ROUTINE
1254
1255 spin_lock_init(&list_lock);
1256 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1257
1258 if (!php_ctlr) { /* allocate controller state data */
1259 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1260 goto abort;
1261 }
1262
1263 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1264
1265 pdev = dev->port;
1266 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1267
1a9ed1bf 1268 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1269 __FUNCTION__, pdev->vendor, pdev->device);
1da177e4
LT		 1270
1271 saved_cap_base = pcie_cap_base;
1272
1273 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1274 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1275 goto abort_free_ctlr;
1276 }
1277
8b245e45 1278 ctrl->cap_base = cap_base;
1da177e4
LT		 1279
1280 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1281
8b245e45 1282 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1da177e4
LT		 1283 if (rc) {
1284 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1285 goto abort_free_ctlr;
1286 }
8b245e45 1287 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1da177e4 1288
8b245e45
DS		 1289 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1290 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1da177e4
LT		 1291 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1292 goto abort_free_ctlr;
1293 }
1294
8b245e45 1295 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 1296 if (rc) {
1297 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1298 goto abort_free_ctlr;
1299 }
8b245e45 1300 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 1301
1302 if (!(slot_cap & HP_CAP)) {
1303 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1304 goto abort_free_ctlr;
1305 }
1306 /* For debugging purpose */
8b245e45 1307 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1308 if (rc) {
1309 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1310 goto abort_free_ctlr;
1311 }
8b245e45 1312 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4 1313
8b245e45 1314 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1da177e4
LT		 1315 if (rc) {
1316 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1317 goto abort_free_ctlr;
1318 }
8b245e45 1319 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1da177e4
LT		 1320
1321 if (first) {
1322 spin_lock_init(&hpc_event_lock);
1323 first = 0;
1324 }
1325
1da177e4
LT		 1326 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1327 if (pci_resource_len(pdev, rc) > 0)
1328 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1329 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1330
1331 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1332 pdev->subsystem_vendor, pdev->subsystem_device);
1333
1334 if (pci_enable_device(pdev))
1335 goto abort_free_ctlr;
1336
6aa4cdd0 1337 mutex_init(&ctrl->crit_sect);
1da177e4
LT		 1338 /* setup wait queue */
1339 init_waitqueue_head(&ctrl->queue);
1340
1341 /* find the IRQ */
1342 php_ctlr->irq = dev->irq;
1da177e4
LT		 1343
1344 /* Save interrupt callback info */
ed6cbcf2 1345 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1346 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1347 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1348 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1da177e4
LT		 1349 php_ctlr->callback_instance_id = instance_id;
1350
1351 /* return PCI Controller Info */
1352 php_ctlr->slot_device_offset = 0;
1353 php_ctlr->num_slots = 1;
1354
1355 /* Mask Hot-plug Interrupt Enable */
8b245e45 1356 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1357 if (rc) {
1358 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1359 goto abort_free_ctlr;
1360 }
1361
8b245e45 1362 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1363 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1364
8b245e45 1365 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1366 if (rc) {
1367 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1368 goto abort_free_ctlr;
1369 }
1da177e4 1370
8b245e45 1371 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1372 if (rc) {
1373 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1374 goto abort_free_ctlr;
1375 }
1da177e4
LT		 1376
1377 temp_word = 0x1F; /* Clear all events */
8b245e45 1378 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 1379 if (rc) {
1380 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1381 goto abort_free_ctlr;
1382 }
1da177e4
LT		 1383
1384 if (pciehp_poll_mode) {/* Install interrupt polling code */
1385 /* Install and start the interrupt polling timer */
1386 init_timer(&php_ctlr->int_poll_timer);
1387 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1388 } else {
1389 /* Installs the interrupt handler */
1390 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1391 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1392 if (rc) {
1393 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1394 goto abort_free_ctlr;
1395 }
1396 }
1397
1a9ed1bf 1398 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1399 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1400
8b245e45 1401 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1402 if (rc) {
1403 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1404 goto abort_free_ctlr;
1405 }
1da177e4
LT		 1406
1407 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1408
1409 if (ATTN_BUTTN(slot_cap))
1410 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1411
1412 if (POWER_CTRL(slot_cap))
1413 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1414
1415 if (MRL_SENS(slot_cap))
1416 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1417
1418 temp_word = (temp_word & ~intr_enable) | intr_enable;
1419
1420 if (pciehp_poll_mode) {
1421 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1422 } else {
1423 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1424 }
1da177e4
LT		 1425
1426 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
8b245e45 1427 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1428 if (rc) {
1429 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1430 goto abort_free_ctlr;
1431 }
8b245e45 1432 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1433 if (rc) {
1434 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1435 goto abort_free_ctlr;
1436 }
1da177e4
LT		 1437
1438 temp_word = 0x1F; /* Clear all events */
8b245e45 1439 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 1440 if (rc) {
1441 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1442 goto abort_free_ctlr;
1443 }
1da177e4 1444
a3a45ec8 1445 if (pciehp_force) {
1446 dbg("Bypassing BIOS check for pciehp use on %s\n",
1447 pci_name(ctrl->pci_dev));
1448 } else {
6560aa5c 1449 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
a3a45ec8 1450 if (rc)
1451 goto abort_free_ctlr;
1452 }
a8a2be94 1453
1da177e4
LT		 1454 /* Add this HPC instance into the HPC list */
1455 spin_lock(&list_lock);
1456 if (php_ctlr_list_head == 0) {
1457 php_ctlr_list_head = php_ctlr;
1458 p = php_ctlr_list_head;
1459 p->pnext = NULL;
1460 } else {
1461 p = php_ctlr_list_head;
1462
1463 while (p->pnext)
1464 p = p->pnext;
1465
1466 p->pnext = php_ctlr;
1467 }
1468 spin_unlock(&list_lock);
1469
1470 ctlr_seq_num++;
1471 ctrl->hpc_ctlr_handle = php_ctlr;
1472 ctrl->hpc_ops = &pciehp_hpc_ops;
1473
1474 DBG_LEAVE_ROUTINE
1475 return 0;
1476
1477 /* We end up here for the many possible ways to fail this API. */
1478abort_free_ctlr:
1479 pcie_cap_base = saved_cap_base;
1480 kfree(php_ctlr);
1481abort:
1482 DBG_LEAVE_ROUTINE
1483 return -1;
1484}
Linux 6.x block layer and io_uring tree(s)