Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
a0f018da KK |
45 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
46 | { | |
385e2491 | 47 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 48 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
49 | } |
50 | ||
51 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
52 | { | |
385e2491 | 53 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 54 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
55 | } |
56 | ||
57 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
58 | { | |
385e2491 | 59 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 60 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
61 | } |
62 | ||
63 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
64 | { | |
385e2491 | 65 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 66 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 67 | } |
1da177e4 | 68 | |
1da177e4 LT |
69 | /* Power Control Command */ |
70 | #define POWER_ON 0 | |
322162a7 | 71 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 72 | |
48fe3915 KK |
73 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
74 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
75 | |
76 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 77 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 78 | { |
48fe3915 | 79 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 80 | |
1da177e4 | 81 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 82 | pcie_isr(0, ctrl); |
1da177e4 | 83 | |
48fe3915 | 84 | init_timer(&ctrl->poll_timer); |
1da177e4 | 85 | if (!pciehp_poll_time) |
40730d10 | 86 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 87 | |
48fe3915 | 88 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
89 | } |
90 | ||
91 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 92 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 93 | { |
48fe3915 KK |
94 | /* Clamp to sane value */ |
95 | if ((sec <= 0) || (sec > 60)) | |
96 | sec = 2; | |
97 | ||
98 | ctrl->poll_timer.function = &int_poll_timeout; | |
99 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
100 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
101 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
102 | } |
103 | ||
2aeeef11 KK |
104 | static inline int pciehp_request_irq(struct controller *ctrl) |
105 | { | |
f7a10e32 | 106 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
107 | |
108 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
109 | if (pciehp_poll_mode) { | |
110 | init_timer(&ctrl->poll_timer); | |
111 | start_int_poll_timer(ctrl, 10); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | /* Installs the interrupt handler */ | |
116 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
117 | if (retval) | |
7f2feec1 TI |
118 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
119 | irq); | |
2aeeef11 KK |
120 | return retval; |
121 | } | |
122 | ||
123 | static inline void pciehp_free_irq(struct controller *ctrl) | |
124 | { | |
125 | if (pciehp_poll_mode) | |
126 | del_timer_sync(&ctrl->poll_timer); | |
127 | else | |
f7a10e32 | 128 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
129 | } |
130 | ||
563f1190 | 131 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
132 | { |
133 | u16 slot_status; | |
322162a7 | 134 | int err, timeout = 1000; |
6592e02a | 135 | |
322162a7 KK |
136 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
137 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
138 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
139 | return 1; | |
820943b6 | 140 | } |
a5827f40 | 141 | while (timeout > 0) { |
66618bad KK |
142 | msleep(10); |
143 | timeout -= 10; | |
322162a7 KK |
144 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
145 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
146 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
147 | return 1; | |
820943b6 | 148 | } |
6592e02a KK |
149 | } |
150 | return 0; /* timeout */ | |
6592e02a KK |
151 | } |
152 | ||
563f1190 | 153 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 154 | { |
262303fe KK |
155 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
156 | unsigned long timeout = msecs_to_jiffies(msecs); | |
157 | int rc; | |
158 | ||
6592e02a KK |
159 | if (poll) |
160 | rc = pcie_poll_cmd(ctrl); | |
161 | else | |
d737bdc1 | 162 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 163 | if (!rc) |
7f2feec1 | 164 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
165 | } |
166 | ||
f4778364 KK |
167 | /** |
168 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 169 | * @ctrl: controller to which the command is issued |
f4778364 KK |
170 | * @cmd: command value written to slot control register |
171 | * @mask: bitmask of slot control register to be modified | |
172 | */ | |
c27fb883 | 173 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 174 | { |
1da177e4 LT |
175 | int retval = 0; |
176 | u16 slot_status; | |
f4778364 | 177 | u16 slot_ctrl; |
1da177e4 | 178 | |
44ef4cef KK |
179 | mutex_lock(&ctrl->ctrl_lock); |
180 | ||
322162a7 | 181 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 182 | if (retval) { |
7f2feec1 TI |
183 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
184 | __func__); | |
44ef4cef | 185 | goto out; |
a0f018da KK |
186 | } |
187 | ||
322162a7 | 188 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
189 | if (!ctrl->no_cmd_complete) { |
190 | /* | |
191 | * After 1 sec and CMD_COMPLETED still not set, just | |
192 | * proceed forward to issue the next command according | |
193 | * to spec. Just print out the error message. | |
194 | */ | |
18b341b7 | 195 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
196 | } else if (!NO_CMD_CMPL(ctrl)) { |
197 | /* | |
198 | * This controller semms to notify of command completed | |
199 | * event even though it supports none of power | |
200 | * controller, attention led, power led and EMI. | |
201 | */ | |
18b341b7 TI |
202 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
203 | "wait for command completed event.\n"); | |
5808639b KK |
204 | ctrl->no_cmd_complete = 0; |
205 | } else { | |
18b341b7 TI |
206 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
207 | "the controller is broken.\n"); | |
5808639b | 208 | } |
1da177e4 LT |
209 | } |
210 | ||
322162a7 | 211 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 212 | if (retval) { |
7f2feec1 | 213 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 214 | goto out; |
1da177e4 | 215 | } |
1da177e4 | 216 | |
f4778364 | 217 | slot_ctrl &= ~mask; |
b7aa1f16 | 218 | slot_ctrl |= (cmd & mask); |
f4778364 | 219 | ctrl->cmd_busy = 1; |
2d32a9ae | 220 | smp_mb(); |
322162a7 | 221 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 222 | if (retval) |
18b341b7 | 223 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 224 | |
44ef4cef KK |
225 | /* |
226 | * Wait for command completion. | |
227 | */ | |
6592e02a KK |
228 | if (!retval && !ctrl->no_cmd_complete) { |
229 | int poll = 0; | |
230 | /* | |
231 | * if hotplug interrupt is not enabled or command | |
232 | * completed interrupt is not enabled, we need to poll | |
233 | * command completed event. | |
234 | */ | |
322162a7 KK |
235 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
236 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 237 | poll = 1; |
d737bdc1 | 238 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 239 | } |
44ef4cef KK |
240 | out: |
241 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
242 | return retval; |
243 | } | |
244 | ||
f18e9625 KK |
245 | static inline int check_link_active(struct controller *ctrl) |
246 | { | |
247 | u16 link_status; | |
248 | ||
322162a7 | 249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 250 | return 0; |
322162a7 | 251 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
252 | } |
253 | ||
254 | static void pcie_wait_link_active(struct controller *ctrl) | |
255 | { | |
256 | int timeout = 1000; | |
257 | ||
258 | if (check_link_active(ctrl)) | |
259 | return; | |
260 | while (timeout > 0) { | |
261 | msleep(10); | |
262 | timeout -= 10; | |
263 | if (check_link_active(ctrl)) | |
264 | return; | |
265 | } | |
266 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
267 | } | |
268 | ||
82a9e79e | 269 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 270 | { |
1da177e4 LT |
271 | u16 lnk_status; |
272 | int retval = 0; | |
273 | ||
f18e9625 KK |
274 | /* |
275 | * Data Link Layer Link Active Reporting must be capable for | |
276 | * hot-plug capable downstream port. But old controller might | |
277 | * not implement it. In this case, we wait for 1000 ms. | |
278 | */ | |
279 | if (ctrl->link_active_reporting){ | |
280 | /* Wait for Data Link Layer Link Active bit to be set */ | |
281 | pcie_wait_link_active(ctrl); | |
282 | /* | |
283 | * We must wait for 100 ms after the Data Link Layer | |
284 | * Link Active bit reads 1b before initiating a | |
285 | * configuration access to the hot added device. | |
286 | */ | |
287 | msleep(100); | |
288 | } else | |
289 | msleep(1000); | |
290 | ||
322162a7 | 291 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 292 | if (retval) { |
18b341b7 | 293 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
294 | return retval; |
295 | } | |
296 | ||
7f2feec1 | 297 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
298 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
299 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 300 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
301 | retval = -1; |
302 | return retval; | |
303 | } | |
304 | ||
1da177e4 LT |
305 | return retval; |
306 | } | |
307 | ||
82a9e79e | 308 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 309 | { |
48fe3915 | 310 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
311 | u16 slot_ctrl; |
312 | u8 atten_led_state; | |
313 | int retval = 0; | |
1da177e4 | 314 | |
322162a7 | 315 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 316 | if (retval) { |
7f2feec1 | 317 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
318 | return retval; |
319 | } | |
320 | ||
1518c17a KK |
321 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
322 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 323 | |
322162a7 | 324 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
325 | |
326 | switch (atten_led_state) { | |
327 | case 0: | |
328 | *status = 0xFF; /* Reserved */ | |
329 | break; | |
330 | case 1: | |
331 | *status = 1; /* On */ | |
332 | break; | |
333 | case 2: | |
334 | *status = 2; /* Blink */ | |
335 | break; | |
336 | case 3: | |
337 | *status = 0; /* Off */ | |
338 | break; | |
339 | default: | |
340 | *status = 0xFF; | |
341 | break; | |
342 | } | |
343 | ||
1da177e4 LT |
344 | return 0; |
345 | } | |
346 | ||
82a9e79e | 347 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 348 | { |
48fe3915 | 349 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
350 | u16 slot_ctrl; |
351 | u8 pwr_state; | |
352 | int retval = 0; | |
1da177e4 | 353 | |
322162a7 | 354 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 355 | if (retval) { |
7f2feec1 | 356 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
357 | return retval; |
358 | } | |
1518c17a KK |
359 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
360 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 361 | |
322162a7 | 362 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
363 | |
364 | switch (pwr_state) { | |
365 | case 0: | |
366 | *status = 1; | |
367 | break; | |
368 | case 1: | |
71ad556d | 369 | *status = 0; |
1da177e4 LT |
370 | break; |
371 | default: | |
372 | *status = 0xFF; | |
373 | break; | |
374 | } | |
375 | ||
1da177e4 LT |
376 | return retval; |
377 | } | |
378 | ||
82a9e79e | 379 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 380 | { |
48fe3915 | 381 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 382 | u16 slot_status; |
322162a7 | 383 | int retval; |
1da177e4 | 384 | |
322162a7 | 385 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 386 | if (retval) { |
7f2feec1 TI |
387 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
388 | __func__); | |
1da177e4 LT |
389 | return retval; |
390 | } | |
322162a7 | 391 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
392 | return 0; |
393 | } | |
394 | ||
82a9e79e | 395 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 396 | { |
48fe3915 | 397 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 398 | u16 slot_status; |
322162a7 | 399 | int retval; |
1da177e4 | 400 | |
322162a7 | 401 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 402 | if (retval) { |
7f2feec1 TI |
403 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
404 | __func__); | |
1da177e4 LT |
405 | return retval; |
406 | } | |
322162a7 | 407 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
408 | return 0; |
409 | } | |
410 | ||
82a9e79e | 411 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 412 | { |
48fe3915 | 413 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 414 | u16 slot_status; |
322162a7 | 415 | int retval; |
1da177e4 | 416 | |
322162a7 | 417 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 418 | if (retval) { |
18b341b7 | 419 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
420 | return retval; |
421 | } | |
322162a7 | 422 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
423 | } |
424 | ||
82a9e79e | 425 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 426 | { |
48fe3915 | 427 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
428 | u16 slot_cmd; |
429 | u16 cmd_mask; | |
1da177e4 | 430 | |
322162a7 | 431 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 432 | switch (value) { |
445f7985 KK |
433 | case 0 : /* turn off */ |
434 | slot_cmd = 0x00C0; | |
435 | break; | |
436 | case 1: /* turn on */ | |
437 | slot_cmd = 0x0040; | |
438 | break; | |
439 | case 2: /* turn blink */ | |
440 | slot_cmd = 0x0080; | |
441 | break; | |
442 | default: | |
443 | return -EINVAL; | |
1da177e4 | 444 | } |
1518c17a KK |
445 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
446 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 447 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
448 | } |
449 | ||
82a9e79e | 450 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 451 | { |
48fe3915 | 452 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 453 | u16 slot_cmd; |
f4778364 | 454 | u16 cmd_mask; |
71ad556d | 455 | |
f4778364 | 456 | slot_cmd = 0x0100; |
322162a7 | 457 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 458 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
459 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
460 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
461 | } |
462 | ||
82a9e79e | 463 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 464 | { |
48fe3915 | 465 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 466 | u16 slot_cmd; |
f4778364 | 467 | u16 cmd_mask; |
1da177e4 | 468 | |
f4778364 | 469 | slot_cmd = 0x0300; |
322162a7 | 470 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 471 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
472 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
473 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
474 | } |
475 | ||
82a9e79e | 476 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 477 | { |
48fe3915 | 478 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 479 | u16 slot_cmd; |
f4778364 | 480 | u16 cmd_mask; |
71ad556d | 481 | |
f4778364 | 482 | slot_cmd = 0x0200; |
322162a7 | 483 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 484 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
485 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
486 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
487 | } |
488 | ||
82a9e79e | 489 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 490 | { |
48fe3915 | 491 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 492 | u16 slot_cmd; |
f4778364 KK |
493 | u16 cmd_mask; |
494 | u16 slot_status; | |
3749c51a | 495 | u16 lnk_status; |
1da177e4 LT |
496 | int retval = 0; |
497 | ||
5a49f203 | 498 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 499 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 500 | if (retval) { |
7f2feec1 TI |
501 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
502 | __func__); | |
a0f018da KK |
503 | return retval; |
504 | } | |
322162a7 | 505 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 506 | if (slot_status) { |
322162a7 | 507 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 508 | if (retval) { |
7f2feec1 TI |
509 | ctrl_err(ctrl, |
510 | "%s: Cannot write to SLOTSTATUS register\n", | |
511 | __func__); | |
a0f018da KK |
512 | return retval; |
513 | } | |
514 | } | |
5651c48c | 515 | ctrl->power_fault_detected = 0; |
1da177e4 | 516 | |
f4778364 | 517 | slot_cmd = POWER_ON; |
322162a7 | 518 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 519 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 520 | if (retval) { |
18b341b7 | 521 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 522 | return retval; |
1da177e4 | 523 | } |
1518c17a KK |
524 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
525 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 526 | |
3749c51a MW |
527 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
528 | if (retval) { | |
529 | ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n", | |
530 | __func__); | |
531 | return retval; | |
532 | } | |
533 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); | |
534 | ||
1da177e4 LT |
535 | return retval; |
536 | } | |
537 | ||
82a9e79e | 538 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 539 | { |
48fe3915 | 540 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 541 | u16 slot_cmd; |
f4778364 | 542 | u16 cmd_mask; |
3c3a1b17 | 543 | int retval; |
f1050a35 | 544 | |
f4778364 | 545 | slot_cmd = POWER_OFF; |
322162a7 | 546 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 547 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 548 | if (retval) { |
18b341b7 | 549 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 550 | return retval; |
1da177e4 | 551 | } |
1518c17a KK |
552 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
553 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 554 | return 0; |
1da177e4 LT |
555 | } |
556 | ||
48fe3915 | 557 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 558 | { |
48fe3915 | 559 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 560 | struct slot *slot = ctrl->slot; |
c6b069e9 | 561 | u16 detected, intr_loc; |
1da177e4 | 562 | |
c6b069e9 KK |
563 | /* |
564 | * In order to guarantee that all interrupt events are | |
565 | * serviced, we need to re-inspect Slot Status register after | |
566 | * clearing what is presumed to be the last pending interrupt. | |
567 | */ | |
568 | intr_loc = 0; | |
569 | do { | |
322162a7 | 570 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
571 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
572 | __func__); | |
1da177e4 LT |
573 | return IRQ_NONE; |
574 | } | |
575 | ||
322162a7 KK |
576 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
577 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
578 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 579 | detected &= ~intr_loc; |
c6b069e9 KK |
580 | intr_loc |= detected; |
581 | if (!intr_loc) | |
1da177e4 | 582 | return IRQ_NONE; |
81b840cd | 583 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
584 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
585 | __func__); | |
1da177e4 LT |
586 | return IRQ_NONE; |
587 | } | |
c6b069e9 | 588 | } while (detected); |
71ad556d | 589 | |
7f2feec1 | 590 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 591 | |
c6b069e9 | 592 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 593 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 594 | ctrl->cmd_busy = 0; |
2d32a9ae | 595 | smp_mb(); |
d737bdc1 | 596 | wake_up(&ctrl->queue); |
1da177e4 LT |
597 | } |
598 | ||
322162a7 | 599 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
600 | return IRQ_HANDLED; |
601 | ||
c6b069e9 | 602 | /* Check MRL Sensor Changed */ |
322162a7 | 603 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 604 | pciehp_handle_switch_change(slot); |
48fe3915 | 605 | |
c6b069e9 | 606 | /* Check Attention Button Pressed */ |
322162a7 | 607 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 608 | pciehp_handle_attention_button(slot); |
48fe3915 | 609 | |
c6b069e9 | 610 | /* Check Presence Detect Changed */ |
322162a7 | 611 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 612 | pciehp_handle_presence_change(slot); |
48fe3915 | 613 | |
c6b069e9 | 614 | /* Check Power Fault Detected */ |
99f0169c KK |
615 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
616 | ctrl->power_fault_detected = 1; | |
8720d27d | 617 | pciehp_handle_power_fault(slot); |
99f0169c | 618 | } |
1da177e4 LT |
619 | return IRQ_HANDLED; |
620 | } | |
621 | ||
82a9e79e | 622 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 623 | enum pcie_link_width *value) |
1da177e4 | 624 | { |
48fe3915 | 625 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
626 | enum pcie_link_width lnk_wdth; |
627 | u32 lnk_cap; | |
628 | int retval = 0; | |
629 | ||
322162a7 | 630 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 631 | if (retval) { |
7f2feec1 | 632 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
633 | return retval; |
634 | } | |
635 | ||
322162a7 | 636 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
637 | case 0: |
638 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
639 | break; | |
640 | case 1: | |
641 | lnk_wdth = PCIE_LNK_X1; | |
642 | break; | |
643 | case 2: | |
644 | lnk_wdth = PCIE_LNK_X2; | |
645 | break; | |
646 | case 4: | |
647 | lnk_wdth = PCIE_LNK_X4; | |
648 | break; | |
649 | case 8: | |
650 | lnk_wdth = PCIE_LNK_X8; | |
651 | break; | |
652 | case 12: | |
653 | lnk_wdth = PCIE_LNK_X12; | |
654 | break; | |
655 | case 16: | |
656 | lnk_wdth = PCIE_LNK_X16; | |
657 | break; | |
658 | case 32: | |
659 | lnk_wdth = PCIE_LNK_X32; | |
660 | break; | |
661 | default: | |
662 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
663 | break; | |
664 | } | |
665 | ||
666 | *value = lnk_wdth; | |
7f2feec1 | 667 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 668 | |
1da177e4 LT |
669 | return retval; |
670 | } | |
671 | ||
82a9e79e | 672 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 673 | enum pcie_link_width *value) |
1da177e4 | 674 | { |
48fe3915 | 675 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
676 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
677 | int retval = 0; | |
678 | u16 lnk_status; | |
679 | ||
322162a7 | 680 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 681 | if (retval) { |
7f2feec1 TI |
682 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
683 | __func__); | |
1da177e4 LT |
684 | return retval; |
685 | } | |
71ad556d | 686 | |
322162a7 | 687 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
688 | case 0: |
689 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
690 | break; | |
691 | case 1: | |
692 | lnk_wdth = PCIE_LNK_X1; | |
693 | break; | |
694 | case 2: | |
695 | lnk_wdth = PCIE_LNK_X2; | |
696 | break; | |
697 | case 4: | |
698 | lnk_wdth = PCIE_LNK_X4; | |
699 | break; | |
700 | case 8: | |
701 | lnk_wdth = PCIE_LNK_X8; | |
702 | break; | |
703 | case 12: | |
704 | lnk_wdth = PCIE_LNK_X12; | |
705 | break; | |
706 | case 16: | |
707 | lnk_wdth = PCIE_LNK_X16; | |
708 | break; | |
709 | case 32: | |
710 | lnk_wdth = PCIE_LNK_X32; | |
711 | break; | |
712 | default: | |
713 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
714 | break; | |
715 | } | |
716 | ||
717 | *value = lnk_wdth; | |
7f2feec1 | 718 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 719 | |
1da177e4 LT |
720 | return retval; |
721 | } | |
722 | ||
c4635eb0 | 723 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 724 | { |
c27fb883 | 725 | u16 cmd, mask; |
1da177e4 | 726 | |
5651c48c KK |
727 | /* |
728 | * TBD: Power fault detected software notification support. | |
729 | * | |
730 | * Power fault detected software notification is not enabled | |
731 | * now, because it caused power fault detected interrupt storm | |
732 | * on some machines. On those machines, power fault detected | |
733 | * bit in the slot status register was set again immediately | |
734 | * when it is cleared in the interrupt service routine, and | |
735 | * next power fault detected interrupt was notified again. | |
736 | */ | |
322162a7 | 737 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 738 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 739 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 740 | if (MRL_SENS(ctrl)) |
322162a7 | 741 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 742 | if (!pciehp_poll_mode) |
322162a7 | 743 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 744 | |
322162a7 KK |
745 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
746 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
747 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
748 | |
749 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 750 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 751 | return -1; |
1da177e4 | 752 | } |
c4635eb0 KK |
753 | return 0; |
754 | } | |
755 | ||
756 | static void pcie_disable_notification(struct controller *ctrl) | |
757 | { | |
758 | u16 mask; | |
322162a7 KK |
759 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
760 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
761 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
762 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 763 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 764 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
765 | } |
766 | ||
dbc7e1e5 | 767 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
768 | { |
769 | if (pciehp_request_irq(ctrl)) | |
770 | return -1; | |
771 | if (pcie_enable_notification(ctrl)) { | |
772 | pciehp_free_irq(ctrl); | |
773 | return -1; | |
774 | } | |
dbc7e1e5 | 775 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
776 | return 0; |
777 | } | |
778 | ||
779 | static void pcie_shutdown_notification(struct controller *ctrl) | |
780 | { | |
dbc7e1e5 EB |
781 | if (ctrl->notification_enabled) { |
782 | pcie_disable_notification(ctrl); | |
783 | pciehp_free_irq(ctrl); | |
784 | ctrl->notification_enabled = 0; | |
785 | } | |
c4635eb0 KK |
786 | } |
787 | ||
c4635eb0 KK |
788 | static int pcie_init_slot(struct controller *ctrl) |
789 | { | |
790 | struct slot *slot; | |
791 | ||
792 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
793 | if (!slot) | |
794 | return -ENOMEM; | |
795 | ||
c4635eb0 | 796 | slot->ctrl = ctrl; |
c4635eb0 KK |
797 | mutex_init(&slot->lock); |
798 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 799 | ctrl->slot = slot; |
1da177e4 | 800 | return 0; |
1da177e4 | 801 | } |
08e7a7d2 | 802 | |
c4635eb0 KK |
803 | static void pcie_cleanup_slot(struct controller *ctrl) |
804 | { | |
8720d27d | 805 | struct slot *slot = ctrl->slot; |
c4635eb0 KK |
806 | cancel_delayed_work(&slot->work); |
807 | flush_scheduled_work(); | |
808 | flush_workqueue(pciehp_wq); | |
809 | kfree(slot); | |
810 | } | |
811 | ||
2aeeef11 | 812 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 813 | { |
2aeeef11 KK |
814 | int i; |
815 | u16 reg16; | |
385e2491 | 816 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 817 | |
2aeeef11 KK |
818 | if (!pciehp_debug) |
819 | return; | |
08e7a7d2 | 820 | |
7f2feec1 TI |
821 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
822 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
823 | pci_name(pdev), pdev->irq); | |
824 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
825 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
826 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
827 | pdev->subsystem_device); | |
828 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
829 | pdev->subsystem_vendor); | |
1518c17a KK |
830 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
831 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
832 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
833 | if (!pci_resource_len(pdev, i)) | |
834 | continue; | |
e1944c6b BH |
835 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
836 | i, &pdev->resource[i]); | |
08e7a7d2 | 837 | } |
7f2feec1 | 838 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 839 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
840 | ctrl_info(ctrl, " Attention Button : %3s\n", |
841 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
842 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
843 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
844 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
845 | MRL_SENS(ctrl) ? "yes" : "no"); | |
846 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
847 | ATTN_LED(ctrl) ? "yes" : "no"); | |
848 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
849 | PWR_LED(ctrl) ? "yes" : "no"); | |
850 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
851 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
852 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
853 | EMI(ctrl) ? "yes" : "no"); | |
854 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
855 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 856 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 857 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 858 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 859 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 860 | } |
08e7a7d2 | 861 | |
c4635eb0 | 862 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 863 | { |
c4635eb0 | 864 | struct controller *ctrl; |
f18e9625 | 865 | u32 slot_cap, link_cap; |
2aeeef11 | 866 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 867 | |
c4635eb0 KK |
868 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
869 | if (!ctrl) { | |
18b341b7 | 870 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
871 | goto abort; |
872 | } | |
f7a10e32 | 873 | ctrl->pcie = dev; |
1518c17a | 874 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 875 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 876 | goto abort_ctrl; |
08e7a7d2 | 877 | } |
322162a7 | 878 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 879 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 880 | goto abort_ctrl; |
08e7a7d2 | 881 | } |
08e7a7d2 | 882 | |
2aeeef11 | 883 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 884 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 885 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 886 | dbg_ctrl(ctrl); |
5808639b KK |
887 | /* |
888 | * Controller doesn't notify of command completion if the "No | |
889 | * Command Completed Support" bit is set in Slot Capability | |
890 | * register or the controller supports none of power | |
891 | * controller, attention led, power led and EMI. | |
892 | */ | |
893 | if (NO_CMD_CMPL(ctrl) || | |
894 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
895 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 896 | |
f18e9625 | 897 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 898 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
899 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
900 | goto abort_ctrl; | |
901 | } | |
322162a7 | 902 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
903 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
904 | ctrl->link_active_reporting = 1; | |
905 | } | |
906 | ||
c4635eb0 | 907 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 908 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 909 | goto abort_ctrl; |
08e7a7d2 | 910 | |
c4635eb0 KK |
911 | /* Disable sotfware notification */ |
912 | pcie_disable_notification(ctrl); | |
ecdde939 ML |
913 | |
914 | /* | |
915 | * If this is the first controller to be initialized, | |
916 | * initialize the pciehp work queue | |
917 | */ | |
918 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
919 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
c4635eb0 KK |
920 | if (!pciehp_wq) |
921 | goto abort_ctrl; | |
ecdde939 ML |
922 | } |
923 | ||
7f2feec1 TI |
924 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
925 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
926 | pdev->subsystem_device); | |
c4635eb0 KK |
927 | |
928 | if (pcie_init_slot(ctrl)) | |
929 | goto abort_ctrl; | |
2aeeef11 | 930 | |
c4635eb0 KK |
931 | return ctrl; |
932 | ||
c4635eb0 KK |
933 | abort_ctrl: |
934 | kfree(ctrl); | |
08e7a7d2 | 935 | abort: |
c4635eb0 KK |
936 | return NULL; |
937 | } | |
938 | ||
82a9e79e | 939 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
940 | { |
941 | pcie_shutdown_notification(ctrl); | |
942 | pcie_cleanup_slot(ctrl); | |
943 | /* | |
944 | * If this is the last controller to be released, destroy the | |
945 | * pciehp work queue | |
946 | */ | |
947 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
948 | destroy_workqueue(pciehp_wq); | |
949 | kfree(ctrl); | |
08e7a7d2 | 950 | } |