Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
a0f018da KK |
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
45 | { | |
385e2491 | 46 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 47 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
48 | } |
49 | ||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
51 | { | |
385e2491 | 52 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 53 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
54 | } |
55 | ||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
57 | { | |
385e2491 | 58 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 59 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
60 | } |
61 | ||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
63 | { | |
385e2491 | 64 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 65 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 66 | } |
1da177e4 | 67 | |
1da177e4 LT |
68 | /* Power Control Command */ |
69 | #define POWER_ON 0 | |
322162a7 | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 71 | |
48fe3915 KK |
72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
73 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
74 | |
75 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 76 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 77 | { |
48fe3915 | 78 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 79 | |
1da177e4 | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 81 | pcie_isr(0, ctrl); |
1da177e4 | 82 | |
48fe3915 | 83 | init_timer(&ctrl->poll_timer); |
1da177e4 | 84 | if (!pciehp_poll_time) |
40730d10 | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 86 | |
48fe3915 | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
88 | } |
89 | ||
90 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 92 | { |
48fe3915 KK |
93 | /* Clamp to sane value */ |
94 | if ((sec <= 0) || (sec > 60)) | |
95 | sec = 2; | |
96 | ||
97 | ctrl->poll_timer.function = &int_poll_timeout; | |
98 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
99 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
100 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
101 | } |
102 | ||
2aeeef11 KK |
103 | static inline int pciehp_request_irq(struct controller *ctrl) |
104 | { | |
f7a10e32 | 105 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
106 | |
107 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
108 | if (pciehp_poll_mode) { | |
109 | init_timer(&ctrl->poll_timer); | |
110 | start_int_poll_timer(ctrl, 10); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | /* Installs the interrupt handler */ | |
115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
116 | if (retval) | |
7f2feec1 TI |
117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
118 | irq); | |
2aeeef11 KK |
119 | return retval; |
120 | } | |
121 | ||
122 | static inline void pciehp_free_irq(struct controller *ctrl) | |
123 | { | |
124 | if (pciehp_poll_mode) | |
125 | del_timer_sync(&ctrl->poll_timer); | |
126 | else | |
f7a10e32 | 127 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
128 | } |
129 | ||
563f1190 | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
131 | { |
132 | u16 slot_status; | |
322162a7 | 133 | int err, timeout = 1000; |
6592e02a | 134 | |
322162a7 KK |
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
138 | return 1; | |
820943b6 | 139 | } |
a5827f40 | 140 | while (timeout > 0) { |
66618bad KK |
141 | msleep(10); |
142 | timeout -= 10; | |
322162a7 KK |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
146 | return 1; | |
820943b6 | 147 | } |
6592e02a KK |
148 | } |
149 | return 0; /* timeout */ | |
6592e02a KK |
150 | } |
151 | ||
563f1190 | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 153 | { |
262303fe KK |
154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
155 | unsigned long timeout = msecs_to_jiffies(msecs); | |
156 | int rc; | |
157 | ||
6592e02a KK |
158 | if (poll) |
159 | rc = pcie_poll_cmd(ctrl); | |
160 | else | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 162 | if (!rc) |
7f2feec1 | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
164 | } |
165 | ||
f4778364 KK |
166 | /** |
167 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 168 | * @ctrl: controller to which the command is issued |
f4778364 KK |
169 | * @cmd: command value written to slot control register |
170 | * @mask: bitmask of slot control register to be modified | |
171 | */ | |
c27fb883 | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 173 | { |
1da177e4 LT |
174 | int retval = 0; |
175 | u16 slot_status; | |
f4778364 | 176 | u16 slot_ctrl; |
1da177e4 | 177 | |
44ef4cef KK |
178 | mutex_lock(&ctrl->ctrl_lock); |
179 | ||
322162a7 | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 181 | if (retval) { |
7f2feec1 TI |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | |
44ef4cef | 184 | goto out; |
a0f018da KK |
185 | } |
186 | ||
322162a7 | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
188 | if (!ctrl->no_cmd_complete) { |
189 | /* | |
190 | * After 1 sec and CMD_COMPLETED still not set, just | |
191 | * proceed forward to issue the next command according | |
192 | * to spec. Just print out the error message. | |
193 | */ | |
18b341b7 | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
195 | } else if (!NO_CMD_CMPL(ctrl)) { |
196 | /* | |
197 | * This controller semms to notify of command completed | |
198 | * event even though it supports none of power | |
199 | * controller, attention led, power led and EMI. | |
200 | */ | |
18b341b7 TI |
201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
202 | "wait for command completed event.\n"); | |
5808639b KK |
203 | ctrl->no_cmd_complete = 0; |
204 | } else { | |
18b341b7 TI |
205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
206 | "the controller is broken.\n"); | |
5808639b | 207 | } |
1da177e4 LT |
208 | } |
209 | ||
322162a7 | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 211 | if (retval) { |
7f2feec1 | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 213 | goto out; |
1da177e4 | 214 | } |
1da177e4 | 215 | |
f4778364 | 216 | slot_ctrl &= ~mask; |
b7aa1f16 | 217 | slot_ctrl |= (cmd & mask); |
f4778364 | 218 | ctrl->cmd_busy = 1; |
2d32a9ae | 219 | smp_mb(); |
322162a7 | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 221 | if (retval) |
18b341b7 | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 223 | |
44ef4cef KK |
224 | /* |
225 | * Wait for command completion. | |
226 | */ | |
6592e02a KK |
227 | if (!retval && !ctrl->no_cmd_complete) { |
228 | int poll = 0; | |
229 | /* | |
230 | * if hotplug interrupt is not enabled or command | |
231 | * completed interrupt is not enabled, we need to poll | |
232 | * command completed event. | |
233 | */ | |
322162a7 KK |
234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 236 | poll = 1; |
d737bdc1 | 237 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 238 | } |
44ef4cef KK |
239 | out: |
240 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
241 | return retval; |
242 | } | |
243 | ||
f18e9625 KK |
244 | static inline int check_link_active(struct controller *ctrl) |
245 | { | |
246 | u16 link_status; | |
247 | ||
322162a7 | 248 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 249 | return 0; |
322162a7 | 250 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
251 | } |
252 | ||
253 | static void pcie_wait_link_active(struct controller *ctrl) | |
254 | { | |
255 | int timeout = 1000; | |
256 | ||
257 | if (check_link_active(ctrl)) | |
258 | return; | |
259 | while (timeout > 0) { | |
260 | msleep(10); | |
261 | timeout -= 10; | |
262 | if (check_link_active(ctrl)) | |
263 | return; | |
264 | } | |
265 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
266 | } | |
267 | ||
82a9e79e | 268 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 269 | { |
1da177e4 LT |
270 | u16 lnk_status; |
271 | int retval = 0; | |
272 | ||
f18e9625 KK |
273 | /* |
274 | * Data Link Layer Link Active Reporting must be capable for | |
275 | * hot-plug capable downstream port. But old controller might | |
276 | * not implement it. In this case, we wait for 1000 ms. | |
277 | */ | |
0cab0841 | 278 | if (ctrl->link_active_reporting) |
f18e9625 | 279 | pcie_wait_link_active(ctrl); |
0cab0841 | 280 | else |
f18e9625 KK |
281 | msleep(1000); |
282 | ||
322162a7 | 283 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 284 | if (retval) { |
18b341b7 | 285 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
286 | return retval; |
287 | } | |
288 | ||
7f2feec1 | 289 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
290 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
291 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 292 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
293 | retval = -1; |
294 | return retval; | |
295 | } | |
296 | ||
1da177e4 LT |
297 | return retval; |
298 | } | |
299 | ||
82a9e79e | 300 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 301 | { |
48fe3915 | 302 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
303 | u16 slot_ctrl; |
304 | u8 atten_led_state; | |
305 | int retval = 0; | |
1da177e4 | 306 | |
322162a7 | 307 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 308 | if (retval) { |
7f2feec1 | 309 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
310 | return retval; |
311 | } | |
312 | ||
1518c17a KK |
313 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
314 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 315 | |
322162a7 | 316 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
317 | |
318 | switch (atten_led_state) { | |
319 | case 0: | |
320 | *status = 0xFF; /* Reserved */ | |
321 | break; | |
322 | case 1: | |
323 | *status = 1; /* On */ | |
324 | break; | |
325 | case 2: | |
326 | *status = 2; /* Blink */ | |
327 | break; | |
328 | case 3: | |
329 | *status = 0; /* Off */ | |
330 | break; | |
331 | default: | |
332 | *status = 0xFF; | |
333 | break; | |
334 | } | |
335 | ||
1da177e4 LT |
336 | return 0; |
337 | } | |
338 | ||
82a9e79e | 339 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 340 | { |
48fe3915 | 341 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
342 | u16 slot_ctrl; |
343 | u8 pwr_state; | |
344 | int retval = 0; | |
1da177e4 | 345 | |
322162a7 | 346 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 347 | if (retval) { |
7f2feec1 | 348 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
349 | return retval; |
350 | } | |
1518c17a KK |
351 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
352 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 353 | |
322162a7 | 354 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
355 | |
356 | switch (pwr_state) { | |
357 | case 0: | |
358 | *status = 1; | |
359 | break; | |
360 | case 1: | |
71ad556d | 361 | *status = 0; |
1da177e4 LT |
362 | break; |
363 | default: | |
364 | *status = 0xFF; | |
365 | break; | |
366 | } | |
367 | ||
1da177e4 LT |
368 | return retval; |
369 | } | |
370 | ||
82a9e79e | 371 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 372 | { |
48fe3915 | 373 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 374 | u16 slot_status; |
322162a7 | 375 | int retval; |
1da177e4 | 376 | |
322162a7 | 377 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 378 | if (retval) { |
7f2feec1 TI |
379 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
380 | __func__); | |
1da177e4 LT |
381 | return retval; |
382 | } | |
322162a7 | 383 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
384 | return 0; |
385 | } | |
386 | ||
82a9e79e | 387 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 388 | { |
48fe3915 | 389 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 390 | u16 slot_status; |
322162a7 | 391 | int retval; |
1da177e4 | 392 | |
322162a7 | 393 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 394 | if (retval) { |
7f2feec1 TI |
395 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
396 | __func__); | |
1da177e4 LT |
397 | return retval; |
398 | } | |
322162a7 | 399 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
400 | return 0; |
401 | } | |
402 | ||
82a9e79e | 403 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 404 | { |
48fe3915 | 405 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 406 | u16 slot_status; |
322162a7 | 407 | int retval; |
1da177e4 | 408 | |
322162a7 | 409 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 410 | if (retval) { |
18b341b7 | 411 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
412 | return retval; |
413 | } | |
322162a7 | 414 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
415 | } |
416 | ||
82a9e79e | 417 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 418 | { |
48fe3915 | 419 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
420 | u16 slot_cmd; |
421 | u16 cmd_mask; | |
1da177e4 | 422 | |
322162a7 | 423 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 424 | switch (value) { |
445f7985 KK |
425 | case 0 : /* turn off */ |
426 | slot_cmd = 0x00C0; | |
427 | break; | |
428 | case 1: /* turn on */ | |
429 | slot_cmd = 0x0040; | |
430 | break; | |
431 | case 2: /* turn blink */ | |
432 | slot_cmd = 0x0080; | |
433 | break; | |
434 | default: | |
435 | return -EINVAL; | |
1da177e4 | 436 | } |
1518c17a KK |
437 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
438 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 439 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
440 | } |
441 | ||
82a9e79e | 442 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 443 | { |
48fe3915 | 444 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 445 | u16 slot_cmd; |
f4778364 | 446 | u16 cmd_mask; |
71ad556d | 447 | |
f4778364 | 448 | slot_cmd = 0x0100; |
322162a7 | 449 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 450 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
451 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
452 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
453 | } |
454 | ||
82a9e79e | 455 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 456 | { |
48fe3915 | 457 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 458 | u16 slot_cmd; |
f4778364 | 459 | u16 cmd_mask; |
1da177e4 | 460 | |
f4778364 | 461 | slot_cmd = 0x0300; |
322162a7 | 462 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 463 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
464 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
465 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
466 | } |
467 | ||
82a9e79e | 468 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 469 | { |
48fe3915 | 470 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 471 | u16 slot_cmd; |
f4778364 | 472 | u16 cmd_mask; |
71ad556d | 473 | |
f4778364 | 474 | slot_cmd = 0x0200; |
322162a7 | 475 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 476 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
477 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
478 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
479 | } |
480 | ||
82a9e79e | 481 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 482 | { |
48fe3915 | 483 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 484 | u16 slot_cmd; |
f4778364 KK |
485 | u16 cmd_mask; |
486 | u16 slot_status; | |
3749c51a | 487 | u16 lnk_status; |
1da177e4 LT |
488 | int retval = 0; |
489 | ||
5a49f203 | 490 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 491 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 492 | if (retval) { |
7f2feec1 TI |
493 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
494 | __func__); | |
a0f018da KK |
495 | return retval; |
496 | } | |
322162a7 | 497 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 498 | if (slot_status) { |
322162a7 | 499 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 500 | if (retval) { |
7f2feec1 TI |
501 | ctrl_err(ctrl, |
502 | "%s: Cannot write to SLOTSTATUS register\n", | |
503 | __func__); | |
a0f018da KK |
504 | return retval; |
505 | } | |
506 | } | |
5651c48c | 507 | ctrl->power_fault_detected = 0; |
1da177e4 | 508 | |
f4778364 | 509 | slot_cmd = POWER_ON; |
322162a7 | 510 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 511 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 512 | if (retval) { |
18b341b7 | 513 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 514 | return retval; |
1da177e4 | 515 | } |
1518c17a KK |
516 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
517 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 518 | |
3749c51a MW |
519 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
520 | if (retval) { | |
521 | ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n", | |
522 | __func__); | |
523 | return retval; | |
524 | } | |
525 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); | |
526 | ||
1da177e4 LT |
527 | return retval; |
528 | } | |
529 | ||
82a9e79e | 530 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 531 | { |
48fe3915 | 532 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 533 | u16 slot_cmd; |
f4778364 | 534 | u16 cmd_mask; |
3c3a1b17 | 535 | int retval; |
f1050a35 | 536 | |
f4778364 | 537 | slot_cmd = POWER_OFF; |
322162a7 | 538 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 539 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 540 | if (retval) { |
18b341b7 | 541 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 542 | return retval; |
1da177e4 | 543 | } |
1518c17a KK |
544 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
545 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 546 | return 0; |
1da177e4 LT |
547 | } |
548 | ||
48fe3915 | 549 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 550 | { |
48fe3915 | 551 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 552 | struct slot *slot = ctrl->slot; |
c6b069e9 | 553 | u16 detected, intr_loc; |
1da177e4 | 554 | |
c6b069e9 KK |
555 | /* |
556 | * In order to guarantee that all interrupt events are | |
557 | * serviced, we need to re-inspect Slot Status register after | |
558 | * clearing what is presumed to be the last pending interrupt. | |
559 | */ | |
560 | intr_loc = 0; | |
561 | do { | |
322162a7 | 562 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
563 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
564 | __func__); | |
1da177e4 LT |
565 | return IRQ_NONE; |
566 | } | |
567 | ||
322162a7 KK |
568 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
569 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
570 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 571 | detected &= ~intr_loc; |
c6b069e9 KK |
572 | intr_loc |= detected; |
573 | if (!intr_loc) | |
1da177e4 | 574 | return IRQ_NONE; |
81b840cd | 575 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
576 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
577 | __func__); | |
1da177e4 LT |
578 | return IRQ_NONE; |
579 | } | |
c6b069e9 | 580 | } while (detected); |
71ad556d | 581 | |
7f2feec1 | 582 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 583 | |
c6b069e9 | 584 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 585 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 586 | ctrl->cmd_busy = 0; |
2d32a9ae | 587 | smp_mb(); |
d737bdc1 | 588 | wake_up(&ctrl->queue); |
1da177e4 LT |
589 | } |
590 | ||
322162a7 | 591 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
592 | return IRQ_HANDLED; |
593 | ||
c6b069e9 | 594 | /* Check MRL Sensor Changed */ |
322162a7 | 595 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 596 | pciehp_handle_switch_change(slot); |
48fe3915 | 597 | |
c6b069e9 | 598 | /* Check Attention Button Pressed */ |
322162a7 | 599 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 600 | pciehp_handle_attention_button(slot); |
48fe3915 | 601 | |
c6b069e9 | 602 | /* Check Presence Detect Changed */ |
322162a7 | 603 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 604 | pciehp_handle_presence_change(slot); |
48fe3915 | 605 | |
c6b069e9 | 606 | /* Check Power Fault Detected */ |
99f0169c KK |
607 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
608 | ctrl->power_fault_detected = 1; | |
8720d27d | 609 | pciehp_handle_power_fault(slot); |
99f0169c | 610 | } |
1da177e4 LT |
611 | return IRQ_HANDLED; |
612 | } | |
613 | ||
82a9e79e | 614 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 615 | enum pcie_link_width *value) |
1da177e4 | 616 | { |
48fe3915 | 617 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
618 | enum pcie_link_width lnk_wdth; |
619 | u32 lnk_cap; | |
620 | int retval = 0; | |
621 | ||
322162a7 | 622 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 623 | if (retval) { |
7f2feec1 | 624 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
625 | return retval; |
626 | } | |
627 | ||
322162a7 | 628 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
629 | case 0: |
630 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
631 | break; | |
632 | case 1: | |
633 | lnk_wdth = PCIE_LNK_X1; | |
634 | break; | |
635 | case 2: | |
636 | lnk_wdth = PCIE_LNK_X2; | |
637 | break; | |
638 | case 4: | |
639 | lnk_wdth = PCIE_LNK_X4; | |
640 | break; | |
641 | case 8: | |
642 | lnk_wdth = PCIE_LNK_X8; | |
643 | break; | |
644 | case 12: | |
645 | lnk_wdth = PCIE_LNK_X12; | |
646 | break; | |
647 | case 16: | |
648 | lnk_wdth = PCIE_LNK_X16; | |
649 | break; | |
650 | case 32: | |
651 | lnk_wdth = PCIE_LNK_X32; | |
652 | break; | |
653 | default: | |
654 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
655 | break; | |
656 | } | |
657 | ||
658 | *value = lnk_wdth; | |
7f2feec1 | 659 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 660 | |
1da177e4 LT |
661 | return retval; |
662 | } | |
663 | ||
82a9e79e | 664 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 665 | enum pcie_link_width *value) |
1da177e4 | 666 | { |
48fe3915 | 667 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
668 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
669 | int retval = 0; | |
670 | u16 lnk_status; | |
671 | ||
322162a7 | 672 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 673 | if (retval) { |
7f2feec1 TI |
674 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
675 | __func__); | |
1da177e4 LT |
676 | return retval; |
677 | } | |
71ad556d | 678 | |
322162a7 | 679 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
680 | case 0: |
681 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
682 | break; | |
683 | case 1: | |
684 | lnk_wdth = PCIE_LNK_X1; | |
685 | break; | |
686 | case 2: | |
687 | lnk_wdth = PCIE_LNK_X2; | |
688 | break; | |
689 | case 4: | |
690 | lnk_wdth = PCIE_LNK_X4; | |
691 | break; | |
692 | case 8: | |
693 | lnk_wdth = PCIE_LNK_X8; | |
694 | break; | |
695 | case 12: | |
696 | lnk_wdth = PCIE_LNK_X12; | |
697 | break; | |
698 | case 16: | |
699 | lnk_wdth = PCIE_LNK_X16; | |
700 | break; | |
701 | case 32: | |
702 | lnk_wdth = PCIE_LNK_X32; | |
703 | break; | |
704 | default: | |
705 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
706 | break; | |
707 | } | |
708 | ||
709 | *value = lnk_wdth; | |
7f2feec1 | 710 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 711 | |
1da177e4 LT |
712 | return retval; |
713 | } | |
714 | ||
c4635eb0 | 715 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 716 | { |
c27fb883 | 717 | u16 cmd, mask; |
1da177e4 | 718 | |
5651c48c KK |
719 | /* |
720 | * TBD: Power fault detected software notification support. | |
721 | * | |
722 | * Power fault detected software notification is not enabled | |
723 | * now, because it caused power fault detected interrupt storm | |
724 | * on some machines. On those machines, power fault detected | |
725 | * bit in the slot status register was set again immediately | |
726 | * when it is cleared in the interrupt service routine, and | |
727 | * next power fault detected interrupt was notified again. | |
728 | */ | |
322162a7 | 729 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 730 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 731 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 732 | if (MRL_SENS(ctrl)) |
322162a7 | 733 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 734 | if (!pciehp_poll_mode) |
322162a7 | 735 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 736 | |
322162a7 KK |
737 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
738 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
739 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
740 | |
741 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 742 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 743 | return -1; |
1da177e4 | 744 | } |
c4635eb0 KK |
745 | return 0; |
746 | } | |
747 | ||
748 | static void pcie_disable_notification(struct controller *ctrl) | |
749 | { | |
750 | u16 mask; | |
322162a7 KK |
751 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
752 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
753 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
754 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 755 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 756 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
757 | } |
758 | ||
dbc7e1e5 | 759 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
760 | { |
761 | if (pciehp_request_irq(ctrl)) | |
762 | return -1; | |
763 | if (pcie_enable_notification(ctrl)) { | |
764 | pciehp_free_irq(ctrl); | |
765 | return -1; | |
766 | } | |
dbc7e1e5 | 767 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
768 | return 0; |
769 | } | |
770 | ||
771 | static void pcie_shutdown_notification(struct controller *ctrl) | |
772 | { | |
dbc7e1e5 EB |
773 | if (ctrl->notification_enabled) { |
774 | pcie_disable_notification(ctrl); | |
775 | pciehp_free_irq(ctrl); | |
776 | ctrl->notification_enabled = 0; | |
777 | } | |
c4635eb0 KK |
778 | } |
779 | ||
c4635eb0 KK |
780 | static int pcie_init_slot(struct controller *ctrl) |
781 | { | |
782 | struct slot *slot; | |
783 | ||
784 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
785 | if (!slot) | |
786 | return -ENOMEM; | |
787 | ||
c4635eb0 | 788 | slot->ctrl = ctrl; |
c4635eb0 KK |
789 | mutex_init(&slot->lock); |
790 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 791 | ctrl->slot = slot; |
1da177e4 | 792 | return 0; |
1da177e4 | 793 | } |
08e7a7d2 | 794 | |
c4635eb0 KK |
795 | static void pcie_cleanup_slot(struct controller *ctrl) |
796 | { | |
8720d27d | 797 | struct slot *slot = ctrl->slot; |
c4635eb0 | 798 | cancel_delayed_work(&slot->work); |
c4635eb0 | 799 | flush_workqueue(pciehp_wq); |
a827ea30 | 800 | flush_workqueue(pciehp_ordered_wq); |
c4635eb0 KK |
801 | kfree(slot); |
802 | } | |
803 | ||
2aeeef11 | 804 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 805 | { |
2aeeef11 KK |
806 | int i; |
807 | u16 reg16; | |
385e2491 | 808 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 809 | |
2aeeef11 KK |
810 | if (!pciehp_debug) |
811 | return; | |
08e7a7d2 | 812 | |
7f2feec1 TI |
813 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
814 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
815 | pci_name(pdev), pdev->irq); | |
816 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
817 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
818 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
819 | pdev->subsystem_device); | |
820 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
821 | pdev->subsystem_vendor); | |
1518c17a KK |
822 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
823 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
824 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
825 | if (!pci_resource_len(pdev, i)) | |
826 | continue; | |
e1944c6b BH |
827 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
828 | i, &pdev->resource[i]); | |
08e7a7d2 | 829 | } |
7f2feec1 | 830 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 831 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
832 | ctrl_info(ctrl, " Attention Button : %3s\n", |
833 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
834 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
835 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
836 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
837 | MRL_SENS(ctrl) ? "yes" : "no"); | |
838 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
839 | ATTN_LED(ctrl) ? "yes" : "no"); | |
840 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
841 | PWR_LED(ctrl) ? "yes" : "no"); | |
842 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
843 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
844 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
845 | EMI(ctrl) ? "yes" : "no"); | |
846 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
847 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 848 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 849 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 850 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 851 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 852 | } |
08e7a7d2 | 853 | |
c4635eb0 | 854 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 855 | { |
c4635eb0 | 856 | struct controller *ctrl; |
f18e9625 | 857 | u32 slot_cap, link_cap; |
2aeeef11 | 858 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 859 | |
c4635eb0 KK |
860 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
861 | if (!ctrl) { | |
18b341b7 | 862 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
863 | goto abort; |
864 | } | |
f7a10e32 | 865 | ctrl->pcie = dev; |
1518c17a | 866 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 867 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 868 | goto abort_ctrl; |
08e7a7d2 | 869 | } |
322162a7 | 870 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 871 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 872 | goto abort_ctrl; |
08e7a7d2 | 873 | } |
08e7a7d2 | 874 | |
2aeeef11 | 875 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 876 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 877 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 878 | dbg_ctrl(ctrl); |
5808639b KK |
879 | /* |
880 | * Controller doesn't notify of command completion if the "No | |
881 | * Command Completed Support" bit is set in Slot Capability | |
882 | * register or the controller supports none of power | |
883 | * controller, attention led, power led and EMI. | |
884 | */ | |
885 | if (NO_CMD_CMPL(ctrl) || | |
886 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
887 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 888 | |
f18e9625 | 889 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 890 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
891 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
892 | goto abort_ctrl; | |
893 | } | |
322162a7 | 894 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
895 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
896 | ctrl->link_active_reporting = 1; | |
897 | } | |
898 | ||
c4635eb0 | 899 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 900 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 901 | goto abort_ctrl; |
08e7a7d2 | 902 | |
c4635eb0 KK |
903 | /* Disable sotfware notification */ |
904 | pcie_disable_notification(ctrl); | |
ecdde939 | 905 | |
7f2feec1 TI |
906 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
907 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
908 | pdev->subsystem_device); | |
c4635eb0 KK |
909 | |
910 | if (pcie_init_slot(ctrl)) | |
911 | goto abort_ctrl; | |
2aeeef11 | 912 | |
c4635eb0 KK |
913 | return ctrl; |
914 | ||
c4635eb0 KK |
915 | abort_ctrl: |
916 | kfree(ctrl); | |
08e7a7d2 | 917 | abort: |
c4635eb0 KK |
918 | return NULL; |
919 | } | |
920 | ||
82a9e79e | 921 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
922 | { |
923 | pcie_shutdown_notification(ctrl); | |
924 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 925 | kfree(ctrl); |
08e7a7d2 | 926 | } |