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[PATCH] getting rid of all casts of k[cmz]alloc() calls
[linux-2.6-block.git] / drivers / pci / hotplug / pciehp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
de25968c
TS		 33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
1da177e4 36#include <linux/pci.h>
5d1b8c9e
AM		 37#include <linux/interrupt.h>
38
1da177e4
LT		 39#include "../pci.h"
40#include "pciehp.h"
1da177e4
LT		 41#ifdef DEBUG
42#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
43#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
44#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
45#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
46#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
47#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
48/* Redefine this flagword to set debug level */
49#define DEBUG_LEVEL DBG_K_STANDARD
50
51#define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
52
53#define DBG_PRINT( dbg_flags, args... ) \
54 do { \
55 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
56 { \
57 int len; \
58 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
59 __FILE__, __LINE__, __FUNCTION__ ); \
60 sprintf( __dbg_str_buf + len, args ); \
61 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
62 } \
63 } while (0)
64
65#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
66#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
67#else
68#define DEFINE_DBG_BUFFER
69#define DBG_ENTER_ROUTINE
70#define DBG_LEAVE_ROUTINE
71#endif /* DEBUG */
72
73struct ctrl_reg {
74 u8 cap_id;
75 u8 nxt_ptr;
76 u16 cap_reg;
77 u32 dev_cap;
78 u16 dev_ctrl;
79 u16 dev_status;
80 u32 lnk_cap;
81 u16 lnk_ctrl;
82 u16 lnk_status;
83 u32 slot_cap;
84 u16 slot_ctrl;
85 u16 slot_status;
86 u16 root_ctrl;
87 u16 rsvp;
88 u32 root_status;
89} __attribute__ ((packed));
90
91/* offsets to the controller registers based on the above structure layout */
92enum ctrl_offsets {
93 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
94 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
95 CAPREG = offsetof(struct ctrl_reg, cap_reg),
96 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
97 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
98 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
99 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
100 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
101 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
102 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
103 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
104 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
105 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
106 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
107};
108static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
109
8b245e45
DS		 110#define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
111#define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
112#define CAP_REG(cb) ( cb + CAPREG )
113#define DEV_CAP(cb) ( cb + DEVCAP )
114#define DEV_CTRL(cb) ( cb + DEVCTRL )
115#define DEV_STATUS(cb) ( cb + DEVSTATUS )
116#define LNK_CAP(cb) ( cb + LNKCAP )
117#define LNK_CTRL(cb) ( cb + LNKCTRL )
118#define LNK_STATUS(cb) ( cb + LNKSTATUS )
119#define SLOT_CAP(cb) ( cb + SLOTCAP )
120#define SLOT_CTRL(cb) ( cb + SLOTCTRL )
121#define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
122#define ROOT_CTRL(cb) ( cb + ROOTCTRL )
123#define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
1da177e4
LT		 124
125#define hp_register_read_word(pdev, reg , value) \
126 pci_read_config_word(pdev, reg, &value)
127
128#define hp_register_read_dword(pdev, reg , value) \
129 pci_read_config_dword(pdev, reg, &value)
130
131#define hp_register_write_word(pdev, reg , value) \
132 pci_write_config_word(pdev, reg, value)
133
134#define hp_register_dwrite_word(pdev, reg , value) \
135 pci_write_config_dword(pdev, reg, value)
136
137/* Field definitions in PCI Express Capabilities Register */
138#define CAP_VER 0x000F
139#define DEV_PORT_TYPE 0x00F0
140#define SLOT_IMPL 0x0100
141#define MSG_NUM 0x3E00
142
143/* Device or Port Type */
144#define NAT_ENDPT 0x00
145#define LEG_ENDPT 0x01
146#define ROOT_PORT 0x04
147#define UP_STREAM 0x05
148#define DN_STREAM 0x06
149#define PCIE_PCI_BRDG 0x07
150#define PCI_PCIE_BRDG 0x10
151
152/* Field definitions in Device Capabilities Register */
153#define DATTN_BUTTN_PRSN 0x1000
154#define DATTN_LED_PRSN 0x2000
155#define DPWR_LED_PRSN 0x4000
156
157/* Field definitions in Link Capabilities Register */
158#define MAX_LNK_SPEED 0x000F
159#define MAX_LNK_WIDTH 0x03F0
160
161/* Link Width Encoding */
162#define LNK_X1 0x01
163#define LNK_X2 0x02
164#define LNK_X4 0x04
165#define LNK_X8 0x08
166#define LNK_X12 0x0C
167#define LNK_X16 0x10
168#define LNK_X32 0x20
169
170/*Field definitions of Link Status Register */
171#define LNK_SPEED 0x000F
172#define NEG_LINK_WD 0x03F0
173#define LNK_TRN_ERR 0x0400
174#define LNK_TRN 0x0800
175#define SLOT_CLK_CONF 0x1000
176
177/* Field definitions in Slot Capabilities Register */
178#define ATTN_BUTTN_PRSN 0x00000001
179#define PWR_CTRL_PRSN 0x00000002
180#define MRL_SENS_PRSN 0x00000004
181#define ATTN_LED_PRSN 0x00000008
182#define PWR_LED_PRSN 0x00000010
183#define HP_SUPR_RM_SUP 0x00000020
184#define HP_CAP 0x00000040
185#define SLOT_PWR_VALUE 0x000003F8
186#define SLOT_PWR_LIMIT 0x00000C00
187#define PSN 0xFFF80000 /* PSN: Physical Slot Number */
188
189/* Field definitions in Slot Control Register */
190#define ATTN_BUTTN_ENABLE 0x0001
191#define PWR_FAULT_DETECT_ENABLE 0x0002
192#define MRL_DETECT_ENABLE 0x0004
193#define PRSN_DETECT_ENABLE 0x0008
194#define CMD_CMPL_INTR_ENABLE 0x0010
195#define HP_INTR_ENABLE 0x0020
196#define ATTN_LED_CTRL 0x00C0
197#define PWR_LED_CTRL 0x0300
198#define PWR_CTRL 0x0400
199
200/* Attention indicator and Power indicator states */
201#define LED_ON 0x01
202#define LED_BLINK 0x10
203#define LED_OFF 0x11
204
205/* Power Control Command */
206#define POWER_ON 0
207#define POWER_OFF 0x0400
208
209/* Field definitions in Slot Status Register */
210#define ATTN_BUTTN_PRESSED 0x0001
211#define PWR_FAULT_DETECTED 0x0002
212#define MRL_SENS_CHANGED 0x0004
213#define PRSN_DETECT_CHANGED 0x0008
214#define CMD_COMPLETED 0x0010
215#define MRL_STATE 0x0020
216#define PRSN_STATE 0x0040
217
1da177e4
LT		 218static spinlock_t hpc_event_lock;
219
220DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
221static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
222static int ctlr_seq_num = 0; /* Controller sequence # */
223static spinlock_t list_lock;
224
7d12e780 225static irqreturn_t pcie_isr(int IRQ, void *dev_id);
1da177e4
LT		 226
227static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
228
229/* This is the interrupt polling timeout function. */
230static void int_poll_timeout(unsigned long lphp_ctlr)
231{
232 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
233
234 DBG_ENTER_ROUTINE
235
236 if ( !php_ctlr ) {
237 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
238 return;
239 }
240
241 /* Poll for interrupt events. regs == NULL => polling */
7d12e780 242 pcie_isr( 0, (void *)php_ctlr );
1da177e4
LT		 243
244 init_timer(&php_ctlr->int_poll_timer);
245
246 if (!pciehp_poll_time)
247 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
248
249 start_int_poll_timer(php_ctlr, pciehp_poll_time);
250
251 return;
252}
253
254/* This function starts the interrupt polling timer. */
255static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
256{
257 if (!php_ctlr) {
258 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
259 return;
260 }
261
262 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
263 seconds = 2; /* Clamp to sane value */
264
265 php_ctlr->int_poll_timer.function = &int_poll_timeout;
266 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
267 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
268 add_timer(&php_ctlr->int_poll_timer);
269
270 return;
271}
272
273static int pcie_write_cmd(struct slot *slot, u16 cmd)
274{
275 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
276 int retval = 0;
277 u16 slot_status;
278
279 DBG_ENTER_ROUTINE
280
1da177e4
LT		 281 if (!php_ctlr) {
282 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
283 return -1;
284 }
285
8b245e45 286 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 287 if (retval) {
288 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
289 return retval;
290 }
1da177e4
LT		 291
292 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
293 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
294 the next command according to spec. Just print out the error message */
295 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
296 }
297
8b245e45 298 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
1da177e4
LT		 299 if (retval) {
300 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
301 return retval;
302 }
1da177e4
LT		 303
304 DBG_LEAVE_ROUTINE
305 return retval;
306}
307
308static int hpc_check_lnk_status(struct controller *ctrl)
309{
310 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
311 u16 lnk_status;
312 int retval = 0;
313
314 DBG_ENTER_ROUTINE
315
316 if (!php_ctlr) {
317 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
318 return -1;
319 }
320
8b245e45 321 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
1da177e4
LT		 322
323 if (retval) {
324 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
325 return retval;
326 }
327
328 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
329 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
330 !(lnk_status & NEG_LINK_WD)) {
331 err("%s : Link Training Error occurs \n", __FUNCTION__);
332 retval = -1;
333 return retval;
334 }
335
336 DBG_LEAVE_ROUTINE
337 return retval;
338}
339
340
341static int hpc_get_attention_status(struct slot *slot, u8 *status)
342{
343 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
344 u16 slot_ctrl;
345 u8 atten_led_state;
346 int retval = 0;
347
348 DBG_ENTER_ROUTINE
349
350 if (!php_ctlr) {
351 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
352 return -1;
353 }
354
8b245e45 355 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 356
357 if (retval) {
358 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
359 return retval;
360 }
361
8b245e45 362 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 363
364 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
365
366 switch (atten_led_state) {
367 case 0:
368 *status = 0xFF; /* Reserved */
369 break;
370 case 1:
371 *status = 1; /* On */
372 break;
373 case 2:
374 *status = 2; /* Blink */
375 break;
376 case 3:
377 *status = 0; /* Off */
378 break;
379 default:
380 *status = 0xFF;
381 break;
382 }
383
384 DBG_LEAVE_ROUTINE
385 return 0;
386}
387
388static int hpc_get_power_status(struct slot * slot, u8 *status)
389{
390 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
391 u16 slot_ctrl;
392 u8 pwr_state;
393 int retval = 0;
394
395 DBG_ENTER_ROUTINE
396
397 if (!php_ctlr) {
398 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
399 return -1;
400 }
401
8b245e45 402 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 403
404 if (retval) {
405 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
406 return retval;
407 }
8b245e45 408 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 409
410 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
411
412 switch (pwr_state) {
413 case 0:
414 *status = 1;
415 break;
416 case 1:
417 *status = 0;
418 break;
419 default:
420 *status = 0xFF;
421 break;
422 }
423
424 DBG_LEAVE_ROUTINE
425 return retval;
426}
427
428
429static int hpc_get_latch_status(struct slot *slot, u8 *status)
430{
431 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
432 u16 slot_status;
433 int retval = 0;
434
435 DBG_ENTER_ROUTINE
436
437 if (!php_ctlr) {
438 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
439 return -1;
440 }
441
8b245e45 442 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 443
444 if (retval) {
445 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
446 return retval;
447 }
448
449 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
450
451 DBG_LEAVE_ROUTINE
452 return 0;
453}
454
455static int hpc_get_adapter_status(struct slot *slot, u8 *status)
456{
457 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
458 u16 slot_status;
459 u8 card_state;
460 int retval = 0;
461
462 DBG_ENTER_ROUTINE
463
464 if (!php_ctlr) {
465 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
466 return -1;
467 }
468
8b245e45 469 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 470
471 if (retval) {
472 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
473 return retval;
474 }
475 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
476 *status = (card_state == 1) ? 1 : 0;
477
478 DBG_LEAVE_ROUTINE
479 return 0;
480}
481
482static int hpc_query_power_fault(struct slot * slot)
483{
484 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
485 u16 slot_status;
486 u8 pwr_fault;
487 int retval = 0;
1da177e4
LT		 488
489 DBG_ENTER_ROUTINE
490
491 if (!php_ctlr) {
492 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
493 return -1;
494 }
495
8b245e45 496 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
1da177e4
LT		 497
498 if (retval) {
8239def1 499 err("%s : Cannot check for power fault\n", __FUNCTION__);
1da177e4
LT		 500 return retval;
501 }
502 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
1da177e4
LT		 503
504 DBG_LEAVE_ROUTINE
8239def1 505 return pwr_fault;
1da177e4
LT		 506}
507
508static int hpc_set_attention_status(struct slot *slot, u8 value)
509{
510 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
511 u16 slot_cmd = 0;
512 u16 slot_ctrl;
513 int rc = 0;
514
1a9ed1bf 515 DBG_ENTER_ROUTINE
516
1da177e4
LT		 517 if (!php_ctlr) {
518 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
519 return -1;
520 }
521
522 if (slot->hp_slot >= php_ctlr->num_slots) {
523 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
524 return -1;
525 }
8b245e45 526 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 527
528 if (rc) {
529 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
530 return rc;
531 }
1da177e4
LT		 532
533 switch (value) {
534 case 0 : /* turn off */
535 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
536 break;
537 case 1: /* turn on */
538 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
539 break;
540 case 2: /* turn blink */
541 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
542 break;
543 default:
544 return -1;
545 }
546 if (!pciehp_poll_mode)
547 slot_cmd = slot_cmd | HP_INTR_ENABLE;
548
549 pcie_write_cmd(slot, slot_cmd);
8b245e45 550 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4 551
1a9ed1bf 552 DBG_LEAVE_ROUTINE
1da177e4
LT		 553 return rc;
554}
555
556
557static void hpc_set_green_led_on(struct slot *slot)
558{
559 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
560 u16 slot_cmd;
561 u16 slot_ctrl;
562 int rc = 0;
563
1a9ed1bf 564 DBG_ENTER_ROUTINE
565
1da177e4
LT		 566 if (!php_ctlr) {
567 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
568 return ;
569 }
570
571 if (slot->hp_slot >= php_ctlr->num_slots) {
572 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
573 return ;
574 }
575
8b245e45 576 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 577
578 if (rc) {
579 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
580 return;
581 }
1da177e4
LT		 582 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
583 if (!pciehp_poll_mode)
584 slot_cmd = slot_cmd | HP_INTR_ENABLE;
585
586 pcie_write_cmd(slot, slot_cmd);
587
8b245e45 588 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1a9ed1bf 589 DBG_LEAVE_ROUTINE
1da177e4
LT		 590 return;
591}
592
593static void hpc_set_green_led_off(struct slot *slot)
594{
595 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
596 u16 slot_cmd;
597 u16 slot_ctrl;
598 int rc = 0;
599
1a9ed1bf 600 DBG_ENTER_ROUTINE
601
1da177e4
LT		 602 if (!php_ctlr) {
603 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
604 return ;
605 }
606
607 if (slot->hp_slot >= php_ctlr->num_slots) {
608 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
609 return ;
610 }
611
8b245e45 612 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 613
614 if (rc) {
615 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
616 return;
617 }
1da177e4
LT		 618
619 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
620
621 if (!pciehp_poll_mode)
622 slot_cmd = slot_cmd | HP_INTR_ENABLE;
623 pcie_write_cmd(slot, slot_cmd);
8b245e45 624 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4 625
1a9ed1bf 626 DBG_LEAVE_ROUTINE
1da177e4
LT		 627 return;
628}
629
630static void hpc_set_green_led_blink(struct slot *slot)
631{
632 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
633 u16 slot_cmd;
634 u16 slot_ctrl;
635 int rc = 0;
636
1a9ed1bf 637 DBG_ENTER_ROUTINE
638
1da177e4
LT		 639 if (!php_ctlr) {
640 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
641 return ;
642 }
643
644 if (slot->hp_slot >= php_ctlr->num_slots) {
645 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
646 return ;
647 }
648
8b245e45 649 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 650
651 if (rc) {
652 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
653 return;
654 }
1da177e4
LT		 655
656 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
657
658 if (!pciehp_poll_mode)
659 slot_cmd = slot_cmd | HP_INTR_ENABLE;
660 pcie_write_cmd(slot, slot_cmd);
661
8b245e45 662 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1a9ed1bf 663 DBG_LEAVE_ROUTINE
1da177e4
LT		 664 return;
665}
666
667int pcie_get_ctlr_slot_config(struct controller *ctrl,
668 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
669 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
670 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
671 u8 *ctrlcap)
672{
673 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
674 u32 slot_cap;
675 int rc = 0;
676
677 DBG_ENTER_ROUTINE
678
679 if (!php_ctlr) {
680 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
681 return -1;
682 }
683
684 *first_device_num = 0;
685 *num_ctlr_slots = 1;
686
8b245e45 687 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 688
689 if (rc) {
690 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
691 return -1;
692 }
693
694 *physical_slot_num = slot_cap >> 19;
695 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
696
697 *ctrlcap = slot_cap & 0x0000007f;
698
699 DBG_LEAVE_ROUTINE
700 return 0;
701}
702
703static void hpc_release_ctlr(struct controller *ctrl)
704{
705 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
706 struct php_ctlr_state_s *p, *p_prev;
707
708 DBG_ENTER_ROUTINE
709
710 if (!php_ctlr) {
711 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
712 return ;
713 }
714
715 if (pciehp_poll_mode) {
716 del_timer(&php_ctlr->int_poll_timer);
717 } else {
718 if (php_ctlr->irq) {
719 free_irq(php_ctlr->irq, ctrl);
720 php_ctlr->irq = 0;
1da177e4
LT		 721 }
722 }
723 if (php_ctlr->pci_dev)
724 php_ctlr->pci_dev = NULL;
725
726 spin_lock(&list_lock);
727 p = php_ctlr_list_head;
728 p_prev = NULL;
729 while (p) {
730 if (p == php_ctlr) {
731 if (p_prev)
732 p_prev->pnext = p->pnext;
733 else
734 php_ctlr_list_head = p->pnext;
735 break;
736 } else {
737 p_prev = p;
738 p = p->pnext;
739 }
740 }
741 spin_unlock(&list_lock);
742
743 kfree(php_ctlr);
744
745 DBG_LEAVE_ROUTINE
746
747}
748
749static int hpc_power_on_slot(struct slot * slot)
750{
751 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
752 u16 slot_cmd;
5a49f203 753 u16 slot_ctrl, slot_status;
1da177e4
LT		 754
755 int retval = 0;
756
757 DBG_ENTER_ROUTINE
1da177e4
LT		 758
759 if (!php_ctlr) {
760 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
761 return -1;
762 }
763
764 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
765 if (slot->hp_slot >= php_ctlr->num_slots) {
766 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
767 return -1;
768 }
769
5a49f203
RS		 770 /* Clear sticky power-fault bit from previous power failures */
771 hp_register_read_word(php_ctlr->pci_dev,
772 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
773 slot_status &= PWR_FAULT_DETECTED;
774 if (slot_status)
775 hp_register_write_word(php_ctlr->pci_dev,
776 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
777
8b245e45 778 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 779
780 if (retval) {
781 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
782 return retval;
783 }
1da177e4
LT		 784
785 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
786
c7ab337f 787 /* Enable detection that we turned off at slot power-off time */
1da177e4 788 if (!pciehp_poll_mode)
c7ab337f
TS		 789 slot_cmd = slot_cmd |
790 PWR_FAULT_DETECT_ENABLE |
791 MRL_DETECT_ENABLE |
792 PRSN_DETECT_ENABLE |
793 HP_INTR_ENABLE;
1da177e4
LT		 794
795 retval = pcie_write_cmd(slot, slot_cmd);
796
797 if (retval) {
798 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
799 return -1;
800 }
8b245e45 801 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4
LT		 802
803 DBG_LEAVE_ROUTINE
804
805 return retval;
806}
807
808static int hpc_power_off_slot(struct slot * slot)
809{
810 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
811 u16 slot_cmd;
812 u16 slot_ctrl;
813
814 int retval = 0;
815
816 DBG_ENTER_ROUTINE
1da177e4
LT		 817
818 if (!php_ctlr) {
819 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
820 return -1;
821 }
822
823 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
824 slot->hp_slot = 0;
825 if (slot->hp_slot >= php_ctlr->num_slots) {
826 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
827 return -1;
828 }
8b245e45 829 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
1da177e4
LT		 830
831 if (retval) {
832 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
833 return retval;
834 }
1da177e4
LT		 835
836 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
837
c7ab337f
TS		 838 /*
839 * If we get MRL or presence detect interrupts now, the isr
840 * will notice the sticky power-fault bit too and issue power
841 * indicator change commands. This will lead to an endless loop
842 * of command completions, since the power-fault bit remains on
843 * till the slot is powered on again.
844 */
1da177e4 845 if (!pciehp_poll_mode)
c7ab337f
TS		 846 slot_cmd = (slot_cmd &
847 ~PWR_FAULT_DETECT_ENABLE &
848 ~MRL_DETECT_ENABLE &
849 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
1da177e4
LT		 850
851 retval = pcie_write_cmd(slot, slot_cmd);
852
853 if (retval) {
854 err("%s: Write command failed!\n", __FUNCTION__);
855 return -1;
856 }
8b245e45 857 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
1da177e4
LT		 858
859 DBG_LEAVE_ROUTINE
860
861 return retval;
862}
863
7d12e780 864static irqreturn_t pcie_isr(int IRQ, void *dev_id)
1da177e4
LT		 865{
866 struct controller *ctrl = NULL;
867 struct php_ctlr_state_s *php_ctlr;
868 u8 schedule_flag = 0;
869 u16 slot_status, intr_detect, intr_loc;
870 u16 temp_word;
871 int hp_slot = 0; /* only 1 slot per PCI Express port */
872 int rc = 0;
873
874 if (!dev_id)
875 return IRQ_NONE;
876
877 if (!pciehp_poll_mode) {
878 ctrl = dev_id;
879 php_ctlr = ctrl->hpc_ctlr_handle;
880 } else {
881 php_ctlr = dev_id;
882 ctrl = (struct controller *)php_ctlr->callback_instance_id;
883 }
884
885 if (!ctrl) {
886 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
887 return IRQ_NONE;
888 }
889
890 if (!php_ctlr) {
891 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
892 return IRQ_NONE;
893 }
894
8b245e45 895 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 896 if (rc) {
897 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
898 return IRQ_NONE;
899 }
900
901 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
902 PRSN_DETECT_CHANGED | CMD_COMPLETED );
903
904 intr_loc = slot_status & intr_detect;
905
906 /* Check to see if it was our interrupt */
907 if ( !intr_loc )
908 return IRQ_NONE;
909
910 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
911 /* Mask Hot-plug Interrupt Enable */
912 if (!pciehp_poll_mode) {
8b245e45 913 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 914 if (rc) {
915 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
916 return IRQ_NONE;
917 }
918
1da177e4
LT		 919 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
920 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
921
8b245e45 922 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 923 if (rc) {
924 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
925 return IRQ_NONE;
926 }
1da177e4 927
8b245e45 928 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 929 if (rc) {
930 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
931 return IRQ_NONE;
932 }
933 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
934
935 /* Clear command complete interrupt caused by this write */
936 temp_word = 0x1f;
8b245e45 937 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 938 if (rc) {
939 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
940 return IRQ_NONE;
941 }
1da177e4
LT		 942 }
943
944 if (intr_loc & CMD_COMPLETED) {
945 /*
946 * Command Complete Interrupt Pending
947 */
1da177e4
LT		 948 wake_up_interruptible(&ctrl->queue);
949 }
950
951 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
952 schedule_flag += php_ctlr->switch_change_callback(
953 hp_slot, php_ctlr->callback_instance_id);
954 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
955 schedule_flag += php_ctlr->attention_button_callback(
956 hp_slot, php_ctlr->callback_instance_id);
957 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
958 schedule_flag += php_ctlr->presence_change_callback(
959 hp_slot , php_ctlr->callback_instance_id);
960 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
961 schedule_flag += php_ctlr->power_fault_callback(
962 hp_slot, php_ctlr->callback_instance_id);
963
964 /* Clear all events after serving them */
965 temp_word = 0x1F;
8b245e45 966 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 967 if (rc) {
968 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
969 return IRQ_NONE;
970 }
971 /* Unmask Hot-plug Interrupt Enable */
972 if (!pciehp_poll_mode) {
8b245e45 973 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 974 if (rc) {
975 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
976 return IRQ_NONE;
977 }
978
979 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
1da177e4
LT		 980 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
981
8b245e45 982 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 983 if (rc) {
984 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
985 return IRQ_NONE;
986 }
1da177e4 987
8b245e45 988 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 989 if (rc) {
990 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
991 return IRQ_NONE;
992 }
1da177e4
LT		 993
994 /* Clear command complete interrupt caused by this write */
995 temp_word = 0x1F;
8b245e45 996 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 997 if (rc) {
998 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
999 return IRQ_NONE;
1000 }
1001 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1002 }
1003
1004 return IRQ_HANDLED;
1005}
1006
1007static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1008{
1009 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1010 enum pcie_link_speed lnk_speed;
1011 u32 lnk_cap;
1012 int retval = 0;
1013
1014 DBG_ENTER_ROUTINE
1015
1016 if (!php_ctlr) {
1017 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1018 return -1;
1019 }
1020
1021 if (slot->hp_slot >= php_ctlr->num_slots) {
1022 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1023 return -1;
1024 }
1025
8b245e45 1026 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1da177e4
LT		 1027
1028 if (retval) {
1029 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1030 return retval;
1031 }
1032
1033 switch (lnk_cap & 0x000F) {
1034 case 1:
1035 lnk_speed = PCIE_2PT5GB;
1036 break;
1037 default:
1038 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1039 break;
1040 }
1041
1042 *value = lnk_speed;
1043 dbg("Max link speed = %d\n", lnk_speed);
1044 DBG_LEAVE_ROUTINE
1045 return retval;
1046}
1047
1048static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1049{
1050 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1051 enum pcie_link_width lnk_wdth;
1052 u32 lnk_cap;
1053 int retval = 0;
1054
1055 DBG_ENTER_ROUTINE
1056
1057 if (!php_ctlr) {
1058 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1059 return -1;
1060 }
1061
1062 if (slot->hp_slot >= php_ctlr->num_slots) {
1063 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1064 return -1;
1065 }
1066
8b245e45 1067 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1da177e4
LT		 1068
1069 if (retval) {
1070 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1071 return retval;
1072 }
1073
1074 switch ((lnk_cap & 0x03F0) >> 4){
1075 case 0:
1076 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1077 break;
1078 case 1:
1079 lnk_wdth = PCIE_LNK_X1;
1080 break;
1081 case 2:
1082 lnk_wdth = PCIE_LNK_X2;
1083 break;
1084 case 4:
1085 lnk_wdth = PCIE_LNK_X4;
1086 break;
1087 case 8:
1088 lnk_wdth = PCIE_LNK_X8;
1089 break;
1090 case 12:
1091 lnk_wdth = PCIE_LNK_X12;
1092 break;
1093 case 16:
1094 lnk_wdth = PCIE_LNK_X16;
1095 break;
1096 case 32:
1097 lnk_wdth = PCIE_LNK_X32;
1098 break;
1099 default:
1100 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1101 break;
1102 }
1103
1104 *value = lnk_wdth;
1105 dbg("Max link width = %d\n", lnk_wdth);
1106 DBG_LEAVE_ROUTINE
1107 return retval;
1108}
1109
1110static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1111{
1112 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1113 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1114 int retval = 0;
1115 u16 lnk_status;
1116
1117 DBG_ENTER_ROUTINE
1118
1119 if (!php_ctlr) {
1120 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1121 return -1;
1122 }
1123
1124 if (slot->hp_slot >= php_ctlr->num_slots) {
1125 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1126 return -1;
1127 }
1128
8b245e45 1129 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1da177e4
LT		 1130
1131 if (retval) {
1132 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1133 return retval;
1134 }
1135
1136 switch (lnk_status & 0x0F) {
1137 case 1:
1138 lnk_speed = PCIE_2PT5GB;
1139 break;
1140 default:
1141 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1142 break;
1143 }
1144
1145 *value = lnk_speed;
1146 dbg("Current link speed = %d\n", lnk_speed);
1147 DBG_LEAVE_ROUTINE
1148 return retval;
1149}
1150
1151static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1152{
1153 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1154 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1155 int retval = 0;
1156 u16 lnk_status;
1157
1158 DBG_ENTER_ROUTINE
1159
1160 if (!php_ctlr) {
1161 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1162 return -1;
1163 }
1164
1165 if (slot->hp_slot >= php_ctlr->num_slots) {
1166 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1167 return -1;
1168 }
1169
8b245e45 1170 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1da177e4
LT		 1171
1172 if (retval) {
1173 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1174 return retval;
1175 }
1176
1177 switch ((lnk_status & 0x03F0) >> 4){
1178 case 0:
1179 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1180 break;
1181 case 1:
1182 lnk_wdth = PCIE_LNK_X1;
1183 break;
1184 case 2:
1185 lnk_wdth = PCIE_LNK_X2;
1186 break;
1187 case 4:
1188 lnk_wdth = PCIE_LNK_X4;
1189 break;
1190 case 8:
1191 lnk_wdth = PCIE_LNK_X8;
1192 break;
1193 case 12:
1194 lnk_wdth = PCIE_LNK_X12;
1195 break;
1196 case 16:
1197 lnk_wdth = PCIE_LNK_X16;
1198 break;
1199 case 32:
1200 lnk_wdth = PCIE_LNK_X32;
1201 break;
1202 default:
1203 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1204 break;
1205 }
1206
1207 *value = lnk_wdth;
1208 dbg("Current link width = %d\n", lnk_wdth);
1209 DBG_LEAVE_ROUTINE
1210 return retval;
1211}
1212
1213static struct hpc_ops pciehp_hpc_ops = {
1214 .power_on_slot = hpc_power_on_slot,
1215 .power_off_slot = hpc_power_off_slot,
1216 .set_attention_status = hpc_set_attention_status,
1217 .get_power_status = hpc_get_power_status,
1218 .get_attention_status = hpc_get_attention_status,
1219 .get_latch_status = hpc_get_latch_status,
1220 .get_adapter_status = hpc_get_adapter_status,
1221
1222 .get_max_bus_speed = hpc_get_max_lnk_speed,
1223 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1224 .get_max_lnk_width = hpc_get_max_lnk_width,
1225 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1226
1227 .query_power_fault = hpc_query_power_fault,
1228 .green_led_on = hpc_set_green_led_on,
1229 .green_led_off = hpc_set_green_led_off,
1230 .green_led_blink = hpc_set_green_led_blink,
1231
1232 .release_ctlr = hpc_release_ctlr,
1233 .check_lnk_status = hpc_check_lnk_status,
1234};
1235
783c49fc
KA		 1236#ifdef CONFIG_ACPI
1237int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1238{
1239 acpi_status status;
1240 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1241 struct pci_dev *pdev = dev;
1242 struct pci_bus *parent;
b2e6e3ba 1243 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
783c49fc
KA		 1244
1245 /*
1246 * Per PCI firmware specification, we should run the ACPI _OSC
1247 * method to get control of hotplug hardware before using it.
1248 * If an _OSC is missing, we look for an OSHP to do the same thing.
1249 * To handle different BIOS behavior, we look for _OSC and OSHP
1250 * within the scope of the hotplug controller and its parents, upto
1251 * the host bridge under which this controller exists.
1252 */
1253 while (!handle) {
1254 /*
1255 * This hotplug controller was not listed in the ACPI name
1256 * space at all. Try to get acpi handle of parent pci bus.
1257 */
1258 if (!pdev || !pdev->bus->parent)
1259 break;
1260 parent = pdev->bus->parent;
1261 dbg("Could not find %s in acpi namespace, trying parent\n",
1262 pci_name(pdev));
1263 if (!parent->self)
1264 /* Parent must be a host bridge */
1265 handle = acpi_get_pci_rootbridge_handle(
1266 pci_domain_nr(parent),
1267 parent->number);
1268 else
1269 handle = DEVICE_ACPI_HANDLE(
1270 &(parent->self->dev));
1271 pdev = parent->self;
1272 }
1273
1274 while (handle) {
b2e6e3ba
MT		 1275 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1276 dbg("Trying to get hotplug control for %s \n",
1277 (char *)string.pointer);
783c49fc
KA		 1278 status = pci_osc_control_set(handle,
1279 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1280 if (status == AE_NOT_FOUND)
1281 status = acpi_run_oshp(handle);
1282 if (ACPI_SUCCESS(status)) {
1283 dbg("Gained control for hotplug HW for pci %s (%s)\n",
b2e6e3ba 1284 pci_name(dev), (char *)string.pointer);
81b26bca 1285 kfree(string.pointer);
783c49fc
KA		 1286 return 0;
1287 }
1288 if (acpi_root_bridge(handle))
1289 break;
1290 chandle = handle;
1291 status = acpi_get_parent(chandle, &handle);
1292 if (ACPI_FAILURE(status))
1293 break;
1294 }
1295
1296 err("Cannot get control of hotplug hardware for pci %s\n",
1297 pci_name(dev));
b2e6e3ba 1298
81b26bca 1299 kfree(string.pointer);
783c49fc
KA		 1300 return -1;
1301}
1302#endif
1303
1304
1305
ed6cbcf2 1306int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1da177e4
LT		 1307{
1308 struct php_ctlr_state_s *php_ctlr, *p;
1309 void *instance_id = ctrl;
1310 int rc;
1311 static int first = 1;
1312 u16 temp_word;
1313 u16 cap_reg;
1314 u16 intr_enable = 0;
1315 u32 slot_cap;
1316 int cap_base, saved_cap_base;
1317 u16 slot_status, slot_ctrl;
1318 struct pci_dev *pdev;
1319
1320 DBG_ENTER_ROUTINE
1321
1322 spin_lock_init(&list_lock);
5cbded58 1323 php_ctlr = kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1da177e4
LT		 1324
1325 if (!php_ctlr) { /* allocate controller state data */
1326 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1327 goto abort;
1328 }
1329
1330 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1331
1332 pdev = dev->port;
1333 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1334
1a9ed1bf 1335 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1336 __FUNCTION__, pdev->vendor, pdev->device);
1da177e4
LT		 1337
1338 saved_cap_base = pcie_cap_base;
1339
1340 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1341 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1342 goto abort_free_ctlr;
1343 }
1344
8b245e45 1345 ctrl->cap_base = cap_base;
1da177e4
LT		 1346
1347 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1348
8b245e45 1349 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1da177e4
LT		 1350 if (rc) {
1351 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1352 goto abort_free_ctlr;
1353 }
8b245e45 1354 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1da177e4 1355
8b245e45
DS		 1356 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1357 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1da177e4
LT		 1358 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1359 goto abort_free_ctlr;
1360 }
1361
8b245e45 1362 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 1363 if (rc) {
1364 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1365 goto abort_free_ctlr;
1366 }
8b245e45 1367 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1da177e4
LT		 1368
1369 if (!(slot_cap & HP_CAP)) {
1370 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1371 goto abort_free_ctlr;
1372 }
1373 /* For debugging purpose */
8b245e45 1374 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1375 if (rc) {
1376 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1377 goto abort_free_ctlr;
1378 }
8b245e45 1379 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4 1380
8b245e45 1381 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1da177e4
LT		 1382 if (rc) {
1383 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1384 goto abort_free_ctlr;
1385 }
8b245e45 1386 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1da177e4
LT		 1387
1388 if (first) {
1389 spin_lock_init(&hpc_event_lock);
1390 first = 0;
1391 }
1392
1da177e4
LT		 1393 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1394 if (pci_resource_len(pdev, rc) > 0)
1396a8c3
GKH		 1395 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1396 (unsigned long long)pci_resource_start(pdev, rc),
1397 (unsigned long long)pci_resource_len(pdev, rc));
1da177e4
LT		 1398
1399 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1400 pdev->subsystem_vendor, pdev->subsystem_device);
1401
6aa4cdd0 1402 mutex_init(&ctrl->crit_sect);
dd5619cb
KK		 1403 mutex_init(&ctrl->ctrl_lock);
1404
1da177e4
LT		 1405 /* setup wait queue */
1406 init_waitqueue_head(&ctrl->queue);
1407
1408 /* find the IRQ */
1409 php_ctlr->irq = dev->irq;
1da177e4
LT		 1410
1411 /* Save interrupt callback info */
ed6cbcf2 1412 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1413 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1414 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1415 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1da177e4
LT		 1416 php_ctlr->callback_instance_id = instance_id;
1417
1418 /* return PCI Controller Info */
1419 php_ctlr->slot_device_offset = 0;
1420 php_ctlr->num_slots = 1;
1421
1422 /* Mask Hot-plug Interrupt Enable */
8b245e45 1423 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1424 if (rc) {
1425 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1426 goto abort_free_ctlr;
1427 }
1428
8b245e45 1429 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1430 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1431
8b245e45 1432 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1433 if (rc) {
1434 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1435 goto abort_free_ctlr;
1436 }
1da177e4 1437
8b245e45 1438 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1439 if (rc) {
1440 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1441 goto abort_free_ctlr;
1442 }
1da177e4
LT		 1443
1444 temp_word = 0x1F; /* Clear all events */
8b245e45 1445 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 1446 if (rc) {
1447 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1448 goto abort_free_ctlr;
1449 }
1da177e4
LT		 1450
1451 if (pciehp_poll_mode) {/* Install interrupt polling code */
1452 /* Install and start the interrupt polling timer */
1453 init_timer(&php_ctlr->int_poll_timer);
1454 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1455 } else {
1456 /* Installs the interrupt handler */
6b4486e2 1457 rc = request_irq(php_ctlr->irq, pcie_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
1da177e4
LT		 1458 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1459 if (rc) {
1460 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1461 goto abort_free_ctlr;
1462 }
1463 }
1464
1a9ed1bf 1465 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1466 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1467
8b245e45 1468 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1469 if (rc) {
1470 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
9c64f977 1471 goto abort_free_irq;
1da177e4 1472 }
1da177e4
LT		 1473
1474 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1475
1476 if (ATTN_BUTTN(slot_cap))
1477 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1478
1479 if (POWER_CTRL(slot_cap))
1480 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1481
1482 if (MRL_SENS(slot_cap))
1483 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1484
1485 temp_word = (temp_word & ~intr_enable) | intr_enable;
1486
1487 if (pciehp_poll_mode) {
1488 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1489 } else {
1490 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1491 }
1da177e4
LT		 1492
1493 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
8b245e45 1494 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1da177e4
LT		 1495 if (rc) {
1496 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
9c64f977 1497 goto abort_free_irq;
1da177e4 1498 }
8b245e45 1499 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1da177e4
LT		 1500 if (rc) {
1501 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
9c64f977 1502 goto abort_disable_intr;
1da177e4 1503 }
1da177e4
LT		 1504
1505 temp_word = 0x1F; /* Clear all events */
8b245e45 1506 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1da177e4
LT		 1507 if (rc) {
1508 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
9c64f977 1509 goto abort_disable_intr;
1da177e4 1510 }
1da177e4 1511
a3a45ec8 1512 if (pciehp_force) {
1513 dbg("Bypassing BIOS check for pciehp use on %s\n",
1514 pci_name(ctrl->pci_dev));
1515 } else {
6560aa5c 1516 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
a3a45ec8 1517 if (rc)
9c64f977 1518 goto abort_disable_intr;
a3a45ec8 1519 }
a8a2be94 1520
1da177e4
LT		 1521 /* Add this HPC instance into the HPC list */
1522 spin_lock(&list_lock);
1523 if (php_ctlr_list_head == 0) {
1524 php_ctlr_list_head = php_ctlr;
1525 p = php_ctlr_list_head;
1526 p->pnext = NULL;
1527 } else {
1528 p = php_ctlr_list_head;
1529
1530 while (p->pnext)
1531 p = p->pnext;
1532
1533 p->pnext = php_ctlr;
1534 }
1535 spin_unlock(&list_lock);
1536
1537 ctlr_seq_num++;
1538 ctrl->hpc_ctlr_handle = php_ctlr;
1539 ctrl->hpc_ops = &pciehp_hpc_ops;
1540
1541 DBG_LEAVE_ROUTINE
1542 return 0;
1543
1544 /* We end up here for the many possible ways to fail this API. */
9c64f977
JB		 1545abort_disable_intr:
1546 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1547 if (!rc) {
1548 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1549 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1550 }
1551 if (rc)
1552 err("%s : disabling interrupts failed\n", __FUNCTION__);
1553
1554abort_free_irq:
1555 if (pciehp_poll_mode)
1556 del_timer_sync(&php_ctlr->int_poll_timer);
1557 else
1558 free_irq(php_ctlr->irq, ctrl);
1559
1da177e4
LT		 1560abort_free_ctlr:
1561 pcie_cap_base = saved_cap_base;
1562 kfree(php_ctlr);
1563abort:
1564 DBG_LEAVE_ROUTINE
1565 return -1;
1566}
Linux 6.x block layer and io_uring tree(s)