Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
a0f018da KK |
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
45 | { | |
385e2491 | 46 | struct pci_dev *dev = ctrl->pcie->port; |
537a77e6 | 47 | return pcie_capability_read_word(dev, reg, value); |
a0f018da KK |
48 | } |
49 | ||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
51 | { | |
385e2491 | 52 | struct pci_dev *dev = ctrl->pcie->port; |
537a77e6 | 53 | return pcie_capability_read_dword(dev, reg, value); |
a0f018da KK |
54 | } |
55 | ||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
57 | { | |
385e2491 | 58 | struct pci_dev *dev = ctrl->pcie->port; |
537a77e6 | 59 | return pcie_capability_write_word(dev, reg, value); |
a0f018da KK |
60 | } |
61 | ||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
63 | { | |
385e2491 | 64 | struct pci_dev *dev = ctrl->pcie->port; |
537a77e6 | 65 | return pcie_capability_write_dword(dev, reg, value); |
a0f018da | 66 | } |
1da177e4 | 67 | |
1da177e4 LT |
68 | /* Power Control Command */ |
69 | #define POWER_ON 0 | |
322162a7 | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 71 | |
48fe3915 KK |
72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
73 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
74 | |
75 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 76 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 77 | { |
48fe3915 | 78 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 79 | |
1da177e4 | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 81 | pcie_isr(0, ctrl); |
1da177e4 | 82 | |
48fe3915 | 83 | init_timer(&ctrl->poll_timer); |
1da177e4 | 84 | if (!pciehp_poll_time) |
40730d10 | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 86 | |
48fe3915 | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
88 | } |
89 | ||
90 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 92 | { |
48fe3915 KK |
93 | /* Clamp to sane value */ |
94 | if ((sec <= 0) || (sec > 60)) | |
95 | sec = 2; | |
96 | ||
97 | ctrl->poll_timer.function = &int_poll_timeout; | |
98 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
99 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
100 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
101 | } |
102 | ||
2aeeef11 KK |
103 | static inline int pciehp_request_irq(struct controller *ctrl) |
104 | { | |
f7a10e32 | 105 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
106 | |
107 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
108 | if (pciehp_poll_mode) { | |
109 | init_timer(&ctrl->poll_timer); | |
110 | start_int_poll_timer(ctrl, 10); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | /* Installs the interrupt handler */ | |
115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
116 | if (retval) | |
7f2feec1 TI |
117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
118 | irq); | |
2aeeef11 KK |
119 | return retval; |
120 | } | |
121 | ||
122 | static inline void pciehp_free_irq(struct controller *ctrl) | |
123 | { | |
124 | if (pciehp_poll_mode) | |
125 | del_timer_sync(&ctrl->poll_timer); | |
126 | else | |
f7a10e32 | 127 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
128 | } |
129 | ||
563f1190 | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
131 | { |
132 | u16 slot_status; | |
322162a7 | 133 | int err, timeout = 1000; |
6592e02a | 134 | |
322162a7 KK |
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
138 | return 1; | |
820943b6 | 139 | } |
a5827f40 | 140 | while (timeout > 0) { |
66618bad KK |
141 | msleep(10); |
142 | timeout -= 10; | |
322162a7 KK |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
146 | return 1; | |
820943b6 | 147 | } |
6592e02a KK |
148 | } |
149 | return 0; /* timeout */ | |
6592e02a KK |
150 | } |
151 | ||
563f1190 | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 153 | { |
262303fe KK |
154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
155 | unsigned long timeout = msecs_to_jiffies(msecs); | |
156 | int rc; | |
157 | ||
6592e02a KK |
158 | if (poll) |
159 | rc = pcie_poll_cmd(ctrl); | |
160 | else | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 162 | if (!rc) |
7f2feec1 | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
164 | } |
165 | ||
f4778364 KK |
166 | /** |
167 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 168 | * @ctrl: controller to which the command is issued |
f4778364 KK |
169 | * @cmd: command value written to slot control register |
170 | * @mask: bitmask of slot control register to be modified | |
171 | */ | |
c27fb883 | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 173 | { |
1da177e4 LT |
174 | int retval = 0; |
175 | u16 slot_status; | |
f4778364 | 176 | u16 slot_ctrl; |
1da177e4 | 177 | |
44ef4cef KK |
178 | mutex_lock(&ctrl->ctrl_lock); |
179 | ||
322162a7 | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 181 | if (retval) { |
7f2feec1 TI |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | |
44ef4cef | 184 | goto out; |
a0f018da KK |
185 | } |
186 | ||
322162a7 | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
188 | if (!ctrl->no_cmd_complete) { |
189 | /* | |
190 | * After 1 sec and CMD_COMPLETED still not set, just | |
191 | * proceed forward to issue the next command according | |
192 | * to spec. Just print out the error message. | |
193 | */ | |
18b341b7 | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
195 | } else if (!NO_CMD_CMPL(ctrl)) { |
196 | /* | |
197 | * This controller semms to notify of command completed | |
198 | * event even though it supports none of power | |
199 | * controller, attention led, power led and EMI. | |
200 | */ | |
18b341b7 TI |
201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
202 | "wait for command completed event.\n"); | |
5808639b KK |
203 | ctrl->no_cmd_complete = 0; |
204 | } else { | |
18b341b7 TI |
205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
206 | "the controller is broken.\n"); | |
5808639b | 207 | } |
1da177e4 LT |
208 | } |
209 | ||
322162a7 | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 211 | if (retval) { |
7f2feec1 | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 213 | goto out; |
1da177e4 | 214 | } |
1da177e4 | 215 | |
f4778364 | 216 | slot_ctrl &= ~mask; |
b7aa1f16 | 217 | slot_ctrl |= (cmd & mask); |
f4778364 | 218 | ctrl->cmd_busy = 1; |
2d32a9ae | 219 | smp_mb(); |
322162a7 | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 221 | if (retval) |
18b341b7 | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 223 | |
44ef4cef KK |
224 | /* |
225 | * Wait for command completion. | |
226 | */ | |
6592e02a KK |
227 | if (!retval && !ctrl->no_cmd_complete) { |
228 | int poll = 0; | |
229 | /* | |
230 | * if hotplug interrupt is not enabled or command | |
231 | * completed interrupt is not enabled, we need to poll | |
232 | * command completed event. | |
233 | */ | |
322162a7 KK |
234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 236 | poll = 1; |
d737bdc1 | 237 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 238 | } |
44ef4cef KK |
239 | out: |
240 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
241 | return retval; |
242 | } | |
243 | ||
4e2ce405 | 244 | static bool check_link_active(struct controller *ctrl) |
f18e9625 | 245 | { |
4e2ce405 YL |
246 | bool ret = false; |
247 | u16 lnk_status; | |
f18e9625 | 248 | |
4e2ce405 YL |
249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status)) |
250 | return ret; | |
251 | ||
252 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
253 | ||
254 | if (ret) | |
255 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
256 | ||
257 | return ret; | |
f18e9625 KK |
258 | } |
259 | ||
bffe4f72 | 260 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
261 | { |
262 | int timeout = 1000; | |
263 | ||
bffe4f72 | 264 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
265 | return; |
266 | while (timeout > 0) { | |
267 | msleep(10); | |
268 | timeout -= 10; | |
bffe4f72 | 269 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
270 | return; |
271 | } | |
bffe4f72 YL |
272 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
273 | active ? "set" : "cleared"); | |
274 | } | |
275 | ||
276 | static void pcie_wait_link_active(struct controller *ctrl) | |
277 | { | |
278 | __pcie_wait_link_active(ctrl, true); | |
279 | } | |
280 | ||
281 | static void pcie_wait_link_not_active(struct controller *ctrl) | |
282 | { | |
283 | __pcie_wait_link_active(ctrl, false); | |
f18e9625 KK |
284 | } |
285 | ||
2f5d8e4f YL |
286 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
287 | { | |
288 | u32 l; | |
289 | int count = 0; | |
290 | int delay = 1000, step = 20; | |
291 | bool found = false; | |
292 | ||
293 | do { | |
294 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
295 | count++; | |
296 | ||
297 | if (found) | |
298 | break; | |
299 | ||
300 | msleep(step); | |
301 | delay -= step; | |
302 | } while (delay > 0); | |
303 | ||
304 | if (count > 1 && pciehp_debug) | |
305 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
306 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
307 | PCI_FUNC(devfn), count, step, l); | |
308 | ||
309 | return found; | |
310 | } | |
311 | ||
82a9e79e | 312 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 313 | { |
1da177e4 LT |
314 | u16 lnk_status; |
315 | int retval = 0; | |
2f5d8e4f | 316 | bool found = false; |
1da177e4 | 317 | |
f18e9625 KK |
318 | /* |
319 | * Data Link Layer Link Active Reporting must be capable for | |
320 | * hot-plug capable downstream port. But old controller might | |
321 | * not implement it. In this case, we wait for 1000 ms. | |
322 | */ | |
0cab0841 | 323 | if (ctrl->link_active_reporting) |
f18e9625 | 324 | pcie_wait_link_active(ctrl); |
0cab0841 | 325 | else |
f18e9625 KK |
326 | msleep(1000); |
327 | ||
2f5d8e4f YL |
328 | /* wait 100ms before read pci conf, and try in 1s */ |
329 | msleep(100); | |
330 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
331 | PCI_DEVFN(0, 0)); | |
0027cb3e | 332 | |
322162a7 | 333 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 334 | if (retval) { |
18b341b7 | 335 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
336 | return retval; |
337 | } | |
338 | ||
7f2feec1 | 339 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
340 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
341 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 342 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
343 | retval = -1; |
344 | return retval; | |
345 | } | |
346 | ||
fdbd3ce9 YL |
347 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
348 | ||
2f5d8e4f YL |
349 | if (!found && !retval) |
350 | retval = -1; | |
351 | ||
1da177e4 LT |
352 | return retval; |
353 | } | |
354 | ||
7f822999 YL |
355 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
356 | { | |
357 | u16 lnk_ctrl; | |
358 | int retval = 0; | |
359 | ||
360 | retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl); | |
361 | if (retval) { | |
362 | ctrl_err(ctrl, "Cannot read LNKCTRL register\n"); | |
363 | return retval; | |
364 | } | |
365 | ||
366 | if (enable) | |
367 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
368 | else | |
369 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
370 | ||
371 | retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl); | |
372 | if (retval) { | |
373 | ctrl_err(ctrl, "Cannot write LNKCTRL register\n"); | |
374 | return retval; | |
375 | } | |
376 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); | |
377 | ||
378 | return retval; | |
379 | } | |
380 | ||
381 | static int pciehp_link_enable(struct controller *ctrl) | |
382 | { | |
383 | return __pciehp_link_set(ctrl, true); | |
384 | } | |
385 | ||
386 | static int pciehp_link_disable(struct controller *ctrl) | |
387 | { | |
388 | return __pciehp_link_set(ctrl, false); | |
389 | } | |
390 | ||
82a9e79e | 391 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 392 | { |
48fe3915 | 393 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
394 | u16 slot_ctrl; |
395 | u8 atten_led_state; | |
396 | int retval = 0; | |
1da177e4 | 397 | |
322162a7 | 398 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 399 | if (retval) { |
7f2feec1 | 400 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
401 | return retval; |
402 | } | |
403 | ||
1518c17a KK |
404 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
405 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 406 | |
322162a7 | 407 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
408 | |
409 | switch (atten_led_state) { | |
410 | case 0: | |
411 | *status = 0xFF; /* Reserved */ | |
412 | break; | |
413 | case 1: | |
414 | *status = 1; /* On */ | |
415 | break; | |
416 | case 2: | |
417 | *status = 2; /* Blink */ | |
418 | break; | |
419 | case 3: | |
420 | *status = 0; /* Off */ | |
421 | break; | |
422 | default: | |
423 | *status = 0xFF; | |
424 | break; | |
425 | } | |
426 | ||
1da177e4 LT |
427 | return 0; |
428 | } | |
429 | ||
82a9e79e | 430 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 431 | { |
48fe3915 | 432 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
433 | u16 slot_ctrl; |
434 | u8 pwr_state; | |
435 | int retval = 0; | |
1da177e4 | 436 | |
322162a7 | 437 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 438 | if (retval) { |
7f2feec1 | 439 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
440 | return retval; |
441 | } | |
1518c17a KK |
442 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
443 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 444 | |
322162a7 | 445 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
446 | |
447 | switch (pwr_state) { | |
448 | case 0: | |
449 | *status = 1; | |
450 | break; | |
451 | case 1: | |
71ad556d | 452 | *status = 0; |
1da177e4 LT |
453 | break; |
454 | default: | |
455 | *status = 0xFF; | |
456 | break; | |
457 | } | |
458 | ||
1da177e4 LT |
459 | return retval; |
460 | } | |
461 | ||
82a9e79e | 462 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 463 | { |
48fe3915 | 464 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 465 | u16 slot_status; |
322162a7 | 466 | int retval; |
1da177e4 | 467 | |
322162a7 | 468 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 469 | if (retval) { |
7f2feec1 TI |
470 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
471 | __func__); | |
1da177e4 LT |
472 | return retval; |
473 | } | |
322162a7 | 474 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
475 | return 0; |
476 | } | |
477 | ||
82a9e79e | 478 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 479 | { |
48fe3915 | 480 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 481 | u16 slot_status; |
322162a7 | 482 | int retval; |
1da177e4 | 483 | |
322162a7 | 484 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 485 | if (retval) { |
7f2feec1 TI |
486 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
487 | __func__); | |
1da177e4 LT |
488 | return retval; |
489 | } | |
322162a7 | 490 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
491 | return 0; |
492 | } | |
493 | ||
82a9e79e | 494 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 495 | { |
48fe3915 | 496 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 497 | u16 slot_status; |
322162a7 | 498 | int retval; |
1da177e4 | 499 | |
322162a7 | 500 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 501 | if (retval) { |
18b341b7 | 502 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
503 | return retval; |
504 | } | |
322162a7 | 505 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
506 | } |
507 | ||
82a9e79e | 508 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 509 | { |
48fe3915 | 510 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
511 | u16 slot_cmd; |
512 | u16 cmd_mask; | |
1da177e4 | 513 | |
322162a7 | 514 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 515 | switch (value) { |
445f7985 KK |
516 | case 0 : /* turn off */ |
517 | slot_cmd = 0x00C0; | |
518 | break; | |
519 | case 1: /* turn on */ | |
520 | slot_cmd = 0x0040; | |
521 | break; | |
522 | case 2: /* turn blink */ | |
523 | slot_cmd = 0x0080; | |
524 | break; | |
525 | default: | |
526 | return -EINVAL; | |
1da177e4 | 527 | } |
1518c17a KK |
528 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
529 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 530 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
531 | } |
532 | ||
82a9e79e | 533 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 534 | { |
48fe3915 | 535 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 536 | u16 slot_cmd; |
f4778364 | 537 | u16 cmd_mask; |
71ad556d | 538 | |
f4778364 | 539 | slot_cmd = 0x0100; |
322162a7 | 540 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 541 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
542 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
543 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
544 | } |
545 | ||
82a9e79e | 546 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 547 | { |
48fe3915 | 548 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 549 | u16 slot_cmd; |
f4778364 | 550 | u16 cmd_mask; |
1da177e4 | 551 | |
f4778364 | 552 | slot_cmd = 0x0300; |
322162a7 | 553 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 554 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
555 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
556 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
557 | } |
558 | ||
82a9e79e | 559 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 560 | { |
48fe3915 | 561 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 562 | u16 slot_cmd; |
f4778364 | 563 | u16 cmd_mask; |
71ad556d | 564 | |
f4778364 | 565 | slot_cmd = 0x0200; |
322162a7 | 566 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 567 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
568 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
569 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
570 | } |
571 | ||
82a9e79e | 572 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 573 | { |
48fe3915 | 574 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 575 | u16 slot_cmd; |
f4778364 KK |
576 | u16 cmd_mask; |
577 | u16 slot_status; | |
1da177e4 LT |
578 | int retval = 0; |
579 | ||
5a49f203 | 580 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 581 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 582 | if (retval) { |
7f2feec1 TI |
583 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
584 | __func__); | |
a0f018da KK |
585 | return retval; |
586 | } | |
322162a7 | 587 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 588 | if (slot_status) { |
322162a7 | 589 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 590 | if (retval) { |
7f2feec1 TI |
591 | ctrl_err(ctrl, |
592 | "%s: Cannot write to SLOTSTATUS register\n", | |
593 | __func__); | |
a0f018da KK |
594 | return retval; |
595 | } | |
596 | } | |
5651c48c | 597 | ctrl->power_fault_detected = 0; |
1da177e4 | 598 | |
f4778364 | 599 | slot_cmd = POWER_ON; |
322162a7 | 600 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 601 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 602 | if (retval) { |
18b341b7 | 603 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 604 | return retval; |
1da177e4 | 605 | } |
1518c17a KK |
606 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
607 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 608 | |
2debd928 YL |
609 | retval = pciehp_link_enable(ctrl); |
610 | if (retval) | |
611 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
612 | ||
1da177e4 LT |
613 | return retval; |
614 | } | |
615 | ||
82a9e79e | 616 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 617 | { |
48fe3915 | 618 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 619 | u16 slot_cmd; |
f4778364 | 620 | u16 cmd_mask; |
3c3a1b17 | 621 | int retval; |
f1050a35 | 622 | |
2debd928 YL |
623 | /* Disable the link at first */ |
624 | pciehp_link_disable(ctrl); | |
625 | /* wait the link is down */ | |
626 | if (ctrl->link_active_reporting) | |
627 | pcie_wait_link_not_active(ctrl); | |
628 | else | |
629 | msleep(1000); | |
630 | ||
f4778364 | 631 | slot_cmd = POWER_OFF; |
322162a7 | 632 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 633 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 634 | if (retval) { |
18b341b7 | 635 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 636 | return retval; |
1da177e4 | 637 | } |
1518c17a KK |
638 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
639 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 640 | return 0; |
1da177e4 LT |
641 | } |
642 | ||
48fe3915 | 643 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 644 | { |
48fe3915 | 645 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 646 | struct slot *slot = ctrl->slot; |
c6b069e9 | 647 | u16 detected, intr_loc; |
1da177e4 | 648 | |
c6b069e9 KK |
649 | /* |
650 | * In order to guarantee that all interrupt events are | |
651 | * serviced, we need to re-inspect Slot Status register after | |
652 | * clearing what is presumed to be the last pending interrupt. | |
653 | */ | |
654 | intr_loc = 0; | |
655 | do { | |
322162a7 | 656 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
657 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
658 | __func__); | |
1da177e4 LT |
659 | return IRQ_NONE; |
660 | } | |
661 | ||
322162a7 KK |
662 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
663 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
664 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 665 | detected &= ~intr_loc; |
c6b069e9 KK |
666 | intr_loc |= detected; |
667 | if (!intr_loc) | |
1da177e4 | 668 | return IRQ_NONE; |
81b840cd | 669 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
670 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
671 | __func__); | |
1da177e4 LT |
672 | return IRQ_NONE; |
673 | } | |
c6b069e9 | 674 | } while (detected); |
71ad556d | 675 | |
7f2feec1 | 676 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 677 | |
c6b069e9 | 678 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 679 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 680 | ctrl->cmd_busy = 0; |
2d32a9ae | 681 | smp_mb(); |
d737bdc1 | 682 | wake_up(&ctrl->queue); |
1da177e4 LT |
683 | } |
684 | ||
322162a7 | 685 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
686 | return IRQ_HANDLED; |
687 | ||
c6b069e9 | 688 | /* Check MRL Sensor Changed */ |
322162a7 | 689 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 690 | pciehp_handle_switch_change(slot); |
48fe3915 | 691 | |
c6b069e9 | 692 | /* Check Attention Button Pressed */ |
322162a7 | 693 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 694 | pciehp_handle_attention_button(slot); |
48fe3915 | 695 | |
c6b069e9 | 696 | /* Check Presence Detect Changed */ |
322162a7 | 697 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 698 | pciehp_handle_presence_change(slot); |
48fe3915 | 699 | |
c6b069e9 | 700 | /* Check Power Fault Detected */ |
99f0169c KK |
701 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
702 | ctrl->power_fault_detected = 1; | |
8720d27d | 703 | pciehp_handle_power_fault(slot); |
99f0169c | 704 | } |
1da177e4 LT |
705 | return IRQ_HANDLED; |
706 | } | |
707 | ||
c4635eb0 | 708 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 709 | { |
c27fb883 | 710 | u16 cmd, mask; |
1da177e4 | 711 | |
5651c48c KK |
712 | /* |
713 | * TBD: Power fault detected software notification support. | |
714 | * | |
715 | * Power fault detected software notification is not enabled | |
716 | * now, because it caused power fault detected interrupt storm | |
717 | * on some machines. On those machines, power fault detected | |
718 | * bit in the slot status register was set again immediately | |
719 | * when it is cleared in the interrupt service routine, and | |
720 | * next power fault detected interrupt was notified again. | |
721 | */ | |
322162a7 | 722 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 723 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 724 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 725 | if (MRL_SENS(ctrl)) |
322162a7 | 726 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 727 | if (!pciehp_poll_mode) |
322162a7 | 728 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 729 | |
322162a7 KK |
730 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
731 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
732 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
733 | |
734 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 735 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 736 | return -1; |
1da177e4 | 737 | } |
c4635eb0 KK |
738 | return 0; |
739 | } | |
740 | ||
741 | static void pcie_disable_notification(struct controller *ctrl) | |
742 | { | |
743 | u16 mask; | |
322162a7 KK |
744 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
745 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
746 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
747 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 748 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 749 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
750 | } |
751 | ||
dbc7e1e5 | 752 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
753 | { |
754 | if (pciehp_request_irq(ctrl)) | |
755 | return -1; | |
756 | if (pcie_enable_notification(ctrl)) { | |
757 | pciehp_free_irq(ctrl); | |
758 | return -1; | |
759 | } | |
dbc7e1e5 | 760 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
761 | return 0; |
762 | } | |
763 | ||
764 | static void pcie_shutdown_notification(struct controller *ctrl) | |
765 | { | |
dbc7e1e5 EB |
766 | if (ctrl->notification_enabled) { |
767 | pcie_disable_notification(ctrl); | |
768 | pciehp_free_irq(ctrl); | |
769 | ctrl->notification_enabled = 0; | |
770 | } | |
c4635eb0 KK |
771 | } |
772 | ||
c4635eb0 KK |
773 | static int pcie_init_slot(struct controller *ctrl) |
774 | { | |
775 | struct slot *slot; | |
776 | ||
777 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
778 | if (!slot) | |
779 | return -ENOMEM; | |
780 | ||
d8537548 | 781 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
782 | if (!slot->wq) |
783 | goto abort; | |
784 | ||
c4635eb0 | 785 | slot->ctrl = ctrl; |
c4635eb0 KK |
786 | mutex_init(&slot->lock); |
787 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 788 | ctrl->slot = slot; |
1da177e4 | 789 | return 0; |
c2be6f93 YW |
790 | abort: |
791 | kfree(slot); | |
792 | return -ENOMEM; | |
1da177e4 | 793 | } |
08e7a7d2 | 794 | |
c4635eb0 KK |
795 | static void pcie_cleanup_slot(struct controller *ctrl) |
796 | { | |
8720d27d | 797 | struct slot *slot = ctrl->slot; |
c4635eb0 | 798 | cancel_delayed_work(&slot->work); |
c2be6f93 | 799 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
800 | kfree(slot); |
801 | } | |
802 | ||
2aeeef11 | 803 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 804 | { |
2aeeef11 KK |
805 | int i; |
806 | u16 reg16; | |
385e2491 | 807 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 808 | |
2aeeef11 KK |
809 | if (!pciehp_debug) |
810 | return; | |
08e7a7d2 | 811 | |
7f2feec1 TI |
812 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
813 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
814 | pci_name(pdev), pdev->irq); | |
815 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
816 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
817 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
818 | pdev->subsystem_device); | |
819 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
820 | pdev->subsystem_vendor); | |
1518c17a KK |
821 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
822 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
823 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
824 | if (!pci_resource_len(pdev, i)) | |
825 | continue; | |
e1944c6b BH |
826 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
827 | i, &pdev->resource[i]); | |
08e7a7d2 | 828 | } |
7f2feec1 | 829 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 830 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
831 | ctrl_info(ctrl, " Attention Button : %3s\n", |
832 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
833 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
834 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
835 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
836 | MRL_SENS(ctrl) ? "yes" : "no"); | |
837 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
838 | ATTN_LED(ctrl) ? "yes" : "no"); | |
839 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
840 | PWR_LED(ctrl) ? "yes" : "no"); | |
841 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
842 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
843 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
844 | EMI(ctrl) ? "yes" : "no"); | |
845 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
846 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 847 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 848 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 849 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 850 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 851 | } |
08e7a7d2 | 852 | |
c4635eb0 | 853 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 854 | { |
c4635eb0 | 855 | struct controller *ctrl; |
f18e9625 | 856 | u32 slot_cap, link_cap; |
2aeeef11 | 857 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 858 | |
c4635eb0 KK |
859 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
860 | if (!ctrl) { | |
18b341b7 | 861 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
862 | goto abort; |
863 | } | |
f7a10e32 | 864 | ctrl->pcie = dev; |
322162a7 | 865 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 866 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 867 | goto abort_ctrl; |
08e7a7d2 | 868 | } |
08e7a7d2 | 869 | |
2aeeef11 | 870 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 871 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 872 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 873 | dbg_ctrl(ctrl); |
5808639b KK |
874 | /* |
875 | * Controller doesn't notify of command completion if the "No | |
876 | * Command Completed Support" bit is set in Slot Capability | |
877 | * register or the controller supports none of power | |
878 | * controller, attention led, power led and EMI. | |
879 | */ | |
880 | if (NO_CMD_CMPL(ctrl) || | |
881 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
882 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 883 | |
f18e9625 | 884 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 885 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
886 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
887 | goto abort_ctrl; | |
888 | } | |
322162a7 | 889 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
890 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
891 | ctrl->link_active_reporting = 1; | |
892 | } | |
893 | ||
c4635eb0 | 894 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 895 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 896 | goto abort_ctrl; |
08e7a7d2 | 897 | |
c4635eb0 KK |
898 | /* Disable sotfware notification */ |
899 | pcie_disable_notification(ctrl); | |
ecdde939 | 900 | |
7f2feec1 TI |
901 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
902 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
903 | pdev->subsystem_device); | |
c4635eb0 KK |
904 | |
905 | if (pcie_init_slot(ctrl)) | |
906 | goto abort_ctrl; | |
2aeeef11 | 907 | |
c4635eb0 KK |
908 | return ctrl; |
909 | ||
c4635eb0 KK |
910 | abort_ctrl: |
911 | kfree(ctrl); | |
08e7a7d2 | 912 | abort: |
c4635eb0 KK |
913 | return NULL; |
914 | } | |
915 | ||
82a9e79e | 916 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
917 | { |
918 | pcie_shutdown_notification(ctrl); | |
919 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 920 | kfree(ctrl); |
08e7a7d2 | 921 | } |