Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
1da177e4 LT |
49 | /* Power Control Command */ |
50 | #define POWER_ON 0 | |
322162a7 | 51 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 52 | |
48fe3915 KK |
53 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
54 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
55 | |
56 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 57 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 58 | { |
48fe3915 | 59 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 60 | |
1da177e4 | 61 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 62 | pcie_isr(0, ctrl); |
1da177e4 | 63 | |
48fe3915 | 64 | init_timer(&ctrl->poll_timer); |
1da177e4 | 65 | if (!pciehp_poll_time) |
40730d10 | 66 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 67 | |
48fe3915 | 68 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
69 | } |
70 | ||
71 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 72 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 73 | { |
48fe3915 KK |
74 | /* Clamp to sane value */ |
75 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 76 | sec = 2; |
48fe3915 KK |
77 | |
78 | ctrl->poll_timer.function = &int_poll_timeout; | |
79 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
80 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
81 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
82 | } |
83 | ||
2aeeef11 KK |
84 | static inline int pciehp_request_irq(struct controller *ctrl) |
85 | { | |
f7a10e32 | 86 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
87 | |
88 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
89 | if (pciehp_poll_mode) { | |
90 | init_timer(&ctrl->poll_timer); | |
91 | start_int_poll_timer(ctrl, 10); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | /* Installs the interrupt handler */ | |
96 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
97 | if (retval) | |
7f2feec1 TI |
98 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
99 | irq); | |
2aeeef11 KK |
100 | return retval; |
101 | } | |
102 | ||
103 | static inline void pciehp_free_irq(struct controller *ctrl) | |
104 | { | |
105 | if (pciehp_poll_mode) | |
106 | del_timer_sync(&ctrl->poll_timer); | |
107 | else | |
f7a10e32 | 108 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
109 | } |
110 | ||
563f1190 | 111 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a | 112 | { |
cd84d340 | 113 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 114 | u16 slot_status; |
1a84b99c | 115 | int timeout = 1000; |
6592e02a | 116 | |
1a84b99c BH |
117 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
118 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
119 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
120 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 121 | return 1; |
820943b6 | 122 | } |
a5827f40 | 123 | while (timeout > 0) { |
66618bad KK |
124 | msleep(10); |
125 | timeout -= 10; | |
1a84b99c BH |
126 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
127 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
128 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
129 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 130 | return 1; |
820943b6 | 131 | } |
6592e02a KK |
132 | } |
133 | return 0; /* timeout */ | |
6592e02a KK |
134 | } |
135 | ||
563f1190 | 136 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 137 | { |
262303fe KK |
138 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
139 | unsigned long timeout = msecs_to_jiffies(msecs); | |
140 | int rc; | |
141 | ||
6592e02a KK |
142 | if (poll) |
143 | rc = pcie_poll_cmd(ctrl); | |
144 | else | |
d737bdc1 | 145 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 146 | if (!rc) |
7f2feec1 | 147 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
148 | } |
149 | ||
f4778364 KK |
150 | /** |
151 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 152 | * @ctrl: controller to which the command is issued |
f4778364 KK |
153 | * @cmd: command value written to slot control register |
154 | * @mask: bitmask of slot control register to be modified | |
155 | */ | |
c27fb883 | 156 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 157 | { |
cd84d340 | 158 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 159 | u16 slot_status; |
f4778364 | 160 | u16 slot_ctrl; |
1da177e4 | 161 | |
44ef4cef KK |
162 | mutex_lock(&ctrl->ctrl_lock); |
163 | ||
1a84b99c | 164 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 165 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
166 | if (!ctrl->no_cmd_complete) { |
167 | /* | |
168 | * After 1 sec and CMD_COMPLETED still not set, just | |
169 | * proceed forward to issue the next command according | |
170 | * to spec. Just print out the error message. | |
171 | */ | |
18b341b7 | 172 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
173 | } else if (!NO_CMD_CMPL(ctrl)) { |
174 | /* | |
f7625980 | 175 | * This controller seems to notify of command completed |
5808639b KK |
176 | * event even though it supports none of power |
177 | * controller, attention led, power led and EMI. | |
178 | */ | |
18b341b7 TI |
179 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
180 | "wait for command completed event.\n"); | |
5808639b KK |
181 | ctrl->no_cmd_complete = 0; |
182 | } else { | |
18b341b7 TI |
183 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
184 | "the controller is broken.\n"); | |
5808639b | 185 | } |
1da177e4 LT |
186 | } |
187 | ||
1a84b99c | 188 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
f4778364 | 189 | slot_ctrl &= ~mask; |
b7aa1f16 | 190 | slot_ctrl |= (cmd & mask); |
f4778364 | 191 | ctrl->cmd_busy = 1; |
2d32a9ae | 192 | smp_mb(); |
1a84b99c | 193 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 194 | |
44ef4cef KK |
195 | /* |
196 | * Wait for command completion. | |
197 | */ | |
1a84b99c | 198 | if (!ctrl->no_cmd_complete) { |
6592e02a KK |
199 | int poll = 0; |
200 | /* | |
201 | * if hotplug interrupt is not enabled or command | |
202 | * completed interrupt is not enabled, we need to poll | |
203 | * command completed event. | |
204 | */ | |
322162a7 KK |
205 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
206 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 207 | poll = 1; |
d737bdc1 | 208 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 209 | } |
44ef4cef | 210 | mutex_unlock(&ctrl->ctrl_lock); |
1a84b99c | 211 | return 0; |
1da177e4 LT |
212 | } |
213 | ||
4e2ce405 | 214 | static bool check_link_active(struct controller *ctrl) |
f18e9625 | 215 | { |
cd84d340 | 216 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 217 | u16 lnk_status; |
1a84b99c | 218 | bool ret; |
f18e9625 | 219 | |
1a84b99c | 220 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
221 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
222 | ||
223 | if (ret) | |
224 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
225 | ||
226 | return ret; | |
f18e9625 KK |
227 | } |
228 | ||
bffe4f72 | 229 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
230 | { |
231 | int timeout = 1000; | |
232 | ||
bffe4f72 | 233 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
234 | return; |
235 | while (timeout > 0) { | |
236 | msleep(10); | |
237 | timeout -= 10; | |
bffe4f72 | 238 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
239 | return; |
240 | } | |
bffe4f72 YL |
241 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
242 | active ? "set" : "cleared"); | |
243 | } | |
244 | ||
245 | static void pcie_wait_link_active(struct controller *ctrl) | |
246 | { | |
247 | __pcie_wait_link_active(ctrl, true); | |
248 | } | |
249 | ||
250 | static void pcie_wait_link_not_active(struct controller *ctrl) | |
251 | { | |
252 | __pcie_wait_link_active(ctrl, false); | |
f18e9625 KK |
253 | } |
254 | ||
2f5d8e4f YL |
255 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
256 | { | |
257 | u32 l; | |
258 | int count = 0; | |
259 | int delay = 1000, step = 20; | |
260 | bool found = false; | |
261 | ||
262 | do { | |
263 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
264 | count++; | |
265 | ||
266 | if (found) | |
267 | break; | |
268 | ||
269 | msleep(step); | |
270 | delay -= step; | |
271 | } while (delay > 0); | |
272 | ||
273 | if (count > 1 && pciehp_debug) | |
274 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
275 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
276 | PCI_FUNC(devfn), count, step, l); | |
277 | ||
278 | return found; | |
279 | } | |
280 | ||
82a9e79e | 281 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 282 | { |
cd84d340 | 283 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 284 | bool found; |
1da177e4 | 285 | u16 lnk_status; |
1da177e4 | 286 | |
f18e9625 KK |
287 | /* |
288 | * Data Link Layer Link Active Reporting must be capable for | |
289 | * hot-plug capable downstream port. But old controller might | |
290 | * not implement it. In this case, we wait for 1000 ms. | |
291 | */ | |
0cab0841 | 292 | if (ctrl->link_active_reporting) |
f18e9625 | 293 | pcie_wait_link_active(ctrl); |
0cab0841 | 294 | else |
f18e9625 KK |
295 | msleep(1000); |
296 | ||
2f5d8e4f YL |
297 | /* wait 100ms before read pci conf, and try in 1s */ |
298 | msleep(100); | |
299 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
300 | PCI_DEVFN(0, 0)); | |
0027cb3e | 301 | |
1a84b99c | 302 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 303 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
304 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
305 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 306 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1a84b99c | 307 | return -1; |
1da177e4 LT |
308 | } |
309 | ||
fdbd3ce9 YL |
310 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
311 | ||
1a84b99c BH |
312 | if (!found) |
313 | return -1; | |
2f5d8e4f | 314 | |
1a84b99c | 315 | return 0; |
1da177e4 LT |
316 | } |
317 | ||
7f822999 YL |
318 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
319 | { | |
cd84d340 | 320 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 321 | u16 lnk_ctrl; |
7f822999 | 322 | |
1a84b99c | 323 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
324 | |
325 | if (enable) | |
326 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
327 | else | |
328 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
329 | ||
1a84b99c | 330 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 331 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 332 | return 0; |
7f822999 YL |
333 | } |
334 | ||
335 | static int pciehp_link_enable(struct controller *ctrl) | |
336 | { | |
337 | return __pciehp_link_set(ctrl, true); | |
338 | } | |
339 | ||
340 | static int pciehp_link_disable(struct controller *ctrl) | |
341 | { | |
342 | return __pciehp_link_set(ctrl, false); | |
343 | } | |
344 | ||
82a9e79e | 345 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 346 | { |
48fe3915 | 347 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 348 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 LT |
349 | u16 slot_ctrl; |
350 | u8 atten_led_state; | |
1da177e4 | 351 | |
1a84b99c | 352 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
353 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
354 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 355 | |
322162a7 | 356 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
357 | |
358 | switch (atten_led_state) { | |
359 | case 0: | |
360 | *status = 0xFF; /* Reserved */ | |
361 | break; | |
362 | case 1: | |
363 | *status = 1; /* On */ | |
364 | break; | |
365 | case 2: | |
366 | *status = 2; /* Blink */ | |
367 | break; | |
368 | case 3: | |
369 | *status = 0; /* Off */ | |
370 | break; | |
371 | default: | |
372 | *status = 0xFF; | |
373 | break; | |
374 | } | |
375 | ||
1da177e4 LT |
376 | return 0; |
377 | } | |
378 | ||
82a9e79e | 379 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 380 | { |
48fe3915 | 381 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 382 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 LT |
383 | u16 slot_ctrl; |
384 | u8 pwr_state; | |
1da177e4 | 385 | |
1a84b99c | 386 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
387 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
388 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 389 | |
322162a7 | 390 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
391 | |
392 | switch (pwr_state) { | |
393 | case 0: | |
394 | *status = 1; | |
395 | break; | |
396 | case 1: | |
71ad556d | 397 | *status = 0; |
1da177e4 LT |
398 | break; |
399 | default: | |
400 | *status = 0xFF; | |
401 | break; | |
402 | } | |
403 | ||
1a84b99c | 404 | return 0; |
1da177e4 LT |
405 | } |
406 | ||
82a9e79e | 407 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 408 | { |
1a84b99c | 409 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 410 | u16 slot_status; |
1da177e4 | 411 | |
1a84b99c | 412 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 413 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
414 | return 0; |
415 | } | |
416 | ||
82a9e79e | 417 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 418 | { |
1a84b99c | 419 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 420 | u16 slot_status; |
1da177e4 | 421 | |
1a84b99c | 422 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 423 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
424 | return 0; |
425 | } | |
426 | ||
82a9e79e | 427 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 428 | { |
1a84b99c | 429 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 430 | u16 slot_status; |
1da177e4 | 431 | |
1a84b99c | 432 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 433 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
434 | } |
435 | ||
82a9e79e | 436 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 437 | { |
48fe3915 | 438 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
439 | u16 slot_cmd; |
440 | u16 cmd_mask; | |
1da177e4 | 441 | |
322162a7 | 442 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 443 | switch (value) { |
445f7985 KK |
444 | case 0 : /* turn off */ |
445 | slot_cmd = 0x00C0; | |
446 | break; | |
447 | case 1: /* turn on */ | |
448 | slot_cmd = 0x0040; | |
449 | break; | |
450 | case 2: /* turn blink */ | |
451 | slot_cmd = 0x0080; | |
452 | break; | |
453 | default: | |
454 | return -EINVAL; | |
1da177e4 | 455 | } |
1518c17a KK |
456 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
457 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 458 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
459 | } |
460 | ||
82a9e79e | 461 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 462 | { |
48fe3915 | 463 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 464 | u16 slot_cmd; |
f4778364 | 465 | u16 cmd_mask; |
71ad556d | 466 | |
f4778364 | 467 | slot_cmd = 0x0100; |
322162a7 | 468 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 469 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
470 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
471 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
472 | } |
473 | ||
82a9e79e | 474 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 475 | { |
48fe3915 | 476 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 477 | u16 slot_cmd; |
f4778364 | 478 | u16 cmd_mask; |
1da177e4 | 479 | |
f4778364 | 480 | slot_cmd = 0x0300; |
322162a7 | 481 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 482 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
483 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
484 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
485 | } |
486 | ||
82a9e79e | 487 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 488 | { |
48fe3915 | 489 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 490 | u16 slot_cmd; |
f4778364 | 491 | u16 cmd_mask; |
71ad556d | 492 | |
f4778364 | 493 | slot_cmd = 0x0200; |
322162a7 | 494 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 495 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
496 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
497 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
498 | } |
499 | ||
82a9e79e | 500 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 501 | { |
48fe3915 | 502 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 503 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 504 | u16 slot_cmd; |
f4778364 KK |
505 | u16 cmd_mask; |
506 | u16 slot_status; | |
1a84b99c | 507 | int retval; |
1da177e4 | 508 | |
5a49f203 | 509 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 510 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 511 | slot_status &= PCI_EXP_SLTSTA_PFD; |
1a84b99c BH |
512 | if (slot_status) |
513 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, slot_status); | |
5651c48c | 514 | ctrl->power_fault_detected = 0; |
1da177e4 | 515 | |
f4778364 | 516 | slot_cmd = POWER_ON; |
322162a7 | 517 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 518 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 519 | if (retval) { |
18b341b7 | 520 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 521 | return retval; |
1da177e4 | 522 | } |
1518c17a KK |
523 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
524 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 525 | |
2debd928 YL |
526 | retval = pciehp_link_enable(ctrl); |
527 | if (retval) | |
528 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
529 | ||
1da177e4 LT |
530 | return retval; |
531 | } | |
532 | ||
82a9e79e | 533 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 534 | { |
48fe3915 | 535 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 536 | u16 slot_cmd; |
f4778364 | 537 | u16 cmd_mask; |
3c3a1b17 | 538 | int retval; |
f1050a35 | 539 | |
2debd928 YL |
540 | /* Disable the link at first */ |
541 | pciehp_link_disable(ctrl); | |
542 | /* wait the link is down */ | |
543 | if (ctrl->link_active_reporting) | |
544 | pcie_wait_link_not_active(ctrl); | |
545 | else | |
546 | msleep(1000); | |
547 | ||
f4778364 | 548 | slot_cmd = POWER_OFF; |
322162a7 | 549 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 550 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 551 | if (retval) { |
18b341b7 | 552 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 553 | return retval; |
1da177e4 | 554 | } |
1518c17a KK |
555 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
556 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 557 | return 0; |
1da177e4 LT |
558 | } |
559 | ||
48fe3915 | 560 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 561 | { |
48fe3915 | 562 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 563 | struct pci_dev *pdev = ctrl_dev(ctrl); |
8720d27d | 564 | struct slot *slot = ctrl->slot; |
c6b069e9 | 565 | u16 detected, intr_loc; |
1da177e4 | 566 | |
c6b069e9 KK |
567 | /* |
568 | * In order to guarantee that all interrupt events are | |
569 | * serviced, we need to re-inspect Slot Status register after | |
570 | * clearing what is presumed to be the last pending interrupt. | |
571 | */ | |
572 | intr_loc = 0; | |
573 | do { | |
1a84b99c | 574 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
1da177e4 | 575 | |
322162a7 KK |
576 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
577 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
578 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 579 | detected &= ~intr_loc; |
c6b069e9 KK |
580 | intr_loc |= detected; |
581 | if (!intr_loc) | |
1da177e4 | 582 | return IRQ_NONE; |
1a84b99c BH |
583 | if (detected) |
584 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
585 | intr_loc); | |
c6b069e9 | 586 | } while (detected); |
71ad556d | 587 | |
7f2feec1 | 588 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 589 | |
c6b069e9 | 590 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 591 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 592 | ctrl->cmd_busy = 0; |
2d32a9ae | 593 | smp_mb(); |
d737bdc1 | 594 | wake_up(&ctrl->queue); |
1da177e4 LT |
595 | } |
596 | ||
322162a7 | 597 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
598 | return IRQ_HANDLED; |
599 | ||
c6b069e9 | 600 | /* Check MRL Sensor Changed */ |
322162a7 | 601 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 602 | pciehp_handle_switch_change(slot); |
48fe3915 | 603 | |
c6b069e9 | 604 | /* Check Attention Button Pressed */ |
322162a7 | 605 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 606 | pciehp_handle_attention_button(slot); |
48fe3915 | 607 | |
c6b069e9 | 608 | /* Check Presence Detect Changed */ |
322162a7 | 609 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 610 | pciehp_handle_presence_change(slot); |
48fe3915 | 611 | |
c6b069e9 | 612 | /* Check Power Fault Detected */ |
99f0169c KK |
613 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
614 | ctrl->power_fault_detected = 1; | |
8720d27d | 615 | pciehp_handle_power_fault(slot); |
99f0169c | 616 | } |
1da177e4 LT |
617 | return IRQ_HANDLED; |
618 | } | |
619 | ||
c4635eb0 | 620 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 621 | { |
c27fb883 | 622 | u16 cmd, mask; |
1da177e4 | 623 | |
5651c48c KK |
624 | /* |
625 | * TBD: Power fault detected software notification support. | |
626 | * | |
627 | * Power fault detected software notification is not enabled | |
628 | * now, because it caused power fault detected interrupt storm | |
629 | * on some machines. On those machines, power fault detected | |
630 | * bit in the slot status register was set again immediately | |
631 | * when it is cleared in the interrupt service routine, and | |
632 | * next power fault detected interrupt was notified again. | |
633 | */ | |
322162a7 | 634 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 635 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 636 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 637 | if (MRL_SENS(ctrl)) |
322162a7 | 638 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 639 | if (!pciehp_poll_mode) |
322162a7 | 640 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 641 | |
322162a7 KK |
642 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
643 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
644 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
645 | |
646 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 647 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 648 | return -1; |
1da177e4 | 649 | } |
c4635eb0 KK |
650 | return 0; |
651 | } | |
652 | ||
653 | static void pcie_disable_notification(struct controller *ctrl) | |
654 | { | |
655 | u16 mask; | |
322162a7 KK |
656 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
657 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
658 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
659 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 660 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 661 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
662 | } |
663 | ||
2e35afae AW |
664 | /* |
665 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
666 | * bus reset of the bridge, but if the slot supports surprise removal we need | |
667 | * to disable presence detection around the bus reset and clear any spurious | |
668 | * events after. | |
669 | */ | |
670 | int pciehp_reset_slot(struct slot *slot, int probe) | |
671 | { | |
672 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 673 | struct pci_dev *pdev = ctrl_dev(ctrl); |
2e35afae AW |
674 | |
675 | if (probe) | |
676 | return 0; | |
677 | ||
678 | if (HP_SUPR_RM(ctrl)) { | |
679 | pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); | |
680 | if (pciehp_poll_mode) | |
681 | del_timer_sync(&ctrl->poll_timer); | |
682 | } | |
683 | ||
684 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
685 | ||
686 | if (HP_SUPR_RM(ctrl)) { | |
cd84d340 BH |
687 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
688 | PCI_EXP_SLTSTA_PDC); | |
2e35afae AW |
689 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
690 | if (pciehp_poll_mode) | |
691 | int_poll_timeout(ctrl->poll_timer.data); | |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
dbc7e1e5 | 697 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
698 | { |
699 | if (pciehp_request_irq(ctrl)) | |
700 | return -1; | |
701 | if (pcie_enable_notification(ctrl)) { | |
702 | pciehp_free_irq(ctrl); | |
703 | return -1; | |
704 | } | |
dbc7e1e5 | 705 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
706 | return 0; |
707 | } | |
708 | ||
709 | static void pcie_shutdown_notification(struct controller *ctrl) | |
710 | { | |
dbc7e1e5 EB |
711 | if (ctrl->notification_enabled) { |
712 | pcie_disable_notification(ctrl); | |
713 | pciehp_free_irq(ctrl); | |
714 | ctrl->notification_enabled = 0; | |
715 | } | |
c4635eb0 KK |
716 | } |
717 | ||
c4635eb0 KK |
718 | static int pcie_init_slot(struct controller *ctrl) |
719 | { | |
720 | struct slot *slot; | |
721 | ||
722 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
723 | if (!slot) | |
724 | return -ENOMEM; | |
725 | ||
d8537548 | 726 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
727 | if (!slot->wq) |
728 | goto abort; | |
729 | ||
c4635eb0 | 730 | slot->ctrl = ctrl; |
c4635eb0 KK |
731 | mutex_init(&slot->lock); |
732 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 733 | ctrl->slot = slot; |
1da177e4 | 734 | return 0; |
c2be6f93 YW |
735 | abort: |
736 | kfree(slot); | |
737 | return -ENOMEM; | |
1da177e4 | 738 | } |
08e7a7d2 | 739 | |
c4635eb0 KK |
740 | static void pcie_cleanup_slot(struct controller *ctrl) |
741 | { | |
8720d27d | 742 | struct slot *slot = ctrl->slot; |
c4635eb0 | 743 | cancel_delayed_work(&slot->work); |
c2be6f93 | 744 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
745 | kfree(slot); |
746 | } | |
747 | ||
2aeeef11 | 748 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 749 | { |
2aeeef11 KK |
750 | int i; |
751 | u16 reg16; | |
385e2491 | 752 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 753 | |
2aeeef11 KK |
754 | if (!pciehp_debug) |
755 | return; | |
08e7a7d2 | 756 | |
7f2feec1 TI |
757 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
758 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
759 | pci_name(pdev), pdev->irq); | |
760 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
761 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
762 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
763 | pdev->subsystem_device); | |
764 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
765 | pdev->subsystem_vendor); | |
1518c17a KK |
766 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
767 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
768 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
769 | if (!pci_resource_len(pdev, i)) | |
770 | continue; | |
e1944c6b BH |
771 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
772 | i, &pdev->resource[i]); | |
08e7a7d2 | 773 | } |
7f2feec1 | 774 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 775 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
776 | ctrl_info(ctrl, " Attention Button : %3s\n", |
777 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
778 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
779 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
780 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
781 | MRL_SENS(ctrl) ? "yes" : "no"); | |
782 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
783 | ATTN_LED(ctrl) ? "yes" : "no"); | |
784 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
785 | PWR_LED(ctrl) ? "yes" : "no"); | |
786 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
787 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
788 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
789 | EMI(ctrl) ? "yes" : "no"); | |
790 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
791 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
cd84d340 | 792 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 793 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 794 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 795 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 796 | } |
08e7a7d2 | 797 | |
c4635eb0 | 798 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 799 | { |
c4635eb0 | 800 | struct controller *ctrl; |
f18e9625 | 801 | u32 slot_cap, link_cap; |
2aeeef11 | 802 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 803 | |
c4635eb0 KK |
804 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
805 | if (!ctrl) { | |
18b341b7 | 806 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
807 | goto abort; |
808 | } | |
f7a10e32 | 809 | ctrl->pcie = dev; |
1a84b99c | 810 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
2aeeef11 | 811 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 812 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 813 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 814 | dbg_ctrl(ctrl); |
5808639b KK |
815 | /* |
816 | * Controller doesn't notify of command completion if the "No | |
817 | * Command Completed Support" bit is set in Slot Capability | |
818 | * register or the controller supports none of power | |
819 | * controller, attention led, power led and EMI. | |
820 | */ | |
821 | if (NO_CMD_CMPL(ctrl) || | |
822 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
823 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 824 | |
f18e9625 | 825 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
1a84b99c | 826 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); |
322162a7 | 827 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
828 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
829 | ctrl->link_active_reporting = 1; | |
830 | } | |
831 | ||
c4635eb0 | 832 | /* Clear all remaining event bits in Slot Status register */ |
1a84b99c | 833 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 0x1f); |
08e7a7d2 | 834 | |
f7625980 | 835 | /* Disable software notification */ |
c4635eb0 | 836 | pcie_disable_notification(ctrl); |
ecdde939 | 837 | |
7f2feec1 TI |
838 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
839 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
840 | pdev->subsystem_device); | |
c4635eb0 KK |
841 | |
842 | if (pcie_init_slot(ctrl)) | |
843 | goto abort_ctrl; | |
2aeeef11 | 844 | |
c4635eb0 KK |
845 | return ctrl; |
846 | ||
c4635eb0 KK |
847 | abort_ctrl: |
848 | kfree(ctrl); | |
08e7a7d2 | 849 | abort: |
c4635eb0 KK |
850 | return NULL; |
851 | } | |
852 | ||
82a9e79e | 853 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
854 | { |
855 | pcie_shutdown_notification(ctrl); | |
856 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 857 | kfree(ctrl); |
08e7a7d2 | 858 | } |