Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
5d386e1a KK |
44 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
45 | ||
a0f018da KK |
46 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
47 | { | |
385e2491 | 48 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 49 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
50 | } |
51 | ||
52 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
53 | { | |
385e2491 | 54 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 55 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
56 | } |
57 | ||
58 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
59 | { | |
385e2491 | 60 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 61 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
62 | } |
63 | ||
64 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
65 | { | |
385e2491 | 66 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 67 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 68 | } |
1da177e4 | 69 | |
1da177e4 LT |
70 | /* Power Control Command */ |
71 | #define POWER_ON 0 | |
322162a7 | 72 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 73 | |
48fe3915 KK |
74 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
75 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
76 | |
77 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 78 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 79 | { |
48fe3915 | 80 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 81 | |
1da177e4 | 82 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 83 | pcie_isr(0, ctrl); |
1da177e4 | 84 | |
48fe3915 | 85 | init_timer(&ctrl->poll_timer); |
1da177e4 | 86 | if (!pciehp_poll_time) |
40730d10 | 87 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 88 | |
48fe3915 | 89 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
90 | } |
91 | ||
92 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 93 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 94 | { |
48fe3915 KK |
95 | /* Clamp to sane value */ |
96 | if ((sec <= 0) || (sec > 60)) | |
97 | sec = 2; | |
98 | ||
99 | ctrl->poll_timer.function = &int_poll_timeout; | |
100 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
101 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
102 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
103 | } |
104 | ||
2aeeef11 KK |
105 | static inline int pciehp_request_irq(struct controller *ctrl) |
106 | { | |
f7a10e32 | 107 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
108 | |
109 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
110 | if (pciehp_poll_mode) { | |
111 | init_timer(&ctrl->poll_timer); | |
112 | start_int_poll_timer(ctrl, 10); | |
113 | return 0; | |
114 | } | |
115 | ||
116 | /* Installs the interrupt handler */ | |
117 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
118 | if (retval) | |
7f2feec1 TI |
119 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
120 | irq); | |
2aeeef11 KK |
121 | return retval; |
122 | } | |
123 | ||
124 | static inline void pciehp_free_irq(struct controller *ctrl) | |
125 | { | |
126 | if (pciehp_poll_mode) | |
127 | del_timer_sync(&ctrl->poll_timer); | |
128 | else | |
f7a10e32 | 129 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
130 | } |
131 | ||
563f1190 | 132 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
133 | { |
134 | u16 slot_status; | |
322162a7 | 135 | int err, timeout = 1000; |
6592e02a | 136 | |
322162a7 KK |
137 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
138 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
139 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
140 | return 1; | |
820943b6 | 141 | } |
a5827f40 | 142 | while (timeout > 0) { |
66618bad KK |
143 | msleep(10); |
144 | timeout -= 10; | |
322162a7 KK |
145 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
146 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
147 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
148 | return 1; | |
820943b6 | 149 | } |
6592e02a KK |
150 | } |
151 | return 0; /* timeout */ | |
6592e02a KK |
152 | } |
153 | ||
563f1190 | 154 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 155 | { |
262303fe KK |
156 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
157 | unsigned long timeout = msecs_to_jiffies(msecs); | |
158 | int rc; | |
159 | ||
6592e02a KK |
160 | if (poll) |
161 | rc = pcie_poll_cmd(ctrl); | |
162 | else | |
d737bdc1 | 163 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 164 | if (!rc) |
7f2feec1 | 165 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
166 | } |
167 | ||
f4778364 KK |
168 | /** |
169 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 170 | * @ctrl: controller to which the command is issued |
f4778364 KK |
171 | * @cmd: command value written to slot control register |
172 | * @mask: bitmask of slot control register to be modified | |
173 | */ | |
c27fb883 | 174 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 175 | { |
1da177e4 LT |
176 | int retval = 0; |
177 | u16 slot_status; | |
f4778364 | 178 | u16 slot_ctrl; |
1da177e4 | 179 | |
44ef4cef KK |
180 | mutex_lock(&ctrl->ctrl_lock); |
181 | ||
322162a7 | 182 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 183 | if (retval) { |
7f2feec1 TI |
184 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
185 | __func__); | |
44ef4cef | 186 | goto out; |
a0f018da KK |
187 | } |
188 | ||
322162a7 | 189 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
190 | if (!ctrl->no_cmd_complete) { |
191 | /* | |
192 | * After 1 sec and CMD_COMPLETED still not set, just | |
193 | * proceed forward to issue the next command according | |
194 | * to spec. Just print out the error message. | |
195 | */ | |
18b341b7 | 196 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
197 | } else if (!NO_CMD_CMPL(ctrl)) { |
198 | /* | |
199 | * This controller semms to notify of command completed | |
200 | * event even though it supports none of power | |
201 | * controller, attention led, power led and EMI. | |
202 | */ | |
18b341b7 TI |
203 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
204 | "wait for command completed event.\n"); | |
5808639b KK |
205 | ctrl->no_cmd_complete = 0; |
206 | } else { | |
18b341b7 TI |
207 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
208 | "the controller is broken.\n"); | |
5808639b | 209 | } |
1da177e4 LT |
210 | } |
211 | ||
322162a7 | 212 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 213 | if (retval) { |
7f2feec1 | 214 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 215 | goto out; |
1da177e4 | 216 | } |
1da177e4 | 217 | |
f4778364 | 218 | slot_ctrl &= ~mask; |
b7aa1f16 | 219 | slot_ctrl |= (cmd & mask); |
f4778364 | 220 | ctrl->cmd_busy = 1; |
2d32a9ae | 221 | smp_mb(); |
322162a7 | 222 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 223 | if (retval) |
18b341b7 | 224 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 225 | |
44ef4cef KK |
226 | /* |
227 | * Wait for command completion. | |
228 | */ | |
6592e02a KK |
229 | if (!retval && !ctrl->no_cmd_complete) { |
230 | int poll = 0; | |
231 | /* | |
232 | * if hotplug interrupt is not enabled or command | |
233 | * completed interrupt is not enabled, we need to poll | |
234 | * command completed event. | |
235 | */ | |
322162a7 KK |
236 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
237 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 238 | poll = 1; |
d737bdc1 | 239 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 240 | } |
44ef4cef KK |
241 | out: |
242 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
243 | return retval; |
244 | } | |
245 | ||
f18e9625 KK |
246 | static inline int check_link_active(struct controller *ctrl) |
247 | { | |
248 | u16 link_status; | |
249 | ||
322162a7 | 250 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 251 | return 0; |
322162a7 | 252 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
253 | } |
254 | ||
255 | static void pcie_wait_link_active(struct controller *ctrl) | |
256 | { | |
257 | int timeout = 1000; | |
258 | ||
259 | if (check_link_active(ctrl)) | |
260 | return; | |
261 | while (timeout > 0) { | |
262 | msleep(10); | |
263 | timeout -= 10; | |
264 | if (check_link_active(ctrl)) | |
265 | return; | |
266 | } | |
267 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
268 | } | |
269 | ||
82a9e79e | 270 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 271 | { |
1da177e4 LT |
272 | u16 lnk_status; |
273 | int retval = 0; | |
274 | ||
f18e9625 KK |
275 | /* |
276 | * Data Link Layer Link Active Reporting must be capable for | |
277 | * hot-plug capable downstream port. But old controller might | |
278 | * not implement it. In this case, we wait for 1000 ms. | |
279 | */ | |
280 | if (ctrl->link_active_reporting){ | |
281 | /* Wait for Data Link Layer Link Active bit to be set */ | |
282 | pcie_wait_link_active(ctrl); | |
283 | /* | |
284 | * We must wait for 100 ms after the Data Link Layer | |
285 | * Link Active bit reads 1b before initiating a | |
286 | * configuration access to the hot added device. | |
287 | */ | |
288 | msleep(100); | |
289 | } else | |
290 | msleep(1000); | |
291 | ||
322162a7 | 292 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 293 | if (retval) { |
18b341b7 | 294 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
295 | return retval; |
296 | } | |
297 | ||
7f2feec1 | 298 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
299 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
300 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 301 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
302 | retval = -1; |
303 | return retval; | |
304 | } | |
305 | ||
1da177e4 LT |
306 | return retval; |
307 | } | |
308 | ||
82a9e79e | 309 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 310 | { |
48fe3915 | 311 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
312 | u16 slot_ctrl; |
313 | u8 atten_led_state; | |
314 | int retval = 0; | |
1da177e4 | 315 | |
322162a7 | 316 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 317 | if (retval) { |
7f2feec1 | 318 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
319 | return retval; |
320 | } | |
321 | ||
1518c17a KK |
322 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
323 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 324 | |
322162a7 | 325 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
326 | |
327 | switch (atten_led_state) { | |
328 | case 0: | |
329 | *status = 0xFF; /* Reserved */ | |
330 | break; | |
331 | case 1: | |
332 | *status = 1; /* On */ | |
333 | break; | |
334 | case 2: | |
335 | *status = 2; /* Blink */ | |
336 | break; | |
337 | case 3: | |
338 | *status = 0; /* Off */ | |
339 | break; | |
340 | default: | |
341 | *status = 0xFF; | |
342 | break; | |
343 | } | |
344 | ||
1da177e4 LT |
345 | return 0; |
346 | } | |
347 | ||
82a9e79e | 348 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 349 | { |
48fe3915 | 350 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
351 | u16 slot_ctrl; |
352 | u8 pwr_state; | |
353 | int retval = 0; | |
1da177e4 | 354 | |
322162a7 | 355 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 356 | if (retval) { |
7f2feec1 | 357 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
358 | return retval; |
359 | } | |
1518c17a KK |
360 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
361 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 362 | |
322162a7 | 363 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
364 | |
365 | switch (pwr_state) { | |
366 | case 0: | |
367 | *status = 1; | |
368 | break; | |
369 | case 1: | |
71ad556d | 370 | *status = 0; |
1da177e4 LT |
371 | break; |
372 | default: | |
373 | *status = 0xFF; | |
374 | break; | |
375 | } | |
376 | ||
1da177e4 LT |
377 | return retval; |
378 | } | |
379 | ||
82a9e79e | 380 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 381 | { |
48fe3915 | 382 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 383 | u16 slot_status; |
322162a7 | 384 | int retval; |
1da177e4 | 385 | |
322162a7 | 386 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 387 | if (retval) { |
7f2feec1 TI |
388 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
389 | __func__); | |
1da177e4 LT |
390 | return retval; |
391 | } | |
322162a7 | 392 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
393 | return 0; |
394 | } | |
395 | ||
82a9e79e | 396 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 397 | { |
48fe3915 | 398 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 399 | u16 slot_status; |
322162a7 | 400 | int retval; |
1da177e4 | 401 | |
322162a7 | 402 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 403 | if (retval) { |
7f2feec1 TI |
404 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
405 | __func__); | |
1da177e4 LT |
406 | return retval; |
407 | } | |
322162a7 | 408 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
409 | return 0; |
410 | } | |
411 | ||
82a9e79e | 412 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 413 | { |
48fe3915 | 414 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 415 | u16 slot_status; |
322162a7 | 416 | int retval; |
1da177e4 | 417 | |
322162a7 | 418 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 419 | if (retval) { |
18b341b7 | 420 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
421 | return retval; |
422 | } | |
322162a7 | 423 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
424 | } |
425 | ||
82a9e79e | 426 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 427 | { |
48fe3915 | 428 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
429 | u16 slot_cmd; |
430 | u16 cmd_mask; | |
1da177e4 | 431 | |
322162a7 | 432 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 433 | switch (value) { |
445f7985 KK |
434 | case 0 : /* turn off */ |
435 | slot_cmd = 0x00C0; | |
436 | break; | |
437 | case 1: /* turn on */ | |
438 | slot_cmd = 0x0040; | |
439 | break; | |
440 | case 2: /* turn blink */ | |
441 | slot_cmd = 0x0080; | |
442 | break; | |
443 | default: | |
444 | return -EINVAL; | |
1da177e4 | 445 | } |
1518c17a KK |
446 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
447 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 448 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
449 | } |
450 | ||
82a9e79e | 451 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 452 | { |
48fe3915 | 453 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 454 | u16 slot_cmd; |
f4778364 | 455 | u16 cmd_mask; |
71ad556d | 456 | |
f4778364 | 457 | slot_cmd = 0x0100; |
322162a7 | 458 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 459 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
460 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
461 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
462 | } |
463 | ||
82a9e79e | 464 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 465 | { |
48fe3915 | 466 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 467 | u16 slot_cmd; |
f4778364 | 468 | u16 cmd_mask; |
1da177e4 | 469 | |
f4778364 | 470 | slot_cmd = 0x0300; |
322162a7 | 471 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 472 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
473 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
474 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
475 | } |
476 | ||
82a9e79e | 477 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 478 | { |
48fe3915 | 479 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 480 | u16 slot_cmd; |
f4778364 | 481 | u16 cmd_mask; |
71ad556d | 482 | |
f4778364 | 483 | slot_cmd = 0x0200; |
322162a7 | 484 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 485 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
486 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
487 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
488 | } |
489 | ||
82a9e79e | 490 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 491 | { |
48fe3915 | 492 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 493 | u16 slot_cmd; |
f4778364 KK |
494 | u16 cmd_mask; |
495 | u16 slot_status; | |
3749c51a | 496 | u16 lnk_status; |
1da177e4 LT |
497 | int retval = 0; |
498 | ||
5a49f203 | 499 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 500 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 501 | if (retval) { |
7f2feec1 TI |
502 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
503 | __func__); | |
a0f018da KK |
504 | return retval; |
505 | } | |
322162a7 | 506 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 507 | if (slot_status) { |
322162a7 | 508 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 509 | if (retval) { |
7f2feec1 TI |
510 | ctrl_err(ctrl, |
511 | "%s: Cannot write to SLOTSTATUS register\n", | |
512 | __func__); | |
a0f018da KK |
513 | return retval; |
514 | } | |
515 | } | |
5651c48c | 516 | ctrl->power_fault_detected = 0; |
1da177e4 | 517 | |
f4778364 | 518 | slot_cmd = POWER_ON; |
322162a7 | 519 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 520 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 521 | if (retval) { |
18b341b7 | 522 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 523 | return retval; |
1da177e4 | 524 | } |
1518c17a KK |
525 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
526 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 527 | |
3749c51a MW |
528 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
529 | if (retval) { | |
530 | ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n", | |
531 | __func__); | |
532 | return retval; | |
533 | } | |
534 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); | |
535 | ||
1da177e4 LT |
536 | return retval; |
537 | } | |
538 | ||
82a9e79e | 539 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 540 | { |
48fe3915 | 541 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 542 | u16 slot_cmd; |
f4778364 | 543 | u16 cmd_mask; |
3c3a1b17 | 544 | int retval; |
f1050a35 | 545 | |
f4778364 | 546 | slot_cmd = POWER_OFF; |
322162a7 | 547 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 548 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 549 | if (retval) { |
18b341b7 | 550 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 551 | return retval; |
1da177e4 | 552 | } |
1518c17a KK |
553 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
554 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 555 | return 0; |
1da177e4 LT |
556 | } |
557 | ||
48fe3915 | 558 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 559 | { |
48fe3915 | 560 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 561 | struct slot *slot = ctrl->slot; |
c6b069e9 | 562 | u16 detected, intr_loc; |
1da177e4 | 563 | |
c6b069e9 KK |
564 | /* |
565 | * In order to guarantee that all interrupt events are | |
566 | * serviced, we need to re-inspect Slot Status register after | |
567 | * clearing what is presumed to be the last pending interrupt. | |
568 | */ | |
569 | intr_loc = 0; | |
570 | do { | |
322162a7 | 571 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
572 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
573 | __func__); | |
1da177e4 LT |
574 | return IRQ_NONE; |
575 | } | |
576 | ||
322162a7 KK |
577 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
578 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
579 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 580 | detected &= ~intr_loc; |
c6b069e9 KK |
581 | intr_loc |= detected; |
582 | if (!intr_loc) | |
1da177e4 | 583 | return IRQ_NONE; |
81b840cd | 584 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
585 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
586 | __func__); | |
1da177e4 LT |
587 | return IRQ_NONE; |
588 | } | |
c6b069e9 | 589 | } while (detected); |
71ad556d | 590 | |
7f2feec1 | 591 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 592 | |
c6b069e9 | 593 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 594 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 595 | ctrl->cmd_busy = 0; |
2d32a9ae | 596 | smp_mb(); |
d737bdc1 | 597 | wake_up(&ctrl->queue); |
1da177e4 LT |
598 | } |
599 | ||
322162a7 | 600 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
601 | return IRQ_HANDLED; |
602 | ||
c6b069e9 | 603 | /* Check MRL Sensor Changed */ |
322162a7 | 604 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 605 | pciehp_handle_switch_change(slot); |
48fe3915 | 606 | |
c6b069e9 | 607 | /* Check Attention Button Pressed */ |
322162a7 | 608 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 609 | pciehp_handle_attention_button(slot); |
48fe3915 | 610 | |
c6b069e9 | 611 | /* Check Presence Detect Changed */ |
322162a7 | 612 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 613 | pciehp_handle_presence_change(slot); |
48fe3915 | 614 | |
c6b069e9 | 615 | /* Check Power Fault Detected */ |
99f0169c KK |
616 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
617 | ctrl->power_fault_detected = 1; | |
8720d27d | 618 | pciehp_handle_power_fault(slot); |
99f0169c | 619 | } |
1da177e4 LT |
620 | return IRQ_HANDLED; |
621 | } | |
622 | ||
82a9e79e | 623 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 624 | enum pcie_link_width *value) |
1da177e4 | 625 | { |
48fe3915 | 626 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
627 | enum pcie_link_width lnk_wdth; |
628 | u32 lnk_cap; | |
629 | int retval = 0; | |
630 | ||
322162a7 | 631 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 632 | if (retval) { |
7f2feec1 | 633 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
634 | return retval; |
635 | } | |
636 | ||
322162a7 | 637 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
638 | case 0: |
639 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
640 | break; | |
641 | case 1: | |
642 | lnk_wdth = PCIE_LNK_X1; | |
643 | break; | |
644 | case 2: | |
645 | lnk_wdth = PCIE_LNK_X2; | |
646 | break; | |
647 | case 4: | |
648 | lnk_wdth = PCIE_LNK_X4; | |
649 | break; | |
650 | case 8: | |
651 | lnk_wdth = PCIE_LNK_X8; | |
652 | break; | |
653 | case 12: | |
654 | lnk_wdth = PCIE_LNK_X12; | |
655 | break; | |
656 | case 16: | |
657 | lnk_wdth = PCIE_LNK_X16; | |
658 | break; | |
659 | case 32: | |
660 | lnk_wdth = PCIE_LNK_X32; | |
661 | break; | |
662 | default: | |
663 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
664 | break; | |
665 | } | |
666 | ||
667 | *value = lnk_wdth; | |
7f2feec1 | 668 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 669 | |
1da177e4 LT |
670 | return retval; |
671 | } | |
672 | ||
82a9e79e | 673 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 674 | enum pcie_link_width *value) |
1da177e4 | 675 | { |
48fe3915 | 676 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
677 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
678 | int retval = 0; | |
679 | u16 lnk_status; | |
680 | ||
322162a7 | 681 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 682 | if (retval) { |
7f2feec1 TI |
683 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
684 | __func__); | |
1da177e4 LT |
685 | return retval; |
686 | } | |
71ad556d | 687 | |
322162a7 | 688 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
689 | case 0: |
690 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
691 | break; | |
692 | case 1: | |
693 | lnk_wdth = PCIE_LNK_X1; | |
694 | break; | |
695 | case 2: | |
696 | lnk_wdth = PCIE_LNK_X2; | |
697 | break; | |
698 | case 4: | |
699 | lnk_wdth = PCIE_LNK_X4; | |
700 | break; | |
701 | case 8: | |
702 | lnk_wdth = PCIE_LNK_X8; | |
703 | break; | |
704 | case 12: | |
705 | lnk_wdth = PCIE_LNK_X12; | |
706 | break; | |
707 | case 16: | |
708 | lnk_wdth = PCIE_LNK_X16; | |
709 | break; | |
710 | case 32: | |
711 | lnk_wdth = PCIE_LNK_X32; | |
712 | break; | |
713 | default: | |
714 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
715 | break; | |
716 | } | |
717 | ||
718 | *value = lnk_wdth; | |
7f2feec1 | 719 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 720 | |
1da177e4 LT |
721 | return retval; |
722 | } | |
723 | ||
c4635eb0 | 724 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 725 | { |
c27fb883 | 726 | u16 cmd, mask; |
1da177e4 | 727 | |
5651c48c KK |
728 | /* |
729 | * TBD: Power fault detected software notification support. | |
730 | * | |
731 | * Power fault detected software notification is not enabled | |
732 | * now, because it caused power fault detected interrupt storm | |
733 | * on some machines. On those machines, power fault detected | |
734 | * bit in the slot status register was set again immediately | |
735 | * when it is cleared in the interrupt service routine, and | |
736 | * next power fault detected interrupt was notified again. | |
737 | */ | |
322162a7 | 738 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 739 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 740 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 741 | if (MRL_SENS(ctrl)) |
322162a7 | 742 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 743 | if (!pciehp_poll_mode) |
322162a7 | 744 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 745 | |
322162a7 KK |
746 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
747 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
748 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
749 | |
750 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 751 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 752 | return -1; |
1da177e4 | 753 | } |
c4635eb0 KK |
754 | return 0; |
755 | } | |
756 | ||
757 | static void pcie_disable_notification(struct controller *ctrl) | |
758 | { | |
759 | u16 mask; | |
322162a7 KK |
760 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
761 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
762 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
763 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 764 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 765 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
766 | } |
767 | ||
dbc7e1e5 | 768 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
769 | { |
770 | if (pciehp_request_irq(ctrl)) | |
771 | return -1; | |
772 | if (pcie_enable_notification(ctrl)) { | |
773 | pciehp_free_irq(ctrl); | |
774 | return -1; | |
775 | } | |
dbc7e1e5 | 776 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
777 | return 0; |
778 | } | |
779 | ||
780 | static void pcie_shutdown_notification(struct controller *ctrl) | |
781 | { | |
dbc7e1e5 EB |
782 | if (ctrl->notification_enabled) { |
783 | pcie_disable_notification(ctrl); | |
784 | pciehp_free_irq(ctrl); | |
785 | ctrl->notification_enabled = 0; | |
786 | } | |
c4635eb0 KK |
787 | } |
788 | ||
c4635eb0 KK |
789 | static int pcie_init_slot(struct controller *ctrl) |
790 | { | |
791 | struct slot *slot; | |
792 | ||
793 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
794 | if (!slot) | |
795 | return -ENOMEM; | |
796 | ||
c4635eb0 | 797 | slot->ctrl = ctrl; |
c4635eb0 KK |
798 | mutex_init(&slot->lock); |
799 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 800 | ctrl->slot = slot; |
1da177e4 | 801 | return 0; |
1da177e4 | 802 | } |
08e7a7d2 | 803 | |
c4635eb0 KK |
804 | static void pcie_cleanup_slot(struct controller *ctrl) |
805 | { | |
8720d27d | 806 | struct slot *slot = ctrl->slot; |
c4635eb0 KK |
807 | cancel_delayed_work(&slot->work); |
808 | flush_scheduled_work(); | |
809 | flush_workqueue(pciehp_wq); | |
810 | kfree(slot); | |
811 | } | |
812 | ||
2aeeef11 | 813 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 814 | { |
2aeeef11 KK |
815 | int i; |
816 | u16 reg16; | |
385e2491 | 817 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 818 | |
2aeeef11 KK |
819 | if (!pciehp_debug) |
820 | return; | |
08e7a7d2 | 821 | |
7f2feec1 TI |
822 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
823 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
824 | pci_name(pdev), pdev->irq); | |
825 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
826 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
827 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
828 | pdev->subsystem_device); | |
829 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
830 | pdev->subsystem_vendor); | |
1518c17a KK |
831 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
832 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
833 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
834 | if (!pci_resource_len(pdev, i)) | |
835 | continue; | |
e1944c6b BH |
836 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
837 | i, &pdev->resource[i]); | |
08e7a7d2 | 838 | } |
7f2feec1 | 839 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 840 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
841 | ctrl_info(ctrl, " Attention Button : %3s\n", |
842 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
843 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
844 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
845 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
846 | MRL_SENS(ctrl) ? "yes" : "no"); | |
847 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
848 | ATTN_LED(ctrl) ? "yes" : "no"); | |
849 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
850 | PWR_LED(ctrl) ? "yes" : "no"); | |
851 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
852 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
853 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
854 | EMI(ctrl) ? "yes" : "no"); | |
855 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
856 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 857 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 858 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 859 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 860 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 861 | } |
08e7a7d2 | 862 | |
c4635eb0 | 863 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 864 | { |
c4635eb0 | 865 | struct controller *ctrl; |
f18e9625 | 866 | u32 slot_cap, link_cap; |
2aeeef11 | 867 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 868 | |
c4635eb0 KK |
869 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
870 | if (!ctrl) { | |
18b341b7 | 871 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
872 | goto abort; |
873 | } | |
f7a10e32 | 874 | ctrl->pcie = dev; |
1518c17a | 875 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 876 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 877 | goto abort_ctrl; |
08e7a7d2 | 878 | } |
322162a7 | 879 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 880 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 881 | goto abort_ctrl; |
08e7a7d2 | 882 | } |
08e7a7d2 | 883 | |
2aeeef11 | 884 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 885 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 886 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 887 | dbg_ctrl(ctrl); |
5808639b KK |
888 | /* |
889 | * Controller doesn't notify of command completion if the "No | |
890 | * Command Completed Support" bit is set in Slot Capability | |
891 | * register or the controller supports none of power | |
892 | * controller, attention led, power led and EMI. | |
893 | */ | |
894 | if (NO_CMD_CMPL(ctrl) || | |
895 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
896 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 897 | |
f18e9625 | 898 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 899 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
900 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
901 | goto abort_ctrl; | |
902 | } | |
322162a7 | 903 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
904 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
905 | ctrl->link_active_reporting = 1; | |
906 | } | |
907 | ||
c4635eb0 | 908 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 909 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 910 | goto abort_ctrl; |
08e7a7d2 | 911 | |
c4635eb0 KK |
912 | /* Disable sotfware notification */ |
913 | pcie_disable_notification(ctrl); | |
ecdde939 ML |
914 | |
915 | /* | |
916 | * If this is the first controller to be initialized, | |
917 | * initialize the pciehp work queue | |
918 | */ | |
919 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
920 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
c4635eb0 KK |
921 | if (!pciehp_wq) |
922 | goto abort_ctrl; | |
ecdde939 ML |
923 | } |
924 | ||
7f2feec1 TI |
925 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
926 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
927 | pdev->subsystem_device); | |
c4635eb0 KK |
928 | |
929 | if (pcie_init_slot(ctrl)) | |
930 | goto abort_ctrl; | |
2aeeef11 | 931 | |
c4635eb0 KK |
932 | return ctrl; |
933 | ||
c4635eb0 KK |
934 | abort_ctrl: |
935 | kfree(ctrl); | |
08e7a7d2 | 936 | abort: |
c4635eb0 KK |
937 | return NULL; |
938 | } | |
939 | ||
82a9e79e | 940 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
941 | { |
942 | pcie_shutdown_notification(ctrl); | |
943 | pcie_cleanup_slot(ctrl); | |
944 | /* | |
945 | * If this is the last controller to be released, destroy the | |
946 | * pciehp work queue | |
947 | */ | |
948 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
949 | destroy_workqueue(pciehp_wq); | |
950 | kfree(ctrl); | |
08e7a7d2 | 951 | } |