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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
5d1b8c9e AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "../pci.h" |
37 | #include "pciehp.h" | |
38 | ||
39 | #ifdef DEBUG | |
40 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
41 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
42 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
43 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
44 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
45 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
46 | /* Redefine this flagword to set debug level */ | |
47 | #define DEBUG_LEVEL DBG_K_STANDARD | |
48 | ||
49 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
50 | ||
51 | #define DBG_PRINT( dbg_flags, args... ) \ | |
52 | do { \ | |
53 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
54 | { \ | |
55 | int len; \ | |
56 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
57 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
58 | sprintf( __dbg_str_buf + len, args ); \ | |
59 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
60 | } \ | |
61 | } while (0) | |
62 | ||
63 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
64 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
65 | #else | |
66 | #define DEFINE_DBG_BUFFER | |
67 | #define DBG_ENTER_ROUTINE | |
68 | #define DBG_LEAVE_ROUTINE | |
69 | #endif /* DEBUG */ | |
70 | ||
71 | struct ctrl_reg { | |
72 | u8 cap_id; | |
73 | u8 nxt_ptr; | |
74 | u16 cap_reg; | |
75 | u32 dev_cap; | |
76 | u16 dev_ctrl; | |
77 | u16 dev_status; | |
78 | u32 lnk_cap; | |
79 | u16 lnk_ctrl; | |
80 | u16 lnk_status; | |
81 | u32 slot_cap; | |
82 | u16 slot_ctrl; | |
83 | u16 slot_status; | |
84 | u16 root_ctrl; | |
85 | u16 rsvp; | |
86 | u32 root_status; | |
87 | } __attribute__ ((packed)); | |
88 | ||
89 | /* offsets to the controller registers based on the above structure layout */ | |
90 | enum ctrl_offsets { | |
91 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
92 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
93 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
94 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
95 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
96 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
97 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
98 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
99 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
100 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
101 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
102 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
103 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
104 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
105 | }; | |
106 | static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */ | |
107 | ||
8b245e45 DS |
108 | #define PCIE_CAP_ID(cb) ( cb + PCIECAPID ) |
109 | #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR ) | |
110 | #define CAP_REG(cb) ( cb + CAPREG ) | |
111 | #define DEV_CAP(cb) ( cb + DEVCAP ) | |
112 | #define DEV_CTRL(cb) ( cb + DEVCTRL ) | |
113 | #define DEV_STATUS(cb) ( cb + DEVSTATUS ) | |
114 | #define LNK_CAP(cb) ( cb + LNKCAP ) | |
115 | #define LNK_CTRL(cb) ( cb + LNKCTRL ) | |
116 | #define LNK_STATUS(cb) ( cb + LNKSTATUS ) | |
117 | #define SLOT_CAP(cb) ( cb + SLOTCAP ) | |
118 | #define SLOT_CTRL(cb) ( cb + SLOTCTRL ) | |
119 | #define SLOT_STATUS(cb) ( cb + SLOTSTATUS ) | |
120 | #define ROOT_CTRL(cb) ( cb + ROOTCTRL ) | |
121 | #define ROOT_STATUS(cb) ( cb + ROOTSTATUS ) | |
1da177e4 LT |
122 | |
123 | #define hp_register_read_word(pdev, reg , value) \ | |
124 | pci_read_config_word(pdev, reg, &value) | |
125 | ||
126 | #define hp_register_read_dword(pdev, reg , value) \ | |
127 | pci_read_config_dword(pdev, reg, &value) | |
128 | ||
129 | #define hp_register_write_word(pdev, reg , value) \ | |
130 | pci_write_config_word(pdev, reg, value) | |
131 | ||
132 | #define hp_register_dwrite_word(pdev, reg , value) \ | |
133 | pci_write_config_dword(pdev, reg, value) | |
134 | ||
135 | /* Field definitions in PCI Express Capabilities Register */ | |
136 | #define CAP_VER 0x000F | |
137 | #define DEV_PORT_TYPE 0x00F0 | |
138 | #define SLOT_IMPL 0x0100 | |
139 | #define MSG_NUM 0x3E00 | |
140 | ||
141 | /* Device or Port Type */ | |
142 | #define NAT_ENDPT 0x00 | |
143 | #define LEG_ENDPT 0x01 | |
144 | #define ROOT_PORT 0x04 | |
145 | #define UP_STREAM 0x05 | |
146 | #define DN_STREAM 0x06 | |
147 | #define PCIE_PCI_BRDG 0x07 | |
148 | #define PCI_PCIE_BRDG 0x10 | |
149 | ||
150 | /* Field definitions in Device Capabilities Register */ | |
151 | #define DATTN_BUTTN_PRSN 0x1000 | |
152 | #define DATTN_LED_PRSN 0x2000 | |
153 | #define DPWR_LED_PRSN 0x4000 | |
154 | ||
155 | /* Field definitions in Link Capabilities Register */ | |
156 | #define MAX_LNK_SPEED 0x000F | |
157 | #define MAX_LNK_WIDTH 0x03F0 | |
158 | ||
159 | /* Link Width Encoding */ | |
160 | #define LNK_X1 0x01 | |
161 | #define LNK_X2 0x02 | |
162 | #define LNK_X4 0x04 | |
163 | #define LNK_X8 0x08 | |
164 | #define LNK_X12 0x0C | |
165 | #define LNK_X16 0x10 | |
166 | #define LNK_X32 0x20 | |
167 | ||
168 | /*Field definitions of Link Status Register */ | |
169 | #define LNK_SPEED 0x000F | |
170 | #define NEG_LINK_WD 0x03F0 | |
171 | #define LNK_TRN_ERR 0x0400 | |
172 | #define LNK_TRN 0x0800 | |
173 | #define SLOT_CLK_CONF 0x1000 | |
174 | ||
175 | /* Field definitions in Slot Capabilities Register */ | |
176 | #define ATTN_BUTTN_PRSN 0x00000001 | |
177 | #define PWR_CTRL_PRSN 0x00000002 | |
178 | #define MRL_SENS_PRSN 0x00000004 | |
179 | #define ATTN_LED_PRSN 0x00000008 | |
180 | #define PWR_LED_PRSN 0x00000010 | |
181 | #define HP_SUPR_RM_SUP 0x00000020 | |
182 | #define HP_CAP 0x00000040 | |
183 | #define SLOT_PWR_VALUE 0x000003F8 | |
184 | #define SLOT_PWR_LIMIT 0x00000C00 | |
185 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
186 | ||
187 | /* Field definitions in Slot Control Register */ | |
188 | #define ATTN_BUTTN_ENABLE 0x0001 | |
189 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
190 | #define MRL_DETECT_ENABLE 0x0004 | |
191 | #define PRSN_DETECT_ENABLE 0x0008 | |
192 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
193 | #define HP_INTR_ENABLE 0x0020 | |
194 | #define ATTN_LED_CTRL 0x00C0 | |
195 | #define PWR_LED_CTRL 0x0300 | |
196 | #define PWR_CTRL 0x0400 | |
197 | ||
198 | /* Attention indicator and Power indicator states */ | |
199 | #define LED_ON 0x01 | |
200 | #define LED_BLINK 0x10 | |
201 | #define LED_OFF 0x11 | |
202 | ||
203 | /* Power Control Command */ | |
204 | #define POWER_ON 0 | |
205 | #define POWER_OFF 0x0400 | |
206 | ||
207 | /* Field definitions in Slot Status Register */ | |
208 | #define ATTN_BUTTN_PRESSED 0x0001 | |
209 | #define PWR_FAULT_DETECTED 0x0002 | |
210 | #define MRL_SENS_CHANGED 0x0004 | |
211 | #define PRSN_DETECT_CHANGED 0x0008 | |
212 | #define CMD_COMPLETED 0x0010 | |
213 | #define MRL_STATE 0x0020 | |
214 | #define PRSN_STATE 0x0040 | |
215 | ||
1da177e4 LT |
216 | static spinlock_t hpc_event_lock; |
217 | ||
218 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | |
219 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | |
220 | static int ctlr_seq_num = 0; /* Controller sequence # */ | |
221 | static spinlock_t list_lock; | |
222 | ||
223 | static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs); | |
224 | ||
225 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); | |
226 | ||
227 | /* This is the interrupt polling timeout function. */ | |
228 | static void int_poll_timeout(unsigned long lphp_ctlr) | |
229 | { | |
230 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; | |
231 | ||
232 | DBG_ENTER_ROUTINE | |
233 | ||
234 | if ( !php_ctlr ) { | |
235 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
236 | return; | |
237 | } | |
238 | ||
239 | /* Poll for interrupt events. regs == NULL => polling */ | |
240 | pcie_isr( 0, (void *)php_ctlr, NULL ); | |
241 | ||
242 | init_timer(&php_ctlr->int_poll_timer); | |
243 | ||
244 | if (!pciehp_poll_time) | |
245 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
246 | ||
247 | start_int_poll_timer(php_ctlr, pciehp_poll_time); | |
248 | ||
249 | return; | |
250 | } | |
251 | ||
252 | /* This function starts the interrupt polling timer. */ | |
253 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) | |
254 | { | |
255 | if (!php_ctlr) { | |
256 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
257 | return; | |
258 | } | |
259 | ||
260 | if ( ( seconds <= 0 ) || ( seconds > 60 ) ) | |
261 | seconds = 2; /* Clamp to sane value */ | |
262 | ||
263 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | |
264 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ | |
265 | php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; | |
266 | add_timer(&php_ctlr->int_poll_timer); | |
267 | ||
268 | return; | |
269 | } | |
270 | ||
271 | static int pcie_write_cmd(struct slot *slot, u16 cmd) | |
272 | { | |
273 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
274 | int retval = 0; | |
275 | u16 slot_status; | |
276 | ||
277 | DBG_ENTER_ROUTINE | |
278 | ||
1da177e4 LT |
279 | if (!php_ctlr) { |
280 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
281 | return -1; | |
282 | } | |
283 | ||
8b245e45 | 284 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
285 | if (retval) { |
286 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
287 | return retval; | |
288 | } | |
1da177e4 LT |
289 | |
290 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { | |
291 | /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue | |
292 | the next command according to spec. Just print out the error message */ | |
293 | dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__); | |
294 | } | |
295 | ||
8b245e45 | 296 | retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE); |
1da177e4 LT |
297 | if (retval) { |
298 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
299 | return retval; | |
300 | } | |
1da177e4 LT |
301 | |
302 | DBG_LEAVE_ROUTINE | |
303 | return retval; | |
304 | } | |
305 | ||
306 | static int hpc_check_lnk_status(struct controller *ctrl) | |
307 | { | |
308 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
309 | u16 lnk_status; | |
310 | int retval = 0; | |
311 | ||
312 | DBG_ENTER_ROUTINE | |
313 | ||
314 | if (!php_ctlr) { | |
315 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
316 | return -1; | |
317 | } | |
318 | ||
8b245e45 | 319 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status); |
1da177e4 LT |
320 | |
321 | if (retval) { | |
322 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
323 | return retval; | |
324 | } | |
325 | ||
326 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); | |
327 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || | |
328 | !(lnk_status & NEG_LINK_WD)) { | |
329 | err("%s : Link Training Error occurs \n", __FUNCTION__); | |
330 | retval = -1; | |
331 | return retval; | |
332 | } | |
333 | ||
334 | DBG_LEAVE_ROUTINE | |
335 | return retval; | |
336 | } | |
337 | ||
338 | ||
339 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
340 | { | |
341 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
342 | u16 slot_ctrl; | |
343 | u8 atten_led_state; | |
344 | int retval = 0; | |
345 | ||
346 | DBG_ENTER_ROUTINE | |
347 | ||
348 | if (!php_ctlr) { | |
349 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
350 | return -1; | |
351 | } | |
352 | ||
8b245e45 | 353 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
354 | |
355 | if (retval) { | |
356 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
357 | return retval; | |
358 | } | |
359 | ||
8b245e45 | 360 | dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
361 | |
362 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
363 | ||
364 | switch (atten_led_state) { | |
365 | case 0: | |
366 | *status = 0xFF; /* Reserved */ | |
367 | break; | |
368 | case 1: | |
369 | *status = 1; /* On */ | |
370 | break; | |
371 | case 2: | |
372 | *status = 2; /* Blink */ | |
373 | break; | |
374 | case 3: | |
375 | *status = 0; /* Off */ | |
376 | break; | |
377 | default: | |
378 | *status = 0xFF; | |
379 | break; | |
380 | } | |
381 | ||
382 | DBG_LEAVE_ROUTINE | |
383 | return 0; | |
384 | } | |
385 | ||
386 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
387 | { | |
388 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
389 | u16 slot_ctrl; | |
390 | u8 pwr_state; | |
391 | int retval = 0; | |
392 | ||
393 | DBG_ENTER_ROUTINE | |
394 | ||
395 | if (!php_ctlr) { | |
396 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
397 | return -1; | |
398 | } | |
399 | ||
8b245e45 | 400 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
401 | |
402 | if (retval) { | |
403 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
404 | return retval; | |
405 | } | |
8b245e45 | 406 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
407 | |
408 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
409 | ||
410 | switch (pwr_state) { | |
411 | case 0: | |
412 | *status = 1; | |
413 | break; | |
414 | case 1: | |
415 | *status = 0; | |
416 | break; | |
417 | default: | |
418 | *status = 0xFF; | |
419 | break; | |
420 | } | |
421 | ||
422 | DBG_LEAVE_ROUTINE | |
423 | return retval; | |
424 | } | |
425 | ||
426 | ||
427 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
428 | { | |
429 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
430 | u16 slot_status; | |
431 | int retval = 0; | |
432 | ||
433 | DBG_ENTER_ROUTINE | |
434 | ||
435 | if (!php_ctlr) { | |
436 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
437 | return -1; | |
438 | } | |
439 | ||
8b245e45 | 440 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
441 | |
442 | if (retval) { | |
443 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
444 | return retval; | |
445 | } | |
446 | ||
447 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; | |
448 | ||
449 | DBG_LEAVE_ROUTINE | |
450 | return 0; | |
451 | } | |
452 | ||
453 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
454 | { | |
455 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
456 | u16 slot_status; | |
457 | u8 card_state; | |
458 | int retval = 0; | |
459 | ||
460 | DBG_ENTER_ROUTINE | |
461 | ||
462 | if (!php_ctlr) { | |
463 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
464 | return -1; | |
465 | } | |
466 | ||
8b245e45 | 467 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
468 | |
469 | if (retval) { | |
470 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
471 | return retval; | |
472 | } | |
473 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
474 | *status = (card_state == 1) ? 1 : 0; | |
475 | ||
476 | DBG_LEAVE_ROUTINE | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static int hpc_query_power_fault(struct slot * slot) | |
481 | { | |
482 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
483 | u16 slot_status; | |
484 | u8 pwr_fault; | |
485 | int retval = 0; | |
1da177e4 LT |
486 | |
487 | DBG_ENTER_ROUTINE | |
488 | ||
489 | if (!php_ctlr) { | |
490 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
491 | return -1; | |
492 | } | |
493 | ||
8b245e45 | 494 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
495 | |
496 | if (retval) { | |
8239def1 | 497 | err("%s : Cannot check for power fault\n", __FUNCTION__); |
1da177e4 LT |
498 | return retval; |
499 | } | |
500 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
1da177e4 LT |
501 | |
502 | DBG_LEAVE_ROUTINE | |
8239def1 | 503 | return pwr_fault; |
1da177e4 LT |
504 | } |
505 | ||
506 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
507 | { | |
508 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
509 | u16 slot_cmd = 0; | |
510 | u16 slot_ctrl; | |
511 | int rc = 0; | |
512 | ||
1a9ed1bf | 513 | DBG_ENTER_ROUTINE |
514 | ||
1da177e4 LT |
515 | if (!php_ctlr) { |
516 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
517 | return -1; | |
518 | } | |
519 | ||
520 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
521 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
522 | return -1; | |
523 | } | |
8b245e45 | 524 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
525 | |
526 | if (rc) { | |
527 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
528 | return rc; | |
529 | } | |
1da177e4 LT |
530 | |
531 | switch (value) { | |
532 | case 0 : /* turn off */ | |
533 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; | |
534 | break; | |
535 | case 1: /* turn on */ | |
536 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; | |
537 | break; | |
538 | case 2: /* turn blink */ | |
539 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; | |
540 | break; | |
541 | default: | |
542 | return -1; | |
543 | } | |
544 | if (!pciehp_poll_mode) | |
545 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
546 | ||
547 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 548 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 549 | |
1a9ed1bf | 550 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
551 | return rc; |
552 | } | |
553 | ||
554 | ||
555 | static void hpc_set_green_led_on(struct slot *slot) | |
556 | { | |
557 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
558 | u16 slot_cmd; | |
559 | u16 slot_ctrl; | |
560 | int rc = 0; | |
561 | ||
1a9ed1bf | 562 | DBG_ENTER_ROUTINE |
563 | ||
1da177e4 LT |
564 | if (!php_ctlr) { |
565 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
566 | return ; | |
567 | } | |
568 | ||
569 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
570 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
571 | return ; | |
572 | } | |
573 | ||
8b245e45 | 574 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
575 | |
576 | if (rc) { | |
577 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
578 | return; | |
579 | } | |
1da177e4 LT |
580 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; |
581 | if (!pciehp_poll_mode) | |
582 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
583 | ||
584 | pcie_write_cmd(slot, slot_cmd); | |
585 | ||
8b245e45 | 586 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 587 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
588 | return; |
589 | } | |
590 | ||
591 | static void hpc_set_green_led_off(struct slot *slot) | |
592 | { | |
593 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
594 | u16 slot_cmd; | |
595 | u16 slot_ctrl; | |
596 | int rc = 0; | |
597 | ||
1a9ed1bf | 598 | DBG_ENTER_ROUTINE |
599 | ||
1da177e4 LT |
600 | if (!php_ctlr) { |
601 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
602 | return ; | |
603 | } | |
604 | ||
605 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
606 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
607 | return ; | |
608 | } | |
609 | ||
8b245e45 | 610 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
611 | |
612 | if (rc) { | |
613 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
614 | return; | |
615 | } | |
1da177e4 LT |
616 | |
617 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; | |
618 | ||
619 | if (!pciehp_poll_mode) | |
620 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
621 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 622 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 623 | |
1a9ed1bf | 624 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
625 | return; |
626 | } | |
627 | ||
628 | static void hpc_set_green_led_blink(struct slot *slot) | |
629 | { | |
630 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
631 | u16 slot_cmd; | |
632 | u16 slot_ctrl; | |
633 | int rc = 0; | |
634 | ||
1a9ed1bf | 635 | DBG_ENTER_ROUTINE |
636 | ||
1da177e4 LT |
637 | if (!php_ctlr) { |
638 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
639 | return ; | |
640 | } | |
641 | ||
642 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
643 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
644 | return ; | |
645 | } | |
646 | ||
8b245e45 | 647 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
648 | |
649 | if (rc) { | |
650 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
651 | return; | |
652 | } | |
1da177e4 LT |
653 | |
654 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; | |
655 | ||
656 | if (!pciehp_poll_mode) | |
657 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
658 | pcie_write_cmd(slot, slot_cmd); | |
659 | ||
8b245e45 | 660 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 661 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
662 | return; |
663 | } | |
664 | ||
665 | int pcie_get_ctlr_slot_config(struct controller *ctrl, | |
666 | int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */ | |
667 | int *first_device_num, /* PCI dev num of the first slot in this PCIE */ | |
668 | int *physical_slot_num, /* phy slot num of the first slot in this PCIE */ | |
669 | u8 *ctrlcap) | |
670 | { | |
671 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
672 | u32 slot_cap; | |
673 | int rc = 0; | |
674 | ||
675 | DBG_ENTER_ROUTINE | |
676 | ||
677 | if (!php_ctlr) { | |
678 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
679 | return -1; | |
680 | } | |
681 | ||
682 | *first_device_num = 0; | |
683 | *num_ctlr_slots = 1; | |
684 | ||
8b245e45 | 685 | rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
686 | |
687 | if (rc) { | |
688 | err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__); | |
689 | return -1; | |
690 | } | |
691 | ||
692 | *physical_slot_num = slot_cap >> 19; | |
693 | dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num); | |
694 | ||
695 | *ctrlcap = slot_cap & 0x0000007f; | |
696 | ||
697 | DBG_LEAVE_ROUTINE | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static void hpc_release_ctlr(struct controller *ctrl) | |
702 | { | |
703 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
704 | struct php_ctlr_state_s *p, *p_prev; | |
705 | ||
706 | DBG_ENTER_ROUTINE | |
707 | ||
708 | if (!php_ctlr) { | |
709 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
710 | return ; | |
711 | } | |
712 | ||
713 | if (pciehp_poll_mode) { | |
714 | del_timer(&php_ctlr->int_poll_timer); | |
715 | } else { | |
716 | if (php_ctlr->irq) { | |
717 | free_irq(php_ctlr->irq, ctrl); | |
718 | php_ctlr->irq = 0; | |
719 | if (!pcie_mch_quirk) | |
720 | pci_disable_msi(php_ctlr->pci_dev); | |
721 | } | |
722 | } | |
723 | if (php_ctlr->pci_dev) | |
724 | php_ctlr->pci_dev = NULL; | |
725 | ||
726 | spin_lock(&list_lock); | |
727 | p = php_ctlr_list_head; | |
728 | p_prev = NULL; | |
729 | while (p) { | |
730 | if (p == php_ctlr) { | |
731 | if (p_prev) | |
732 | p_prev->pnext = p->pnext; | |
733 | else | |
734 | php_ctlr_list_head = p->pnext; | |
735 | break; | |
736 | } else { | |
737 | p_prev = p; | |
738 | p = p->pnext; | |
739 | } | |
740 | } | |
741 | spin_unlock(&list_lock); | |
742 | ||
743 | kfree(php_ctlr); | |
744 | ||
745 | DBG_LEAVE_ROUTINE | |
746 | ||
747 | } | |
748 | ||
749 | static int hpc_power_on_slot(struct slot * slot) | |
750 | { | |
751 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
752 | u16 slot_cmd; | |
5a49f203 | 753 | u16 slot_ctrl, slot_status; |
1da177e4 LT |
754 | |
755 | int retval = 0; | |
756 | ||
757 | DBG_ENTER_ROUTINE | |
1da177e4 LT |
758 | |
759 | if (!php_ctlr) { | |
760 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
761 | return -1; | |
762 | } | |
763 | ||
764 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | |
765 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
766 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
767 | return -1; | |
768 | } | |
769 | ||
5a49f203 RS |
770 | /* Clear sticky power-fault bit from previous power failures */ |
771 | hp_register_read_word(php_ctlr->pci_dev, | |
772 | SLOT_STATUS(slot->ctrl->cap_base), slot_status); | |
773 | slot_status &= PWR_FAULT_DETECTED; | |
774 | if (slot_status) | |
775 | hp_register_write_word(php_ctlr->pci_dev, | |
776 | SLOT_STATUS(slot->ctrl->cap_base), slot_status); | |
777 | ||
8b245e45 | 778 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
779 | |
780 | if (retval) { | |
781 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
782 | return retval; | |
783 | } | |
1da177e4 LT |
784 | |
785 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; | |
786 | ||
787 | if (!pciehp_poll_mode) | |
788 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
789 | ||
790 | retval = pcie_write_cmd(slot, slot_cmd); | |
791 | ||
792 | if (retval) { | |
793 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); | |
794 | return -1; | |
795 | } | |
8b245e45 | 796 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
797 | |
798 | DBG_LEAVE_ROUTINE | |
799 | ||
800 | return retval; | |
801 | } | |
802 | ||
803 | static int hpc_power_off_slot(struct slot * slot) | |
804 | { | |
805 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
806 | u16 slot_cmd; | |
807 | u16 slot_ctrl; | |
808 | ||
809 | int retval = 0; | |
810 | ||
811 | DBG_ENTER_ROUTINE | |
1da177e4 LT |
812 | |
813 | if (!php_ctlr) { | |
814 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
815 | return -1; | |
816 | } | |
817 | ||
818 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | |
819 | slot->hp_slot = 0; | |
820 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
821 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
822 | return -1; | |
823 | } | |
8b245e45 | 824 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
825 | |
826 | if (retval) { | |
827 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
828 | return retval; | |
829 | } | |
1da177e4 LT |
830 | |
831 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; | |
832 | ||
833 | if (!pciehp_poll_mode) | |
834 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
835 | ||
836 | retval = pcie_write_cmd(slot, slot_cmd); | |
837 | ||
838 | if (retval) { | |
839 | err("%s: Write command failed!\n", __FUNCTION__); | |
840 | return -1; | |
841 | } | |
8b245e45 | 842 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
843 | |
844 | DBG_LEAVE_ROUTINE | |
845 | ||
846 | return retval; | |
847 | } | |
848 | ||
849 | static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |
850 | { | |
851 | struct controller *ctrl = NULL; | |
852 | struct php_ctlr_state_s *php_ctlr; | |
853 | u8 schedule_flag = 0; | |
854 | u16 slot_status, intr_detect, intr_loc; | |
855 | u16 temp_word; | |
856 | int hp_slot = 0; /* only 1 slot per PCI Express port */ | |
857 | int rc = 0; | |
858 | ||
859 | if (!dev_id) | |
860 | return IRQ_NONE; | |
861 | ||
862 | if (!pciehp_poll_mode) { | |
863 | ctrl = dev_id; | |
864 | php_ctlr = ctrl->hpc_ctlr_handle; | |
865 | } else { | |
866 | php_ctlr = dev_id; | |
867 | ctrl = (struct controller *)php_ctlr->callback_instance_id; | |
868 | } | |
869 | ||
870 | if (!ctrl) { | |
871 | dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id); | |
872 | return IRQ_NONE; | |
873 | } | |
874 | ||
875 | if (!php_ctlr) { | |
876 | dbg("%s: php_ctlr == NULL\n", __FUNCTION__); | |
877 | return IRQ_NONE; | |
878 | } | |
879 | ||
8b245e45 | 880 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
881 | if (rc) { |
882 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
883 | return IRQ_NONE; | |
884 | } | |
885 | ||
886 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | | |
887 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); | |
888 | ||
889 | intr_loc = slot_status & intr_detect; | |
890 | ||
891 | /* Check to see if it was our interrupt */ | |
892 | if ( !intr_loc ) | |
893 | return IRQ_NONE; | |
894 | ||
895 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | |
896 | /* Mask Hot-plug Interrupt Enable */ | |
897 | if (!pciehp_poll_mode) { | |
8b245e45 | 898 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
899 | if (rc) { |
900 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
901 | return IRQ_NONE; | |
902 | } | |
903 | ||
1da177e4 LT |
904 | dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); |
905 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; | |
906 | ||
8b245e45 | 907 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
908 | if (rc) { |
909 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
910 | return IRQ_NONE; | |
911 | } | |
1da177e4 | 912 | |
8b245e45 | 913 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
914 | if (rc) { |
915 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
916 | return IRQ_NONE; | |
917 | } | |
918 | dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status); | |
919 | ||
920 | /* Clear command complete interrupt caused by this write */ | |
921 | temp_word = 0x1f; | |
8b245e45 | 922 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
923 | if (rc) { |
924 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
925 | return IRQ_NONE; | |
926 | } | |
1da177e4 LT |
927 | } |
928 | ||
929 | if (intr_loc & CMD_COMPLETED) { | |
930 | /* | |
931 | * Command Complete Interrupt Pending | |
932 | */ | |
1da177e4 LT |
933 | wake_up_interruptible(&ctrl->queue); |
934 | } | |
935 | ||
936 | if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED)) | |
937 | schedule_flag += php_ctlr->switch_change_callback( | |
938 | hp_slot, php_ctlr->callback_instance_id); | |
939 | if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED)) | |
940 | schedule_flag += php_ctlr->attention_button_callback( | |
941 | hp_slot, php_ctlr->callback_instance_id); | |
942 | if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED)) | |
943 | schedule_flag += php_ctlr->presence_change_callback( | |
944 | hp_slot , php_ctlr->callback_instance_id); | |
945 | if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED)) | |
946 | schedule_flag += php_ctlr->power_fault_callback( | |
947 | hp_slot, php_ctlr->callback_instance_id); | |
948 | ||
949 | /* Clear all events after serving them */ | |
950 | temp_word = 0x1F; | |
8b245e45 | 951 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
952 | if (rc) { |
953 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
954 | return IRQ_NONE; | |
955 | } | |
956 | /* Unmask Hot-plug Interrupt Enable */ | |
957 | if (!pciehp_poll_mode) { | |
8b245e45 | 958 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
959 | if (rc) { |
960 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
961 | return IRQ_NONE; | |
962 | } | |
963 | ||
964 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); | |
1da177e4 LT |
965 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
966 | ||
8b245e45 | 967 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
968 | if (rc) { |
969 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
970 | return IRQ_NONE; | |
971 | } | |
1da177e4 | 972 | |
8b245e45 | 973 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
974 | if (rc) { |
975 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
976 | return IRQ_NONE; | |
977 | } | |
1da177e4 LT |
978 | |
979 | /* Clear command complete interrupt caused by this write */ | |
980 | temp_word = 0x1F; | |
8b245e45 | 981 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
982 | if (rc) { |
983 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
984 | return IRQ_NONE; | |
985 | } | |
986 | dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word); | |
987 | } | |
988 | ||
989 | return IRQ_HANDLED; | |
990 | } | |
991 | ||
992 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
993 | { | |
994 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
995 | enum pcie_link_speed lnk_speed; | |
996 | u32 lnk_cap; | |
997 | int retval = 0; | |
998 | ||
999 | DBG_ENTER_ROUTINE | |
1000 | ||
1001 | if (!php_ctlr) { | |
1002 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1003 | return -1; | |
1004 | } | |
1005 | ||
1006 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1007 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1008 | return -1; | |
1009 | } | |
1010 | ||
8b245e45 | 1011 | retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap); |
1da177e4 LT |
1012 | |
1013 | if (retval) { | |
1014 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
1015 | return retval; | |
1016 | } | |
1017 | ||
1018 | switch (lnk_cap & 0x000F) { | |
1019 | case 1: | |
1020 | lnk_speed = PCIE_2PT5GB; | |
1021 | break; | |
1022 | default: | |
1023 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | *value = lnk_speed; | |
1028 | dbg("Max link speed = %d\n", lnk_speed); | |
1029 | DBG_LEAVE_ROUTINE | |
1030 | return retval; | |
1031 | } | |
1032 | ||
1033 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
1034 | { | |
1035 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1036 | enum pcie_link_width lnk_wdth; | |
1037 | u32 lnk_cap; | |
1038 | int retval = 0; | |
1039 | ||
1040 | DBG_ENTER_ROUTINE | |
1041 | ||
1042 | if (!php_ctlr) { | |
1043 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1044 | return -1; | |
1045 | } | |
1046 | ||
1047 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1048 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1049 | return -1; | |
1050 | } | |
1051 | ||
8b245e45 | 1052 | retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap); |
1da177e4 LT |
1053 | |
1054 | if (retval) { | |
1055 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
1056 | return retval; | |
1057 | } | |
1058 | ||
1059 | switch ((lnk_cap & 0x03F0) >> 4){ | |
1060 | case 0: | |
1061 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
1062 | break; | |
1063 | case 1: | |
1064 | lnk_wdth = PCIE_LNK_X1; | |
1065 | break; | |
1066 | case 2: | |
1067 | lnk_wdth = PCIE_LNK_X2; | |
1068 | break; | |
1069 | case 4: | |
1070 | lnk_wdth = PCIE_LNK_X4; | |
1071 | break; | |
1072 | case 8: | |
1073 | lnk_wdth = PCIE_LNK_X8; | |
1074 | break; | |
1075 | case 12: | |
1076 | lnk_wdth = PCIE_LNK_X12; | |
1077 | break; | |
1078 | case 16: | |
1079 | lnk_wdth = PCIE_LNK_X16; | |
1080 | break; | |
1081 | case 32: | |
1082 | lnk_wdth = PCIE_LNK_X32; | |
1083 | break; | |
1084 | default: | |
1085 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1086 | break; | |
1087 | } | |
1088 | ||
1089 | *value = lnk_wdth; | |
1090 | dbg("Max link width = %d\n", lnk_wdth); | |
1091 | DBG_LEAVE_ROUTINE | |
1092 | return retval; | |
1093 | } | |
1094 | ||
1095 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
1096 | { | |
1097 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1098 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; | |
1099 | int retval = 0; | |
1100 | u16 lnk_status; | |
1101 | ||
1102 | DBG_ENTER_ROUTINE | |
1103 | ||
1104 | if (!php_ctlr) { | |
1105 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1106 | return -1; | |
1107 | } | |
1108 | ||
1109 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1110 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1111 | return -1; | |
1112 | } | |
1113 | ||
8b245e45 | 1114 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status); |
1da177e4 LT |
1115 | |
1116 | if (retval) { | |
1117 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
1118 | return retval; | |
1119 | } | |
1120 | ||
1121 | switch (lnk_status & 0x0F) { | |
1122 | case 1: | |
1123 | lnk_speed = PCIE_2PT5GB; | |
1124 | break; | |
1125 | default: | |
1126 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
1127 | break; | |
1128 | } | |
1129 | ||
1130 | *value = lnk_speed; | |
1131 | dbg("Current link speed = %d\n", lnk_speed); | |
1132 | DBG_LEAVE_ROUTINE | |
1133 | return retval; | |
1134 | } | |
1135 | ||
1136 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
1137 | { | |
1138 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1139 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1140 | int retval = 0; | |
1141 | u16 lnk_status; | |
1142 | ||
1143 | DBG_ENTER_ROUTINE | |
1144 | ||
1145 | if (!php_ctlr) { | |
1146 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1147 | return -1; | |
1148 | } | |
1149 | ||
1150 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1151 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1152 | return -1; | |
1153 | } | |
1154 | ||
8b245e45 | 1155 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status); |
1da177e4 LT |
1156 | |
1157 | if (retval) { | |
1158 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
1159 | return retval; | |
1160 | } | |
1161 | ||
1162 | switch ((lnk_status & 0x03F0) >> 4){ | |
1163 | case 0: | |
1164 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
1165 | break; | |
1166 | case 1: | |
1167 | lnk_wdth = PCIE_LNK_X1; | |
1168 | break; | |
1169 | case 2: | |
1170 | lnk_wdth = PCIE_LNK_X2; | |
1171 | break; | |
1172 | case 4: | |
1173 | lnk_wdth = PCIE_LNK_X4; | |
1174 | break; | |
1175 | case 8: | |
1176 | lnk_wdth = PCIE_LNK_X8; | |
1177 | break; | |
1178 | case 12: | |
1179 | lnk_wdth = PCIE_LNK_X12; | |
1180 | break; | |
1181 | case 16: | |
1182 | lnk_wdth = PCIE_LNK_X16; | |
1183 | break; | |
1184 | case 32: | |
1185 | lnk_wdth = PCIE_LNK_X32; | |
1186 | break; | |
1187 | default: | |
1188 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1189 | break; | |
1190 | } | |
1191 | ||
1192 | *value = lnk_wdth; | |
1193 | dbg("Current link width = %d\n", lnk_wdth); | |
1194 | DBG_LEAVE_ROUTINE | |
1195 | return retval; | |
1196 | } | |
1197 | ||
1198 | static struct hpc_ops pciehp_hpc_ops = { | |
1199 | .power_on_slot = hpc_power_on_slot, | |
1200 | .power_off_slot = hpc_power_off_slot, | |
1201 | .set_attention_status = hpc_set_attention_status, | |
1202 | .get_power_status = hpc_get_power_status, | |
1203 | .get_attention_status = hpc_get_attention_status, | |
1204 | .get_latch_status = hpc_get_latch_status, | |
1205 | .get_adapter_status = hpc_get_adapter_status, | |
1206 | ||
1207 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
1208 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
1209 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
1210 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
1211 | ||
1212 | .query_power_fault = hpc_query_power_fault, | |
1213 | .green_led_on = hpc_set_green_led_on, | |
1214 | .green_led_off = hpc_set_green_led_off, | |
1215 | .green_led_blink = hpc_set_green_led_blink, | |
1216 | ||
1217 | .release_ctlr = hpc_release_ctlr, | |
1218 | .check_lnk_status = hpc_check_lnk_status, | |
1219 | }; | |
1220 | ||
ed6cbcf2 | 1221 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1da177e4 LT |
1222 | { |
1223 | struct php_ctlr_state_s *php_ctlr, *p; | |
1224 | void *instance_id = ctrl; | |
1225 | int rc; | |
1226 | static int first = 1; | |
1227 | u16 temp_word; | |
1228 | u16 cap_reg; | |
1229 | u16 intr_enable = 0; | |
1230 | u32 slot_cap; | |
1231 | int cap_base, saved_cap_base; | |
1232 | u16 slot_status, slot_ctrl; | |
1233 | struct pci_dev *pdev; | |
1234 | ||
1235 | DBG_ENTER_ROUTINE | |
1236 | ||
1237 | spin_lock_init(&list_lock); | |
1238 | php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL); | |
1239 | ||
1240 | if (!php_ctlr) { /* allocate controller state data */ | |
1241 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | |
1242 | goto abort; | |
1243 | } | |
1244 | ||
1245 | memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s)); | |
1246 | ||
1247 | pdev = dev->port; | |
1248 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ | |
1249 | ||
1a9ed1bf | 1250 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
1251 | __FUNCTION__, pdev->vendor, pdev->device); | |
1da177e4 LT |
1252 | |
1253 | saved_cap_base = pcie_cap_base; | |
1254 | ||
1255 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { | |
1256 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); | |
1257 | goto abort_free_ctlr; | |
1258 | } | |
1259 | ||
8b245e45 | 1260 | ctrl->cap_base = cap_base; |
1da177e4 LT |
1261 | |
1262 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base); | |
1263 | ||
8b245e45 | 1264 | rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 LT |
1265 | if (rc) { |
1266 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1267 | goto abort_free_ctlr; | |
1268 | } | |
8b245e45 | 1269 | dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 | 1270 | |
8b245e45 DS |
1271 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) |
1272 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | |
1da177e4 LT |
1273 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); |
1274 | goto abort_free_ctlr; | |
1275 | } | |
1276 | ||
8b245e45 | 1277 | rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1278 | if (rc) { |
1279 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1280 | goto abort_free_ctlr; | |
1281 | } | |
8b245e45 | 1282 | dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1283 | |
1284 | if (!(slot_cap & HP_CAP)) { | |
1285 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); | |
1286 | goto abort_free_ctlr; | |
1287 | } | |
1288 | /* For debugging purpose */ | |
8b245e45 | 1289 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1290 | if (rc) { |
1291 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1292 | goto abort_free_ctlr; | |
1293 | } | |
8b245e45 | 1294 | dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 | 1295 | |
8b245e45 | 1296 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1297 | if (rc) { |
1298 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1299 | goto abort_free_ctlr; | |
1300 | } | |
8b245e45 | 1301 | dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1302 | |
1303 | if (first) { | |
1304 | spin_lock_init(&hpc_event_lock); | |
1305 | first = 0; | |
1306 | } | |
1307 | ||
1da177e4 LT |
1308 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1309 | if (pci_resource_len(pdev, rc) > 0) | |
1310 | dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc, | |
1311 | pci_resource_start(pdev, rc), pci_resource_len(pdev, rc)); | |
1312 | ||
1313 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, | |
1314 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1315 | ||
1316 | if (pci_enable_device(pdev)) | |
1317 | goto abort_free_ctlr; | |
1318 | ||
1319 | init_MUTEX(&ctrl->crit_sect); | |
1320 | /* setup wait queue */ | |
1321 | init_waitqueue_head(&ctrl->queue); | |
1322 | ||
1323 | /* find the IRQ */ | |
1324 | php_ctlr->irq = dev->irq; | |
1da177e4 LT |
1325 | |
1326 | /* Save interrupt callback info */ | |
ed6cbcf2 | 1327 | php_ctlr->attention_button_callback = pciehp_handle_attention_button; |
1328 | php_ctlr->switch_change_callback = pciehp_handle_switch_change; | |
1329 | php_ctlr->presence_change_callback = pciehp_handle_presence_change; | |
1330 | php_ctlr->power_fault_callback = pciehp_handle_power_fault; | |
1da177e4 LT |
1331 | php_ctlr->callback_instance_id = instance_id; |
1332 | ||
1333 | /* return PCI Controller Info */ | |
1334 | php_ctlr->slot_device_offset = 0; | |
1335 | php_ctlr->num_slots = 1; | |
1336 | ||
1337 | /* Mask Hot-plug Interrupt Enable */ | |
8b245e45 | 1338 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1339 | if (rc) { |
1340 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1341 | goto abort_free_ctlr; | |
1342 | } | |
1343 | ||
8b245e45 | 1344 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1345 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
1346 | ||
8b245e45 | 1347 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1348 | if (rc) { |
1349 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
1350 | goto abort_free_ctlr; | |
1351 | } | |
1da177e4 | 1352 | |
8b245e45 | 1353 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1354 | if (rc) { |
1355 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1356 | goto abort_free_ctlr; | |
1357 | } | |
1da177e4 LT |
1358 | |
1359 | temp_word = 0x1F; /* Clear all events */ | |
8b245e45 | 1360 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1361 | if (rc) { |
1362 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
1363 | goto abort_free_ctlr; | |
1364 | } | |
1da177e4 LT |
1365 | |
1366 | if (pciehp_poll_mode) {/* Install interrupt polling code */ | |
1367 | /* Install and start the interrupt polling timer */ | |
1368 | init_timer(&php_ctlr->int_poll_timer); | |
1369 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | |
1370 | } else { | |
1371 | /* Installs the interrupt handler */ | |
1372 | rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); | |
1373 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); | |
1374 | if (rc) { | |
1375 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | |
1376 | goto abort_free_ctlr; | |
1377 | } | |
1378 | } | |
1379 | ||
1a9ed1bf | 1380 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
1381 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | |
1382 | ||
8b245e45 | 1383 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1384 | if (rc) { |
1385 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1386 | goto abort_free_ctlr; | |
1387 | } | |
1da177e4 LT |
1388 | |
1389 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; | |
1390 | ||
1391 | if (ATTN_BUTTN(slot_cap)) | |
1392 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; | |
1393 | ||
1394 | if (POWER_CTRL(slot_cap)) | |
1395 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; | |
1396 | ||
1397 | if (MRL_SENS(slot_cap)) | |
1398 | intr_enable = intr_enable | MRL_DETECT_ENABLE; | |
1399 | ||
1400 | temp_word = (temp_word & ~intr_enable) | intr_enable; | |
1401 | ||
1402 | if (pciehp_poll_mode) { | |
1403 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; | |
1404 | } else { | |
1405 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | |
1406 | } | |
1da177e4 LT |
1407 | |
1408 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ | |
8b245e45 | 1409 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1410 | if (rc) { |
1411 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
1412 | goto abort_free_ctlr; | |
1413 | } | |
8b245e45 | 1414 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1415 | if (rc) { |
1416 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1417 | goto abort_free_ctlr; | |
1418 | } | |
1da177e4 LT |
1419 | |
1420 | temp_word = 0x1F; /* Clear all events */ | |
8b245e45 | 1421 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1422 | if (rc) { |
1423 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
1424 | goto abort_free_ctlr; | |
1425 | } | |
1da177e4 | 1426 | |
a3a45ec8 | 1427 | if (pciehp_force) { |
1428 | dbg("Bypassing BIOS check for pciehp use on %s\n", | |
1429 | pci_name(ctrl->pci_dev)); | |
1430 | } else { | |
6560aa5c | 1431 | rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); |
a3a45ec8 | 1432 | if (rc) |
1433 | goto abort_free_ctlr; | |
1434 | } | |
a8a2be94 | 1435 | |
1da177e4 LT |
1436 | /* Add this HPC instance into the HPC list */ |
1437 | spin_lock(&list_lock); | |
1438 | if (php_ctlr_list_head == 0) { | |
1439 | php_ctlr_list_head = php_ctlr; | |
1440 | p = php_ctlr_list_head; | |
1441 | p->pnext = NULL; | |
1442 | } else { | |
1443 | p = php_ctlr_list_head; | |
1444 | ||
1445 | while (p->pnext) | |
1446 | p = p->pnext; | |
1447 | ||
1448 | p->pnext = php_ctlr; | |
1449 | } | |
1450 | spin_unlock(&list_lock); | |
1451 | ||
1452 | ctlr_seq_num++; | |
1453 | ctrl->hpc_ctlr_handle = php_ctlr; | |
1454 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
1455 | ||
1456 | DBG_LEAVE_ROUTINE | |
1457 | return 0; | |
1458 | ||
1459 | /* We end up here for the many possible ways to fail this API. */ | |
1460 | abort_free_ctlr: | |
1461 | pcie_cap_base = saved_cap_base; | |
1462 | kfree(php_ctlr); | |
1463 | abort: | |
1464 | DBG_LEAVE_ROUTINE | |
1465 | return -1; | |
1466 | } |