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736759ef | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
1da177e4 LT |
2 | /* |
3 | * PCI Express Hot Plug Controller Driver | |
4 | * | |
5 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
6 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
7 | * Copyright (C) 2001 IBM Corp. | |
8 | * Copyright (C) 2003-2004 Intel Corporation | |
9 | * | |
10 | * All rights reserved. | |
11 | * | |
8cf4c195 | 12 | * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com> |
1da177e4 LT |
13 | * |
14 | */ | |
15 | #ifndef _PCIEHP_H | |
16 | #define _PCIEHP_H | |
17 | ||
18 | #include <linux/types.h> | |
19 | #include <linux/pci.h> | |
7a54f25c | 20 | #include <linux/pci_hotplug.h> |
1da177e4 | 21 | #include <linux/delay.h> |
6aa4cdd0 | 22 | #include <linux/mutex.h> |
5b3f7b7d | 23 | #include <linux/rwsem.h> |
a827ea30 | 24 | #include <linux/workqueue.h> |
1da177e4 | 25 | |
ef794260 | 26 | #include "../pcie/portdrv.h" |
c37e627f | 27 | |
90ab5ee9 | 28 | extern bool pciehp_poll_mode; |
1da177e4 | 29 | extern int pciehp_poll_time; |
1da177e4 | 30 | |
01712472 FL |
31 | /* |
32 | * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to | |
33 | * enable debug messages. | |
34 | */ | |
7f2feec1 | 35 | #define ctrl_dbg(ctrl, format, arg...) \ |
94dbc956 | 36 | pci_dbg(ctrl->pcie->port, format, ## arg) |
7f2feec1 | 37 | #define ctrl_err(ctrl, format, arg...) \ |
94dbc956 | 38 | pci_err(ctrl->pcie->port, format, ## arg) |
7f2feec1 | 39 | #define ctrl_info(ctrl, format, arg...) \ |
94dbc956 | 40 | pci_info(ctrl->pcie->port, format, ## arg) |
7f2feec1 | 41 | #define ctrl_warn(ctrl, format, arg...) \ |
94dbc956 | 42 | pci_warn(ctrl->pcie->port, format, ## arg) |
7f2feec1 | 43 | |
a0b17257 | 44 | #define SLOT_NAME_SIZE 10 |
4aed1cd6 | 45 | |
4aed1cd6 LW |
46 | /** |
47 | * struct controller - PCIe hotplug controller | |
4aed1cd6 | 48 | * @pcie: pointer to the controller's PCIe port service device |
4aed1cd6 | 49 | * @slot_cap: cached copy of the Slot Capabilities register |
347269c1 KW |
50 | * @inband_presence_disabled: In-Band Presence Detect Disable supported by |
51 | * controller and disabled per spec recommendation (PCIe r5.0, appendix I | |
52 | * implementation note) | |
4aed1cd6 | 53 | * @slot_ctrl: cached copy of the Slot Control register |
d7587142 | 54 | * @ctrl_lock: serializes writes to the Slot Control register |
4aed1cd6 LW |
55 | * @cmd_started: jiffies when the Slot Control register was last written; |
56 | * the next write is allowed 1 second later, absent a Command Completed | |
57 | * interrupt (PCIe r4.0, sec 6.7.3.2) | |
58 | * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler | |
59 | * on reception of a Command Completed event | |
d7587142 LW |
60 | * @queue: wait queue to wake up on reception of a Command Completed event, |
61 | * used for synchronous writes to the Slot Control register | |
62 | * @pending_events: used by the IRQ handler to save events retrieved from the | |
63 | * Slot Status register for later consumption by the IRQ thread | |
4aed1cd6 LW |
64 | * @notification_enabled: whether the IRQ was requested successfully |
65 | * @power_fault_detected: whether a power fault was detected by the hardware | |
66 | * that has not yet been cleared by the user | |
d7587142 LW |
67 | * @poll_thread: thread to poll for slot events if no IRQ is available, |
68 | * enabled with pciehp_poll_mode module parameter | |
5790a9c7 | 69 | * @state: current state machine position |
4ff3126e LW |
70 | * @state_lock: protects reads and writes of @state; |
71 | * protects scheduling, execution and cancellation of @button_work | |
72 | * @button_work: work item to turn the slot on or off after 5 seconds | |
5790a9c7 | 73 | * in response to an Attention Button press |
125450f8 | 74 | * @hotplug_slot: structure registered with the PCI hotplug core |
d7587142 LW |
75 | * @reset_lock: prevents access to the Data Link Layer Link Active bit in the |
76 | * Link Status register and to the Presence Detect State bit in the Slot | |
77 | * Status register during a slot reset which may cause them to flap | |
085a9f43 HG |
78 | * @depth: Number of additional hotplug ports in the path to the root bus, |
79 | * used as lock subclass for @reset_lock | |
157c1062 | 80 | * @ist_running: flag to keep user request waiting while IRQ thread is running |
32a8cef2 LW |
81 | * @request_result: result of last user request submitted to the IRQ thread |
82 | * @requester: wait queue to wake up on completion of user request, | |
83 | * used for synchronous slot enable/disable request via sysfs | |
5790a9c7 LW |
84 | * |
85 | * PCIe hotplug has a 1:1 relationship between controller and slot, hence | |
86 | * unlike other drivers, the two aren't represented by separate structures. | |
4aed1cd6 | 87 | */ |
1da177e4 | 88 | struct controller { |
4aed1cd6 | 89 | struct pcie_device *pcie; |
d7587142 LW |
90 | |
91 | u32 slot_cap; /* capabilities and quirks */ | |
20285359 | 92 | unsigned int inband_presence_disabled:1; |
d7587142 LW |
93 | |
94 | u16 slot_ctrl; /* control register access */ | |
95 | struct mutex ctrl_lock; | |
96 | unsigned long cmd_started; | |
97 | unsigned int cmd_busy:1; | |
98 | wait_queue_head_t queue; | |
99 | ||
100 | atomic_t pending_events; /* event handling */ | |
dbc7e1e5 | 101 | unsigned int notification_enabled:1; |
99f0169c | 102 | unsigned int power_fault_detected; |
d7587142 LW |
103 | struct task_struct *poll_thread; |
104 | ||
105 | u8 state; /* state machine */ | |
4ff3126e LW |
106 | struct mutex state_lock; |
107 | struct delayed_work button_work; | |
d7587142 | 108 | |
125450f8 | 109 | struct hotplug_slot hotplug_slot; /* hotplug core interface */ |
d7587142 | 110 | struct rw_semaphore reset_lock; |
085a9f43 | 111 | unsigned int depth; |
157c1062 | 112 | unsigned int ist_running; |
32a8cef2 LW |
113 | int request_result; |
114 | wait_queue_head_t requester; | |
1da177e4 LT |
115 | }; |
116 | ||
9590192f LW |
117 | /** |
118 | * DOC: Slot state | |
119 | * | |
120 | * @OFF_STATE: slot is powered off, no subordinate devices are enumerated | |
121 | * @BLINKINGON_STATE: slot will be powered on after the 5 second delay, | |
4a06c2c3 | 122 | * Power Indicator is blinking |
9590192f | 123 | * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay, |
4a06c2c3 | 124 | * Power Indicator is blinking |
9590192f LW |
125 | * @POWERON_STATE: slot is currently powering on |
126 | * @POWEROFF_STATE: slot is currently powering off | |
127 | * @ON_STATE: slot is powered on, subordinate devices have been enumerated | |
128 | */ | |
129 | #define OFF_STATE 0 | |
1da177e4 LT |
130 | #define BLINKINGON_STATE 1 |
131 | #define BLINKINGOFF_STATE 2 | |
132 | #define POWERON_STATE 3 | |
133 | #define POWEROFF_STATE 4 | |
9590192f | 134 | #define ON_STATE 5 |
1da177e4 | 135 | |
32a8cef2 LW |
136 | /** |
137 | * DOC: Flags to request an action from the IRQ thread | |
138 | * | |
139 | * These are stored together with events read from the Slot Status register, | |
140 | * hence must be greater than its 16-bit width. | |
141 | * | |
142 | * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or | |
143 | * an Attention Button press after the 5 second delay | |
6b08c385 LW |
144 | * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the |
145 | * hotplug port was inaccessible when the interrupt occurred, requiring | |
146 | * that the IRQ handler is rerun by the IRQ thread after it has made the | |
147 | * hotplug port accessible by runtime resuming its parents to D0 | |
32a8cef2 LW |
148 | */ |
149 | #define DISABLE_SLOT (1 << 16) | |
6b08c385 | 150 | #define RERUN_ISR (1 << 17) |
32a8cef2 | 151 | |
656927b1 KK |
152 | #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP) |
153 | #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP) | |
154 | #define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP) | |
155 | #define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP) | |
156 | #define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP) | |
656927b1 | 157 | #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS) |
17f830bb | 158 | #define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19) |
1da177e4 | 159 | |
32a8cef2 | 160 | void pciehp_request(struct controller *ctrl, int action); |
5790a9c7 LW |
161 | void pciehp_handle_button_press(struct controller *ctrl); |
162 | void pciehp_handle_disable_request(struct controller *ctrl); | |
163 | void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events); | |
164 | int pciehp_configure_device(struct controller *ctrl); | |
165 | void pciehp_unconfigure_device(struct controller *ctrl, bool presence); | |
f39d5b72 | 166 | void pciehp_queue_pushbutton_work(struct work_struct *work); |
c4635eb0 | 167 | struct controller *pcie_init(struct pcie_device *dev); |
dbc7e1e5 | 168 | int pcie_init_notification(struct controller *ctrl); |
281e878e | 169 | void pcie_shutdown_notification(struct controller *ctrl); |
79037824 | 170 | void pcie_clear_hotplug_events(struct controller *ctrl); |
eb34da60 MW |
171 | void pcie_enable_interrupt(struct controller *ctrl); |
172 | void pcie_disable_interrupt(struct controller *ctrl); | |
5790a9c7 LW |
173 | int pciehp_power_on_slot(struct controller *ctrl); |
174 | void pciehp_power_off_slot(struct controller *ctrl); | |
175 | void pciehp_get_power_status(struct controller *ctrl, u8 *status); | |
176 | ||
688033f5 DE |
177 | #define INDICATOR_NOOP -1 /* Leave indicator unchanged */ |
178 | void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn); | |
179 | ||
5790a9c7 LW |
180 | void pciehp_get_latch_status(struct controller *ctrl, u8 *status); |
181 | int pciehp_query_power_fault(struct controller *ctrl); | |
87d0f2a5 MW |
182 | int pciehp_card_present(struct controller *ctrl); |
183 | int pciehp_card_present_or_link_active(struct controller *ctrl); | |
82a9e79e | 184 | int pciehp_check_link_status(struct controller *ctrl); |
87d0f2a5 | 185 | int pciehp_check_link_active(struct controller *ctrl); |
82a9e79e | 186 | void pciehp_release_ctrl(struct controller *ctrl); |
1da177e4 | 187 | |
eee6e273 LW |
188 | int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot); |
189 | int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot); | |
9bdc81ce | 190 | int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe); |
eee6e273 | 191 | int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status); |
576243b3 KB |
192 | int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status); |
193 | int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status); | |
194 | ||
ea401499 LW |
195 | int pciehp_slot_reset(struct pcie_device *dev); |
196 | ||
5790a9c7 | 197 | static inline const char *slot_name(struct controller *ctrl) |
e1acb24f | 198 | { |
125450f8 LW |
199 | return hotplug_slot_name(&ctrl->hotplug_slot); |
200 | } | |
201 | ||
202 | static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot) | |
203 | { | |
204 | return container_of(hotplug_slot, struct controller, hotplug_slot); | |
e1acb24f AC |
205 | } |
206 | ||
1da177e4 | 207 | #endif /* _PCIEHP_H */ |