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c25da477 PE |
1 | /* |
2 | * PCIe driver for Renesas R-Car SoCs | |
3 | * Copyright (C) 2014 Renesas Electronics Europe Ltd | |
4 | * | |
5 | * Based on: | |
6 | * arch/sh/drivers/pci/pcie-sh7786.c | |
7 | * arch/sh/drivers/pci/ops-sh7786.c | |
8 | * Copyright (C) 2009 - 2011 Paul Mundt | |
9 | * | |
42d10719 PG |
10 | * Author: Phil Edworthy <phil.edworthy@renesas.com> |
11 | * | |
c25da477 PE |
12 | * This file is licensed under the terms of the GNU General Public |
13 | * License version 2. This program is licensed "as is" without any | |
14 | * warranty of any kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/interrupt.h> | |
290c1fb3 PE |
20 | #include <linux/irq.h> |
21 | #include <linux/irqdomain.h> | |
c25da477 | 22 | #include <linux/kernel.h> |
42d10719 | 23 | #include <linux/init.h> |
290c1fb3 | 24 | #include <linux/msi.h> |
c25da477 PE |
25 | #include <linux/of_address.h> |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/platform_device.h> | |
de1be9a8 | 31 | #include <linux/pm_runtime.h> |
c25da477 PE |
32 | #include <linux/slab.h> |
33 | ||
c25da477 PE |
34 | #define PCIECAR 0x000010 |
35 | #define PCIECCTLR 0x000018 | |
36 | #define CONFIG_SEND_ENABLE (1 << 31) | |
37 | #define TYPE0 (0 << 8) | |
38 | #define TYPE1 (1 << 8) | |
39 | #define PCIECDR 0x000020 | |
40 | #define PCIEMSR 0x000028 | |
41 | #define PCIEINTXR 0x000400 | |
290c1fb3 | 42 | #define PCIEMSITXR 0x000840 |
c25da477 PE |
43 | |
44 | /* Transfer control */ | |
45 | #define PCIETCTLR 0x02000 | |
46 | #define CFINIT 1 | |
47 | #define PCIETSTR 0x02004 | |
48 | #define DATA_LINK_ACTIVE 1 | |
49 | #define PCIEERRFR 0x02020 | |
50 | #define UNSUPPORTED_REQUEST (1 << 4) | |
290c1fb3 PE |
51 | #define PCIEMSIFR 0x02044 |
52 | #define PCIEMSIALR 0x02048 | |
53 | #define MSIFE 1 | |
54 | #define PCIEMSIAUR 0x0204c | |
55 | #define PCIEMSIIER 0x02050 | |
c25da477 PE |
56 | |
57 | /* root port address */ | |
58 | #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) | |
59 | ||
60 | /* local address reg & mask */ | |
61 | #define PCIELAR(x) (0x02200 + ((x) * 0x20)) | |
62 | #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) | |
63 | #define LAM_PREFETCH (1 << 3) | |
64 | #define LAM_64BIT (1 << 2) | |
65 | #define LAR_ENABLE (1 << 1) | |
66 | ||
67 | /* PCIe address reg & mask */ | |
ecd06305 NI |
68 | #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) |
69 | #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) | |
c25da477 PE |
70 | #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) |
71 | #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) | |
72 | #define PAR_ENABLE (1 << 31) | |
73 | #define IO_SPACE (1 << 8) | |
74 | ||
75 | /* Configuration */ | |
76 | #define PCICONF(x) (0x010000 + ((x) * 0x4)) | |
77 | #define PMCAP(x) (0x010040 + ((x) * 0x4)) | |
78 | #define EXPCAP(x) (0x010070 + ((x) * 0x4)) | |
79 | #define VCCAP(x) (0x010100 + ((x) * 0x4)) | |
80 | ||
81 | /* link layer */ | |
82 | #define IDSETR1 0x011004 | |
83 | #define TLCTLR 0x011048 | |
84 | #define MACSR 0x011054 | |
b3327f7f SS |
85 | #define SPCHGFIN (1 << 4) |
86 | #define SPCHGFAIL (1 << 6) | |
87 | #define SPCHGSUC (1 << 7) | |
88 | #define LINK_SPEED (0xf << 16) | |
89 | #define LINK_SPEED_2_5GTS (1 << 16) | |
90 | #define LINK_SPEED_5_0GTS (2 << 16) | |
c25da477 | 91 | #define MACCTLR 0x011058 |
b3327f7f | 92 | #define SPEED_CHANGE (1 << 24) |
c25da477 | 93 | #define SCRAMBLE_DISABLE (1 << 27) |
b3327f7f SS |
94 | #define MACS2R 0x011078 |
95 | #define MACCGSPSETR 0x011084 | |
96 | #define SPCNGRSN (1 << 31) | |
c25da477 PE |
97 | |
98 | /* R-Car H1 PHY */ | |
99 | #define H1_PCIEPHYADRR 0x04000c | |
100 | #define WRITE_CMD (1 << 16) | |
101 | #define PHY_ACK (1 << 24) | |
102 | #define RATE_POS 12 | |
103 | #define LANE_POS 8 | |
104 | #define ADR_POS 0 | |
105 | #define H1_PCIEPHYDOUTR 0x040014 | |
106 | #define H1_PCIEPHYSR 0x040018 | |
107 | ||
581d9434 PE |
108 | /* R-Car Gen2 PHY */ |
109 | #define GEN2_PCIEPHYADDR 0x780 | |
110 | #define GEN2_PCIEPHYDATA 0x784 | |
111 | #define GEN2_PCIEPHYCTRL 0x78c | |
112 | ||
290c1fb3 PE |
113 | #define INT_PCI_MSI_NR 32 |
114 | ||
c25da477 PE |
115 | #define RCONF(x) (PCICONF(0)+(x)) |
116 | #define RPMCAP(x) (PMCAP(0)+(x)) | |
117 | #define REXPCAP(x) (EXPCAP(0)+(x)) | |
118 | #define RVCCAP(x) (VCCAP(0)+(x)) | |
119 | ||
120 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) | |
121 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) | |
122 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) | |
123 | ||
b7718849 | 124 | #define RCAR_PCI_MAX_RESOURCES 4 |
c25da477 PE |
125 | #define MAX_NR_INBOUND_MAPS 6 |
126 | ||
290c1fb3 PE |
127 | struct rcar_msi { |
128 | DECLARE_BITMAP(used, INT_PCI_MSI_NR); | |
129 | struct irq_domain *domain; | |
c2791b80 | 130 | struct msi_controller chip; |
290c1fb3 PE |
131 | unsigned long pages; |
132 | struct mutex lock; | |
133 | int irq1; | |
134 | int irq2; | |
135 | }; | |
136 | ||
c2791b80 | 137 | static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip) |
290c1fb3 PE |
138 | { |
139 | return container_of(chip, struct rcar_msi, chip); | |
140 | } | |
141 | ||
c25da477 PE |
142 | /* Structure representing the PCIe interface */ |
143 | struct rcar_pcie { | |
144 | struct device *dev; | |
145 | void __iomem *base; | |
5d2917d4 | 146 | struct list_head resources; |
c25da477 PE |
147 | int root_bus_nr; |
148 | struct clk *clk; | |
149 | struct clk *bus_clk; | |
290c1fb3 | 150 | struct rcar_msi msi; |
c25da477 PE |
151 | }; |
152 | ||
b7718849 PE |
153 | static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val, |
154 | unsigned long reg) | |
c25da477 PE |
155 | { |
156 | writel(val, pcie->base + reg); | |
157 | } | |
158 | ||
b7718849 PE |
159 | static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie, |
160 | unsigned long reg) | |
c25da477 PE |
161 | { |
162 | return readl(pcie->base + reg); | |
163 | } | |
164 | ||
165 | enum { | |
b7718849 PE |
166 | RCAR_PCI_ACCESS_READ, |
167 | RCAR_PCI_ACCESS_WRITE, | |
c25da477 PE |
168 | }; |
169 | ||
170 | static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) | |
171 | { | |
172 | int shift = 8 * (where & 3); | |
b7718849 | 173 | u32 val = rcar_pci_read_reg(pcie, where & ~3); |
c25da477 PE |
174 | |
175 | val &= ~(mask << shift); | |
176 | val |= data << shift; | |
b7718849 | 177 | rcar_pci_write_reg(pcie, val, where & ~3); |
c25da477 PE |
178 | } |
179 | ||
180 | static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) | |
181 | { | |
182 | int shift = 8 * (where & 3); | |
b7718849 | 183 | u32 val = rcar_pci_read_reg(pcie, where & ~3); |
c25da477 PE |
184 | |
185 | return val >> shift; | |
186 | } | |
187 | ||
188 | /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ | |
189 | static int rcar_pcie_config_access(struct rcar_pcie *pcie, | |
190 | unsigned char access_type, struct pci_bus *bus, | |
191 | unsigned int devfn, int where, u32 *data) | |
192 | { | |
193 | int dev, func, reg, index; | |
194 | ||
195 | dev = PCI_SLOT(devfn); | |
196 | func = PCI_FUNC(devfn); | |
197 | reg = where & ~3; | |
198 | index = reg / 4; | |
199 | ||
200 | /* | |
201 | * While each channel has its own memory-mapped extended config | |
202 | * space, it's generally only accessible when in endpoint mode. | |
203 | * When in root complex mode, the controller is unable to target | |
204 | * itself with either type 0 or type 1 accesses, and indeed, any | |
205 | * controller initiated target transfer to its own config space | |
206 | * result in a completer abort. | |
207 | * | |
208 | * Each channel effectively only supports a single device, but as | |
209 | * the same channel <-> device access works for any PCI_SLOT() | |
210 | * value, we cheat a bit here and bind the controller's config | |
211 | * space to devfn 0 in order to enable self-enumeration. In this | |
212 | * case the regular ECAR/ECDR path is sidelined and the mangled | |
213 | * config access itself is initiated as an internal bus transaction. | |
214 | */ | |
215 | if (pci_is_root_bus(bus)) { | |
216 | if (dev != 0) | |
217 | return PCIBIOS_DEVICE_NOT_FOUND; | |
218 | ||
b7718849 PE |
219 | if (access_type == RCAR_PCI_ACCESS_READ) { |
220 | *data = rcar_pci_read_reg(pcie, PCICONF(index)); | |
c25da477 PE |
221 | } else { |
222 | /* Keep an eye out for changes to the root bus number */ | |
223 | if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) | |
224 | pcie->root_bus_nr = *data & 0xff; | |
225 | ||
b7718849 | 226 | rcar_pci_write_reg(pcie, *data, PCICONF(index)); |
c25da477 PE |
227 | } |
228 | ||
229 | return PCIBIOS_SUCCESSFUL; | |
230 | } | |
231 | ||
232 | if (pcie->root_bus_nr < 0) | |
233 | return PCIBIOS_DEVICE_NOT_FOUND; | |
234 | ||
235 | /* Clear errors */ | |
b7718849 | 236 | rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); |
c25da477 PE |
237 | |
238 | /* Set the PIO address */ | |
b7718849 PE |
239 | rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | |
240 | PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); | |
c25da477 PE |
241 | |
242 | /* Enable the configuration access */ | |
243 | if (bus->parent->number == pcie->root_bus_nr) | |
b7718849 | 244 | rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); |
c25da477 | 245 | else |
b7718849 | 246 | rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); |
c25da477 PE |
247 | |
248 | /* Check for errors */ | |
b7718849 | 249 | if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) |
c25da477 PE |
250 | return PCIBIOS_DEVICE_NOT_FOUND; |
251 | ||
252 | /* Check for master and target aborts */ | |
253 | if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & | |
254 | (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) | |
255 | return PCIBIOS_DEVICE_NOT_FOUND; | |
256 | ||
b7718849 PE |
257 | if (access_type == RCAR_PCI_ACCESS_READ) |
258 | *data = rcar_pci_read_reg(pcie, PCIECDR); | |
c25da477 | 259 | else |
b7718849 | 260 | rcar_pci_write_reg(pcie, *data, PCIECDR); |
c25da477 PE |
261 | |
262 | /* Disable the configuration access */ | |
b7718849 | 263 | rcar_pci_write_reg(pcie, 0, PCIECCTLR); |
c25da477 PE |
264 | |
265 | return PCIBIOS_SUCCESSFUL; | |
266 | } | |
267 | ||
268 | static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, | |
269 | int where, int size, u32 *val) | |
270 | { | |
79953dd2 | 271 | struct rcar_pcie *pcie = bus->sysdata; |
c25da477 PE |
272 | int ret; |
273 | ||
b7718849 | 274 | ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, |
c25da477 PE |
275 | bus, devfn, where, val); |
276 | if (ret != PCIBIOS_SUCCESSFUL) { | |
277 | *val = 0xffffffff; | |
278 | return ret; | |
279 | } | |
280 | ||
281 | if (size == 1) | |
282 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
283 | else if (size == 2) | |
284 | *val = (*val >> (8 * (where & 2))) & 0xffff; | |
285 | ||
227f0647 RD |
286 | dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", |
287 | bus->number, devfn, where, size, (unsigned long)*val); | |
c25da477 PE |
288 | |
289 | return ret; | |
290 | } | |
291 | ||
292 | /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ | |
293 | static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, | |
294 | int where, int size, u32 val) | |
295 | { | |
79953dd2 | 296 | struct rcar_pcie *pcie = bus->sysdata; |
c25da477 PE |
297 | int shift, ret; |
298 | u32 data; | |
299 | ||
b7718849 | 300 | ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ, |
c25da477 PE |
301 | bus, devfn, where, &data); |
302 | if (ret != PCIBIOS_SUCCESSFUL) | |
303 | return ret; | |
304 | ||
227f0647 RD |
305 | dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n", |
306 | bus->number, devfn, where, size, (unsigned long)val); | |
c25da477 PE |
307 | |
308 | if (size == 1) { | |
309 | shift = 8 * (where & 3); | |
310 | data &= ~(0xff << shift); | |
311 | data |= ((val & 0xff) << shift); | |
312 | } else if (size == 2) { | |
313 | shift = 8 * (where & 2); | |
314 | data &= ~(0xffff << shift); | |
315 | data |= ((val & 0xffff) << shift); | |
316 | } else | |
317 | data = val; | |
318 | ||
b7718849 | 319 | ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE, |
c25da477 PE |
320 | bus, devfn, where, &data); |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static struct pci_ops rcar_pcie_ops = { | |
326 | .read = rcar_pcie_read_conf, | |
327 | .write = rcar_pcie_write_conf, | |
328 | }; | |
329 | ||
5d2917d4 PE |
330 | static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie, |
331 | struct resource *res) | |
c25da477 PE |
332 | { |
333 | /* Setup PCIe address space mappings for each resource */ | |
334 | resource_size_t size; | |
0b0b0893 | 335 | resource_size_t res_start; |
c25da477 PE |
336 | u32 mask; |
337 | ||
b7718849 | 338 | rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); |
c25da477 PE |
339 | |
340 | /* | |
341 | * The PAMR mask is calculated in units of 128Bytes, which | |
342 | * keeps things pretty simple. | |
343 | */ | |
344 | size = resource_size(res); | |
345 | mask = (roundup_pow_of_two(size) / SZ_128) - 1; | |
b7718849 | 346 | rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); |
c25da477 | 347 | |
0b0b0893 LD |
348 | if (res->flags & IORESOURCE_IO) |
349 | res_start = pci_pio_to_address(res->start); | |
350 | else | |
351 | res_start = res->start; | |
352 | ||
ecd06305 | 353 | rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); |
2ea2a273 | 354 | rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, |
ecd06305 | 355 | PCIEPALR(win)); |
c25da477 PE |
356 | |
357 | /* First resource is for IO */ | |
358 | mask = PAR_ENABLE; | |
359 | if (res->flags & IORESOURCE_IO) | |
360 | mask |= IO_SPACE; | |
361 | ||
b7718849 | 362 | rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); |
c25da477 PE |
363 | } |
364 | ||
5d2917d4 | 365 | static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci) |
c25da477 | 366 | { |
5d2917d4 PE |
367 | struct resource_entry *win; |
368 | int i = 0; | |
c25da477 PE |
369 | |
370 | /* Setup PCI resources */ | |
5d2917d4 PE |
371 | resource_list_for_each_entry(win, &pci->resources) { |
372 | struct resource *res = win->res; | |
c25da477 | 373 | |
c25da477 PE |
374 | if (!res->flags) |
375 | continue; | |
376 | ||
5d2917d4 PE |
377 | switch (resource_type(res)) { |
378 | case IORESOURCE_IO: | |
379 | case IORESOURCE_MEM: | |
380 | rcar_pcie_setup_window(i, pci, res); | |
381 | i++; | |
382 | break; | |
383 | case IORESOURCE_BUS: | |
384 | pci->root_bus_nr = res->start; | |
385 | break; | |
386 | default: | |
387 | continue; | |
d0c3f4db PE |
388 | } |
389 | ||
79953dd2 | 390 | pci_add_resource(resource, res); |
c25da477 | 391 | } |
c25da477 PE |
392 | |
393 | return 1; | |
394 | } | |
395 | ||
b3327f7f SS |
396 | static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) |
397 | { | |
4ef80d72 | 398 | struct device *dev = pcie->dev; |
b3327f7f SS |
399 | unsigned int timeout = 1000; |
400 | u32 macsr; | |
401 | ||
402 | if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) | |
403 | return; | |
404 | ||
405 | if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { | |
4ef80d72 | 406 | dev_err(dev, "Speed change already in progress\n"); |
b3327f7f SS |
407 | return; |
408 | } | |
409 | ||
410 | macsr = rcar_pci_read_reg(pcie, MACSR); | |
411 | if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) | |
412 | goto done; | |
413 | ||
414 | /* Set target link speed to 5.0 GT/s */ | |
415 | rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, | |
416 | PCI_EXP_LNKSTA_CLS_5_0GB); | |
417 | ||
418 | /* Set speed change reason as intentional factor */ | |
419 | rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); | |
420 | ||
421 | /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ | |
422 | if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) | |
423 | rcar_pci_write_reg(pcie, macsr, MACSR); | |
424 | ||
425 | /* Start link speed change */ | |
426 | rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); | |
427 | ||
428 | while (timeout--) { | |
429 | macsr = rcar_pci_read_reg(pcie, MACSR); | |
430 | if (macsr & SPCHGFIN) { | |
431 | /* Clear the interrupt bits */ | |
432 | rcar_pci_write_reg(pcie, macsr, MACSR); | |
433 | ||
434 | if (macsr & SPCHGFAIL) | |
4ef80d72 | 435 | dev_err(dev, "Speed change failed\n"); |
b3327f7f SS |
436 | |
437 | goto done; | |
438 | } | |
439 | ||
440 | msleep(1); | |
441 | }; | |
442 | ||
4ef80d72 | 443 | dev_err(dev, "Speed change timed out\n"); |
b3327f7f SS |
444 | |
445 | done: | |
4ef80d72 | 446 | dev_info(dev, "Current link speed is %s GT/s\n", |
b3327f7f SS |
447 | (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); |
448 | } | |
449 | ||
79953dd2 | 450 | static int rcar_pcie_enable(struct rcar_pcie *pcie) |
c25da477 | 451 | { |
4ef80d72 | 452 | struct device *dev = pcie->dev; |
90634e85 | 453 | struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); |
79953dd2 | 454 | struct pci_bus *bus, *child; |
90634e85 | 455 | int ret; |
c25da477 | 456 | |
b3327f7f SS |
457 | /* Try setting 5 GT/s link speed */ |
458 | rcar_pcie_force_speedup(pcie); | |
459 | ||
90634e85 | 460 | rcar_pcie_setup(&bridge->windows, pcie); |
79953dd2 | 461 | |
3487c656 | 462 | pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); |
79953dd2 | 463 | |
90634e85 LP |
464 | bridge->dev.parent = dev; |
465 | bridge->sysdata = pcie; | |
466 | bridge->busnr = pcie->root_bus_nr; | |
467 | bridge->ops = &rcar_pcie_ops; | |
79953dd2 | 468 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
90634e85 | 469 | bridge->msi = &pcie->msi.chip; |
79953dd2 | 470 | |
90634e85 LP |
471 | ret = pci_scan_root_bus_bridge(bridge); |
472 | if (ret < 0) { | |
473 | kfree(bridge); | |
474 | return ret; | |
79953dd2 PE |
475 | } |
476 | ||
90634e85 LP |
477 | bus = bridge->bus; |
478 | ||
79953dd2 PE |
479 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); |
480 | ||
3487c656 LP |
481 | pci_bus_size_bridges(bus); |
482 | pci_bus_assign_resources(bus); | |
c25da477 | 483 | |
3487c656 LP |
484 | list_for_each_entry(child, &bus->children, node) |
485 | pcie_bus_configure_settings(child); | |
79953dd2 PE |
486 | |
487 | pci_bus_add_devices(bus); | |
488 | ||
489 | return 0; | |
c25da477 PE |
490 | } |
491 | ||
492 | static int phy_wait_for_ack(struct rcar_pcie *pcie) | |
493 | { | |
4ef80d72 | 494 | struct device *dev = pcie->dev; |
c25da477 PE |
495 | unsigned int timeout = 100; |
496 | ||
497 | while (timeout--) { | |
b7718849 | 498 | if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) |
c25da477 PE |
499 | return 0; |
500 | ||
501 | udelay(100); | |
502 | } | |
503 | ||
4ef80d72 | 504 | dev_err(dev, "Access to PCIe phy timed out\n"); |
c25da477 PE |
505 | |
506 | return -ETIMEDOUT; | |
507 | } | |
508 | ||
509 | static void phy_write_reg(struct rcar_pcie *pcie, | |
510 | unsigned int rate, unsigned int addr, | |
511 | unsigned int lane, unsigned int data) | |
512 | { | |
513 | unsigned long phyaddr; | |
514 | ||
515 | phyaddr = WRITE_CMD | | |
516 | ((rate & 1) << RATE_POS) | | |
517 | ((lane & 0xf) << LANE_POS) | | |
518 | ((addr & 0xff) << ADR_POS); | |
519 | ||
520 | /* Set write data */ | |
b7718849 PE |
521 | rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); |
522 | rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); | |
c25da477 PE |
523 | |
524 | /* Ignore errors as they will be dealt with if the data link is down */ | |
525 | phy_wait_for_ack(pcie); | |
526 | ||
527 | /* Clear command */ | |
b7718849 PE |
528 | rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); |
529 | rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); | |
c25da477 PE |
530 | |
531 | /* Ignore errors as they will be dealt with if the data link is down */ | |
532 | phy_wait_for_ack(pcie); | |
533 | } | |
534 | ||
535 | static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie) | |
536 | { | |
537 | unsigned int timeout = 10; | |
538 | ||
539 | while (timeout--) { | |
b7718849 | 540 | if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE)) |
c25da477 PE |
541 | return 0; |
542 | ||
543 | msleep(5); | |
544 | } | |
545 | ||
546 | return -ETIMEDOUT; | |
547 | } | |
548 | ||
549 | static int rcar_pcie_hw_init(struct rcar_pcie *pcie) | |
550 | { | |
551 | int err; | |
552 | ||
553 | /* Begin initialization */ | |
b7718849 | 554 | rcar_pci_write_reg(pcie, 0, PCIETCTLR); |
c25da477 PE |
555 | |
556 | /* Set mode */ | |
b7718849 | 557 | rcar_pci_write_reg(pcie, 1, PCIEMSR); |
c25da477 PE |
558 | |
559 | /* | |
560 | * Initial header for port config space is type 1, set the device | |
561 | * class to match. Hardware takes care of propagating the IDSETR | |
562 | * settings, so there is no need to bother with a quirk. | |
563 | */ | |
b7718849 | 564 | rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1); |
c25da477 PE |
565 | |
566 | /* | |
567 | * Setup Secondary Bus Number & Subordinate Bus Number, even though | |
568 | * they aren't used, to avoid bridge being detected as broken. | |
569 | */ | |
570 | rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); | |
571 | rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); | |
572 | ||
573 | /* Initialize default capabilities. */ | |
2c3fd4c9 | 574 | rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); |
c25da477 PE |
575 | rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), |
576 | PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); | |
577 | rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, | |
578 | PCI_HEADER_TYPE_BRIDGE); | |
579 | ||
580 | /* Enable data link layer active state reporting */ | |
2c3fd4c9 PE |
581 | rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, |
582 | PCI_EXP_LNKCAP_DLLLARC); | |
c25da477 PE |
583 | |
584 | /* Write out the physical slot number = 0 */ | |
585 | rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); | |
586 | ||
587 | /* Set the completion timer timeout to the maximum 50ms. */ | |
b7718849 | 588 | rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); |
c25da477 PE |
589 | |
590 | /* Terminate list of capabilities (Next Capability Offset=0) */ | |
2c3fd4c9 | 591 | rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); |
c25da477 | 592 | |
290c1fb3 PE |
593 | /* Enable MSI */ |
594 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
1fc6aa96 | 595 | rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); |
290c1fb3 | 596 | |
c25da477 | 597 | /* Finish initialization - establish a PCI Express link */ |
b7718849 | 598 | rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); |
c25da477 PE |
599 | |
600 | /* This will timeout if we don't have a link. */ | |
601 | err = rcar_pcie_wait_for_dl(pcie); | |
602 | if (err) | |
603 | return err; | |
604 | ||
605 | /* Enable INTx interrupts */ | |
606 | rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); | |
607 | ||
c25da477 PE |
608 | wmb(); |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie) | |
614 | { | |
615 | unsigned int timeout = 10; | |
616 | ||
617 | /* Initialize the phy */ | |
618 | phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); | |
619 | phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); | |
620 | phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); | |
621 | phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); | |
622 | phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); | |
623 | phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); | |
624 | phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); | |
625 | phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); | |
626 | phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); | |
627 | phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); | |
628 | phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); | |
629 | phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); | |
630 | ||
631 | phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); | |
632 | phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); | |
633 | phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); | |
634 | ||
635 | while (timeout--) { | |
b7718849 | 636 | if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR)) |
c25da477 PE |
637 | return rcar_pcie_hw_init(pcie); |
638 | ||
639 | msleep(5); | |
640 | } | |
641 | ||
642 | return -ETIMEDOUT; | |
643 | } | |
644 | ||
581d9434 PE |
645 | static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie) |
646 | { | |
647 | /* | |
648 | * These settings come from the R-Car Series, 2nd Generation User's | |
649 | * Manual, section 50.3.1 (2) Initialization of the physical layer. | |
650 | */ | |
651 | rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); | |
652 | rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); | |
653 | rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); | |
654 | rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); | |
655 | ||
656 | rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); | |
657 | /* The following value is for DC connection, no termination resistor */ | |
658 | rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); | |
659 | rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); | |
660 | rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); | |
661 | ||
662 | return rcar_pcie_hw_init(pcie); | |
663 | } | |
664 | ||
290c1fb3 PE |
665 | static int rcar_msi_alloc(struct rcar_msi *chip) |
666 | { | |
667 | int msi; | |
668 | ||
669 | mutex_lock(&chip->lock); | |
670 | ||
671 | msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); | |
672 | if (msi < INT_PCI_MSI_NR) | |
673 | set_bit(msi, chip->used); | |
674 | else | |
675 | msi = -ENOSPC; | |
676 | ||
677 | mutex_unlock(&chip->lock); | |
678 | ||
679 | return msi; | |
680 | } | |
681 | ||
e3123c20 GK |
682 | static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs) |
683 | { | |
684 | int msi; | |
685 | ||
686 | mutex_lock(&chip->lock); | |
687 | msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR, | |
688 | order_base_2(no_irqs)); | |
689 | mutex_unlock(&chip->lock); | |
690 | ||
691 | return msi; | |
692 | } | |
693 | ||
290c1fb3 PE |
694 | static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq) |
695 | { | |
696 | mutex_lock(&chip->lock); | |
697 | clear_bit(irq, chip->used); | |
698 | mutex_unlock(&chip->lock); | |
699 | } | |
700 | ||
701 | static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) | |
702 | { | |
703 | struct rcar_pcie *pcie = data; | |
704 | struct rcar_msi *msi = &pcie->msi; | |
4ef80d72 | 705 | struct device *dev = pcie->dev; |
290c1fb3 PE |
706 | unsigned long reg; |
707 | ||
b7718849 | 708 | reg = rcar_pci_read_reg(pcie, PCIEMSIFR); |
290c1fb3 PE |
709 | |
710 | /* MSI & INTx share an interrupt - we only handle MSI here */ | |
711 | if (!reg) | |
712 | return IRQ_NONE; | |
713 | ||
714 | while (reg) { | |
715 | unsigned int index = find_first_bit(®, 32); | |
716 | unsigned int irq; | |
717 | ||
718 | /* clear the interrupt */ | |
b7718849 | 719 | rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR); |
290c1fb3 PE |
720 | |
721 | irq = irq_find_mapping(msi->domain, index); | |
722 | if (irq) { | |
723 | if (test_bit(index, msi->used)) | |
724 | generic_handle_irq(irq); | |
725 | else | |
4ef80d72 | 726 | dev_info(dev, "unhandled MSI\n"); |
290c1fb3 PE |
727 | } else { |
728 | /* Unknown MSI, just clear it */ | |
4ef80d72 | 729 | dev_dbg(dev, "unexpected MSI\n"); |
290c1fb3 PE |
730 | } |
731 | ||
732 | /* see if there's any more pending in this vector */ | |
b7718849 | 733 | reg = rcar_pci_read_reg(pcie, PCIEMSIFR); |
290c1fb3 PE |
734 | } |
735 | ||
736 | return IRQ_HANDLED; | |
737 | } | |
738 | ||
c2791b80 | 739 | static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, |
290c1fb3 PE |
740 | struct msi_desc *desc) |
741 | { | |
742 | struct rcar_msi *msi = to_rcar_msi(chip); | |
743 | struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); | |
744 | struct msi_msg msg; | |
745 | unsigned int irq; | |
746 | int hwirq; | |
747 | ||
748 | hwirq = rcar_msi_alloc(msi); | |
749 | if (hwirq < 0) | |
750 | return hwirq; | |
751 | ||
e3123c20 | 752 | irq = irq_find_mapping(msi->domain, hwirq); |
290c1fb3 PE |
753 | if (!irq) { |
754 | rcar_msi_free(msi, hwirq); | |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | irq_set_msi_desc(irq, desc); | |
759 | ||
b7718849 PE |
760 | msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; |
761 | msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); | |
290c1fb3 PE |
762 | msg.data = hwirq; |
763 | ||
83a18912 | 764 | pci_write_msi_msg(irq, &msg); |
290c1fb3 PE |
765 | |
766 | return 0; | |
767 | } | |
768 | ||
e3123c20 GK |
769 | static int rcar_msi_setup_irqs(struct msi_controller *chip, |
770 | struct pci_dev *pdev, int nvec, int type) | |
771 | { | |
772 | struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip); | |
773 | struct rcar_msi *msi = to_rcar_msi(chip); | |
774 | struct msi_desc *desc; | |
775 | struct msi_msg msg; | |
776 | unsigned int irq; | |
777 | int hwirq; | |
778 | int i; | |
779 | ||
780 | /* MSI-X interrupts are not supported */ | |
781 | if (type == PCI_CAP_ID_MSIX) | |
782 | return -EINVAL; | |
783 | ||
784 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); | |
785 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); | |
786 | ||
787 | hwirq = rcar_msi_alloc_region(msi, nvec); | |
788 | if (hwirq < 0) | |
789 | return -ENOSPC; | |
790 | ||
791 | irq = irq_find_mapping(msi->domain, hwirq); | |
792 | if (!irq) | |
793 | return -ENOSPC; | |
794 | ||
795 | for (i = 0; i < nvec; i++) { | |
796 | /* | |
797 | * irq_create_mapping() called from rcar_pcie_probe() pre- | |
798 | * allocates descs, so there is no need to allocate descs here. | |
799 | * We can therefore assume that if irq_find_mapping() above | |
800 | * returns non-zero, then the descs are also successfully | |
801 | * allocated. | |
802 | */ | |
803 | if (irq_set_msi_desc_off(irq, i, desc)) { | |
804 | /* TODO: clear */ | |
805 | return -EINVAL; | |
806 | } | |
807 | } | |
808 | ||
809 | desc->nvec_used = nvec; | |
810 | desc->msi_attrib.multiple = order_base_2(nvec); | |
811 | ||
812 | msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; | |
813 | msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); | |
814 | msg.data = hwirq; | |
815 | ||
816 | pci_write_msi_msg(irq, &msg); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
c2791b80 | 821 | static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
290c1fb3 PE |
822 | { |
823 | struct rcar_msi *msi = to_rcar_msi(chip); | |
824 | struct irq_data *d = irq_get_irq_data(irq); | |
825 | ||
826 | rcar_msi_free(msi, d->hwirq); | |
827 | } | |
828 | ||
829 | static struct irq_chip rcar_msi_irq_chip = { | |
830 | .name = "R-Car PCIe MSI", | |
280510f1 TG |
831 | .irq_enable = pci_msi_unmask_irq, |
832 | .irq_disable = pci_msi_mask_irq, | |
833 | .irq_mask = pci_msi_mask_irq, | |
834 | .irq_unmask = pci_msi_unmask_irq, | |
290c1fb3 PE |
835 | }; |
836 | ||
837 | static int rcar_msi_map(struct irq_domain *domain, unsigned int irq, | |
838 | irq_hw_number_t hwirq) | |
839 | { | |
840 | irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq); | |
841 | irq_set_chip_data(irq, domain->host_data); | |
290c1fb3 PE |
842 | |
843 | return 0; | |
844 | } | |
845 | ||
846 | static const struct irq_domain_ops msi_domain_ops = { | |
847 | .map = rcar_msi_map, | |
848 | }; | |
849 | ||
850 | static int rcar_pcie_enable_msi(struct rcar_pcie *pcie) | |
851 | { | |
4ef80d72 | 852 | struct device *dev = pcie->dev; |
290c1fb3 PE |
853 | struct rcar_msi *msi = &pcie->msi; |
854 | unsigned long base; | |
e3123c20 | 855 | int err, i; |
290c1fb3 PE |
856 | |
857 | mutex_init(&msi->lock); | |
858 | ||
4ef80d72 | 859 | msi->chip.dev = dev; |
290c1fb3 | 860 | msi->chip.setup_irq = rcar_msi_setup_irq; |
e3123c20 | 861 | msi->chip.setup_irqs = rcar_msi_setup_irqs; |
290c1fb3 PE |
862 | msi->chip.teardown_irq = rcar_msi_teardown_irq; |
863 | ||
4ef80d72 | 864 | msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, |
290c1fb3 PE |
865 | &msi_domain_ops, &msi->chip); |
866 | if (!msi->domain) { | |
4ef80d72 | 867 | dev_err(dev, "failed to create IRQ domain\n"); |
290c1fb3 PE |
868 | return -ENOMEM; |
869 | } | |
870 | ||
e3123c20 GK |
871 | for (i = 0; i < INT_PCI_MSI_NR; i++) |
872 | irq_create_mapping(msi->domain, i); | |
873 | ||
290c1fb3 | 874 | /* Two irqs are for MSI, but they are also used for non-MSI irqs */ |
4ef80d72 | 875 | err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, |
8ff0ef99 GS |
876 | IRQF_SHARED | IRQF_NO_THREAD, |
877 | rcar_msi_irq_chip.name, pcie); | |
290c1fb3 | 878 | if (err < 0) { |
4ef80d72 | 879 | dev_err(dev, "failed to request IRQ: %d\n", err); |
290c1fb3 PE |
880 | goto err; |
881 | } | |
882 | ||
4ef80d72 | 883 | err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, |
8ff0ef99 GS |
884 | IRQF_SHARED | IRQF_NO_THREAD, |
885 | rcar_msi_irq_chip.name, pcie); | |
290c1fb3 | 886 | if (err < 0) { |
4ef80d72 | 887 | dev_err(dev, "failed to request IRQ: %d\n", err); |
290c1fb3 PE |
888 | goto err; |
889 | } | |
890 | ||
891 | /* setup MSI data target */ | |
892 | msi->pages = __get_free_pages(GFP_KERNEL, 0); | |
893 | base = virt_to_phys((void *)msi->pages); | |
894 | ||
b7718849 PE |
895 | rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR); |
896 | rcar_pci_write_reg(pcie, 0, PCIEMSIAUR); | |
290c1fb3 PE |
897 | |
898 | /* enable all MSI interrupts */ | |
b7718849 | 899 | rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER); |
290c1fb3 PE |
900 | |
901 | return 0; | |
902 | ||
903 | err: | |
904 | irq_domain_remove(msi->domain); | |
905 | return err; | |
906 | } | |
907 | ||
d0206f21 | 908 | static int rcar_pcie_get_resources(struct rcar_pcie *pcie) |
c25da477 | 909 | { |
4ef80d72 | 910 | struct device *dev = pcie->dev; |
c25da477 | 911 | struct resource res; |
290c1fb3 | 912 | int err, i; |
c25da477 | 913 | |
4ef80d72 | 914 | err = of_address_to_resource(dev->of_node, 0, &res); |
c25da477 PE |
915 | if (err) |
916 | return err; | |
917 | ||
4ef80d72 | 918 | pcie->base = devm_ioremap_resource(dev, &res); |
51afa3cc BH |
919 | if (IS_ERR(pcie->base)) |
920 | return PTR_ERR(pcie->base); | |
921 | ||
4ef80d72 | 922 | pcie->clk = devm_clk_get(dev, "pcie"); |
c25da477 | 923 | if (IS_ERR(pcie->clk)) { |
4ef80d72 | 924 | dev_err(dev, "cannot get platform clock\n"); |
c25da477 PE |
925 | return PTR_ERR(pcie->clk); |
926 | } | |
927 | err = clk_prepare_enable(pcie->clk); | |
928 | if (err) | |
3d664b07 | 929 | return err; |
c25da477 | 930 | |
4ef80d72 | 931 | pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); |
c25da477 | 932 | if (IS_ERR(pcie->bus_clk)) { |
4ef80d72 | 933 | dev_err(dev, "cannot get pcie bus clock\n"); |
c25da477 PE |
934 | err = PTR_ERR(pcie->bus_clk); |
935 | goto fail_clk; | |
936 | } | |
937 | err = clk_prepare_enable(pcie->bus_clk); | |
938 | if (err) | |
3d664b07 | 939 | goto fail_clk; |
c25da477 | 940 | |
4ef80d72 | 941 | i = irq_of_parse_and_map(dev->of_node, 0); |
c51d411f | 942 | if (!i) { |
4ef80d72 | 943 | dev_err(dev, "cannot get platform resources for msi interrupt\n"); |
290c1fb3 PE |
944 | err = -ENOENT; |
945 | goto err_map_reg; | |
946 | } | |
947 | pcie->msi.irq1 = i; | |
948 | ||
4ef80d72 | 949 | i = irq_of_parse_and_map(dev->of_node, 1); |
c51d411f | 950 | if (!i) { |
4ef80d72 | 951 | dev_err(dev, "cannot get platform resources for msi interrupt\n"); |
290c1fb3 PE |
952 | err = -ENOENT; |
953 | goto err_map_reg; | |
954 | } | |
955 | pcie->msi.irq2 = i; | |
956 | ||
c25da477 PE |
957 | return 0; |
958 | ||
959 | err_map_reg: | |
960 | clk_disable_unprepare(pcie->bus_clk); | |
961 | fail_clk: | |
962 | clk_disable_unprepare(pcie->clk); | |
963 | ||
964 | return err; | |
965 | } | |
966 | ||
967 | static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, | |
968 | struct of_pci_range *range, | |
969 | int *index) | |
970 | { | |
971 | u64 restype = range->flags; | |
972 | u64 cpu_addr = range->cpu_addr; | |
973 | u64 cpu_end = range->cpu_addr + range->size; | |
974 | u64 pci_addr = range->pci_addr; | |
975 | u32 flags = LAM_64BIT | LAR_ENABLE; | |
976 | u64 mask; | |
977 | u64 size; | |
978 | int idx = *index; | |
979 | ||
980 | if (restype & IORESOURCE_PREFETCH) | |
981 | flags |= LAM_PREFETCH; | |
982 | ||
983 | /* | |
984 | * If the size of the range is larger than the alignment of the start | |
985 | * address, we have to use multiple entries to perform the mapping. | |
986 | */ | |
987 | if (cpu_addr > 0) { | |
988 | unsigned long nr_zeros = __ffs64(cpu_addr); | |
989 | u64 alignment = 1ULL << nr_zeros; | |
b7718849 | 990 | |
c25da477 PE |
991 | size = min(range->size, alignment); |
992 | } else { | |
993 | size = range->size; | |
994 | } | |
995 | /* Hardware supports max 4GiB inbound region */ | |
996 | size = min(size, 1ULL << 32); | |
997 | ||
998 | mask = roundup_pow_of_two(size) - 1; | |
999 | mask &= ~0xf; | |
1000 | ||
1001 | while (cpu_addr < cpu_end) { | |
1002 | /* | |
1003 | * Set up 64-bit inbound regions as the range parser doesn't | |
1004 | * distinguish between 32 and 64-bit types. | |
1005 | */ | |
f7bc6380 SS |
1006 | rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), |
1007 | PCIEPRAR(idx)); | |
b7718849 | 1008 | rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); |
f7bc6380 SS |
1009 | rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, |
1010 | PCIELAMR(idx)); | |
c25da477 | 1011 | |
f7bc6380 SS |
1012 | rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), |
1013 | PCIEPRAR(idx + 1)); | |
1014 | rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), | |
1015 | PCIELAR(idx + 1)); | |
b7718849 | 1016 | rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1)); |
c25da477 PE |
1017 | |
1018 | pci_addr += size; | |
1019 | cpu_addr += size; | |
1020 | idx += 2; | |
1021 | ||
1022 | if (idx > MAX_NR_INBOUND_MAPS) { | |
1023 | dev_err(pcie->dev, "Failed to map inbound regions!\n"); | |
1024 | return -EINVAL; | |
1025 | } | |
1026 | } | |
1027 | *index = idx; | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
1033 | struct device_node *node) | |
1034 | { | |
1035 | const int na = 3, ns = 2; | |
1036 | int rlen; | |
1037 | ||
1038 | parser->node = node; | |
1039 | parser->pna = of_n_addr_cells(node); | |
1040 | parser->np = parser->pna + na + ns; | |
1041 | ||
1042 | parser->range = of_get_property(node, "dma-ranges", &rlen); | |
1043 | if (!parser->range) | |
1044 | return -ENOENT; | |
1045 | ||
1046 | parser->end = parser->range + rlen / sizeof(__be32); | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie, | |
1051 | struct device_node *np) | |
1052 | { | |
1053 | struct of_pci_range range; | |
1054 | struct of_pci_range_parser parser; | |
1055 | int index = 0; | |
1056 | int err; | |
1057 | ||
1058 | if (pci_dma_range_parser_init(&parser, np)) | |
1059 | return -EINVAL; | |
1060 | ||
1061 | /* Get the dma-ranges from DT */ | |
1062 | for_each_of_pci_range(&parser, &range) { | |
1063 | u64 end = range.cpu_addr + range.size - 1; | |
f7bc6380 | 1064 | |
c25da477 PE |
1065 | dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", |
1066 | range.flags, range.cpu_addr, end, range.pci_addr); | |
1067 | ||
1068 | err = rcar_pcie_inbound_ranges(pcie, &range, &index); | |
1069 | if (err) | |
1070 | return err; | |
1071 | } | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static const struct of_device_id rcar_pcie_of_match[] = { | |
1077 | { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 }, | |
f7bc6380 SS |
1078 | { .compatible = "renesas,pcie-r8a7790", |
1079 | .data = rcar_pcie_hw_init_gen2 }, | |
1080 | { .compatible = "renesas,pcie-r8a7791", | |
1081 | .data = rcar_pcie_hw_init_gen2 }, | |
d83a328a SH |
1082 | { .compatible = "renesas,pcie-rcar-gen2", |
1083 | .data = rcar_pcie_hw_init_gen2 }, | |
e015f88c | 1084 | { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init }, |
49da2110 | 1085 | { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init }, |
c25da477 PE |
1086 | {}, |
1087 | }; | |
5d2917d4 PE |
1088 | |
1089 | static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci) | |
1090 | { | |
1091 | int err; | |
1092 | struct device *dev = pci->dev; | |
1093 | struct device_node *np = dev->of_node; | |
1094 | resource_size_t iobase; | |
5e8c8732 | 1095 | struct resource_entry *win, *tmp; |
5d2917d4 | 1096 | |
f7bc6380 SS |
1097 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, |
1098 | &iobase); | |
5d2917d4 PE |
1099 | if (err) |
1100 | return err; | |
1101 | ||
6fd7f550 BH |
1102 | err = devm_request_pci_bus_resources(dev, &pci->resources); |
1103 | if (err) | |
1104 | goto out_release_res; | |
1105 | ||
5e8c8732 | 1106 | resource_list_for_each_entry_safe(win, tmp, &pci->resources) { |
6fd7f550 | 1107 | struct resource *res = win->res; |
5d2917d4 | 1108 | |
4c540a35 | 1109 | if (resource_type(res) == IORESOURCE_IO) { |
5d2917d4 | 1110 | err = pci_remap_iospace(res, iobase); |
5e8c8732 | 1111 | if (err) { |
5d2917d4 PE |
1112 | dev_warn(dev, "error %d: failed to map resource %pR\n", |
1113 | err, res); | |
5e8c8732 LP |
1114 | |
1115 | resource_list_destroy_entry(win); | |
1116 | } | |
5d2917d4 | 1117 | } |
5d2917d4 PE |
1118 | } |
1119 | ||
1120 | return 0; | |
1121 | ||
1122 | out_release_res: | |
4c540a35 | 1123 | pci_free_resource_list(&pci->resources); |
5d2917d4 PE |
1124 | return err; |
1125 | } | |
1126 | ||
c25da477 PE |
1127 | static int rcar_pcie_probe(struct platform_device *pdev) |
1128 | { | |
4ef80d72 | 1129 | struct device *dev = &pdev->dev; |
c25da477 PE |
1130 | struct rcar_pcie *pcie; |
1131 | unsigned int data; | |
5d2917d4 | 1132 | int err; |
c25da477 | 1133 | int (*hw_init_fn)(struct rcar_pcie *); |
90634e85 | 1134 | struct pci_host_bridge *bridge; |
c25da477 | 1135 | |
90634e85 LP |
1136 | bridge = pci_alloc_host_bridge(sizeof(*pcie)); |
1137 | if (!bridge) | |
c25da477 PE |
1138 | return -ENOMEM; |
1139 | ||
90634e85 LP |
1140 | pcie = pci_host_bridge_priv(bridge); |
1141 | ||
4ef80d72 | 1142 | pcie->dev = dev; |
c25da477 | 1143 | |
5d2917d4 | 1144 | INIT_LIST_HEAD(&pcie->resources); |
c25da477 | 1145 | |
5d2917d4 | 1146 | rcar_pcie_parse_request_of_pci_ranges(pcie); |
c25da477 | 1147 | |
d0206f21 | 1148 | err = rcar_pcie_get_resources(pcie); |
c25da477 | 1149 | if (err < 0) { |
4ef80d72 | 1150 | dev_err(dev, "failed to request resources: %d\n", err); |
90634e85 | 1151 | goto err_free_bridge; |
c25da477 PE |
1152 | } |
1153 | ||
4ef80d72 | 1154 | err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node); |
f7bc6380 | 1155 | if (err) |
90634e85 | 1156 | goto err_free_bridge; |
c25da477 | 1157 | |
4ef80d72 BH |
1158 | pm_runtime_enable(dev); |
1159 | err = pm_runtime_get_sync(dev); | |
de1be9a8 | 1160 | if (err < 0) { |
4ef80d72 | 1161 | dev_err(dev, "pm_runtime_get_sync failed\n"); |
de1be9a8 PE |
1162 | goto err_pm_disable; |
1163 | } | |
1164 | ||
c25da477 | 1165 | /* Failure to get a link might just be that no cards are inserted */ |
ff1677e2 | 1166 | hw_init_fn = of_device_get_match_data(dev); |
c25da477 PE |
1167 | err = hw_init_fn(pcie); |
1168 | if (err) { | |
4ef80d72 | 1169 | dev_info(dev, "PCIe link down\n"); |
e94888d2 | 1170 | err = -ENODEV; |
de1be9a8 | 1171 | goto err_pm_put; |
c25da477 PE |
1172 | } |
1173 | ||
b7718849 | 1174 | data = rcar_pci_read_reg(pcie, MACSR); |
4ef80d72 | 1175 | dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); |
c25da477 | 1176 | |
de1be9a8 PE |
1177 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
1178 | err = rcar_pcie_enable_msi(pcie); | |
1179 | if (err < 0) { | |
4ef80d72 | 1180 | dev_err(dev, |
de1be9a8 PE |
1181 | "failed to enable MSI support: %d\n", |
1182 | err); | |
1183 | goto err_pm_put; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | err = rcar_pcie_enable(pcie); | |
1188 | if (err) | |
1189 | goto err_pm_put; | |
1190 | ||
1191 | return 0; | |
1192 | ||
90634e85 LP |
1193 | err_free_bridge: |
1194 | pci_free_host_bridge(bridge); | |
1195 | ||
de1be9a8 | 1196 | err_pm_put: |
4ef80d72 | 1197 | pm_runtime_put(dev); |
de1be9a8 PE |
1198 | |
1199 | err_pm_disable: | |
4ef80d72 | 1200 | pm_runtime_disable(dev); |
de1be9a8 | 1201 | return err; |
c25da477 PE |
1202 | } |
1203 | ||
1204 | static struct platform_driver rcar_pcie_driver = { | |
1205 | .driver = { | |
3ff8e4ac | 1206 | .name = "rcar-pcie", |
c25da477 PE |
1207 | .of_match_table = rcar_pcie_of_match, |
1208 | .suppress_bind_attrs = true, | |
1209 | }, | |
1210 | .probe = rcar_pcie_probe, | |
1211 | }; | |
42d10719 | 1212 | builtin_platform_driver(rcar_pcie_driver); |