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1fb37a81 RJ |
1 | /* |
2 | * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> | |
be908d21 | 3 | * Copyright (C) 2015 Broadcom Corporation |
1fb37a81 RJ |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation version 2. | |
8 | * | |
9 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
10 | * kind, whether express or implied; without even the implied warranty | |
11 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/msi.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/interrupt.h> | |
787b3c4f | 24 | #include <linux/irqchip/arm-gic-v3.h> |
1fb37a81 RJ |
25 | #include <linux/platform_device.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/phy/phy.h> | |
31 | ||
32 | #include "pcie-iproc.h" | |
33 | ||
199ff141 RJ |
34 | #define EP_PERST_SOURCE_SELECT_SHIFT 2 |
35 | #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) | |
1fb37a81 RJ |
36 | #define EP_MODE_SURVIVE_PERST_SHIFT 1 |
37 | #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) | |
38 | #define RC_PCIE_RST_OUTPUT_SHIFT 0 | |
39 | #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) | |
943ebae7 | 40 | #define PAXC_RESET_MASK 0x7f |
1fb37a81 | 41 | |
787b3c4f RJ |
42 | #define GIC_V3_CFG_SHIFT 0 |
43 | #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT) | |
44 | ||
45 | #define MSI_ENABLE_CFG_SHIFT 0 | |
46 | #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT) | |
47 | ||
1fb37a81 RJ |
48 | #define CFG_IND_ADDR_MASK 0x00001ffc |
49 | ||
1fb37a81 RJ |
50 | #define CFG_ADDR_BUS_NUM_SHIFT 20 |
51 | #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 | |
52 | #define CFG_ADDR_DEV_NUM_SHIFT 15 | |
53 | #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 | |
54 | #define CFG_ADDR_FUNC_NUM_SHIFT 12 | |
55 | #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 | |
56 | #define CFG_ADDR_REG_NUM_SHIFT 2 | |
57 | #define CFG_ADDR_REG_NUM_MASK 0x00000ffc | |
58 | #define CFG_ADDR_CFG_TYPE_SHIFT 0 | |
59 | #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 | |
60 | ||
1fb37a81 RJ |
61 | #define SYS_RC_INTX_MASK 0xf |
62 | ||
aaf22ab4 RJ |
63 | #define PCIE_PHYLINKUP_SHIFT 3 |
64 | #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) | |
65 | #define PCIE_DL_ACTIVE_SHIFT 2 | |
66 | #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) | |
67 | ||
538928fd RJ |
68 | #define APB_ERR_EN_SHIFT 0 |
69 | #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT) | |
70 | ||
4213e15c RJ |
71 | /* derive the enum index of the outbound/inbound mapping registers */ |
72 | #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2) | |
73 | ||
74 | /* | |
75 | * Maximum number of outbound mapping window sizes that can be supported by any | |
76 | * OARR/OMAP mapping pair | |
77 | */ | |
78 | #define MAX_NUM_OB_WINDOW_SIZES 4 | |
79 | ||
e99a187b RJ |
80 | #define OARR_VALID_SHIFT 0 |
81 | #define OARR_VALID BIT(OARR_VALID_SHIFT) | |
82 | #define OARR_SIZE_CFG_SHIFT 1 | |
e99a187b | 83 | |
dd9d4e74 RJ |
84 | /* |
85 | * Maximum number of inbound mapping region sizes that can be supported by an | |
86 | * IARR | |
87 | */ | |
88 | #define MAX_NUM_IB_REGION_SIZES 9 | |
89 | ||
90 | #define IMAP_VALID_SHIFT 0 | |
91 | #define IMAP_VALID BIT(IMAP_VALID_SHIFT) | |
92 | ||
e3a1698b BH |
93 | #define PCI_EXP_CAP 0xac |
94 | ||
943ebae7 RJ |
95 | #define IPROC_PCIE_REG_INVALID 0xffff |
96 | ||
4213e15c RJ |
97 | /** |
98 | * iProc PCIe outbound mapping controller specific parameters | |
99 | * | |
100 | * @window_sizes: list of supported outbound mapping window sizes in MB | |
101 | * @nr_sizes: number of supported outbound mapping window sizes | |
102 | */ | |
103 | struct iproc_pcie_ob_map { | |
104 | resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES]; | |
105 | unsigned int nr_sizes; | |
106 | }; | |
107 | ||
108 | static const struct iproc_pcie_ob_map paxb_ob_map[] = { | |
109 | { | |
110 | /* OARR0/OMAP0 */ | |
111 | .window_sizes = { 128, 256 }, | |
112 | .nr_sizes = 2, | |
113 | }, | |
114 | { | |
115 | /* OARR1/OMAP1 */ | |
116 | .window_sizes = { 128, 256 }, | |
117 | .nr_sizes = 2, | |
118 | }, | |
119 | }; | |
120 | ||
c7c44527 RJ |
121 | static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = { |
122 | { | |
123 | /* OARR0/OMAP0 */ | |
124 | .window_sizes = { 128, 256 }, | |
125 | .nr_sizes = 2, | |
126 | }, | |
127 | { | |
128 | /* OARR1/OMAP1 */ | |
129 | .window_sizes = { 128, 256 }, | |
130 | .nr_sizes = 2, | |
131 | }, | |
132 | { | |
133 | /* OARR2/OMAP2 */ | |
134 | .window_sizes = { 128, 256, 512, 1024 }, | |
135 | .nr_sizes = 4, | |
136 | }, | |
137 | { | |
138 | /* OARR3/OMAP3 */ | |
139 | .window_sizes = { 128, 256, 512, 1024 }, | |
140 | .nr_sizes = 4, | |
141 | }, | |
142 | }; | |
143 | ||
dd9d4e74 RJ |
144 | /** |
145 | * iProc PCIe inbound mapping type | |
146 | */ | |
147 | enum iproc_pcie_ib_map_type { | |
148 | /* for DDR memory */ | |
149 | IPROC_PCIE_IB_MAP_MEM = 0, | |
150 | ||
151 | /* for device I/O memory */ | |
152 | IPROC_PCIE_IB_MAP_IO, | |
153 | ||
154 | /* invalid or unused */ | |
155 | IPROC_PCIE_IB_MAP_INVALID | |
156 | }; | |
157 | ||
158 | /** | |
159 | * iProc PCIe inbound mapping controller specific parameters | |
160 | * | |
161 | * @type: inbound mapping region type | |
162 | * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or | |
163 | * SZ_1G | |
164 | * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or | |
165 | * GB, depedning on the size unit | |
166 | * @nr_sizes: number of supported inbound mapping region sizes | |
167 | * @nr_windows: number of supported inbound mapping windows for the region | |
168 | * @imap_addr_offset: register offset between the upper and lower 32-bit | |
169 | * IMAP address registers | |
170 | * @imap_window_offset: register offset between each IMAP window | |
171 | */ | |
172 | struct iproc_pcie_ib_map { | |
173 | enum iproc_pcie_ib_map_type type; | |
174 | unsigned int size_unit; | |
175 | resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES]; | |
176 | unsigned int nr_sizes; | |
177 | unsigned int nr_windows; | |
178 | u16 imap_addr_offset; | |
179 | u16 imap_window_offset; | |
180 | }; | |
181 | ||
c7c44527 RJ |
182 | static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = { |
183 | { | |
184 | /* IARR0/IMAP0 */ | |
185 | .type = IPROC_PCIE_IB_MAP_IO, | |
186 | .size_unit = SZ_1K, | |
187 | .region_sizes = { 32 }, | |
188 | .nr_sizes = 1, | |
189 | .nr_windows = 8, | |
190 | .imap_addr_offset = 0x40, | |
191 | .imap_window_offset = 0x4, | |
192 | }, | |
193 | { | |
194 | /* IARR1/IMAP1 (currently unused) */ | |
195 | .type = IPROC_PCIE_IB_MAP_INVALID, | |
196 | }, | |
197 | { | |
198 | /* IARR2/IMAP2 */ | |
199 | .type = IPROC_PCIE_IB_MAP_MEM, | |
200 | .size_unit = SZ_1M, | |
201 | .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192, | |
202 | 16384 }, | |
203 | .nr_sizes = 9, | |
204 | .nr_windows = 1, | |
205 | .imap_addr_offset = 0x4, | |
206 | .imap_window_offset = 0x8, | |
207 | }, | |
208 | { | |
209 | /* IARR3/IMAP3 */ | |
210 | .type = IPROC_PCIE_IB_MAP_MEM, | |
211 | .size_unit = SZ_1G, | |
212 | .region_sizes = { 1, 2, 4, 8, 16, 32 }, | |
213 | .nr_sizes = 6, | |
214 | .nr_windows = 8, | |
215 | .imap_addr_offset = 0x4, | |
216 | .imap_window_offset = 0x8, | |
217 | }, | |
218 | { | |
219 | /* IARR4/IMAP4 */ | |
220 | .type = IPROC_PCIE_IB_MAP_MEM, | |
221 | .size_unit = SZ_1G, | |
222 | .region_sizes = { 32, 64, 128, 256, 512 }, | |
223 | .nr_sizes = 5, | |
224 | .nr_windows = 8, | |
225 | .imap_addr_offset = 0x4, | |
226 | .imap_window_offset = 0x8, | |
227 | }, | |
228 | }; | |
229 | ||
06324ede RJ |
230 | /* |
231 | * iProc PCIe host registers | |
232 | */ | |
943ebae7 | 233 | enum iproc_pcie_reg { |
06324ede | 234 | /* clock/reset signal control */ |
943ebae7 | 235 | IPROC_PCIE_CLK_CTRL = 0, |
06324ede | 236 | |
787b3c4f RJ |
237 | /* |
238 | * To allow MSI to be steered to an external MSI controller (e.g., ARM | |
239 | * GICv3 ITS) | |
240 | */ | |
241 | IPROC_PCIE_MSI_GIC_MODE, | |
242 | ||
243 | /* | |
244 | * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the | |
245 | * window where the MSI posted writes are written, for the writes to be | |
246 | * interpreted as MSI writes. | |
247 | */ | |
248 | IPROC_PCIE_MSI_BASE_ADDR, | |
249 | IPROC_PCIE_MSI_WINDOW_SIZE, | |
250 | ||
251 | /* | |
252 | * To hold the address of the register where the MSI writes are | |
253 | * programed. When ARM GICv3 ITS is used, this should be programmed | |
254 | * with the address of the GITS_TRANSLATER register. | |
255 | */ | |
256 | IPROC_PCIE_MSI_ADDR_LO, | |
257 | IPROC_PCIE_MSI_ADDR_HI, | |
258 | ||
259 | /* enable MSI */ | |
260 | IPROC_PCIE_MSI_EN_CFG, | |
261 | ||
06324ede | 262 | /* allow access to root complex configuration space */ |
943ebae7 RJ |
263 | IPROC_PCIE_CFG_IND_ADDR, |
264 | IPROC_PCIE_CFG_IND_DATA, | |
06324ede RJ |
265 | |
266 | /* allow access to device configuration space */ | |
943ebae7 RJ |
267 | IPROC_PCIE_CFG_ADDR, |
268 | IPROC_PCIE_CFG_DATA, | |
06324ede RJ |
269 | |
270 | /* enable INTx */ | |
943ebae7 | 271 | IPROC_PCIE_INTX_EN, |
06324ede RJ |
272 | |
273 | /* outbound address mapping */ | |
4213e15c RJ |
274 | IPROC_PCIE_OARR0, |
275 | IPROC_PCIE_OMAP0, | |
276 | IPROC_PCIE_OARR1, | |
277 | IPROC_PCIE_OMAP1, | |
278 | IPROC_PCIE_OARR2, | |
279 | IPROC_PCIE_OMAP2, | |
280 | IPROC_PCIE_OARR3, | |
281 | IPROC_PCIE_OMAP3, | |
06324ede | 282 | |
dd9d4e74 RJ |
283 | /* inbound address mapping */ |
284 | IPROC_PCIE_IARR0, | |
285 | IPROC_PCIE_IMAP0, | |
286 | IPROC_PCIE_IARR1, | |
287 | IPROC_PCIE_IMAP1, | |
288 | IPROC_PCIE_IARR2, | |
289 | IPROC_PCIE_IMAP2, | |
290 | IPROC_PCIE_IARR3, | |
291 | IPROC_PCIE_IMAP3, | |
292 | IPROC_PCIE_IARR4, | |
293 | IPROC_PCIE_IMAP4, | |
294 | ||
06324ede | 295 | /* link status */ |
943ebae7 | 296 | IPROC_PCIE_LINK_STATUS, |
06324ede | 297 | |
538928fd RJ |
298 | /* enable APB error for unsupported requests */ |
299 | IPROC_PCIE_APB_ERR_EN, | |
300 | ||
06324ede RJ |
301 | /* total number of core registers */ |
302 | IPROC_PCIE_MAX_NUM_REG, | |
943ebae7 RJ |
303 | }; |
304 | ||
404349c5 RJ |
305 | /* iProc PCIe PAXB BCMA registers */ |
306 | static const u16 iproc_pcie_reg_paxb_bcma[] = { | |
307 | [IPROC_PCIE_CLK_CTRL] = 0x000, | |
308 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
309 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
310 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
311 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
312 | [IPROC_PCIE_INTX_EN] = 0x330, | |
313 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
314 | }; | |
315 | ||
943ebae7 RJ |
316 | /* iProc PCIe PAXB registers */ |
317 | static const u16 iproc_pcie_reg_paxb[] = { | |
4213e15c RJ |
318 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
319 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
320 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
321 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
322 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
323 | [IPROC_PCIE_INTX_EN] = 0x330, | |
324 | [IPROC_PCIE_OARR0] = 0xd20, | |
325 | [IPROC_PCIE_OMAP0] = 0xd40, | |
326 | [IPROC_PCIE_OARR1] = 0xd28, | |
327 | [IPROC_PCIE_OMAP1] = 0xd48, | |
328 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
329 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
943ebae7 RJ |
330 | }; |
331 | ||
c7c44527 RJ |
332 | /* iProc PCIe PAXB v2 registers */ |
333 | static const u16 iproc_pcie_reg_paxb_v2[] = { | |
334 | [IPROC_PCIE_CLK_CTRL] = 0x000, | |
335 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
336 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
337 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
338 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
339 | [IPROC_PCIE_INTX_EN] = 0x330, | |
340 | [IPROC_PCIE_OARR0] = 0xd20, | |
341 | [IPROC_PCIE_OMAP0] = 0xd40, | |
342 | [IPROC_PCIE_OARR1] = 0xd28, | |
343 | [IPROC_PCIE_OMAP1] = 0xd48, | |
344 | [IPROC_PCIE_OARR2] = 0xd60, | |
345 | [IPROC_PCIE_OMAP2] = 0xd68, | |
346 | [IPROC_PCIE_OARR3] = 0xdf0, | |
347 | [IPROC_PCIE_OMAP3] = 0xdf8, | |
348 | [IPROC_PCIE_IARR0] = 0xd00, | |
349 | [IPROC_PCIE_IMAP0] = 0xc00, | |
350 | [IPROC_PCIE_IARR2] = 0xd10, | |
351 | [IPROC_PCIE_IMAP2] = 0xcc0, | |
352 | [IPROC_PCIE_IARR3] = 0xe00, | |
353 | [IPROC_PCIE_IMAP3] = 0xe08, | |
354 | [IPROC_PCIE_IARR4] = 0xe68, | |
355 | [IPROC_PCIE_IMAP4] = 0xe70, | |
356 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
357 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
358 | }; | |
359 | ||
943ebae7 RJ |
360 | /* iProc PCIe PAXC v1 registers */ |
361 | static const u16 iproc_pcie_reg_paxc[] = { | |
4213e15c RJ |
362 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
363 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
364 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
365 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
366 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
943ebae7 | 367 | }; |
e99a187b | 368 | |
787b3c4f RJ |
369 | /* iProc PCIe PAXC v2 registers */ |
370 | static const u16 iproc_pcie_reg_paxc_v2[] = { | |
371 | [IPROC_PCIE_MSI_GIC_MODE] = 0x050, | |
372 | [IPROC_PCIE_MSI_BASE_ADDR] = 0x074, | |
373 | [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078, | |
374 | [IPROC_PCIE_MSI_ADDR_LO] = 0x07c, | |
375 | [IPROC_PCIE_MSI_ADDR_HI] = 0x080, | |
376 | [IPROC_PCIE_MSI_EN_CFG] = 0x09c, | |
377 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
378 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
379 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
380 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
381 | }; | |
382 | ||
8d9bfe37 | 383 | static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) |
1fb37a81 | 384 | { |
8d9bfe37 RJ |
385 | struct iproc_pcie *pcie; |
386 | #ifdef CONFIG_ARM | |
387 | struct pci_sys_data *sys = bus->sysdata; | |
388 | ||
389 | pcie = sys->private_data; | |
390 | #else | |
391 | pcie = bus->sysdata; | |
392 | #endif | |
393 | return pcie; | |
1fb37a81 RJ |
394 | } |
395 | ||
943ebae7 RJ |
396 | static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) |
397 | { | |
398 | return !!(reg_offset == IPROC_PCIE_REG_INVALID); | |
399 | } | |
400 | ||
401 | static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, | |
402 | enum iproc_pcie_reg reg) | |
403 | { | |
404 | return pcie->reg_offsets[reg]; | |
405 | } | |
406 | ||
407 | static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, | |
408 | enum iproc_pcie_reg reg) | |
409 | { | |
410 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
411 | ||
412 | if (iproc_pcie_reg_is_invalid(offset)) | |
413 | return 0; | |
414 | ||
415 | return readl(pcie->base + offset); | |
416 | } | |
417 | ||
418 | static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, | |
419 | enum iproc_pcie_reg reg, u32 val) | |
420 | { | |
421 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
422 | ||
423 | if (iproc_pcie_reg_is_invalid(offset)) | |
424 | return; | |
425 | ||
426 | writel(val, pcie->base + offset); | |
427 | } | |
428 | ||
538928fd RJ |
429 | /** |
430 | * APB error forwarding can be disabled during access of configuration | |
431 | * registers of the endpoint device, to prevent unsupported requests | |
432 | * (typically seen during enumeration with multi-function devices) from | |
433 | * triggering a system exception. | |
434 | */ | |
435 | static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, | |
436 | bool disable) | |
437 | { | |
438 | struct iproc_pcie *pcie = iproc_data(bus); | |
439 | u32 val; | |
440 | ||
441 | if (bus->number && pcie->has_apb_err_disable) { | |
442 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); | |
443 | if (disable) | |
444 | val &= ~APB_ERR_EN; | |
445 | else | |
446 | val |= APB_ERR_EN; | |
447 | iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); | |
448 | } | |
449 | } | |
450 | ||
1fb37a81 RJ |
451 | /** |
452 | * Note access to the configuration registers are protected at the higher layer | |
453 | * by 'pci_lock' in drivers/pci/access.c | |
454 | */ | |
455 | static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, | |
456 | unsigned int devfn, | |
457 | int where) | |
458 | { | |
8d9bfe37 | 459 | struct iproc_pcie *pcie = iproc_data(bus); |
1fb37a81 RJ |
460 | unsigned slot = PCI_SLOT(devfn); |
461 | unsigned fn = PCI_FUNC(devfn); | |
462 | unsigned busno = bus->number; | |
463 | u32 val; | |
943ebae7 RJ |
464 | u16 offset; |
465 | ||
1fb37a81 RJ |
466 | /* root complex access */ |
467 | if (busno == 0) { | |
46560388 RJ |
468 | if (slot > 0 || fn > 0) |
469 | return NULL; | |
470 | ||
943ebae7 RJ |
471 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, |
472 | where & CFG_IND_ADDR_MASK); | |
473 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); | |
474 | if (iproc_pcie_reg_is_invalid(offset)) | |
1fb37a81 | 475 | return NULL; |
943ebae7 RJ |
476 | else |
477 | return (pcie->base + offset); | |
1fb37a81 RJ |
478 | } |
479 | ||
46560388 RJ |
480 | /* |
481 | * PAXC is connected to an internally emulated EP within the SoC. It | |
482 | * allows only one device. | |
483 | */ | |
06324ede | 484 | if (pcie->ep_is_internal) |
46560388 RJ |
485 | if (slot > 0) |
486 | return NULL; | |
487 | ||
1fb37a81 RJ |
488 | /* EP device access */ |
489 | val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | | |
490 | (slot << CFG_ADDR_DEV_NUM_SHIFT) | | |
491 | (fn << CFG_ADDR_FUNC_NUM_SHIFT) | | |
492 | (where & CFG_ADDR_REG_NUM_MASK) | | |
493 | (1 & CFG_ADDR_CFG_TYPE_MASK); | |
943ebae7 RJ |
494 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); |
495 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); | |
496 | if (iproc_pcie_reg_is_invalid(offset)) | |
497 | return NULL; | |
498 | else | |
499 | return (pcie->base + offset); | |
1fb37a81 RJ |
500 | } |
501 | ||
538928fd RJ |
502 | static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
503 | int where, int size, u32 *val) | |
504 | { | |
505 | int ret; | |
506 | ||
507 | iproc_pcie_apb_err_disable(bus, true); | |
508 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
509 | iproc_pcie_apb_err_disable(bus, false); | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
514 | static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, | |
515 | int where, int size, u32 val) | |
516 | { | |
517 | int ret; | |
518 | ||
519 | iproc_pcie_apb_err_disable(bus, true); | |
520 | ret = pci_generic_config_write32(bus, devfn, where, size, val); | |
521 | iproc_pcie_apb_err_disable(bus, false); | |
522 | ||
523 | return ret; | |
524 | } | |
525 | ||
1fb37a81 RJ |
526 | static struct pci_ops iproc_pcie_ops = { |
527 | .map_bus = iproc_pcie_map_cfg_bus, | |
538928fd RJ |
528 | .read = iproc_pcie_config_read32, |
529 | .write = iproc_pcie_config_write32, | |
1fb37a81 RJ |
530 | }; |
531 | ||
532 | static void iproc_pcie_reset(struct iproc_pcie *pcie) | |
533 | { | |
534 | u32 val; | |
535 | ||
7cbd50d2 RJ |
536 | /* |
537 | * PAXC and the internal emulated endpoint device downstream should not | |
538 | * be reset. If firmware has been loaded on the endpoint device at an | |
539 | * earlier boot stage, reset here causes issues. | |
540 | */ | |
541 | if (pcie->ep_is_internal) | |
943ebae7 | 542 | return; |
943ebae7 | 543 | |
1fb37a81 | 544 | /* |
199ff141 RJ |
545 | * Select perst_b signal as reset source. Put the device into reset, |
546 | * and then bring it out of reset | |
1fb37a81 | 547 | */ |
943ebae7 | 548 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); |
199ff141 RJ |
549 | val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & |
550 | ~RC_PCIE_RST_OUTPUT; | |
943ebae7 | 551 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); |
1fb37a81 | 552 | udelay(250); |
199ff141 RJ |
553 | |
554 | val |= RC_PCIE_RST_OUTPUT; | |
943ebae7 | 555 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); |
199ff141 | 556 | msleep(100); |
1fb37a81 RJ |
557 | } |
558 | ||
559 | static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus) | |
560 | { | |
786aeccb | 561 | struct device *dev = pcie->dev; |
1fb37a81 | 562 | u8 hdr_type; |
aaf22ab4 | 563 | u32 link_ctrl, class, val; |
e3a1698b | 564 | u16 pos = PCI_EXP_CAP, link_status; |
aaf22ab4 RJ |
565 | bool link_is_active = false; |
566 | ||
943ebae7 RJ |
567 | /* |
568 | * PAXC connects to emulated endpoint devices directly and does not | |
569 | * have a Serdes. Therefore skip the link detection logic here. | |
570 | */ | |
06324ede | 571 | if (pcie->ep_is_internal) |
943ebae7 RJ |
572 | return 0; |
573 | ||
574 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); | |
aaf22ab4 | 575 | if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { |
786aeccb | 576 | dev_err(dev, "PHY or data link is INACTIVE!\n"); |
aaf22ab4 RJ |
577 | return -ENODEV; |
578 | } | |
1fb37a81 RJ |
579 | |
580 | /* make sure we are not in EP mode */ | |
581 | pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type); | |
582 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { | |
786aeccb | 583 | dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); |
1fb37a81 RJ |
584 | return -EFAULT; |
585 | } | |
586 | ||
587 | /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ | |
aaf22ab4 RJ |
588 | #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c |
589 | #define PCI_CLASS_BRIDGE_MASK 0xffff00 | |
590 | #define PCI_CLASS_BRIDGE_SHIFT 8 | |
591 | pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class); | |
592 | class &= ~PCI_CLASS_BRIDGE_MASK; | |
593 | class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); | |
594 | pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class); | |
1fb37a81 RJ |
595 | |
596 | /* check link status to see if link is active */ | |
1fb37a81 RJ |
597 | pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status); |
598 | if (link_status & PCI_EXP_LNKSTA_NLW) | |
aaf22ab4 | 599 | link_is_active = true; |
1fb37a81 RJ |
600 | |
601 | if (!link_is_active) { | |
602 | /* try GEN 1 link speed */ | |
1fb37a81 RJ |
603 | #define PCI_TARGET_LINK_SPEED_MASK 0xf |
604 | #define PCI_TARGET_LINK_SPEED_GEN2 0x2 | |
605 | #define PCI_TARGET_LINK_SPEED_GEN1 0x1 | |
606 | pci_bus_read_config_dword(bus, 0, | |
e3a1698b | 607 | pos + PCI_EXP_LNKCTL2, |
1fb37a81 RJ |
608 | &link_ctrl); |
609 | if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) == | |
610 | PCI_TARGET_LINK_SPEED_GEN2) { | |
611 | link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK; | |
612 | link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1; | |
613 | pci_bus_write_config_dword(bus, 0, | |
e3a1698b | 614 | pos + PCI_EXP_LNKCTL2, |
1fb37a81 RJ |
615 | link_ctrl); |
616 | msleep(100); | |
617 | ||
1fb37a81 RJ |
618 | pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, |
619 | &link_status); | |
620 | if (link_status & PCI_EXP_LNKSTA_NLW) | |
aaf22ab4 | 621 | link_is_active = true; |
1fb37a81 RJ |
622 | } |
623 | } | |
624 | ||
786aeccb | 625 | dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); |
1fb37a81 RJ |
626 | |
627 | return link_is_active ? 0 : -ENODEV; | |
628 | } | |
629 | ||
630 | static void iproc_pcie_enable(struct iproc_pcie *pcie) | |
631 | { | |
943ebae7 | 632 | iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); |
1fb37a81 RJ |
633 | } |
634 | ||
4213e15c RJ |
635 | static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, |
636 | int window_idx) | |
637 | { | |
638 | u32 val; | |
639 | ||
640 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); | |
641 | ||
642 | return !!(val & OARR_VALID); | |
643 | } | |
644 | ||
645 | static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, | |
646 | int size_idx, u64 axi_addr, u64 pci_addr) | |
647 | { | |
648 | struct device *dev = pcie->dev; | |
649 | u16 oarr_offset, omap_offset; | |
650 | ||
651 | /* | |
652 | * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based | |
653 | * on window index. | |
654 | */ | |
655 | oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, | |
656 | window_idx)); | |
657 | omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, | |
658 | window_idx)); | |
659 | if (iproc_pcie_reg_is_invalid(oarr_offset) || | |
660 | iproc_pcie_reg_is_invalid(omap_offset)) | |
661 | return -EINVAL; | |
662 | ||
663 | /* | |
664 | * Program the OARR registers. The upper 32-bit OARR register is | |
665 | * always right after the lower 32-bit OARR register. | |
666 | */ | |
667 | writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) | | |
668 | OARR_VALID, pcie->base + oarr_offset); | |
669 | writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); | |
670 | ||
671 | /* now program the OMAP registers */ | |
672 | writel(lower_32_bits(pci_addr), pcie->base + omap_offset); | |
673 | writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); | |
674 | ||
675 | dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", | |
676 | window_idx, oarr_offset, &axi_addr, &pci_addr); | |
677 | dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n", | |
678 | readl(pcie->base + oarr_offset), | |
679 | readl(pcie->base + oarr_offset + 4)); | |
680 | dev_info(dev, "omap lo 0x%x omap hi 0x%x\n", | |
681 | readl(pcie->base + omap_offset), | |
682 | readl(pcie->base + omap_offset + 4)); | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
e99a187b RJ |
687 | /** |
688 | * Some iProc SoCs require the SW to configure the outbound address mapping | |
689 | * | |
690 | * Outbound address translation: | |
691 | * | |
692 | * iproc_pcie_address = axi_address - axi_offset | |
693 | * OARR = iproc_pcie_address | |
694 | * OMAP = pci_addr | |
695 | * | |
696 | * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address | |
697 | */ | |
698 | static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, | |
699 | u64 pci_addr, resource_size_t size) | |
700 | { | |
701 | struct iproc_pcie_ob *ob = &pcie->ob; | |
786aeccb | 702 | struct device *dev = pcie->dev; |
4213e15c | 703 | int ret = -EINVAL, window_idx, size_idx; |
e99a187b RJ |
704 | |
705 | if (axi_addr < ob->axi_offset) { | |
786aeccb | 706 | dev_err(dev, "axi address %pap less than offset %pap\n", |
e99a187b RJ |
707 | &axi_addr, &ob->axi_offset); |
708 | return -EINVAL; | |
709 | } | |
710 | ||
711 | /* | |
712 | * Translate the AXI address to the internal address used by the iProc | |
713 | * PCIe core before programming the OARR | |
714 | */ | |
715 | axi_addr -= ob->axi_offset; | |
716 | ||
4213e15c RJ |
717 | /* iterate through all OARR/OMAP mapping windows */ |
718 | for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { | |
719 | const struct iproc_pcie_ob_map *ob_map = | |
720 | &pcie->ob_map[window_idx]; | |
721 | ||
722 | /* | |
723 | * If current outbound window is already in use, move on to the | |
724 | * next one. | |
725 | */ | |
726 | if (iproc_pcie_ob_is_valid(pcie, window_idx)) | |
727 | continue; | |
728 | ||
729 | /* | |
730 | * Iterate through all supported window sizes within the | |
731 | * OARR/OMAP pair to find a match. Go through the window sizes | |
732 | * in a descending order. | |
733 | */ | |
734 | for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; | |
735 | size_idx--) { | |
736 | resource_size_t window_size = | |
737 | ob_map->window_sizes[size_idx] * SZ_1M; | |
738 | ||
739 | if (size < window_size) | |
740 | continue; | |
741 | ||
742 | if (!IS_ALIGNED(axi_addr, window_size) || | |
743 | !IS_ALIGNED(pci_addr, window_size)) { | |
744 | dev_err(dev, | |
745 | "axi %pap or pci %pap not aligned\n", | |
746 | &axi_addr, &pci_addr); | |
747 | return -EINVAL; | |
748 | } | |
749 | ||
750 | /* | |
751 | * Match found! Program both OARR and OMAP and mark | |
752 | * them as a valid entry. | |
753 | */ | |
754 | ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, | |
755 | axi_addr, pci_addr); | |
756 | if (ret) | |
757 | goto err_ob; | |
758 | ||
759 | size -= window_size; | |
760 | if (size == 0) | |
761 | return 0; | |
762 | ||
763 | /* | |
764 | * If we are here, we are done with the current window, | |
765 | * but not yet finished all mappings. Need to move on | |
766 | * to the next window. | |
767 | */ | |
768 | axi_addr += window_size; | |
769 | pci_addr += window_size; | |
e99a187b | 770 | break; |
4213e15c | 771 | } |
e99a187b RJ |
772 | } |
773 | ||
4213e15c RJ |
774 | err_ob: |
775 | dev_err(dev, "unable to configure outbound mapping\n"); | |
776 | dev_err(dev, | |
777 | "axi %pap, axi offset %pap, pci %pap, res size %pap\n", | |
778 | &axi_addr, &ob->axi_offset, &pci_addr, &size); | |
779 | ||
780 | return ret; | |
e99a187b RJ |
781 | } |
782 | ||
783 | static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, | |
784 | struct list_head *resources) | |
785 | { | |
786aeccb | 786 | struct device *dev = pcie->dev; |
e99a187b RJ |
787 | struct resource_entry *window; |
788 | int ret; | |
789 | ||
790 | resource_list_for_each_entry(window, resources) { | |
791 | struct resource *res = window->res; | |
792 | u64 res_type = resource_type(res); | |
793 | ||
794 | switch (res_type) { | |
795 | case IORESOURCE_IO: | |
796 | case IORESOURCE_BUS: | |
797 | break; | |
798 | case IORESOURCE_MEM: | |
799 | ret = iproc_pcie_setup_ob(pcie, res->start, | |
800 | res->start - window->offset, | |
801 | resource_size(res)); | |
802 | if (ret) | |
803 | return ret; | |
804 | break; | |
805 | default: | |
786aeccb | 806 | dev_err(dev, "invalid resource %pR\n", res); |
e99a187b RJ |
807 | return -EINVAL; |
808 | } | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
dd9d4e74 RJ |
814 | static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, |
815 | int region_idx) | |
816 | { | |
817 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
818 | u32 val; | |
819 | ||
820 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
821 | ||
822 | return !!(val & (BIT(ib_map->nr_sizes) - 1)); | |
823 | } | |
824 | ||
825 | static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map, | |
826 | enum iproc_pcie_ib_map_type type) | |
827 | { | |
828 | return !!(ib_map->type == type); | |
829 | } | |
830 | ||
831 | static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, | |
832 | int size_idx, int nr_windows, u64 axi_addr, | |
833 | u64 pci_addr, resource_size_t size) | |
834 | { | |
835 | struct device *dev = pcie->dev; | |
836 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
837 | u16 iarr_offset, imap_offset; | |
838 | u32 val; | |
839 | int window_idx; | |
840 | ||
841 | iarr_offset = iproc_pcie_reg_offset(pcie, | |
842 | MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
843 | imap_offset = iproc_pcie_reg_offset(pcie, | |
844 | MAP_REG(IPROC_PCIE_IMAP0, region_idx)); | |
845 | if (iproc_pcie_reg_is_invalid(iarr_offset) || | |
846 | iproc_pcie_reg_is_invalid(imap_offset)) | |
847 | return -EINVAL; | |
848 | ||
849 | dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", | |
850 | region_idx, iarr_offset, &axi_addr, &pci_addr); | |
851 | ||
852 | /* | |
853 | * Program the IARR registers. The upper 32-bit IARR register is | |
854 | * always right after the lower 32-bit IARR register. | |
855 | */ | |
856 | writel(lower_32_bits(pci_addr) | BIT(size_idx), | |
857 | pcie->base + iarr_offset); | |
858 | writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); | |
859 | ||
860 | dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n", | |
861 | readl(pcie->base + iarr_offset), | |
862 | readl(pcie->base + iarr_offset + 4)); | |
863 | ||
864 | /* | |
865 | * Now program the IMAP registers. Each IARR region may have one or | |
866 | * more IMAP windows. | |
867 | */ | |
868 | size >>= ilog2(nr_windows); | |
869 | for (window_idx = 0; window_idx < nr_windows; window_idx++) { | |
870 | val = readl(pcie->base + imap_offset); | |
871 | val |= lower_32_bits(axi_addr) | IMAP_VALID; | |
872 | writel(val, pcie->base + imap_offset); | |
873 | writel(upper_32_bits(axi_addr), | |
874 | pcie->base + imap_offset + ib_map->imap_addr_offset); | |
875 | ||
876 | dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n", | |
877 | window_idx, readl(pcie->base + imap_offset), | |
878 | readl(pcie->base + imap_offset + | |
879 | ib_map->imap_addr_offset)); | |
880 | ||
881 | imap_offset += ib_map->imap_window_offset; | |
882 | axi_addr += size; | |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, | |
889 | struct of_pci_range *range, | |
890 | enum iproc_pcie_ib_map_type type) | |
891 | { | |
892 | struct device *dev = pcie->dev; | |
893 | struct iproc_pcie_ib *ib = &pcie->ib; | |
894 | int ret; | |
895 | unsigned int region_idx, size_idx; | |
896 | u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr; | |
897 | resource_size_t size = range->size; | |
898 | ||
899 | /* iterate through all IARR mapping regions */ | |
900 | for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { | |
901 | const struct iproc_pcie_ib_map *ib_map = | |
902 | &pcie->ib_map[region_idx]; | |
903 | ||
904 | /* | |
905 | * If current inbound region is already in use or not a | |
906 | * compatible type, move on to the next. | |
907 | */ | |
908 | if (iproc_pcie_ib_is_in_use(pcie, region_idx) || | |
909 | !iproc_pcie_ib_check_type(ib_map, type)) | |
910 | continue; | |
911 | ||
912 | /* iterate through all supported region sizes to find a match */ | |
913 | for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { | |
914 | resource_size_t region_size = | |
915 | ib_map->region_sizes[size_idx] * ib_map->size_unit; | |
916 | ||
917 | if (size != region_size) | |
918 | continue; | |
919 | ||
920 | if (!IS_ALIGNED(axi_addr, region_size) || | |
921 | !IS_ALIGNED(pci_addr, region_size)) { | |
922 | dev_err(dev, | |
923 | "axi %pap or pci %pap not aligned\n", | |
924 | &axi_addr, &pci_addr); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
928 | /* Match found! Program IARR and all IMAP windows. */ | |
929 | ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, | |
930 | ib_map->nr_windows, axi_addr, | |
931 | pci_addr, size); | |
932 | if (ret) | |
933 | goto err_ib; | |
934 | else | |
935 | return 0; | |
936 | ||
937 | } | |
938 | } | |
939 | ret = -EINVAL; | |
940 | ||
941 | err_ib: | |
942 | dev_err(dev, "unable to configure inbound mapping\n"); | |
943 | dev_err(dev, "axi %pap, pci %pap, res size %pap\n", | |
944 | &axi_addr, &pci_addr, &size); | |
945 | ||
946 | return ret; | |
947 | } | |
948 | ||
949 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
950 | struct device_node *node) | |
951 | { | |
952 | const int na = 3, ns = 2; | |
953 | int rlen; | |
954 | ||
955 | parser->node = node; | |
956 | parser->pna = of_n_addr_cells(node); | |
957 | parser->np = parser->pna + na + ns; | |
958 | ||
959 | parser->range = of_get_property(node, "dma-ranges", &rlen); | |
960 | if (!parser->range) | |
961 | return -ENOENT; | |
962 | ||
963 | parser->end = parser->range + rlen / sizeof(__be32); | |
964 | return 0; | |
965 | } | |
966 | ||
967 | static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) | |
968 | { | |
969 | struct of_pci_range range; | |
970 | struct of_pci_range_parser parser; | |
971 | int ret; | |
972 | ||
973 | /* Get the dma-ranges from DT */ | |
974 | ret = pci_dma_range_parser_init(&parser, pcie->dev->of_node); | |
975 | if (ret) | |
976 | return ret; | |
977 | ||
978 | for_each_of_pci_range(&parser, &range) { | |
979 | /* Each range entry corresponds to an inbound mapping region */ | |
980 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM); | |
981 | if (ret) | |
982 | return ret; | |
983 | } | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
787b3c4f RJ |
988 | static int iproce_pcie_get_msi(struct iproc_pcie *pcie, |
989 | struct device_node *msi_node, | |
990 | u64 *msi_addr) | |
991 | { | |
992 | struct device *dev = pcie->dev; | |
993 | int ret; | |
994 | struct resource res; | |
995 | ||
996 | /* | |
997 | * Check if 'msi-map' points to ARM GICv3 ITS, which is the only | |
998 | * supported external MSI controller that requires steering. | |
999 | */ | |
1000 | if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { | |
1001 | dev_err(dev, "unable to find compatible MSI controller\n"); | |
1002 | return -ENODEV; | |
1003 | } | |
1004 | ||
1005 | /* derive GITS_TRANSLATER address from GICv3 */ | |
1006 | ret = of_address_to_resource(msi_node, 0, &res); | |
1007 | if (ret < 0) { | |
1008 | dev_err(dev, "unable to obtain MSI controller resources\n"); | |
1009 | return ret; | |
1010 | } | |
1011 | ||
1012 | *msi_addr = res.start + GITS_TRANSLATER; | |
1013 | return 0; | |
1014 | } | |
1015 | ||
c7c44527 RJ |
1016 | static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1017 | { | |
1018 | int ret; | |
1019 | struct of_pci_range range; | |
1020 | ||
1021 | memset(&range, 0, sizeof(range)); | |
1022 | range.size = SZ_32K; | |
feacdb4a | 1023 | range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1); |
c7c44527 RJ |
1024 | |
1025 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO); | |
1026 | return ret; | |
1027 | } | |
1028 | ||
787b3c4f RJ |
1029 | static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1030 | { | |
1031 | u32 val; | |
1032 | ||
1033 | /* | |
1034 | * Program bits [43:13] of address of GITS_TRANSLATER register into | |
1035 | * bits [30:0] of the MSI base address register. In fact, in all iProc | |
1036 | * based SoCs, all I/O register bases are well below the 32-bit | |
1037 | * boundary, so we can safely assume bits [43:32] are always zeros. | |
1038 | */ | |
1039 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, | |
1040 | (u32)(msi_addr >> 13)); | |
1041 | ||
1042 | /* use a default 8K window size */ | |
1043 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); | |
1044 | ||
1045 | /* steering MSI to GICv3 ITS */ | |
1046 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); | |
1047 | val |= GIC_V3_CFG; | |
1048 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); | |
1049 | ||
1050 | /* | |
1051 | * Program bits [43:2] of address of GITS_TRANSLATER register into the | |
1052 | * iProc MSI address registers. | |
1053 | */ | |
1054 | msi_addr >>= 2; | |
1055 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, | |
1056 | upper_32_bits(msi_addr)); | |
1057 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, | |
1058 | lower_32_bits(msi_addr)); | |
1059 | ||
1060 | /* enable MSI */ | |
1061 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); | |
1062 | val |= MSI_ENABLE_CFG; | |
1063 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); | |
1064 | } | |
1065 | ||
1066 | static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, | |
1067 | struct device_node *msi_node) | |
1068 | { | |
1069 | struct device *dev = pcie->dev; | |
1070 | int ret; | |
1071 | u64 msi_addr; | |
1072 | ||
1073 | ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); | |
1074 | if (ret < 0) { | |
1075 | dev_err(dev, "msi steering failed\n"); | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | switch (pcie->type) { | |
c7c44527 RJ |
1080 | case IPROC_PCIE_PAXB_V2: |
1081 | ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | break; | |
787b3c4f RJ |
1085 | case IPROC_PCIE_PAXC_V2: |
1086 | iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr); | |
1087 | break; | |
1088 | default: | |
1089 | return -EINVAL; | |
1090 | } | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
3bc2b234 RJ |
1095 | static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) |
1096 | { | |
1097 | struct device_node *msi_node; | |
787b3c4f RJ |
1098 | int ret; |
1099 | ||
1100 | /* | |
1101 | * Either the "msi-parent" or the "msi-map" phandle needs to exist | |
1102 | * for us to obtain the MSI node. | |
1103 | */ | |
3bc2b234 RJ |
1104 | |
1105 | msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); | |
787b3c4f RJ |
1106 | if (!msi_node) { |
1107 | const __be32 *msi_map = NULL; | |
1108 | int len; | |
1109 | u32 phandle; | |
1110 | ||
1111 | msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); | |
1112 | if (!msi_map) | |
1113 | return -ENODEV; | |
1114 | ||
1115 | phandle = be32_to_cpup(msi_map + 1); | |
1116 | msi_node = of_find_node_by_phandle(phandle); | |
1117 | if (!msi_node) | |
1118 | return -ENODEV; | |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * Certain revisions of the iProc PCIe controller require additional | |
1123 | * configurations to steer the MSI writes towards an external MSI | |
1124 | * controller. | |
1125 | */ | |
1126 | if (pcie->need_msi_steer) { | |
1127 | ret = iproc_pcie_msi_steer(pcie, msi_node); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | } | |
3bc2b234 RJ |
1131 | |
1132 | /* | |
1133 | * If another MSI controller is being used, the call below should fail | |
1134 | * but that is okay | |
1135 | */ | |
1136 | return iproc_msi_init(pcie, msi_node); | |
1137 | } | |
1138 | ||
1139 | static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) | |
1140 | { | |
1141 | iproc_msi_exit(pcie); | |
1142 | } | |
1143 | ||
06324ede RJ |
1144 | static int iproc_pcie_rev_init(struct iproc_pcie *pcie) |
1145 | { | |
1146 | struct device *dev = pcie->dev; | |
1147 | unsigned int reg_idx; | |
1148 | const u16 *regs; | |
1149 | ||
1150 | switch (pcie->type) { | |
404349c5 RJ |
1151 | case IPROC_PCIE_PAXB_BCMA: |
1152 | regs = iproc_pcie_reg_paxb_bcma; | |
1153 | break; | |
06324ede RJ |
1154 | case IPROC_PCIE_PAXB: |
1155 | regs = iproc_pcie_reg_paxb; | |
538928fd | 1156 | pcie->has_apb_err_disable = true; |
4213e15c RJ |
1157 | if (pcie->need_ob_cfg) { |
1158 | pcie->ob_map = paxb_ob_map; | |
1159 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); | |
1160 | } | |
06324ede | 1161 | break; |
c7c44527 RJ |
1162 | case IPROC_PCIE_PAXB_V2: |
1163 | regs = iproc_pcie_reg_paxb_v2; | |
1164 | pcie->has_apb_err_disable = true; | |
1165 | if (pcie->need_ob_cfg) { | |
1166 | pcie->ob_map = paxb_v2_ob_map; | |
1167 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); | |
1168 | } | |
1169 | pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); | |
1170 | pcie->ib_map = paxb_v2_ib_map; | |
1171 | pcie->need_msi_steer = true; | |
1172 | break; | |
06324ede RJ |
1173 | case IPROC_PCIE_PAXC: |
1174 | regs = iproc_pcie_reg_paxc; | |
1175 | pcie->ep_is_internal = true; | |
1176 | break; | |
787b3c4f RJ |
1177 | case IPROC_PCIE_PAXC_V2: |
1178 | regs = iproc_pcie_reg_paxc_v2; | |
1179 | pcie->ep_is_internal = true; | |
1180 | pcie->need_msi_steer = true; | |
1181 | break; | |
06324ede RJ |
1182 | default: |
1183 | dev_err(dev, "incompatible iProc PCIe interface\n"); | |
1184 | return -EINVAL; | |
1185 | } | |
1186 | ||
1187 | pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, | |
1188 | sizeof(*pcie->reg_offsets), | |
1189 | GFP_KERNEL); | |
1190 | if (!pcie->reg_offsets) | |
1191 | return -ENOMEM; | |
1192 | ||
1193 | /* go through the register table and populate all valid registers */ | |
787b3c4f RJ |
1194 | pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? |
1195 | IPROC_PCIE_REG_INVALID : regs[0]; | |
06324ede RJ |
1196 | for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) |
1197 | pcie->reg_offsets[reg_idx] = regs[reg_idx] ? | |
1198 | regs[reg_idx] : IPROC_PCIE_REG_INVALID; | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
18c4342a | 1203 | int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) |
1fb37a81 | 1204 | { |
786aeccb | 1205 | struct device *dev; |
1fb37a81 | 1206 | int ret; |
8d9bfe37 | 1207 | void *sysdata; |
4d4836ab | 1208 | struct pci_bus *bus, *child; |
1fb37a81 | 1209 | |
786aeccb | 1210 | dev = pcie->dev; |
06324ede RJ |
1211 | |
1212 | ret = iproc_pcie_rev_init(pcie); | |
1213 | if (ret) { | |
1214 | dev_err(dev, "unable to initialize controller parameters\n"); | |
1215 | return ret; | |
1216 | } | |
1217 | ||
786aeccb | 1218 | ret = devm_request_pci_bus_resources(dev, res); |
c3245a56 BH |
1219 | if (ret) |
1220 | return ret; | |
1221 | ||
93972d18 ME |
1222 | ret = phy_init(pcie->phy); |
1223 | if (ret) { | |
786aeccb | 1224 | dev_err(dev, "unable to initialize PCIe PHY\n"); |
93972d18 ME |
1225 | return ret; |
1226 | } | |
1fb37a81 | 1227 | |
93972d18 ME |
1228 | ret = phy_power_on(pcie->phy); |
1229 | if (ret) { | |
786aeccb | 1230 | dev_err(dev, "unable to power on PCIe PHY\n"); |
93972d18 | 1231 | goto err_exit_phy; |
1fb37a81 RJ |
1232 | } |
1233 | ||
1234 | iproc_pcie_reset(pcie); | |
1235 | ||
e99a187b RJ |
1236 | if (pcie->need_ob_cfg) { |
1237 | ret = iproc_pcie_map_ranges(pcie, res); | |
1238 | if (ret) { | |
786aeccb | 1239 | dev_err(dev, "map failed\n"); |
e99a187b RJ |
1240 | goto err_power_off_phy; |
1241 | } | |
1242 | } | |
1243 | ||
dd9d4e74 RJ |
1244 | ret = iproc_pcie_map_dma_ranges(pcie); |
1245 | if (ret && ret != -ENOENT) | |
1246 | goto err_power_off_phy; | |
1247 | ||
8d9bfe37 | 1248 | #ifdef CONFIG_ARM |
1fb37a81 | 1249 | pcie->sysdata.private_data = pcie; |
8d9bfe37 RJ |
1250 | sysdata = &pcie->sysdata; |
1251 | #else | |
1252 | sysdata = pcie; | |
1253 | #endif | |
1fb37a81 | 1254 | |
786aeccb | 1255 | bus = pci_create_root_bus(dev, 0, &iproc_pcie_ops, sysdata, res); |
1fb37a81 | 1256 | if (!bus) { |
786aeccb | 1257 | dev_err(dev, "unable to create PCI root bus\n"); |
1fb37a81 RJ |
1258 | ret = -ENOMEM; |
1259 | goto err_power_off_phy; | |
1260 | } | |
1261 | pcie->root_bus = bus; | |
1262 | ||
1263 | ret = iproc_pcie_check_link(pcie, bus); | |
1264 | if (ret) { | |
786aeccb | 1265 | dev_err(dev, "no PCIe EP device detected\n"); |
1fb37a81 RJ |
1266 | goto err_rm_root_bus; |
1267 | } | |
1268 | ||
1269 | iproc_pcie_enable(pcie); | |
1270 | ||
3bc2b234 RJ |
1271 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
1272 | if (iproc_pcie_msi_enable(pcie)) | |
786aeccb | 1273 | dev_info(dev, "not using iProc MSI\n"); |
3bc2b234 | 1274 | |
1fb37a81 RJ |
1275 | pci_scan_child_bus(bus); |
1276 | pci_assign_unassigned_bus_resources(bus); | |
ffbd7968 AG |
1277 | |
1278 | if (pcie->map_irq) | |
1279 | pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); | |
1280 | ||
4d4836ab JM |
1281 | list_for_each_entry(child, &bus->children, node) |
1282 | pcie_bus_configure_settings(child); | |
1283 | ||
1fb37a81 RJ |
1284 | pci_bus_add_devices(bus); |
1285 | ||
1286 | return 0; | |
1287 | ||
1288 | err_rm_root_bus: | |
1289 | pci_stop_root_bus(bus); | |
1290 | pci_remove_root_bus(bus); | |
1291 | ||
1292 | err_power_off_phy: | |
93972d18 | 1293 | phy_power_off(pcie->phy); |
1fb37a81 | 1294 | err_exit_phy: |
93972d18 | 1295 | phy_exit(pcie->phy); |
1fb37a81 RJ |
1296 | return ret; |
1297 | } | |
1298 | EXPORT_SYMBOL(iproc_pcie_setup); | |
1299 | ||
1300 | int iproc_pcie_remove(struct iproc_pcie *pcie) | |
1301 | { | |
1302 | pci_stop_root_bus(pcie->root_bus); | |
1303 | pci_remove_root_bus(pcie->root_bus); | |
1304 | ||
3bc2b234 RJ |
1305 | iproc_pcie_msi_disable(pcie); |
1306 | ||
93972d18 ME |
1307 | phy_power_off(pcie->phy); |
1308 | phy_exit(pcie->phy); | |
1fb37a81 RJ |
1309 | |
1310 | return 0; | |
1311 | } | |
1312 | EXPORT_SYMBOL(iproc_pcie_remove); | |
1313 | ||
1314 | MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); | |
1315 | MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver"); | |
1316 | MODULE_LICENSE("GPL v2"); |