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PCI: designware: Add dw_pcie prefix before cfg_read/write
[linux-2.6-block.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
340cba60
JH		 20#include <linux/pci.h>
21#include <linux/pci_regs.h>
340cba60
JH		 22#include <linux/types.h>
23
4b1ced84 24#include "pcie-designware.h"
340cba60
JH		 25
26/* Synopsis specific PCIE configuration registers */
27#define PCIE_PORT_LINK_CONTROL 0x710
28#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 29#define PORT_LINK_MODE_1_LANES (0x1 << 16)
30#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60
JH		 31#define PORT_LINK_MODE_4_LANES (0x7 << 16)
32
33#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
34#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
35#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
4b1ced84
JH		 36#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
37#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
38#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
340cba60
JH		 39
40#define PCIE_MSI_ADDR_LO 0x820
41#define PCIE_MSI_ADDR_HI 0x824
42#define PCIE_MSI_INTR0_ENABLE 0x828
43#define PCIE_MSI_INTR0_MASK 0x82C
44#define PCIE_MSI_INTR0_STATUS 0x830
45
46#define PCIE_ATU_VIEWPORT 0x900
47#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
48#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
49#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
50#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
51#define PCIE_ATU_CR1 0x904
52#define PCIE_ATU_TYPE_MEM (0x0 << 0)
53#define PCIE_ATU_TYPE_IO (0x2 << 0)
54#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
55#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
56#define PCIE_ATU_CR2 0x908
57#define PCIE_ATU_ENABLE (0x1 << 31)
58#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
59#define PCIE_ATU_LOWER_BASE 0x90C
60#define PCIE_ATU_UPPER_BASE 0x910
61#define PCIE_ATU_LIMIT 0x914
62#define PCIE_ATU_LOWER_TARGET 0x918
63#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
64#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
65#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
66#define PCIE_ATU_UPPER_TARGET 0x91C
67
4b1ced84
JH		 68static struct hw_pci dw_pci;
69
73e40850 70static unsigned long global_io_offset;
340cba60
JH		 71
72static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
73{
74 return sys->private_data;
75}
76
a01ef59e 77int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
340cba60
JH		 78{
79 *val = readl(addr);
80
81 if (size == 1)
82 *val = (*val >> (8 * (where & 3))) & 0xff;
83 else if (size == 2)
84 *val = (*val >> (8 * (where & 3))) & 0xffff;
85 else if (size != 4)
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87
88 return PCIBIOS_SUCCESSFUL;
89}
90
a01ef59e 91int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
340cba60
JH		 92{
93 if (size == 4)
94 writel(val, addr);
95 else if (size == 2)
96 writew(val, addr + (where & 2));
97 else if (size == 1)
98 writeb(val, addr + (where & 3));
99 else
100 return PCIBIOS_BAD_REGISTER_NUMBER;
101
102 return PCIBIOS_SUCCESSFUL;
103}
104
f7b7868c 105static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 106{
4b1ced84 107 if (pp->ops->readl_rc)
f7b7868c 108 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 109 else
f7b7868c 110 *val = readl(pp->dbi_base + reg);
340cba60
JH		 111}
112
f7b7868c 113static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 114{
4b1ced84 115 if (pp->ops->writel_rc)
f7b7868c 116 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 117 else
f7b7868c 118 writel(val, pp->dbi_base + reg);
340cba60
JH		 119}
120
73e40850
BH		 121static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
122 u32 *val)
340cba60
JH		 123{
124 int ret;
125
4b1ced84
JH		 126 if (pp->ops->rd_own_conf)
127 ret = pp->ops->rd_own_conf(pp, where, size, val);
128 else
a01ef59e
PA		 129 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
130 size, val);
4b1ced84 131
340cba60
JH		 132 return ret;
133}
134
73e40850
BH		 135static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
136 u32 val)
340cba60
JH		 137{
138 int ret;
139
4b1ced84
JH		 140 if (pp->ops->wr_own_conf)
141 ret = pp->ops->wr_own_conf(pp, where, size, val);
142 else
a01ef59e
PA		 143 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
144 size, val);
4b1ced84 145
340cba60
JH		 146 return ret;
147}
148
f342d940
JH		 149static struct irq_chip dw_msi_irq_chip = {
150 .name = "PCI-MSI",
151 .irq_enable = unmask_msi_irq,
152 .irq_disable = mask_msi_irq,
153 .irq_mask = mask_msi_irq,
154 .irq_unmask = unmask_msi_irq,
155};
156
157/* MSI int handler */
158void dw_handle_msi_irq(struct pcie_port *pp)
159{
160 unsigned long val;
904d0e78 161 int i, pos, irq;
f342d940
JH		 162
163 for (i = 0; i < MAX_MSI_CTRLS; i++) {
164 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
165 (u32 *)&val);
166 if (val) {
167 pos = 0;
168 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 169 irq = irq_find_mapping(pp->irq_domain,
170 i * 32 + pos);
ca165892
HH		 171 dw_pcie_wr_own_conf(pp,
172 PCIE_MSI_INTR0_STATUS + i * 12,
173 4, 1 << pos);
904d0e78 174 generic_handle_irq(irq);
f342d940
JH		 175 pos++;
176 }
177 }
f342d940
JH		 178 }
179}
180
181void dw_pcie_msi_init(struct pcie_port *pp)
182{
183 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
184
185 /* program the msi_data */
186 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
187 virt_to_phys((void *)pp->msi_data));
188 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
189}
190
191static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
192{
193 int flag = 1;
194
195 do {
196 pos = find_next_zero_bit(pp->msi_irq_in_use,
197 MAX_MSI_IRQS, pos);
198 /*if you have reached to the end then get out from here.*/
199 if (pos == MAX_MSI_IRQS)
200 return -ENOSPC;
201 /*
202 * Check if this position is at correct offset.nvec is always a
f7625980 203 * power of two. pos0 must be nvec bit aligned.
f342d940
JH		 204 */
205 if (pos % msgvec)
206 pos += msgvec - (pos % msgvec);
207 else
208 flag = 0;
209 } while (flag);
210
211 *pos0 = pos;
212 return 0;
213}
214
be3f48cb
BEN		 215static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
216 unsigned int nvec, unsigned int pos)
217{
218 unsigned int i, res, bit, val;
219
0b8cfb6a 220 for (i = 0; i < nvec; i++) {
be3f48cb
BEN		 221 irq_set_msi_desc_off(irq_base, i, NULL);
222 clear_bit(pos + i, pp->msi_irq_in_use);
223 /* Disable corresponding interrupt on MSI interrupt controller */
224 res = ((pos + i) / 32) * 12;
225 bit = (pos + i) % 32;
226 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
227 val &= ~(1 << bit);
228 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
be3f48cb
BEN		 229 }
230}
231
f342d940
JH		 232static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
233{
234 int res, bit, irq, pos0, pos1, i;
235 u32 val;
236 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
237
238 if (!pp) {
239 BUG();
240 return -EINVAL;
241 }
242
243 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
244 MAX_MSI_IRQS);
245 if (pos0 % no_irqs) {
246 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
247 goto no_valid_irq;
248 }
249 if (no_irqs > 1) {
250 pos1 = find_next_bit(pp->msi_irq_in_use,
251 MAX_MSI_IRQS, pos0);
252 /* there must be nvec number of consecutive free bits */
253 while ((pos1 - pos0) < no_irqs) {
254 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
255 goto no_valid_irq;
256 pos1 = find_next_bit(pp->msi_irq_in_use,
257 MAX_MSI_IRQS, pos0);
258 }
259 }
260
904d0e78
PA		 261 irq = irq_find_mapping(pp->irq_domain, pos0);
262 if (!irq)
f342d940
JH		 263 goto no_valid_irq;
264
be3f48cb
BEN		 265 /*
266 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
267 * descs so there is no need to allocate descs here. We can therefore
268 * assume that if irq_find_mapping above returns non-zero, then the
269 * descs are also successfully allocated.
270 */
271
0b8cfb6a 272 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 273 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
274 clear_irq_range(pp, irq, i, pos0);
275 goto no_valid_irq;
276 }
f342d940 277 set_bit(pos0 + i, pp->msi_irq_in_use);
f342d940
JH		 278 /*Enable corresponding interrupt in MSI interrupt controller */
279 res = ((pos0 + i) / 32) * 12;
280 bit = (pos0 + i) % 32;
281 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
282 val |= 1 << bit;
283 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
f342d940
JH		 284 }
285
286 *pos = pos0;
287 return irq;
288
289no_valid_irq:
290 *pos = pos0;
291 return -ENOSPC;
292}
293
294static void clear_irq(unsigned int irq)
295{
be3f48cb 296 unsigned int pos, nvec;
f342d940
JH		 297 struct irq_desc *desc;
298 struct msi_desc *msi;
299 struct pcie_port *pp;
904d0e78 300 struct irq_data *data = irq_get_irq_data(irq);
f342d940
JH		 301
302 /* get the port structure */
303 desc = irq_to_desc(irq);
304 msi = irq_desc_get_msi_desc(desc);
305 pp = sys_to_pcie(msi->dev->bus->sysdata);
306 if (!pp) {
307 BUG();
308 return;
309 }
310
be3f48cb 311 /* undo what was done in assign_irq */
904d0e78 312 pos = data->hwirq;
be3f48cb 313 nvec = 1 << msi->msi_attrib.multiple;
f342d940 314
be3f48cb 315 clear_irq_range(pp, irq, nvec, pos);
f342d940 316
be3f48cb
BEN		 317 /* all irqs cleared; reset attributes */
318 msi->irq = 0;
319 msi->msi_attrib.multiple = 0;
f342d940
JH		 320}
321
322static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
323 struct msi_desc *desc)
324{
325 int irq, pos, msgvec;
326 u16 msg_ctr;
327 struct msi_msg msg;
328 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
329
330 if (!pp) {
331 BUG();
332 return -EINVAL;
333 }
334
335 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
336 &msg_ctr);
337 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
338 if (msgvec == 0)
339 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
340 if (msgvec > 5)
341 msgvec = 0;
342
343 irq = assign_irq((1 << msgvec), desc, &pos);
344 if (irq < 0)
345 return irq;
346
64989e73
BEN		 347 /*
348 * write_msi_msg() will update PCI_MSI_FLAGS so there is
349 * no need to explicitly call pci_write_config_word().
350 */
f342d940
JH		 351 desc->msi_attrib.multiple = msgvec;
352
353 msg.address_lo = virt_to_phys((void *)pp->msi_data);
354 msg.address_hi = 0x0;
355 msg.data = pos;
356 write_msi_msg(irq, &msg);
357
358 return 0;
359}
360
361static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
362{
363 clear_irq(irq);
364}
365
366static struct msi_chip dw_pcie_msi_chip = {
367 .setup_irq = dw_msi_setup_irq,
368 .teardown_irq = dw_msi_teardown_irq,
369};
370
4b1ced84
JH		 371int dw_pcie_link_up(struct pcie_port *pp)
372{
373 if (pp->ops->link_up)
374 return pp->ops->link_up(pp);
375 else
376 return 0;
377}
378
f342d940
JH		 379static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
380 irq_hw_number_t hwirq)
381{
382 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
383 irq_set_chip_data(irq, domain->host_data);
384 set_irq_flags(irq, IRQF_VALID);
385
386 return 0;
387}
388
389static const struct irq_domain_ops msi_domain_ops = {
390 .map = dw_pcie_msi_map,
391};
392
4b1ced84
JH		 393int __init dw_pcie_host_init(struct pcie_port *pp)
394{
395 struct device_node *np = pp->dev->of_node;
396 struct of_pci_range range;
397 struct of_pci_range_parser parser;
398 u32 val;
904d0e78 399 int i;
f342d940 400
4b1ced84
JH		 401 if (of_pci_range_parser_init(&parser, np)) {
402 dev_err(pp->dev, "missing ranges property\n");
403 return -EINVAL;
404 }
405
406 /* Get the I/O and memory ranges from DT */
407 for_each_of_pci_range(&parser, &range) {
408 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
409 if (restype == IORESOURCE_IO) {
410 of_pci_range_to_resource(&range, np, &pp->io);
411 pp->io.name = "I/O";
412 pp->io.start = max_t(resource_size_t,
413 PCIBIOS_MIN_IO,
414 range.pci_addr + global_io_offset);
415 pp->io.end = min_t(resource_size_t,
416 IO_SPACE_LIMIT,
417 range.pci_addr + range.size
418 + global_io_offset);
419 pp->config.io_size = resource_size(&pp->io);
420 pp->config.io_bus_addr = range.pci_addr;
421 }
422 if (restype == IORESOURCE_MEM) {
423 of_pci_range_to_resource(&range, np, &pp->mem);
424 pp->mem.name = "MEM";
425 pp->config.mem_size = resource_size(&pp->mem);
426 pp->config.mem_bus_addr = range.pci_addr;
427 }
428 if (restype == 0) {
429 of_pci_range_to_resource(&range, np, &pp->cfg);
430 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
431 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
432 }
433 }
434
435 if (!pp->dbi_base) {
436 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
437 resource_size(&pp->cfg));
438 if (!pp->dbi_base) {
439 dev_err(pp->dev, "error with ioremap\n");
440 return -ENOMEM;
441 }
442 }
443
444 pp->cfg0_base = pp->cfg.start;
445 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
446 pp->io_base = pp->io.start;
447 pp->mem_base = pp->mem.start;
448
449 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
450 pp->config.cfg0_size);
451 if (!pp->va_cfg0_base) {
452 dev_err(pp->dev, "error with ioremap in function\n");
453 return -ENOMEM;
454 }
455 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
456 pp->config.cfg1_size);
457 if (!pp->va_cfg1_base) {
458 dev_err(pp->dev, "error with ioremap\n");
459 return -ENOMEM;
460 }
461
462 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
463 dev_err(pp->dev, "Failed to parse the number of lanes\n");
464 return -EINVAL;
465 }
466
f342d940 467 if (IS_ENABLED(CONFIG_PCI_MSI)) {
904d0e78 468 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
f342d940
JH		 469 MAX_MSI_IRQS, &msi_domain_ops,
470 &dw_pcie_msi_chip);
904d0e78 471 if (!pp->irq_domain) {
f342d940
JH		 472 dev_err(pp->dev, "irq domain init failed\n");
473 return -ENXIO;
474 }
475
904d0e78
PA		 476 for (i = 0; i < MAX_MSI_IRQS; i++)
477 irq_create_mapping(pp->irq_domain, i);
f342d940
JH		 478 }
479
4b1ced84
JH		 480 if (pp->ops->host_init)
481 pp->ops->host_init(pp);
482
483 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
484
485 /* program correct class for RC */
486 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
487
488 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
489 val |= PORT_LOGIC_SPEED_CHANGE;
490 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
491
492 dw_pci.nr_controllers = 1;
493 dw_pci.private_data = (void **)&pp;
494
495 pci_common_init(&dw_pci);
496 pci_assign_unassigned_resources();
497#ifdef CONFIG_PCI_DOMAINS
498 dw_pci.domain++;
499#endif
500
501 return 0;
502}
503
504static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
340cba60 505{
340cba60 506 /* Program viewport 0 : OUTBOUND : CFG0 */
f7b7868c
SJ		 507 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
508 PCIE_ATU_VIEWPORT);
509 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
510 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 511 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
f7b7868c
SJ		 512 PCIE_ATU_LIMIT);
513 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
514 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
515 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
516 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 517}
518
4b1ced84 519static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
340cba60 520{
340cba60 521 /* Program viewport 1 : OUTBOUND : CFG1 */
f7b7868c
SJ		 522 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
523 PCIE_ATU_VIEWPORT);
524 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
525 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
526 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
527 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 528 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
f7b7868c
SJ		 529 PCIE_ATU_LIMIT);
530 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
531 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
340cba60
JH		 532}
533
4b1ced84 534static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
340cba60 535{
340cba60 536 /* Program viewport 0 : OUTBOUND : MEM */
f7b7868c
SJ		 537 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
538 PCIE_ATU_VIEWPORT);
539 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
540 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
541 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
542 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 543 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
f7b7868c
SJ		 544 PCIE_ATU_LIMIT);
545 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 546 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
f7b7868c 547 PCIE_ATU_UPPER_TARGET);
340cba60
JH		 548}
549
4b1ced84 550static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
340cba60 551{
340cba60 552 /* Program viewport 1 : OUTBOUND : IO */
f7b7868c
SJ		 553 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
554 PCIE_ATU_VIEWPORT);
555 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
556 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
557 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
558 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 559 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
f7b7868c
SJ		 560 PCIE_ATU_LIMIT);
561 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 562 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
f7b7868c 563 PCIE_ATU_UPPER_TARGET);
340cba60
JH		 564}
565
4b1ced84 566static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 567 u32 devfn, int where, int size, u32 *val)
568{
569 int ret = PCIBIOS_SUCCESSFUL;
570 u32 address, busdev;
571
572 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
573 PCIE_ATU_FUNC(PCI_FUNC(devfn));
574 address = where & ~0x3;
575
576 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 577 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 578 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
579 val);
4b1ced84 580 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 581 } else {
4b1ced84 582 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 583 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
584 val);
4b1ced84 585 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 586 }
587
588 return ret;
589}
590
4b1ced84 591static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 592 u32 devfn, int where, int size, u32 val)
593{
594 int ret = PCIBIOS_SUCCESSFUL;
595 u32 address, busdev;
596
597 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
598 PCIE_ATU_FUNC(PCI_FUNC(devfn));
599 address = where & ~0x3;
600
601 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 602 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 603 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
604 val);
4b1ced84 605 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 606 } else {
4b1ced84 607 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 608 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
609 val);
4b1ced84 610 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 611 }
612
613 return ret;
614}
615
340cba60 616
4b1ced84 617static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 618 struct pci_bus *bus, int dev)
619{
620 /* If there is no link, then there is no device */
621 if (bus->number != pp->root_bus_nr) {
4b1ced84 622 if (!dw_pcie_link_up(pp))
340cba60
JH		 623 return 0;
624 }
625
626 /* access only one slot on each root port */
627 if (bus->number == pp->root_bus_nr && dev > 0)
628 return 0;
629
630 /*
631 * do not read more than one device on the bus directly attached
632 * to RC's (Virtual Bridge's) DS side.
633 */
634 if (bus->primary == pp->root_bus_nr && dev > 0)
635 return 0;
636
637 return 1;
638}
639
4b1ced84 640static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 641 int size, u32 *val)
642{
643 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
644 unsigned long flags;
645 int ret;
646
647 if (!pp) {
648 BUG();
649 return -EINVAL;
650 }
651
4b1ced84 652 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 653 *val = 0xffffffff;
654 return PCIBIOS_DEVICE_NOT_FOUND;
655 }
656
657 spin_lock_irqsave(&pp->conf_lock, flags);
658 if (bus->number != pp->root_bus_nr)
4b1ced84 659 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 660 where, size, val);
661 else
4b1ced84 662 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 663 spin_unlock_irqrestore(&pp->conf_lock, flags);
664
665 return ret;
666}
667
4b1ced84 668static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 669 int where, int size, u32 val)
670{
671 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
672 unsigned long flags;
673 int ret;
674
675 if (!pp) {
676 BUG();
677 return -EINVAL;
678 }
679
4b1ced84 680 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 681 return PCIBIOS_DEVICE_NOT_FOUND;
682
683 spin_lock_irqsave(&pp->conf_lock, flags);
684 if (bus->number != pp->root_bus_nr)
4b1ced84 685 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 686 where, size, val);
687 else
4b1ced84 688 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 689 spin_unlock_irqrestore(&pp->conf_lock, flags);
690
691 return ret;
692}
693
4b1ced84
JH		 694static struct pci_ops dw_pcie_ops = {
695 .read = dw_pcie_rd_conf,
696 .write = dw_pcie_wr_conf,
340cba60
JH		 697};
698
73e40850 699static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 700{
701 struct pcie_port *pp;
702
703 pp = sys_to_pcie(sys);
704
705 if (!pp)
706 return 0;
707
708 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
709 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
710 pci_ioremap_io(sys->io_offset, pp->io.start);
711 global_io_offset += SZ_64K;
712 pci_add_resource_offset(&sys->resources, &pp->io,
713 sys->io_offset);
714 }
715
716 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
717 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
718
719 return 1;
720}
721
73e40850 722static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 723{
724 struct pci_bus *bus;
725 struct pcie_port *pp = sys_to_pcie(sys);
726
727 if (pp) {
728 pp->root_bus_nr = sys->busnr;
4b1ced84 729 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
340cba60
JH		 730 sys, &sys->resources);
731 } else {
732 bus = NULL;
733 BUG();
734 }
735
736 return bus;
737}
738
73e40850 739static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 740{
741 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
742
743 return pp->irq;
744}
745
f342d940
JH		 746static void dw_pcie_add_bus(struct pci_bus *bus)
747{
748 if (IS_ENABLED(CONFIG_PCI_MSI)) {
749 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
750
751 dw_pcie_msi_chip.dev = pp->dev;
752 bus->msi = &dw_pcie_msi_chip;
753 }
754}
755
4b1ced84
JH		 756static struct hw_pci dw_pci = {
757 .setup = dw_pcie_setup,
758 .scan = dw_pcie_scan_bus,
759 .map_irq = dw_pcie_map_irq,
f342d940 760 .add_bus = dw_pcie_add_bus,
340cba60
JH		 761};
762
4b1ced84 763void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60
JH		 764{
765 struct pcie_port_info *config = &pp->config;
340cba60
JH		 766 u32 val;
767 u32 membase;
768 u32 memlimit;
769
770 /* set the number of lines as 4 */
f7b7868c 771 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 772 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 773 switch (pp->lanes) {
774 case 1:
775 val |= PORT_LINK_MODE_1_LANES;
776 break;
777 case 2:
778 val |= PORT_LINK_MODE_2_LANES;
779 break;
780 case 4:
781 val |= PORT_LINK_MODE_4_LANES;
782 break;
783 }
f7b7868c 784 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 785
786 /* set link width speed control register */
f7b7868c 787 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 788 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 789 switch (pp->lanes) {
790 case 1:
791 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
792 break;
793 case 2:
794 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
795 break;
796 case 4:
797 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
798 break;
799 }
f7b7868c 800 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 801
802 /* setup RC BARs */
f7b7868c
SJ		 803 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
804 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
340cba60
JH		 805
806 /* setup interrupt pins */
f7b7868c 807 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 808 val &= 0xffff00ff;
809 val |= 0x00000100;
f7b7868c 810 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 811
812 /* setup bus numbers */
f7b7868c 813 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 814 val &= 0xff000000;
815 val |= 0x00010100;
f7b7868c 816 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 817
818 /* setup memory base, memory limit */
819 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
820 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
821 val = memlimit | membase;
f7b7868c 822 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 823
824 /* setup command register */
f7b7868c 825 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 826 val &= 0xffff0000;
827 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
828 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 829 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 830}
340cba60
JH		 831
832MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 833MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 834MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)