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PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
[linux-2.6-block.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
804f57b1 20#include <linux/of_pci.h>
340cba60
JH		 21#include <linux/pci.h>
22#include <linux/pci_regs.h>
4dd964df 23#include <linux/platform_device.h>
340cba60
JH		 24#include <linux/types.h>
25
4b1ced84 26#include "pcie-designware.h"
340cba60
JH		 27
28/* Synopsis specific PCIE configuration registers */
29#define PCIE_PORT_LINK_CONTROL 0x710
30#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 31#define PORT_LINK_MODE_1_LANES (0x1 << 16)
32#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60
JH		 33#define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
4b1ced84
JH		 38#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
340cba60
JH		 41
42#define PCIE_MSI_ADDR_LO 0x820
43#define PCIE_MSI_ADDR_HI 0x824
44#define PCIE_MSI_INTR0_ENABLE 0x828
45#define PCIE_MSI_INTR0_MASK 0x82C
46#define PCIE_MSI_INTR0_STATUS 0x830
47
48#define PCIE_ATU_VIEWPORT 0x900
49#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53#define PCIE_ATU_CR1 0x904
54#define PCIE_ATU_TYPE_MEM (0x0 << 0)
55#define PCIE_ATU_TYPE_IO (0x2 << 0)
56#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58#define PCIE_ATU_CR2 0x908
59#define PCIE_ATU_ENABLE (0x1 << 31)
60#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61#define PCIE_ATU_LOWER_BASE 0x90C
62#define PCIE_ATU_UPPER_BASE 0x910
63#define PCIE_ATU_LIMIT 0x914
64#define PCIE_ATU_LOWER_TARGET 0x918
65#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68#define PCIE_ATU_UPPER_TARGET 0x91C
69
4b1ced84
JH		 70static struct hw_pci dw_pci;
71
73e40850 72static unsigned long global_io_offset;
340cba60
JH		 73
74static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75{
76 return sys->private_data;
77}
78
a01ef59e 79int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
340cba60
JH		 80{
81 *val = readl(addr);
82
83 if (size == 1)
84 *val = (*val >> (8 * (where & 3))) & 0xff;
85 else if (size == 2)
86 *val = (*val >> (8 * (where & 3))) & 0xffff;
87 else if (size != 4)
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 return PCIBIOS_SUCCESSFUL;
91}
92
a01ef59e 93int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
340cba60
JH		 94{
95 if (size == 4)
96 writel(val, addr);
97 else if (size == 2)
98 writew(val, addr + (where & 2));
99 else if (size == 1)
100 writeb(val, addr + (where & 3));
101 else
102 return PCIBIOS_BAD_REGISTER_NUMBER;
103
104 return PCIBIOS_SUCCESSFUL;
105}
106
f7b7868c 107static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 108{
4b1ced84 109 if (pp->ops->readl_rc)
f7b7868c 110 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 111 else
f7b7868c 112 *val = readl(pp->dbi_base + reg);
340cba60
JH		 113}
114
f7b7868c 115static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 116{
4b1ced84 117 if (pp->ops->writel_rc)
f7b7868c 118 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 119 else
f7b7868c 120 writel(val, pp->dbi_base + reg);
340cba60
JH		 121}
122
73e40850
BH		 123static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
124 u32 *val)
340cba60
JH		 125{
126 int ret;
127
4b1ced84
JH		 128 if (pp->ops->rd_own_conf)
129 ret = pp->ops->rd_own_conf(pp, where, size, val);
130 else
a01ef59e
PA		 131 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
132 size, val);
4b1ced84 133
340cba60
JH		 134 return ret;
135}
136
73e40850
BH		 137static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
138 u32 val)
340cba60
JH		 139{
140 int ret;
141
4b1ced84
JH		 142 if (pp->ops->wr_own_conf)
143 ret = pp->ops->wr_own_conf(pp, where, size, val);
144 else
a01ef59e
PA		 145 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
146 size, val);
4b1ced84 147
340cba60
JH		 148 return ret;
149}
150
f342d940
JH		 151static struct irq_chip dw_msi_irq_chip = {
152 .name = "PCI-MSI",
153 .irq_enable = unmask_msi_irq,
154 .irq_disable = mask_msi_irq,
155 .irq_mask = mask_msi_irq,
156 .irq_unmask = unmask_msi_irq,
157};
158
159/* MSI int handler */
7f4f16ee 160irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
f342d940
JH		 161{
162 unsigned long val;
904d0e78 163 int i, pos, irq;
7f4f16ee 164 irqreturn_t ret = IRQ_NONE;
f342d940
JH		 165
166 for (i = 0; i < MAX_MSI_CTRLS; i++) {
167 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
168 (u32 *)&val);
169 if (val) {
7f4f16ee 170 ret = IRQ_HANDLED;
f342d940
JH		 171 pos = 0;
172 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 173 irq = irq_find_mapping(pp->irq_domain,
174 i * 32 + pos);
ca165892
HH		 175 dw_pcie_wr_own_conf(pp,
176 PCIE_MSI_INTR0_STATUS + i * 12,
177 4, 1 << pos);
904d0e78 178 generic_handle_irq(irq);
f342d940
JH		 179 pos++;
180 }
181 }
f342d940 182 }
7f4f16ee
LS		 183
184 return ret;
f342d940
JH		 185}
186
187void dw_pcie_msi_init(struct pcie_port *pp)
188{
189 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
190
191 /* program the msi_data */
192 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
193 virt_to_phys((void *)pp->msi_data));
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
195}
196
197static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
198{
199 int flag = 1;
200
201 do {
202 pos = find_next_zero_bit(pp->msi_irq_in_use,
203 MAX_MSI_IRQS, pos);
204 /*if you have reached to the end then get out from here.*/
205 if (pos == MAX_MSI_IRQS)
206 return -ENOSPC;
207 /*
208 * Check if this position is at correct offset.nvec is always a
f7625980 209 * power of two. pos0 must be nvec bit aligned.
f342d940
JH		 210 */
211 if (pos % msgvec)
212 pos += msgvec - (pos % msgvec);
213 else
214 flag = 0;
215 } while (flag);
216
217 *pos0 = pos;
218 return 0;
219}
220
2f37c5a8
MK		 221static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
222{
223 unsigned int res, bit, val;
224
225 res = (irq / 32) * 12;
226 bit = irq % 32;
227 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
228 val &= ~(1 << bit);
229 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
230}
231
be3f48cb 232static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
58275f2f 233 unsigned int nvec, unsigned int pos)
be3f48cb 234{
2f37c5a8 235 unsigned int i;
be3f48cb 236
0b8cfb6a 237 for (i = 0; i < nvec; i++) {
be3f48cb
BEN		 238 irq_set_msi_desc_off(irq_base, i, NULL);
239 clear_bit(pos + i, pp->msi_irq_in_use);
58275f2f 240 /* Disable corresponding interrupt on MSI controller */
2f37c5a8
MK		 241 if (pp->ops->msi_clear_irq)
242 pp->ops->msi_clear_irq(pp, pos + i);
243 else
244 dw_pcie_msi_clear_irq(pp, pos + i);
be3f48cb
BEN		 245 }
246}
247
2f37c5a8
MK		 248static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
249{
250 unsigned int res, bit, val;
251
252 res = (irq / 32) * 12;
253 bit = irq % 32;
254 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
255 val |= 1 << bit;
256 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
257}
258
f342d940
JH		 259static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
260{
2f37c5a8 261 int irq, pos0, pos1, i;
f342d940
JH		 262 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
263
264 if (!pp) {
265 BUG();
266 return -EINVAL;
267 }
268
269 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
270 MAX_MSI_IRQS);
271 if (pos0 % no_irqs) {
272 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
273 goto no_valid_irq;
274 }
275 if (no_irqs > 1) {
276 pos1 = find_next_bit(pp->msi_irq_in_use,
277 MAX_MSI_IRQS, pos0);
278 /* there must be nvec number of consecutive free bits */
279 while ((pos1 - pos0) < no_irqs) {
280 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
281 goto no_valid_irq;
282 pos1 = find_next_bit(pp->msi_irq_in_use,
283 MAX_MSI_IRQS, pos0);
284 }
285 }
286
904d0e78
PA		 287 irq = irq_find_mapping(pp->irq_domain, pos0);
288 if (!irq)
f342d940
JH		 289 goto no_valid_irq;
290
be3f48cb
BEN		 291 /*
292 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
293 * descs so there is no need to allocate descs here. We can therefore
294 * assume that if irq_find_mapping above returns non-zero, then the
295 * descs are also successfully allocated.
296 */
297
0b8cfb6a 298 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 299 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
300 clear_irq_range(pp, irq, i, pos0);
301 goto no_valid_irq;
302 }
f342d940 303 set_bit(pos0 + i, pp->msi_irq_in_use);
f342d940 304 /*Enable corresponding interrupt in MSI interrupt controller */
2f37c5a8
MK		 305 if (pp->ops->msi_set_irq)
306 pp->ops->msi_set_irq(pp, pos0 + i);
307 else
308 dw_pcie_msi_set_irq(pp, pos0 + i);
f342d940
JH		 309 }
310
311 *pos = pos0;
312 return irq;
313
314no_valid_irq:
315 *pos = pos0;
316 return -ENOSPC;
317}
318
319static void clear_irq(unsigned int irq)
320{
be3f48cb 321 unsigned int pos, nvec;
f342d940
JH		 322 struct msi_desc *msi;
323 struct pcie_port *pp;
904d0e78 324 struct irq_data *data = irq_get_irq_data(irq);
f342d940
JH		 325
326 /* get the port structure */
f7bfca6d 327 msi = irq_data_get_msi(data);
f342d940
JH		 328 pp = sys_to_pcie(msi->dev->bus->sysdata);
329 if (!pp) {
330 BUG();
331 return;
332 }
333
be3f48cb 334 /* undo what was done in assign_irq */
904d0e78 335 pos = data->hwirq;
be3f48cb 336 nvec = 1 << msi->msi_attrib.multiple;
f342d940 337
be3f48cb 338 clear_irq_range(pp, irq, nvec, pos);
f342d940 339
be3f48cb
BEN		 340 /* all irqs cleared; reset attributes */
341 msi->irq = 0;
342 msi->msi_attrib.multiple = 0;
f342d940
JH		 343}
344
345static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
346 struct msi_desc *desc)
347{
348 int irq, pos, msgvec;
349 u16 msg_ctr;
350 struct msi_msg msg;
351 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
352
353 if (!pp) {
354 BUG();
355 return -EINVAL;
356 }
357
48c3c38f
YW		 358 pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_FLAGS, &msg_ctr);
359 msgvec = (msg_ctr & PCI_MSI_FLAGS_QSIZE) >> 4;
f342d940
JH		 360 if (msgvec == 0)
361 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
362 if (msgvec > 5)
363 msgvec = 0;
364
365 irq = assign_irq((1 << msgvec), desc, &pos);
366 if (irq < 0)
367 return irq;
368
64989e73
BEN		 369 /*
370 * write_msi_msg() will update PCI_MSI_FLAGS so there is
371 * no need to explicitly call pci_write_config_word().
372 */
f342d940
JH		 373 desc->msi_attrib.multiple = msgvec;
374
2f37c5a8
MK		 375 if (pp->ops->get_msi_data)
376 msg.address_lo = pp->ops->get_msi_data(pp);
377 else
378 msg.address_lo = virt_to_phys((void *)pp->msi_data);
f342d940
JH		 379 msg.address_hi = 0x0;
380 msg.data = pos;
381 write_msi_msg(irq, &msg);
382
383 return 0;
384}
385
386static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
387{
388 clear_irq(irq);
389}
390
391static struct msi_chip dw_pcie_msi_chip = {
392 .setup_irq = dw_msi_setup_irq,
393 .teardown_irq = dw_msi_teardown_irq,
394};
395
4b1ced84
JH		 396int dw_pcie_link_up(struct pcie_port *pp)
397{
398 if (pp->ops->link_up)
399 return pp->ops->link_up(pp);
400 else
401 return 0;
402}
403
f342d940
JH		 404static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
405 irq_hw_number_t hwirq)
406{
407 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
408 irq_set_chip_data(irq, domain->host_data);
409 set_irq_flags(irq, IRQF_VALID);
410
411 return 0;
412}
413
414static const struct irq_domain_ops msi_domain_ops = {
415 .map = dw_pcie_msi_map,
416};
417
4b1ced84
JH		 418int __init dw_pcie_host_init(struct pcie_port *pp)
419{
420 struct device_node *np = pp->dev->of_node;
4dd964df 421 struct platform_device *pdev = to_platform_device(pp->dev);
4b1ced84
JH		 422 struct of_pci_range range;
423 struct of_pci_range_parser parser;
4dd964df 424 struct resource *cfg_res;
f4c55c5a
KVA		 425 u32 val, na, ns;
426 const __be32 *addrp;
427 int i, index;
428
429 /* Find the address cell size and the number of cells in order to get
430 * the untranslated address.
431 */
432 of_property_read_u32(np, "#address-cells", &na);
433 ns = of_n_size_cells(np);
f342d940 434
4dd964df
KVA		 435 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
436 if (cfg_res) {
437 pp->config.cfg0_size = resource_size(cfg_res)/2;
438 pp->config.cfg1_size = resource_size(cfg_res)/2;
439 pp->cfg0_base = cfg_res->start;
440 pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
f4c55c5a
KVA		 441
442 /* Find the untranslated configuration space address */
443 index = of_property_match_string(np, "reg-names", "config");
444 addrp = of_get_address(np, index, false, false);
445 pp->cfg0_mod_base = of_read_number(addrp, ns);
446 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size;
4dd964df
KVA		 447 } else {
448 dev_err(pp->dev, "missing *config* reg space\n");
449 }
450
4b1ced84
JH		 451 if (of_pci_range_parser_init(&parser, np)) {
452 dev_err(pp->dev, "missing ranges property\n");
453 return -EINVAL;
454 }
455
456 /* Get the I/O and memory ranges from DT */
457 for_each_of_pci_range(&parser, &range) {
458 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
459 if (restype == IORESOURCE_IO) {
460 of_pci_range_to_resource(&range, np, &pp->io);
461 pp->io.name = "I/O";
462 pp->io.start = max_t(resource_size_t,
463 PCIBIOS_MIN_IO,
464 range.pci_addr + global_io_offset);
465 pp->io.end = min_t(resource_size_t,
466 IO_SPACE_LIMIT,
467 range.pci_addr + range.size
468 + global_io_offset);
469 pp->config.io_size = resource_size(&pp->io);
470 pp->config.io_bus_addr = range.pci_addr;
fce8591f 471 pp->io_base = range.cpu_addr;
f4c55c5a
KVA		 472
473 /* Find the untranslated IO space address */
474 pp->io_mod_base = of_read_number(parser.range -
475 parser.np + na, ns);
4b1ced84
JH		 476 }
477 if (restype == IORESOURCE_MEM) {
478 of_pci_range_to_resource(&range, np, &pp->mem);
479 pp->mem.name = "MEM";
480 pp->config.mem_size = resource_size(&pp->mem);
481 pp->config.mem_bus_addr = range.pci_addr;
f4c55c5a
KVA		 482
483 /* Find the untranslated MEM space address */
484 pp->mem_mod_base = of_read_number(parser.range -
485 parser.np + na, ns);
4b1ced84
JH		 486 }
487 if (restype == 0) {
488 of_pci_range_to_resource(&range, np, &pp->cfg);
489 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
490 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
4dd964df
KVA		 491 pp->cfg0_base = pp->cfg.start;
492 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
f4c55c5a
KVA		 493
494 /* Find the untranslated configuration space address */
495 pp->cfg0_mod_base = of_read_number(parser.range -
496 parser.np + na, ns);
497 pp->cfg1_mod_base = pp->cfg0_mod_base +
498 pp->config.cfg0_size;
4b1ced84
JH		 499 }
500 }
501
502 if (!pp->dbi_base) {
503 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
504 resource_size(&pp->cfg));
505 if (!pp->dbi_base) {
506 dev_err(pp->dev, "error with ioremap\n");
507 return -ENOMEM;
508 }
509 }
510
4b1ced84
JH		 511 pp->mem_base = pp->mem.start;
512
513 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
514 pp->config.cfg0_size);
515 if (!pp->va_cfg0_base) {
516 dev_err(pp->dev, "error with ioremap in function\n");
517 return -ENOMEM;
518 }
519 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
520 pp->config.cfg1_size);
521 if (!pp->va_cfg1_base) {
522 dev_err(pp->dev, "error with ioremap\n");
523 return -ENOMEM;
524 }
525
526 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
527 dev_err(pp->dev, "Failed to parse the number of lanes\n");
528 return -EINVAL;
529 }
530
f342d940 531 if (IS_ENABLED(CONFIG_PCI_MSI)) {
904d0e78 532 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
f342d940
JH		 533 MAX_MSI_IRQS, &msi_domain_ops,
534 &dw_pcie_msi_chip);
904d0e78 535 if (!pp->irq_domain) {
f342d940
JH		 536 dev_err(pp->dev, "irq domain init failed\n");
537 return -ENXIO;
538 }
539
904d0e78
PA		 540 for (i = 0; i < MAX_MSI_IRQS; i++)
541 irq_create_mapping(pp->irq_domain, i);
f342d940
JH		 542 }
543
4b1ced84
JH		 544 if (pp->ops->host_init)
545 pp->ops->host_init(pp);
546
547 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
548
549 /* program correct class for RC */
550 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
551
552 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
553 val |= PORT_LOGIC_SPEED_CHANGE;
554 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
555
556 dw_pci.nr_controllers = 1;
557 dw_pci.private_data = (void **)&pp;
558
804f57b1 559 pci_common_init_dev(pp->dev, &dw_pci);
4b1ced84
JH		 560 pci_assign_unassigned_resources();
561#ifdef CONFIG_PCI_DOMAINS
562 dw_pci.domain++;
563#endif
564
565 return 0;
566}
567
568static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
340cba60 569{
340cba60 570 /* Program viewport 0 : OUTBOUND : CFG0 */
f7b7868c
SJ		 571 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
572 PCIE_ATU_VIEWPORT);
f4c55c5a
KVA		 573 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
574 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
575 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1,
f7b7868c
SJ		 576 PCIE_ATU_LIMIT);
577 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
578 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
579 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
580 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 581}
582
4b1ced84 583static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
340cba60 584{
340cba60 585 /* Program viewport 1 : OUTBOUND : CFG1 */
f7b7868c
SJ		 586 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
587 PCIE_ATU_VIEWPORT);
588 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
f4c55c5a
KVA		 589 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
590 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
591 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1,
f7b7868c
SJ		 592 PCIE_ATU_LIMIT);
593 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
594 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
a19f88bd 595 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 596}
597
4b1ced84 598static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
340cba60 599{
340cba60 600 /* Program viewport 0 : OUTBOUND : MEM */
f7b7868c
SJ		 601 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
602 PCIE_ATU_VIEWPORT);
603 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
f4c55c5a
KVA		 604 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
605 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
606 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1,
f7b7868c
SJ		 607 PCIE_ATU_LIMIT);
608 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 609 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
f7b7868c 610 PCIE_ATU_UPPER_TARGET);
a19f88bd 611 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 612}
613
4b1ced84 614static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
340cba60 615{
340cba60 616 /* Program viewport 1 : OUTBOUND : IO */
f7b7868c
SJ		 617 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
618 PCIE_ATU_VIEWPORT);
619 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
f4c55c5a
KVA		 620 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
621 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
622 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1,
f7b7868c
SJ		 623 PCIE_ATU_LIMIT);
624 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 625 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
f7b7868c 626 PCIE_ATU_UPPER_TARGET);
a19f88bd 627 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 628}
629
4b1ced84 630static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 631 u32 devfn, int where, int size, u32 *val)
632{
633 int ret = PCIBIOS_SUCCESSFUL;
634 u32 address, busdev;
635
636 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
637 PCIE_ATU_FUNC(PCI_FUNC(devfn));
638 address = where & ~0x3;
639
640 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 641 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 642 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
643 val);
4b1ced84 644 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 645 } else {
4b1ced84 646 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 647 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
648 val);
4b1ced84 649 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 650 }
651
652 return ret;
653}
654
4b1ced84 655static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 656 u32 devfn, int where, int size, u32 val)
657{
658 int ret = PCIBIOS_SUCCESSFUL;
659 u32 address, busdev;
660
661 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
662 PCIE_ATU_FUNC(PCI_FUNC(devfn));
663 address = where & ~0x3;
664
665 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 666 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 667 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
668 val);
4b1ced84 669 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 670 } else {
4b1ced84 671 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 672 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
673 val);
4b1ced84 674 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 675 }
676
677 return ret;
678}
679
4b1ced84 680static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 681 struct pci_bus *bus, int dev)
682{
683 /* If there is no link, then there is no device */
684 if (bus->number != pp->root_bus_nr) {
4b1ced84 685 if (!dw_pcie_link_up(pp))
340cba60
JH		 686 return 0;
687 }
688
689 /* access only one slot on each root port */
690 if (bus->number == pp->root_bus_nr && dev > 0)
691 return 0;
692
693 /*
694 * do not read more than one device on the bus directly attached
695 * to RC's (Virtual Bridge's) DS side.
696 */
697 if (bus->primary == pp->root_bus_nr && dev > 0)
698 return 0;
699
700 return 1;
701}
702
4b1ced84 703static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 704 int size, u32 *val)
705{
706 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 707 int ret;
708
709 if (!pp) {
710 BUG();
711 return -EINVAL;
712 }
713
4b1ced84 714 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 715 *val = 0xffffffff;
716 return PCIBIOS_DEVICE_NOT_FOUND;
717 }
718
340cba60 719 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 720 if (pp->ops->rd_other_conf)
721 ret = pp->ops->rd_other_conf(pp, bus, devfn,
722 where, size, val);
723 else
724 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 725 where, size, val);
726 else
4b1ced84 727 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 728
729 return ret;
730}
731
4b1ced84 732static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 733 int where, int size, u32 val)
734{
735 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 736 int ret;
737
738 if (!pp) {
739 BUG();
740 return -EINVAL;
741 }
742
4b1ced84 743 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 744 return PCIBIOS_DEVICE_NOT_FOUND;
745
340cba60 746 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 747 if (pp->ops->wr_other_conf)
748 ret = pp->ops->wr_other_conf(pp, bus, devfn,
749 where, size, val);
750 else
751 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 752 where, size, val);
753 else
4b1ced84 754 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 755
756 return ret;
757}
758
4b1ced84
JH		 759static struct pci_ops dw_pcie_ops = {
760 .read = dw_pcie_rd_conf,
761 .write = dw_pcie_wr_conf,
340cba60
JH		 762};
763
73e40850 764static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 765{
766 struct pcie_port *pp;
767
768 pp = sys_to_pcie(sys);
769
770 if (!pp)
771 return 0;
772
773 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
774 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
fce8591f 775 pci_ioremap_io(global_io_offset, pp->io_base);
4b1ced84
JH		 776 global_io_offset += SZ_64K;
777 pci_add_resource_offset(&sys->resources, &pp->io,
778 sys->io_offset);
779 }
780
781 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
782 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
783
784 return 1;
785}
786
73e40850 787static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 788{
789 struct pci_bus *bus;
790 struct pcie_port *pp = sys_to_pcie(sys);
791
792 if (pp) {
793 pp->root_bus_nr = sys->busnr;
804f57b1 794 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
340cba60
JH		 795 sys, &sys->resources);
796 } else {
797 bus = NULL;
798 BUG();
799 }
800
801 return bus;
802}
803
73e40850 804static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 805{
806 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
804f57b1 807 int irq;
340cba60 808
804f57b1
LS		 809 irq = of_irq_parse_and_map_pci(dev, slot, pin);
810 if (!irq)
811 irq = pp->irq;
340cba60 812
804f57b1 813 return irq;
340cba60
JH		 814}
815
f342d940
JH		 816static void dw_pcie_add_bus(struct pci_bus *bus)
817{
818 if (IS_ENABLED(CONFIG_PCI_MSI)) {
819 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
820
821 dw_pcie_msi_chip.dev = pp->dev;
822 bus->msi = &dw_pcie_msi_chip;
823 }
824}
825
4b1ced84
JH		 826static struct hw_pci dw_pci = {
827 .setup = dw_pcie_setup,
828 .scan = dw_pcie_scan_bus,
829 .map_irq = dw_pcie_map_irq,
f342d940 830 .add_bus = dw_pcie_add_bus,
340cba60
JH		 831};
832
4b1ced84 833void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60
JH		 834{
835 struct pcie_port_info *config = &pp->config;
340cba60
JH		 836 u32 val;
837 u32 membase;
838 u32 memlimit;
839
66c5c34b 840 /* set the number of lanes */
f7b7868c 841 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 842 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 843 switch (pp->lanes) {
844 case 1:
845 val |= PORT_LINK_MODE_1_LANES;
846 break;
847 case 2:
848 val |= PORT_LINK_MODE_2_LANES;
849 break;
850 case 4:
851 val |= PORT_LINK_MODE_4_LANES;
852 break;
853 }
f7b7868c 854 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 855
856 /* set link width speed control register */
f7b7868c 857 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 858 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 859 switch (pp->lanes) {
860 case 1:
861 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
862 break;
863 case 2:
864 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
865 break;
866 case 4:
867 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
868 break;
869 }
f7b7868c 870 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 871
872 /* setup RC BARs */
f7b7868c 873 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dbffdd68 874 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
340cba60
JH		 875
876 /* setup interrupt pins */
f7b7868c 877 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 878 val &= 0xffff00ff;
879 val |= 0x00000100;
f7b7868c 880 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 881
882 /* setup bus numbers */
f7b7868c 883 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 884 val &= 0xff000000;
885 val |= 0x00010100;
f7b7868c 886 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 887
888 /* setup memory base, memory limit */
889 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
890 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
891 val = memlimit | membase;
f7b7868c 892 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 893
894 /* setup command register */
f7b7868c 895 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 896 val &= 0xffff0000;
897 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
898 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 899 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 900}
340cba60
JH		 901
902MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 903MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 904MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)