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bb38919e SC |
1 | /* |
2 | * PCIe host controller driver for Freescale i.MX6 SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Kosagi | |
5 | * http://www.kosagi.com | |
6 | * | |
7 | * Author: Sean Cross <xobs@kosagi.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_gpio.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/resource.h> | |
26 | #include <linux/signal.h> | |
27 | #include <linux/types.h> | |
28 | ||
29 | #include "pcie-designware.h" | |
30 | ||
31 | #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) | |
32 | ||
33 | struct imx6_pcie { | |
34 | int reset_gpio; | |
35 | int power_on_gpio; | |
36 | int wake_up_gpio; | |
37 | int disable_gpio; | |
38 | struct clk *lvds_gate; | |
39 | struct clk *sata_ref_100m; | |
40 | struct clk *pcie_ref_125m; | |
41 | struct clk *pcie_axi; | |
42 | struct pcie_port pp; | |
43 | struct regmap *iomuxc_gpr; | |
44 | void __iomem *mem_base; | |
45 | }; | |
46 | ||
47 | /* PCIe Port Logic registers (memory-mapped) */ | |
48 | #define PL_OFFSET 0x700 | |
49 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) | |
50 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | |
7f9f40c0 MV |
51 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
52 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) | |
bb38919e SC |
53 | |
54 | #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) | |
55 | #define PCIE_PHY_CTRL_DATA_LOC 0 | |
56 | #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 | |
57 | #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 | |
58 | #define PCIE_PHY_CTRL_WR_LOC 18 | |
59 | #define PCIE_PHY_CTRL_RD_LOC 19 | |
60 | ||
61 | #define PCIE_PHY_STAT (PL_OFFSET + 0x110) | |
62 | #define PCIE_PHY_STAT_ACK_LOC 16 | |
63 | ||
64 | /* PHY registers (not memory-mapped) */ | |
65 | #define PCIE_PHY_RX_ASIC_OUT 0x100D | |
66 | ||
67 | #define PHY_RX_OVRD_IN_LO 0x1005 | |
68 | #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) | |
69 | #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) | |
70 | ||
71 | static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) | |
72 | { | |
73 | u32 val; | |
74 | u32 max_iterations = 10; | |
75 | u32 wait_counter = 0; | |
76 | ||
77 | do { | |
78 | val = readl(dbi_base + PCIE_PHY_STAT); | |
79 | val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; | |
80 | wait_counter++; | |
81 | ||
82 | if (val == exp_val) | |
83 | return 0; | |
84 | ||
85 | udelay(1); | |
86 | } while (wait_counter < max_iterations); | |
87 | ||
88 | return -ETIMEDOUT; | |
89 | } | |
90 | ||
91 | static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) | |
92 | { | |
93 | u32 val; | |
94 | int ret; | |
95 | ||
96 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
97 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
98 | ||
99 | val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); | |
100 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
101 | ||
102 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
103 | if (ret) | |
104 | return ret; | |
105 | ||
106 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
107 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
108 | ||
109 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
110 | if (ret) | |
111 | return ret; | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ | |
117 | static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) | |
118 | { | |
119 | u32 val, phy_ctl; | |
120 | int ret; | |
121 | ||
122 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
123 | if (ret) | |
124 | return ret; | |
125 | ||
126 | /* assert Read signal */ | |
127 | phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; | |
128 | writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); | |
129 | ||
130 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
134 | val = readl(dbi_base + PCIE_PHY_STAT); | |
135 | *data = val & 0xffff; | |
136 | ||
137 | /* deassert Read signal */ | |
138 | writel(0x00, dbi_base + PCIE_PHY_CTRL); | |
139 | ||
140 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
141 | if (ret) | |
142 | return ret; | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) | |
148 | { | |
149 | u32 var; | |
150 | int ret; | |
151 | ||
152 | /* write addr */ | |
153 | /* cap addr */ | |
154 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
158 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
159 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
160 | ||
161 | /* capture data */ | |
162 | var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); | |
163 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
164 | ||
165 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
166 | if (ret) | |
167 | return ret; | |
168 | ||
169 | /* deassert cap data */ | |
170 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
171 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
172 | ||
173 | /* wait for ack de-assertion */ | |
174 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
175 | if (ret) | |
176 | return ret; | |
177 | ||
178 | /* assert wr signal */ | |
179 | var = 0x1 << PCIE_PHY_CTRL_WR_LOC; | |
180 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
181 | ||
182 | /* wait for ack */ | |
183 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
184 | if (ret) | |
185 | return ret; | |
186 | ||
187 | /* deassert wr signal */ | |
188 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
189 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
190 | ||
191 | /* wait for ack de-assertion */ | |
192 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
193 | if (ret) | |
194 | return ret; | |
195 | ||
196 | writel(0x0, dbi_base + PCIE_PHY_CTRL); | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | /* Added for PCI abort handling */ | |
202 | static int imx6q_pcie_abort_handler(unsigned long addr, | |
203 | unsigned int fsr, struct pt_regs *regs) | |
204 | { | |
bb38919e SC |
205 | return 0; |
206 | } | |
207 | ||
208 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) | |
209 | { | |
210 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
211 | ||
212 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
213 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); | |
214 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
215 | IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); | |
216 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
217 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); | |
218 | ||
c28f8a1f MV |
219 | /* Some boards don't have PCIe reset GPIO. */ |
220 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { | |
221 | gpio_set_value(imx6_pcie->reset_gpio, 0); | |
222 | msleep(100); | |
223 | gpio_set_value(imx6_pcie->reset_gpio, 1); | |
224 | } | |
bb38919e SC |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) | |
230 | { | |
231 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
232 | int ret; | |
233 | ||
234 | if (gpio_is_valid(imx6_pcie->power_on_gpio)) | |
235 | gpio_set_value(imx6_pcie->power_on_gpio, 1); | |
236 | ||
237 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
238 | IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); | |
239 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
240 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); | |
241 | ||
242 | ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); | |
243 | if (ret) { | |
244 | dev_err(pp->dev, "unable to enable sata_ref_100m\n"); | |
245 | goto err_sata_ref; | |
246 | } | |
247 | ||
248 | ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m); | |
249 | if (ret) { | |
250 | dev_err(pp->dev, "unable to enable pcie_ref_125m\n"); | |
251 | goto err_pcie_ref; | |
252 | } | |
253 | ||
254 | ret = clk_prepare_enable(imx6_pcie->lvds_gate); | |
255 | if (ret) { | |
256 | dev_err(pp->dev, "unable to enable lvds_gate\n"); | |
257 | goto err_lvds_gate; | |
258 | } | |
259 | ||
260 | ret = clk_prepare_enable(imx6_pcie->pcie_axi); | |
261 | if (ret) { | |
262 | dev_err(pp->dev, "unable to enable pcie_axi\n"); | |
263 | goto err_pcie_axi; | |
264 | } | |
265 | ||
266 | /* allow the clocks to stabilize */ | |
267 | usleep_range(200, 500); | |
268 | ||
269 | return 0; | |
270 | ||
271 | err_pcie_axi: | |
272 | clk_disable_unprepare(imx6_pcie->lvds_gate); | |
273 | err_lvds_gate: | |
274 | clk_disable_unprepare(imx6_pcie->pcie_ref_125m); | |
275 | err_pcie_ref: | |
276 | clk_disable_unprepare(imx6_pcie->sata_ref_100m); | |
277 | err_sata_ref: | |
278 | return ret; | |
279 | ||
280 | } | |
281 | ||
282 | static void imx6_pcie_init_phy(struct pcie_port *pp) | |
283 | { | |
284 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
285 | ||
286 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
287 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
288 | ||
289 | /* configure constant input signal to the pcie ctrl and phy */ | |
290 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
291 | IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); | |
292 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
293 | IMX6Q_GPR12_LOS_LEVEL, 9 << 4); | |
294 | ||
295 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
296 | IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); | |
297 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
298 | IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); | |
299 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
300 | IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); | |
301 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
302 | IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); | |
303 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
304 | IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); | |
305 | } | |
306 | ||
66a60f93 MV |
307 | static int imx6_pcie_wait_for_link(struct pcie_port *pp) |
308 | { | |
309 | int count = 200; | |
310 | ||
311 | while (!dw_pcie_link_up(pp)) { | |
312 | usleep_range(100, 1000); | |
313 | if (--count) | |
314 | continue; | |
315 | ||
316 | dev_err(pp->dev, "phy link never came up\n"); | |
317 | dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", | |
318 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), | |
319 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
bb38919e SC |
326 | static void imx6_pcie_host_init(struct pcie_port *pp) |
327 | { | |
328 | int count = 0; | |
329 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
330 | ||
331 | imx6_pcie_assert_core_reset(pp); | |
332 | ||
333 | imx6_pcie_init_phy(pp); | |
334 | ||
335 | imx6_pcie_deassert_core_reset(pp); | |
336 | ||
337 | dw_pcie_setup_rc(pp); | |
338 | ||
339 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
340 | IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); | |
341 | ||
66a60f93 | 342 | imx6_pcie_wait_for_link(pp); |
bb38919e SC |
343 | } |
344 | ||
982aa234 MV |
345 | static void imx6_pcie_reset_phy(struct pcie_port *pp) |
346 | { | |
347 | uint32_t temp; | |
348 | ||
349 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp); | |
350 | temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
351 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
352 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp); | |
353 | ||
354 | usleep_range(2000, 3000); | |
355 | ||
356 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp); | |
357 | temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
358 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
359 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp); | |
360 | } | |
361 | ||
bb38919e SC |
362 | static int imx6_pcie_link_up(struct pcie_port *pp) |
363 | { | |
982aa234 | 364 | u32 rc, ltssm, rx_valid; |
bb38919e | 365 | |
7f9f40c0 MV |
366 | /* |
367 | * Test if the PHY reports that the link is up and also that | |
368 | * the link training finished. It might happen that the PHY | |
369 | * reports the link is already up, but the link training bit | |
370 | * is still set, so make sure to check the training is done | |
371 | * as well here. | |
372 | */ | |
373 | rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); | |
374 | if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) && | |
375 | !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) | |
376 | return 1; | |
bb38919e SC |
377 | |
378 | /* | |
379 | * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. | |
380 | * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). | |
381 | * If (MAC/LTSSM.state == Recovery.RcvrLock) | |
382 | * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition | |
383 | * to gen2 is stuck | |
384 | */ | |
385 | pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); | |
386 | ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; | |
387 | ||
388 | if (rx_valid & 0x01) | |
389 | return 0; | |
390 | ||
391 | if (ltssm != 0x0d) | |
392 | return 0; | |
393 | ||
394 | dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); | |
395 | ||
982aa234 | 396 | imx6_pcie_reset_phy(pp); |
bb38919e SC |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
401 | static struct pcie_host_ops imx6_pcie_host_ops = { | |
402 | .link_up = imx6_pcie_link_up, | |
403 | .host_init = imx6_pcie_host_init, | |
404 | }; | |
405 | ||
406 | static int imx6_add_pcie_port(struct pcie_port *pp, | |
407 | struct platform_device *pdev) | |
408 | { | |
409 | int ret; | |
410 | ||
411 | pp->irq = platform_get_irq(pdev, 0); | |
412 | if (!pp->irq) { | |
413 | dev_err(&pdev->dev, "failed to get irq\n"); | |
414 | return -ENODEV; | |
415 | } | |
416 | ||
417 | pp->root_bus_nr = -1; | |
418 | pp->ops = &imx6_pcie_host_ops; | |
419 | ||
420 | spin_lock_init(&pp->conf_lock); | |
421 | ret = dw_pcie_host_init(pp); | |
422 | if (ret) { | |
423 | dev_err(&pdev->dev, "failed to initialize host\n"); | |
424 | return ret; | |
425 | } | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static int __init imx6_pcie_probe(struct platform_device *pdev) | |
431 | { | |
432 | struct imx6_pcie *imx6_pcie; | |
433 | struct pcie_port *pp; | |
434 | struct device_node *np = pdev->dev.of_node; | |
435 | struct resource *dbi_base; | |
436 | int ret; | |
437 | ||
438 | imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); | |
439 | if (!imx6_pcie) | |
440 | return -ENOMEM; | |
441 | ||
442 | pp = &imx6_pcie->pp; | |
443 | pp->dev = &pdev->dev; | |
444 | ||
445 | /* Added for PCI abort handling */ | |
446 | hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, | |
447 | "imprecise external abort"); | |
448 | ||
449 | dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
bb38919e | 450 | pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); |
b391bf31 FE |
451 | if (IS_ERR(pp->dbi_base)) |
452 | return PTR_ERR(pp->dbi_base); | |
bb38919e SC |
453 | |
454 | /* Fetch GPIOs */ | |
455 | imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); | |
c28f8a1f MV |
456 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
457 | ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio, | |
458 | GPIOF_OUT_INIT_LOW, "PCIe reset"); | |
459 | if (ret) { | |
460 | dev_err(&pdev->dev, "unable to get reset gpio\n"); | |
461 | return ret; | |
462 | } | |
bb38919e SC |
463 | } |
464 | ||
465 | imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0); | |
466 | if (gpio_is_valid(imx6_pcie->power_on_gpio)) { | |
467 | ret = devm_gpio_request_one(&pdev->dev, | |
468 | imx6_pcie->power_on_gpio, | |
469 | GPIOF_OUT_INIT_LOW, | |
470 | "PCIe power enable"); | |
471 | if (ret) { | |
472 | dev_err(&pdev->dev, "unable to get power-on gpio\n"); | |
b391bf31 | 473 | return ret; |
bb38919e SC |
474 | } |
475 | } | |
476 | ||
477 | imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0); | |
478 | if (gpio_is_valid(imx6_pcie->wake_up_gpio)) { | |
479 | ret = devm_gpio_request_one(&pdev->dev, | |
480 | imx6_pcie->wake_up_gpio, | |
481 | GPIOF_IN, | |
482 | "PCIe wake up"); | |
483 | if (ret) { | |
484 | dev_err(&pdev->dev, "unable to get wake-up gpio\n"); | |
b391bf31 | 485 | return ret; |
bb38919e SC |
486 | } |
487 | } | |
488 | ||
489 | imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0); | |
490 | if (gpio_is_valid(imx6_pcie->disable_gpio)) { | |
491 | ret = devm_gpio_request_one(&pdev->dev, | |
492 | imx6_pcie->disable_gpio, | |
493 | GPIOF_OUT_INIT_HIGH, | |
494 | "PCIe disable endpoint"); | |
495 | if (ret) { | |
496 | dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); | |
b391bf31 | 497 | return ret; |
bb38919e SC |
498 | } |
499 | } | |
500 | ||
501 | /* Fetch clocks */ | |
502 | imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate"); | |
503 | if (IS_ERR(imx6_pcie->lvds_gate)) { | |
504 | dev_err(&pdev->dev, | |
505 | "lvds_gate clock select missing or invalid\n"); | |
b391bf31 | 506 | return PTR_ERR(imx6_pcie->lvds_gate); |
bb38919e SC |
507 | } |
508 | ||
509 | imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m"); | |
510 | if (IS_ERR(imx6_pcie->sata_ref_100m)) { | |
511 | dev_err(&pdev->dev, | |
512 | "sata_ref_100m clock source missing or invalid\n"); | |
b391bf31 | 513 | return PTR_ERR(imx6_pcie->sata_ref_100m); |
bb38919e SC |
514 | } |
515 | ||
516 | imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m"); | |
517 | if (IS_ERR(imx6_pcie->pcie_ref_125m)) { | |
518 | dev_err(&pdev->dev, | |
519 | "pcie_ref_125m clock source missing or invalid\n"); | |
b391bf31 | 520 | return PTR_ERR(imx6_pcie->pcie_ref_125m); |
bb38919e SC |
521 | } |
522 | ||
523 | imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi"); | |
524 | if (IS_ERR(imx6_pcie->pcie_axi)) { | |
525 | dev_err(&pdev->dev, | |
526 | "pcie_axi clock source missing or invalid\n"); | |
b391bf31 | 527 | return PTR_ERR(imx6_pcie->pcie_axi); |
bb38919e SC |
528 | } |
529 | ||
530 | /* Grab GPR config register range */ | |
531 | imx6_pcie->iomuxc_gpr = | |
532 | syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
533 | if (IS_ERR(imx6_pcie->iomuxc_gpr)) { | |
534 | dev_err(&pdev->dev, "unable to find iomuxc registers\n"); | |
b391bf31 | 535 | return PTR_ERR(imx6_pcie->iomuxc_gpr); |
bb38919e SC |
536 | } |
537 | ||
538 | ret = imx6_add_pcie_port(pp, pdev); | |
539 | if (ret < 0) | |
b391bf31 | 540 | return ret; |
bb38919e SC |
541 | |
542 | platform_set_drvdata(pdev, imx6_pcie); | |
543 | return 0; | |
bb38919e SC |
544 | } |
545 | ||
546 | static const struct of_device_id imx6_pcie_of_match[] = { | |
547 | { .compatible = "fsl,imx6q-pcie", }, | |
548 | {}, | |
549 | }; | |
550 | MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); | |
551 | ||
552 | static struct platform_driver imx6_pcie_driver = { | |
553 | .driver = { | |
554 | .name = "imx6q-pcie", | |
555 | .owner = THIS_MODULE, | |
8bcadbe1 | 556 | .of_match_table = imx6_pcie_of_match, |
bb38919e SC |
557 | }, |
558 | }; | |
559 | ||
560 | /* Freescale PCIe driver does not allow module unload */ | |
561 | ||
562 | static int __init imx6_pcie_init(void) | |
563 | { | |
564 | return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); | |
565 | } | |
f216f57f | 566 | fs_initcall(imx6_pcie_init); |
bb38919e SC |
567 | |
568 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); | |
569 | MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); | |
570 | MODULE_LICENSE("GPL v2"); |