[linux-2.6-block.git] / drivers / pci / dwc / pcie-hisi.c

/*
 * PCIe host controller driver for HiSilicon SoCs
 *
 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
 *
 * Authors: Zhou Wang <wangzhou1@hisilicon.com>
 *          Dacai Zhu <zhudacai@hisilicon.com>
 *          Gabriele Paoloni <gabriele.paoloni@huawei.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/regmap.h>
#include "../pci.h"

#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))

static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			     int size, u32 *val)
{
	struct pci_config_window *cfg = bus->sysdata;
	int dev = PCI_SLOT(devfn);

	if (bus->number == cfg->busr.start) {
		/* access only one slot on each root port */
		if (dev > 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
		else
			return pci_generic_config_read32(bus, devfn, where,
							 size, val);
	}

	return pci_generic_config_read(bus, devfn, where, size, val);
}

static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			     int where, int size, u32 val)
{
	struct pci_config_window *cfg = bus->sysdata;
	int dev = PCI_SLOT(devfn);

	if (bus->number == cfg->busr.start) {
		/* access only one slot on each root port */
		if (dev > 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
		else
			return pci_generic_config_write32(bus, devfn, where,
							  size, val);
	}

	return pci_generic_config_write(bus, devfn, where, size, val);
}

static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
				       int where)
{
	struct pci_config_window *cfg = bus->sysdata;
	void __iomem *reg_base = cfg->priv;

	if (bus->number == cfg->busr.start)
		return reg_base + where;
	else
		return pci_ecam_map_bus(bus, devfn, where);
}

#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)

static int hisi_pcie_init(struct pci_config_window *cfg)
{
	struct device *dev = cfg->parent;
	struct acpi_device *adev = to_acpi_device(dev);
	struct acpi_pci_root *root = acpi_driver_data(adev);
	struct resource *res;
	void __iomem *reg_base;
	int ret;

	/*
	 * Retrieve RC base and size from a HISI0081 device with _UID
	 * matching our segment.
	 */
	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
	if (!res)
		return -ENOMEM;

	ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
	if (ret) {
		dev_err(dev, "can't get rc base address\n");
		return -ENOMEM;
	}

	reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
	if (!reg_base)
		return -ENOMEM;

	cfg->priv = reg_base;
	return 0;
}

struct pci_ecam_ops hisi_pcie_ops = {
	.bus_shift    = 20,
	.init         =  hisi_pcie_init,
	.pci_ops      = {
		.map_bus    = hisi_pcie_map_bus,
		.read       = hisi_pcie_rd_conf,
		.write      = hisi_pcie_wr_conf,
	}
};

#endif

#ifdef CONFIG_PCI_HISI

#include "pcie-designware.h"

#define PCIE_SUBCTRL_SYS_STATE4_REG		0x6818
#define PCIE_HIP06_CTRL_OFF			0x1000
#define PCIE_SYS_STATE4				(PCIE_HIP06_CTRL_OFF + 0x31c)
#define PCIE_LTSSM_LINKUP_STATE			0x11
#define PCIE_LTSSM_STATE_MASK			0x3F

#define to_hisi_pcie(x)	dev_get_drvdata((x)->dev)

struct hisi_pcie;

struct pcie_soc_ops {
	int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
};

struct hisi_pcie {
	struct dw_pcie *pci;
	struct regmap *subctrl;
	u32 port_id;
	const struct pcie_soc_ops *soc_ops;
};

/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
			      u32 *val)
{
	u32 reg;
	u32 reg_val;
	void *walker = &reg_val;
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	walker += (where & 0x3);
	reg = where & ~0x3;
	reg_val = dw_pcie_readl_dbi(pci, reg);

	if (size == 1)
		*val = *(u8 __force *) walker;
	else if (size == 2)
		*val = *(u16 __force *) walker;
	else if (size == 4)
		*val = reg_val;
	else
		return PCIBIOS_BAD_REGISTER_NUMBER;

	return PCIBIOS_SUCCESSFUL;
}

/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int  size,
				u32 val)
{
	u32 reg_val;
	u32 reg;
	void *walker = &reg_val;
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	walker += (where & 0x3);
	reg = where & ~0x3;
	if (size == 4)
		dw_pcie_writel_dbi(pci, reg, val);
	else if (size == 2) {
		reg_val = dw_pcie_readl_dbi(pci, reg);
		*(u16 __force *) walker = val;
		dw_pcie_writel_dbi(pci, reg, reg_val);
	} else if (size == 1) {
		reg_val = dw_pcie_readl_dbi(pci, reg);
		*(u8 __force *) walker = val;
		dw_pcie_writel_dbi(pci, reg, reg_val);
	} else
		return PCIBIOS_BAD_REGISTER_NUMBER;

	return PCIBIOS_SUCCESSFUL;
}

static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
{
	u32 val;

	regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
		    0x100 * hisi_pcie->port_id, &val);

	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}

static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{
	struct dw_pcie *pci = hisi_pcie->pci;
	u32 val;

	val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);

	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}

static int hisi_pcie_link_up(struct dw_pcie *pci)
{
	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);

	return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
}

static struct dw_pcie_host_ops hisi_pcie_host_ops = {
	.rd_own_conf = hisi_pcie_cfg_read,
	.wr_own_conf = hisi_pcie_cfg_write,
};

static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
			      struct platform_device *pdev)
{
	struct dw_pcie *pci = hisi_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct device *dev = &pdev->dev;
	int ret;
	u32 port_id;

	if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
		dev_err(dev, "failed to read port-id\n");
		return -EINVAL;
	}
	if (port_id > 3) {
		dev_err(dev, "Invalid port-id: %d\n", port_id);
		return -EINVAL;
	}
	hisi_pcie->port_id = port_id;

	pp->ops = &hisi_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static const struct dw_pcie_ops dw_pcie_ops = {
	.link_up = hisi_pcie_link_up,
};

static int hisi_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct hisi_pcie *hisi_pcie;
	struct resource *reg;
	struct device_driver *driver;
	int ret;

	hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
	if (!hisi_pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	pci->dev = dev;
	pci->ops = &dw_pcie_ops;

	driver = dev->driver;

	hisi_pcie->pci = pci;

	hisi_pcie->soc_ops = of_device_get_match_data(dev);

	hisi_pcie->subctrl =
	    syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
	if (IS_ERR(hisi_pcie->subctrl)) {
		dev_err(dev, "cannot get subctrl base\n");
		return PTR_ERR(hisi_pcie->subctrl);
	}

	reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
	pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg);
	if (IS_ERR(pci->dbi_base))
		return PTR_ERR(pci->dbi_base);
	platform_set_drvdata(pdev, hisi_pcie);

	ret = hisi_add_pcie_port(hisi_pcie, pdev);
	if (ret)
		return ret;

	return 0;
}

static struct pcie_soc_ops hip05_ops = {
		&hisi_pcie_link_up_hip05
};

static struct pcie_soc_ops hip06_ops = {
		&hisi_pcie_link_up_hip06
};

static const struct of_device_id hisi_pcie_of_match[] = {
	{
			.compatible = "hisilicon,hip05-pcie",
			.data	    = (void *) &hip05_ops,
	},
	{
			.compatible = "hisilicon,hip06-pcie",
			.data	    = (void *) &hip06_ops,
	},
	{},
};

static struct platform_driver hisi_pcie_driver = {
	.probe  = hisi_pcie_probe,
	.driver = {
		   .name = "hisi-pcie",
		   .of_match_table = hisi_pcie_of_match,
		   .suppress_bind_attrs = true,
	},
};
builtin_platform_driver(hisi_pcie_driver);

static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pci_ecam_ops *ops;

	ops = (struct pci_ecam_ops *)of_device_get_match_data(dev);
	return pci_host_common_probe(pdev, ops);
}

static int hisi_pcie_platform_init(struct pci_config_window *cfg)
{
	struct device *dev = cfg->parent;
	struct platform_device *pdev = to_platform_device(dev);
	struct resource *res;
	void __iomem *reg_base;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(dev, "missing \"reg[1]\"property\n");
		return -EINVAL;
	}

	reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
	if (!reg_base)
		return -ENOMEM;

	cfg->priv = reg_base;
	return 0;
}

struct pci_ecam_ops hisi_pcie_platform_ops = {
	.bus_shift    = 20,
	.init         =  hisi_pcie_platform_init,
	.pci_ops      = {
		.map_bus    = hisi_pcie_map_bus,
		.read       = hisi_pcie_rd_conf,
		.write      = hisi_pcie_wr_conf,
	}
};

static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
	{
		.compatible =  "hisilicon,hip06-pcie-ecam",
		.data	    = (void *) &hisi_pcie_platform_ops,
	},
	{
		.compatible =  "hisilicon,hip07-pcie-ecam",
		.data       = (void *) &hisi_pcie_platform_ops,
	},
	{},
};

static struct platform_driver hisi_pcie_almost_ecam_driver = {
	.probe  = hisi_pcie_almost_ecam_probe,
	.driver = {
		   .name = "hisi-pcie-almost-ecam",
		   .of_match_table = hisi_pcie_almost_ecam_of_match,
		   .suppress_bind_attrs = true,
	},
};
builtin_platform_driver(hisi_pcie_almost_ecam_driver);

#endif
#endif
Commit	Line	Data
500a1d9a	1	/*
5930fe4e	2	* PCIe host controller driver for HiSilicon SoCs
500a1d9a ZW	3	*
	4	* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
	5	*
5930fe4e GP	6	* Authors: Zhou Wang <wangzhou1@hisilicon.com>
	7	* Dacai Zhu <zhudacai@hisilicon.com>
	8	* Gabriele Paoloni <gabriele.paoloni@huawei.com>
500a1d9a ZW	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14	#include <linux/interrupt.h>
fb38118d	15	#include <linux/init.h>
500a1d9a ZW	16	#include <linux/mfd/syscon.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_pci.h>
	19	#include <linux/platform_device.h>
5930fe4e	20	#include <linux/of_device.h>
5f00f1a0 DL	21	#include <linux/pci.h>
	22	#include <linux/pci-acpi.h>
	23	#include <linux/pci-ecam.h>
500a1d9a	24	#include <linux/regmap.h>
5f00f1a0 DL	25	#include "../pci.h"
5f00f1a0 DL	26
a2ec1996	27	#if defined(CONFIG_PCI_HISI) \|\| (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
5f00f1a0	28
4788316f BH	29	static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
4788316f BH	30	int size, u32 *val)
5f00f1a0 DL	31	{
	32	struct pci_config_window *cfg = bus->sysdata;
	33	int dev = PCI_SLOT(devfn);
	34
	35	if (bus->number == cfg->busr.start) {
	36	/* access only one slot on each root port */
	37	if (dev > 0)
	38	return PCIBIOS_DEVICE_NOT_FOUND;
	39	else
	40	return pci_generic_config_read32(bus, devfn, where,
	41	size, val);
	42	}
	43
	44	return pci_generic_config_read(bus, devfn, where, size, val);
	45	}
	46
4788316f BH	47	static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
4788316f BH	48	int where, int size, u32 val)
5f00f1a0 DL	49	{
	50	struct pci_config_window *cfg = bus->sysdata;
	51	int dev = PCI_SLOT(devfn);
	52
	53	if (bus->number == cfg->busr.start) {
	54	/* access only one slot on each root port */
	55	if (dev > 0)
	56	return PCIBIOS_DEVICE_NOT_FOUND;
	57	else
	58	return pci_generic_config_write32(bus, devfn, where,
	59	size, val);
	60	}
	61
	62	return pci_generic_config_write(bus, devfn, where, size, val);
	63	}
	64
	65	static void __iomem hisi_pcie_map_bus(struct pci_bus bus, unsigned int devfn,
	66	int where)
	67	{
	68	struct pci_config_window *cfg = bus->sysdata;
	69	void __iomem *reg_base = cfg->priv;
	70
	71	if (bus->number == cfg->busr.start)
	72	return reg_base + where;
	73	else
	74	return pci_ecam_map_bus(bus, devfn, where);
	75	}
	76
a2ec1996 DL	77	#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
a2ec1996 DL	78
5f00f1a0 DL	79	static int hisi_pcie_init(struct pci_config_window *cfg)
	80	{
	81	struct device *dev = cfg->parent;
	82	struct acpi_device *adev = to_acpi_device(dev);
	83	struct acpi_pci_root *root = acpi_driver_data(adev);
	84	struct resource *res;
	85	void __iomem *reg_base;
	86	int ret;
	87
	88	/*
	89	* Retrieve RC base and size from a HISI0081 device with _UID
	90	* matching our segment.
	91	*/
	92	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
	93	if (!res)
	94	return -ENOMEM;
	95
	96	ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
	97	if (ret) {
	98	dev_err(dev, "can't get rc base address\n");
	99	return -ENOMEM;
	100	}
	101
e313a447	102	reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
5f00f1a0 DL	103	if (!reg_base)
	104	return -ENOMEM;
	105
	106	cfg->priv = reg_base;
	107	return 0;
	108	}
	109
	110	struct pci_ecam_ops hisi_pcie_ops = {
	111	.bus_shift = 20,
	112	.init = hisi_pcie_init,
	113	.pci_ops = {
	114	.map_bus = hisi_pcie_map_bus,
4788316f BH	115	.read = hisi_pcie_rd_conf,
4788316f BH	116	.write = hisi_pcie_wr_conf,
5f00f1a0 DL	117	}
	118	};
	119
	120	#endif
	121
	122	#ifdef CONFIG_PCI_HISI
500a1d9a ZW	123
	124	#include "pcie-designware.h"
	125
a458ce33 BH	126	#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
	127	#define PCIE_HIP06_CTRL_OFF 0x1000
	128	#define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
	129	#define PCIE_LTSSM_LINKUP_STATE 0x11
	130	#define PCIE_LTSSM_STATE_MASK 0x3F
500a1d9a	131
442ec4c0	132	#define to_hisi_pcie(x) dev_get_drvdata((x)->dev)
500a1d9a	133
5930fe4e GP	134	struct hisi_pcie;
	135
	136	struct pcie_soc_ops {
bf4ed37c	137	int (hisi_pcie_link_up)(struct hisi_pcie hisi_pcie);
5930fe4e GP	138	};
5930fe4e GP	139
500a1d9a	140	struct hisi_pcie {
442ec4c0	141	struct dw_pcie *pci;
500a1d9a	142	struct regmap *subctrl;
500a1d9a	143	u32 port_id;
792e0a68	144	const struct pcie_soc_ops *soc_ops;
500a1d9a ZW	145	};
500a1d9a ZW	146
5930fe4e	147	/* HipXX PCIe host only supports 32-bit config access */
500a1d9a ZW	148	static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
	149	u32 *val)
	150	{
	151	u32 reg;
	152	u32 reg_val;
500a1d9a	153	void *walker = &reg_val;
442ec4c0	154	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
500a1d9a ZW	155
	156	walker += (where & 0x3);
	157	reg = where & ~0x3;
442ec4c0	158	reg_val = dw_pcie_readl_dbi(pci, reg);
500a1d9a ZW	159
	160	if (size == 1)
	161	val = (u8 __force *) walker;
	162	else if (size == 2)
	163	val = (u16 __force *) walker;
1dbe162d DL	164	else if (size == 4)
	165	*val = reg_val;
	166	else
500a1d9a ZW	167	return PCIBIOS_BAD_REGISTER_NUMBER;
	168
	169	return PCIBIOS_SUCCESSFUL;
	170	}
	171
5930fe4e	172	/* HipXX PCIe host only supports 32-bit config access */
500a1d9a ZW	173	static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
	174	u32 val)
	175	{
	176	u32 reg_val;
	177	u32 reg;
500a1d9a	178	void *walker = &reg_val;
442ec4c0	179	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
500a1d9a ZW	180
	181	walker += (where & 0x3);
	182	reg = where & ~0x3;
	183	if (size == 4)
442ec4c0	184	dw_pcie_writel_dbi(pci, reg, val);
500a1d9a	185	else if (size == 2) {
442ec4c0	186	reg_val = dw_pcie_readl_dbi(pci, reg);
500a1d9a	187	(u16 __force ) walker = val;
442ec4c0	188	dw_pcie_writel_dbi(pci, reg, reg_val);
500a1d9a	189	} else if (size == 1) {
442ec4c0	190	reg_val = dw_pcie_readl_dbi(pci, reg);
500a1d9a	191	(u8 __force ) walker = val;
442ec4c0	192	dw_pcie_writel_dbi(pci, reg, reg_val);
500a1d9a ZW	193	} else
	194	return PCIBIOS_BAD_REGISTER_NUMBER;
	195
	196	return PCIBIOS_SUCCESSFUL;
	197	}
	198
5930fe4e	199	static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
500a1d9a ZW	200	{
500a1d9a ZW	201	u32 val;
500a1d9a ZW	202
	203	regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
	204	0x100 * hisi_pcie->port_id, &val);
	205
	206	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
	207	}
	208
5930fe4e GP	209	static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
5930fe4e GP	210	{
442ec4c0	211	struct dw_pcie *pci = hisi_pcie->pci;
5930fe4e GP	212	u32 val;
5930fe4e GP	213
442ec4c0	214	val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
5930fe4e GP	215
	216	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
	217	}
	218
442ec4c0	219	static int hisi_pcie_link_up(struct dw_pcie *pci)
5930fe4e	220	{
442ec4c0	221	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);
5930fe4e GP	222
	223	return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
	224	}
	225
442ec4c0	226	static struct dw_pcie_host_ops hisi_pcie_host_ops = {
500a1d9a ZW	227	.rd_own_conf = hisi_pcie_cfg_read,
500a1d9a ZW	228	.wr_own_conf = hisi_pcie_cfg_write,
500a1d9a ZW	229	};
500a1d9a ZW	230
e9480b5a BH	231	static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
e9480b5a BH	232	struct platform_device *pdev)
500a1d9a	233	{
442ec4c0 KVA	234	struct dw_pcie *pci = hisi_pcie->pci;
	235	struct pcie_port *pp = &pci->pp;
	236	struct device *dev = &pdev->dev;
500a1d9a ZW	237	int ret;
500a1d9a ZW	238	u32 port_id;
500a1d9a	239
88790f99 BH	240	if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
88790f99 BH	241	dev_err(dev, "failed to read port-id\n");
500a1d9a ZW	242	return -EINVAL;
	243	}
	244	if (port_id > 3) {
88790f99	245	dev_err(dev, "Invalid port-id: %d\n", port_id);
500a1d9a ZW	246	return -EINVAL;
	247	}
	248	hisi_pcie->port_id = port_id;
	249
	250	pp->ops = &hisi_pcie_host_ops;
	251
	252	ret = dw_pcie_host_init(pp);
	253	if (ret) {
88790f99	254	dev_err(dev, "failed to initialize host\n");
500a1d9a ZW	255	return ret;
	256	}
	257
	258	return 0;
	259	}
	260
442ec4c0 KVA	261	static const struct dw_pcie_ops dw_pcie_ops = {
	262	.link_up = hisi_pcie_link_up,
	263	};
	264
9f55cf56	265	static int hisi_pcie_probe(struct platform_device *pdev)
500a1d9a	266	{
88790f99	267	struct device *dev = &pdev->dev;
442ec4c0	268	struct dw_pcie *pci;
500a1d9a	269	struct hisi_pcie *hisi_pcie;
500a1d9a	270	struct resource *reg;
5930fe4e	271	struct device_driver *driver;
500a1d9a ZW	272	int ret;
500a1d9a ZW	273
88790f99	274	hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
500a1d9a ZW	275	if (!hisi_pcie)
	276	return -ENOMEM;
	277
442ec4c0 KVA	278	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	279	if (!pci)
	280	return -ENOMEM;
	281
	282	pci->dev = dev;
	283	pci->ops = &dw_pcie_ops;
	284
88790f99	285	driver = dev->driver;
5930fe4e	286
c0464062 GR	287	hisi_pcie->pci = pci;
c0464062 GR	288
792e0a68	289	hisi_pcie->soc_ops = of_device_get_match_data(dev);
500a1d9a ZW	290
500a1d9a ZW	291	hisi_pcie->subctrl =
792e0a68	292	syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
500a1d9a	293	if (IS_ERR(hisi_pcie->subctrl)) {
88790f99	294	dev_err(dev, "cannot get subctrl base\n");
500a1d9a ZW	295	return PTR_ERR(hisi_pcie->subctrl);
	296	}
	297
	298	reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
e313a447	299	pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg);
442ec4c0 KVA	300	if (IS_ERR(pci->dbi_base))
442ec4c0 KVA	301	return PTR_ERR(pci->dbi_base);
9bcf0a6f KVA	302	platform_set_drvdata(pdev, hisi_pcie);
9bcf0a6f KVA	303
e9480b5a	304	ret = hisi_add_pcie_port(hisi_pcie, pdev);
500a1d9a ZW	305	if (ret)
	306	return ret;
	307
500a1d9a ZW	308	return 0;
	309	}
	310
5930fe4e GP	311	static struct pcie_soc_ops hip05_ops = {
	312	&hisi_pcie_link_up_hip05
	313	};
	314
	315	static struct pcie_soc_ops hip06_ops = {
	316	&hisi_pcie_link_up_hip06
	317	};
	318
500a1d9a	319	static const struct of_device_id hisi_pcie_of_match[] = {
5930fe4e GP	320	{
	321	.compatible = "hisilicon,hip05-pcie",
	322	.data = (void *) &hip05_ops,
	323	},
	324	{
	325	.compatible = "hisilicon,hip06-pcie",
	326	.data = (void *) &hip06_ops,
	327	},
500a1d9a ZW	328	{},
	329	};
	330
500a1d9a ZW	331	static struct platform_driver hisi_pcie_driver = {
	332	.probe = hisi_pcie_probe,
	333	.driver = {
	334	.name = "hisi-pcie",
	335	.of_match_table = hisi_pcie_of_match,
a5f40e80	336	.suppress_bind_attrs = true,
500a1d9a ZW	337	},
500a1d9a ZW	338	};
fb38118d	339	builtin_platform_driver(hisi_pcie_driver);
5f00f1a0	340
a2ec1996 DL	341	static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev)
	342	{
	343	struct device *dev = &pdev->dev;
	344	struct pci_ecam_ops *ops;
	345
	346	ops = (struct pci_ecam_ops *)of_device_get_match_data(dev);
	347	return pci_host_common_probe(pdev, ops);
	348	}
	349
	350	static int hisi_pcie_platform_init(struct pci_config_window *cfg)
	351	{
	352	struct device *dev = cfg->parent;
	353	struct platform_device *pdev = to_platform_device(dev);
	354	struct resource *res;
	355	void __iomem *reg_base;
	356
	357	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	358	if (!res) {
	359	dev_err(dev, "missing \"reg[1]\"property\n");
	360	return -EINVAL;
	361	}
	362
e313a447	363	reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
a2ec1996 DL	364	if (!reg_base)
	365	return -ENOMEM;
	366
	367	cfg->priv = reg_base;
	368	return 0;
	369	}
	370
	371	struct pci_ecam_ops hisi_pcie_platform_ops = {
	372	.bus_shift = 20,
	373	.init = hisi_pcie_platform_init,
	374	.pci_ops = {
	375	.map_bus = hisi_pcie_map_bus,
4788316f BH	376	.read = hisi_pcie_rd_conf,
4788316f BH	377	.write = hisi_pcie_wr_conf,
a2ec1996 DL	378	}
	379	};
	380
	381	static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
	382	{
b9c1153f	383	.compatible = "hisilicon,hip06-pcie-ecam",
a2ec1996 DL	384	.data = (void *) &hisi_pcie_platform_ops,
a2ec1996 DL	385	},
b9c1153f DL	386	{
	387	.compatible = "hisilicon,hip07-pcie-ecam",
	388	.data = (void *) &hisi_pcie_platform_ops,
	389	},
a2ec1996 DL	390	{},
	391	};
	392
	393	static struct platform_driver hisi_pcie_almost_ecam_driver = {
	394	.probe = hisi_pcie_almost_ecam_probe,
	395	.driver = {
	396	.name = "hisi-pcie-almost-ecam",
	397	.of_match_table = hisi_pcie_almost_ecam_of_match,
a5f40e80	398	.suppress_bind_attrs = true,
a2ec1996 DL	399	},
	400	};
	401	builtin_platform_driver(hisi_pcie_almost_ecam_driver);
	402
	403	#endif
5f00f1a0	404	#endif