[linux-2.6-block.git] / drivers / pci / dwc / pci-layerscape.c

/*
 * PCIe host controller driver for Freescale Layerscape SoCs
 *
 * Copyright (C) 2014 Freescale Semiconductor.
 *
 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pcie-designware.h"

/* PEX1/2 Misc Ports Status Register */
#define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
#define LTSSM_STATE_SHIFT	20
#define LTSSM_STATE_MASK	0x3f
#define LTSSM_PCIE_L0		0x11 /* L0 state */

/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */

struct ls_pcie_drvdata {
	u32 lut_offset;
	u32 ltssm_shift;
	u32 lut_dbg;
	struct dw_pcie_host_ops *ops;
	const struct dw_pcie_ops *dw_pcie_ops;
};

struct ls_pcie {
	struct dw_pcie *pci;
	void __iomem *lut;
	struct regmap *scfg;
	const struct ls_pcie_drvdata *drvdata;
	int index;
};

#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)

static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
{
	struct dw_pcie *pci = pcie->pci;
	u32 header_type;

	header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
	header_type &= 0x7f;

	return header_type == PCI_HEADER_TYPE_BRIDGE;
}

/* Clear multi-function bit */
static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
{
	struct dw_pcie *pci = pcie->pci;

	iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
}

/* Fix class value */
static void ls_pcie_fix_class(struct ls_pcie *pcie)
{
	struct dw_pcie *pci = pcie->pci;

	iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
}

/* Drop MSG TLP except for Vendor MSG */
static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
	u32 val;
	struct dw_pcie *pci = pcie->pci;

	val = ioread32(pci->dbi_base + PCIE_STRFMR1);
	val &= 0xDFFFFFFF;
	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
}

static int ls1021_pcie_link_up(struct dw_pcie *pci)
{
	u32 state;
	struct ls_pcie *pcie = to_ls_pcie(pci);

	if (!pcie->scfg)
		return 0;

	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls1021_pcie_host_init(struct pcie_port *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct ls_pcie *pcie = to_ls_pcie(pci);
	struct device *dev = pci->dev;
	u32 index[2];

	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "fsl,pcie-scfg");
	if (IS_ERR(pcie->scfg)) {
		dev_err(dev, "No syscfg phandle specified\n");
		pcie->scfg = NULL;
		return;
	}

	if (of_property_read_u32_array(dev->of_node,
				       "fsl,pcie-scfg", index, 2)) {
		pcie->scfg = NULL;
		return;
	}
	pcie->index = index[1];

	dw_pcie_setup_rc(pp);

	ls_pcie_drop_msg_tlp(pcie);
}

static int ls_pcie_link_up(struct dw_pcie *pci)
{
	struct ls_pcie *pcie = to_ls_pcie(pci);
	u32 state;

	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
		 pcie->drvdata->ltssm_shift) &
		 LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls_pcie_host_init(struct pcie_port *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct ls_pcie *pcie = to_ls_pcie(pci);

	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
	ls_pcie_fix_class(pcie);
	ls_pcie_clear_multifunction(pcie);
	ls_pcie_drop_msg_tlp(pcie);
	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
}

static int ls_pcie_msi_host_init(struct pcie_port *pp,
				 struct msi_controller *chip)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct device *dev = pci->dev;
	struct device_node *np = dev->of_node;
	struct device_node *msi_node;

	/*
	 * The MSI domain is set by the generic of_msi_configure().  This
	 * .msi_host_init() function keeps us from doing the default MSI
	 * domain setup in dw_pcie_host_init() and also enforces the
	 * requirement that "msi-parent" exists.
	 */
	msi_node = of_parse_phandle(np, "msi-parent", 0);
	if (!msi_node) {
		dev_err(dev, "failed to find msi-parent\n");
		return -EINVAL;
	}

	return 0;
}

static struct dw_pcie_host_ops ls1021_pcie_host_ops = {
	.host_init = ls1021_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static struct dw_pcie_host_ops ls_pcie_host_ops = {
	.host_init = ls_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
	.link_up = ls1021_pcie_link_up,
};

static const struct dw_pcie_ops dw_ls_pcie_ops = {
	.link_up = ls_pcie_link_up,
};

static struct ls_pcie_drvdata ls1021_drvdata = {
	.ops = &ls1021_pcie_host_ops,
	.dw_pcie_ops = &dw_ls1021_pcie_ops,
};

static struct ls_pcie_drvdata ls1043_drvdata = {
	.lut_offset = 0x10000,
	.ltssm_shift = 24,
	.lut_dbg = 0x7fc,
	.ops = &ls_pcie_host_ops,
	.dw_pcie_ops = &dw_ls_pcie_ops,
};

static struct ls_pcie_drvdata ls1046_drvdata = {
	.lut_offset = 0x80000,
	.ltssm_shift = 24,
	.lut_dbg = 0x407fc,
	.ops = &ls_pcie_host_ops,
	.dw_pcie_ops = &dw_ls_pcie_ops,
};

static struct ls_pcie_drvdata ls2080_drvdata = {
	.lut_offset = 0x80000,
	.ltssm_shift = 0,
	.lut_dbg = 0x7fc,
	.ops = &ls_pcie_host_ops,
	.dw_pcie_ops = &dw_ls_pcie_ops,
};

static const struct of_device_id ls_pcie_of_match[] = {
	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
	{ },
};

static int __init ls_add_pcie_port(struct ls_pcie *pcie)
{
	struct dw_pcie *pci = pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct device *dev = pci->dev;
	int ret;

	pp->ops = pcie->drvdata->ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init ls_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct ls_pcie *pcie;
	struct resource *dbi_base;
	int ret;

	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	pcie->drvdata = of_device_get_match_data(dev);

	pci->dev = dev;
	pci->ops = pcie->drvdata->dw_pcie_ops;

	pcie->pci = pci;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
	if (IS_ERR(pci->dbi_base))
		return PTR_ERR(pci->dbi_base);

	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;

	if (!ls_pcie_is_bridge(pcie))
		return -ENODEV;

	platform_set_drvdata(pdev, pcie);

	ret = ls_add_pcie_port(pcie);
	if (ret < 0)
		return ret;

	return 0;
}

static struct platform_driver ls_pcie_driver = {
	.driver = {
		.name = "layerscape-pcie",
		.of_match_table = ls_pcie_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
Commit	Line	Data
62d0ff83 ML	1	/*
	2	* PCIe host controller driver for Freescale Layerscape SoCs
	3	*
	4	* Copyright (C) 2014 Freescale Semiconductor.
	5	*
5192ec7b	6	* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
62d0ff83 ML	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
62d0ff83	14	#include <linux/interrupt.h>
154fb600	15	#include <linux/init.h>
62d0ff83 ML	16	#include <linux/of_pci.h>
	17	#include <linux/of_platform.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
	20	#include <linux/pci.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/resource.h>
	23	#include <linux/mfd/syscon.h>
	24	#include <linux/regmap.h>
	25
	26	#include "pcie-designware.h"
	27
	28	/* PEX1/2 Misc Ports Status Register */
	29	#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
	30	#define LTSSM_STATE_SHIFT 20
	31	#define LTSSM_STATE_MASK 0x3f
	32	#define LTSSM_PCIE_L0 0x11 /* L0 state */
	33
5192ec7b ML	34	/* PEX Internal Configuration Registers */
	35	#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
	36	#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
	37
d6463345	38	struct ls_pcie_drvdata {
5192ec7b ML	39	u32 lut_offset;
5192ec7b ML	40	u32 ltssm_shift;
1d77040b	41	u32 lut_dbg;
442ec4c0 KVA	42	struct dw_pcie_host_ops *ops;
442ec4c0 KVA	43	const struct dw_pcie_ops *dw_pcie_ops;
d6463345 ML	44	};
d6463345 ML	45
62d0ff83	46	struct ls_pcie {
442ec4c0	47	struct dw_pcie *pci;
5192ec7b	48	void __iomem *lut;
62d0ff83	49	struct regmap *scfg;
d6463345	50	const struct ls_pcie_drvdata *drvdata;
62d0ff83	51	int index;
62d0ff83 ML	52	};
62d0ff83 ML	53
442ec4c0	54	#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
62d0ff83	55
7af4ce35 ML	56	static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
7af4ce35 ML	57	{
442ec4c0	58	struct dw_pcie *pci = pcie->pci;
7af4ce35 ML	59	u32 header_type;
7af4ce35 ML	60
442ec4c0	61	header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
7af4ce35 ML	62	header_type &= 0x7f;
	63
	64	return header_type == PCI_HEADER_TYPE_BRIDGE;
	65	}
	66
5192ec7b ML	67	/* Clear multi-function bit */
	68	static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
	69	{
442ec4c0 KVA	70	struct dw_pcie *pci = pcie->pci;
	71
	72	iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
5192ec7b ML	73	}
	74
	75	/* Fix class value */
	76	static void ls_pcie_fix_class(struct ls_pcie *pcie)
	77	{
442ec4c0 KVA	78	struct dw_pcie *pci = pcie->pci;
	79
	80	iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
5192ec7b ML	81	}
5192ec7b ML	82
1195c103 ML	83	/* Drop MSG TLP except for Vendor MSG */
	84	static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
	85	{
	86	u32 val;
442ec4c0	87	struct dw_pcie *pci = pcie->pci;
1195c103	88
442ec4c0	89	val = ioread32(pci->dbi_base + PCIE_STRFMR1);
1195c103	90	val &= 0xDFFFFFFF;
442ec4c0	91	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
1195c103 ML	92	}
1195c103 ML	93
442ec4c0	94	static int ls1021_pcie_link_up(struct dw_pcie *pci)
62d0ff83 ML	95	{
62d0ff83 ML	96	u32 state;
442ec4c0	97	struct ls_pcie *pcie = to_ls_pcie(pci);
62d0ff83	98
d6463345 ML	99	if (!pcie->scfg)
	100	return 0;
	101
62d0ff83 ML	102	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	103	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
	104
	105	if (state < LTSSM_PCIE_L0)
	106	return 0;
	107
	108	return 1;
	109	}
	110
d6463345	111	static void ls1021_pcie_host_init(struct pcie_port *pp)
1d3f9bac	112	{
442ec4c0 KVA	113	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	114	struct ls_pcie *pcie = to_ls_pcie(pci);
	115	struct device *dev = pci->dev;
1195c103	116	u32 index[2];
d6463345	117
c11125eb	118	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
d6463345 ML	119	"fsl,pcie-scfg");
d6463345 ML	120	if (IS_ERR(pcie->scfg)) {
c11125eb	121	dev_err(dev, "No syscfg phandle specified\n");
d6463345 ML	122	pcie->scfg = NULL;
	123	return;
	124	}
	125
c11125eb	126	if (of_property_read_u32_array(dev->of_node,
d6463345 ML	127	"fsl,pcie-scfg", index, 2)) {
	128	pcie->scfg = NULL;
	129	return;
	130	}
	131	pcie->index = index[1];
1d3f9bac BH	132
1d3f9bac BH	133	dw_pcie_setup_rc(pp);
1d3f9bac	134
1195c103	135	ls_pcie_drop_msg_tlp(pcie);
62d0ff83 ML	136	}
62d0ff83 ML	137
442ec4c0	138	static int ls_pcie_link_up(struct dw_pcie *pci)
5192ec7b	139	{
442ec4c0	140	struct ls_pcie *pcie = to_ls_pcie(pci);
5192ec7b ML	141	u32 state;
5192ec7b ML	142
1d77040b	143	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
5192ec7b ML	144	pcie->drvdata->ltssm_shift) &
	145	LTSSM_STATE_MASK;
	146
	147	if (state < LTSSM_PCIE_L0)
	148	return 0;
	149
	150	return 1;
	151	}
	152
	153	static void ls_pcie_host_init(struct pcie_port *pp)
	154	{
442ec4c0 KVA	155	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442ec4c0 KVA	156	struct ls_pcie *pcie = to_ls_pcie(pci);
5192ec7b	157
442ec4c0	158	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	159	ls_pcie_fix_class(pcie);
5192ec7b ML	160	ls_pcie_clear_multifunction(pcie);
1195c103	161	ls_pcie_drop_msg_tlp(pcie);
442ec4c0	162	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	163	}
5192ec7b ML	164
bd33b87a ML	165	static int ls_pcie_msi_host_init(struct pcie_port *pp,
	166	struct msi_controller *chip)
	167	{
442ec4c0 KVA	168	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442ec4c0 KVA	169	struct device *dev = pci->dev;
c11125eb	170	struct device_node *np = dev->of_node;
bd33b87a	171	struct device_node *msi_node;
bd33b87a ML	172
	173	/*
	174	* The MSI domain is set by the generic of_msi_configure(). This
	175	* .msi_host_init() function keeps us from doing the default MSI
	176	* domain setup in dw_pcie_host_init() and also enforces the
	177	* requirement that "msi-parent" exists.
	178	*/
	179	msi_node = of_parse_phandle(np, "msi-parent", 0);
	180	if (!msi_node) {
c11125eb	181	dev_err(dev, "failed to find msi-parent\n");
bd33b87a ML	182	return -EINVAL;
	183	}
	184
	185	return 0;
	186	}
	187
442ec4c0	188	static struct dw_pcie_host_ops ls1021_pcie_host_ops = {
d6463345	189	.host_init = ls1021_pcie_host_init,
bd33b87a	190	.msi_host_init = ls_pcie_msi_host_init,
d6463345 ML	191	};
d6463345 ML	192
442ec4c0	193	static struct dw_pcie_host_ops ls_pcie_host_ops = {
5192ec7b	194	.host_init = ls_pcie_host_init,
bd33b87a	195	.msi_host_init = ls_pcie_msi_host_init,
5192ec7b ML	196	};
5192ec7b ML	197
442ec4c0 KVA	198	static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
	199	.link_up = ls1021_pcie_link_up,
	200	};
	201
	202	static const struct dw_pcie_ops dw_ls_pcie_ops = {
	203	.link_up = ls_pcie_link_up,
	204	};
	205
d6463345 ML	206	static struct ls_pcie_drvdata ls1021_drvdata = {
d6463345 ML	207	.ops = &ls1021_pcie_host_ops,
442ec4c0	208	.dw_pcie_ops = &dw_ls1021_pcie_ops,
62d0ff83 ML	209	};
62d0ff83 ML	210
5192ec7b ML	211	static struct ls_pcie_drvdata ls1043_drvdata = {
	212	.lut_offset = 0x10000,
	213	.ltssm_shift = 24,
1d77040b MH	214	.lut_dbg = 0x7fc,
1d77040b MH	215	.ops = &ls_pcie_host_ops,
442ec4c0	216	.dw_pcie_ops = &dw_ls_pcie_ops,
1d77040b MH	217	};
	218
	219	static struct ls_pcie_drvdata ls1046_drvdata = {
	220	.lut_offset = 0x80000,
	221	.ltssm_shift = 24,
	222	.lut_dbg = 0x407fc,
5192ec7b	223	.ops = &ls_pcie_host_ops,
442ec4c0	224	.dw_pcie_ops = &dw_ls_pcie_ops,
5192ec7b ML	225	};
	226
	227	static struct ls_pcie_drvdata ls2080_drvdata = {
	228	.lut_offset = 0x80000,
	229	.ltssm_shift = 0,
1d77040b	230	.lut_dbg = 0x7fc,
5192ec7b	231	.ops = &ls_pcie_host_ops,
442ec4c0	232	.dw_pcie_ops = &dw_ls_pcie_ops,
5192ec7b ML	233	};
5192ec7b ML	234
d6463345 ML	235	static const struct of_device_id ls_pcie_of_match[] = {
d6463345 ML	236	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
5192ec7b	237	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1d77040b	238	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
5192ec7b	239	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
dbae40b7	240	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
d6463345 ML	241	{ },
d6463345 ML	242	};
d6463345	243
4726a823	244	static int __init ls_add_pcie_port(struct ls_pcie *pcie)
62d0ff83	245	{
442ec4c0 KVA	246	struct dw_pcie *pci = pcie->pci;
	247	struct pcie_port *pp = &pci->pp;
	248	struct device *dev = pci->dev;
62d0ff83 ML	249	int ret;
62d0ff83 ML	250
442ec4c0 KVA	251	pp->ops = pcie->drvdata->ops;
442ec4c0 KVA	252
62d0ff83 ML	253	ret = dw_pcie_host_init(pp);
62d0ff83 ML	254	if (ret) {
c11125eb	255	dev_err(dev, "failed to initialize host\n");
62d0ff83 ML	256	return ret;
	257	}
	258
	259	return 0;
	260	}
	261
	262	static int __init ls_pcie_probe(struct platform_device *pdev)
	263	{
c11125eb	264	struct device *dev = &pdev->dev;
442ec4c0	265	struct dw_pcie *pci;
62d0ff83 ML	266	struct ls_pcie *pcie;
62d0ff83 ML	267	struct resource *dbi_base;
62d0ff83 ML	268	int ret;
62d0ff83 ML	269
c11125eb	270	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
62d0ff83 ML	271	if (!pcie)
	272	return -ENOMEM;
	273
442ec4c0 KVA	274	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	275	if (!pci)
	276	return -ENOMEM;
	277
6dc2c04f	278	pcie->drvdata = of_device_get_match_data(dev);
442ec4c0 KVA	279
	280	pci->dev = dev;
	281	pci->ops = pcie->drvdata->dw_pcie_ops;
fefe6733	282
c0464062 GR	283	pcie->pci = pci;
c0464062 GR	284
62d0ff83	285	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
01bd489d	286	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
442ec4c0 KVA	287	if (IS_ERR(pci->dbi_base))
442ec4c0 KVA	288	return PTR_ERR(pci->dbi_base);
62d0ff83	289
442ec4c0	290	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
62d0ff83	291
7af4ce35 ML	292	if (!ls_pcie_is_bridge(pcie))
	293	return -ENODEV;
	294
9bcf0a6f KVA	295	platform_set_drvdata(pdev, pcie);
9bcf0a6f KVA	296
4726a823	297	ret = ls_add_pcie_port(pcie);
62d0ff83 ML	298	if (ret < 0)
	299	return ret;
	300
62d0ff83 ML	301	return 0;
	302	}
	303
62d0ff83 ML	304	static struct platform_driver ls_pcie_driver = {
	305	.driver = {
	306	.name = "layerscape-pcie",
62d0ff83	307	.of_match_table = ls_pcie_of_match,
a5f40e80	308	.suppress_bind_attrs = true,
62d0ff83 ML	309	},
62d0ff83 ML	310	};
154fb600	311	builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);