[linux-2.6-block.git] / drivers / pci / dwc / pci-dra7xx.c

/*
 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
 *
 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_gpio.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/resource.h>
#include <linux/types.h>

#include "pcie-designware.h"

/* PCIe controller wrapper DRA7XX configuration registers */

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN		0x0024
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN		0x0028
#define	ERR_SYS						BIT(0)
#define	ERR_FATAL					BIT(1)
#define	ERR_NONFATAL					BIT(2)
#define	ERR_COR						BIT(3)
#define	ERR_AXI						BIT(4)
#define	ERR_ECRC					BIT(5)
#define	PME_TURN_OFF					BIT(8)
#define	PME_TO_ACK					BIT(9)
#define	PM_PME						BIT(10)
#define	LINK_REQ_RST					BIT(11)
#define	LINK_UP_EVT					BIT(12)
#define	CFG_BME_EVT					BIT(13)
#define	CFG_MSE_EVT					BIT(14)
#define	INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
			ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
			LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI		0x0034
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI		0x0038
#define	INTA						BIT(0)
#define	INTB						BIT(1)
#define	INTC						BIT(2)
#define	INTD						BIT(3)
#define	MSI						BIT(4)
#define	LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)

#define	PCIECTRL_DRA7XX_CONF_DEVICE_CMD			0x0104
#define	LTSSM_EN					0x1

#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C
#define	LINK_UP						BIT(16)
#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF

#define EXP_CAP_ID_OFFSET				0x70

struct dra7xx_pcie {
	struct pcie_port	pp;
	void __iomem		*base;		/* DT ti_conf */
	int			phy_count;	/* DT phy-names count */
	struct phy		**phy;
	int			link_gen;
};

#define to_dra7xx_pcie(x)	container_of((x), struct dra7xx_pcie, pp)

static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
{
	return readl(pcie->base + offset);
}

static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
				      u32 value)
{
	writel(value, pcie->base + offset);
}

static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);

	return !!(reg & LINK_UP);
}

static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
{
	struct pcie_port *pp = &dra7xx->pp;
	struct device *dev = pp->dev;
	u32 reg;
	u32 exp_cap_off = EXP_CAP_ID_OFFSET;

	if (dw_pcie_link_up(pp)) {
		dev_err(dev, "link is already up\n");
		return 0;
	}

	if (dra7xx->link_gen == 1) {
		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
				 4, &reg);
		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
					  PCI_EXP_LNKCAP, 4, reg);
		}

		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
				 2, &reg);
		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
					  PCI_EXP_LNKCTL2, 2, reg);
		}
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg |= LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	return dw_pcie_wait_for_link(pp);
}

static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
{
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
			   ~INTERRUPTS);
	dra7xx_pcie_writel(dra7xx,
			   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
			   ~LEG_EP_INTERRUPTS & ~MSI);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	else
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
				   LEG_EP_INTERRUPTS);
}

static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;

	dw_pcie_setup_rc(pp);

	dra7xx_pcie_establish_link(dra7xx);
	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
	dra7xx_pcie_enable_interrupts(dra7xx);
}

static struct pcie_host_ops dra7xx_pcie_host_ops = {
	.link_up = dra7xx_pcie_link_up,
	.host_init = dra7xx_pcie_host_init,
};

static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops intx_domain_ops = {
	.map = dra7xx_pcie_intx_map,
};

static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
{
	struct device *dev = pp->dev;
	struct device_node *node = dev->of_node;
	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);

	if (!pcie_intc_node) {
		dev_err(dev, "No PCIe Intc node found\n");
		return -ENODEV;
	}

	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
					       &intx_domain_ops, pp);
	if (!pp->irq_domain) {
		dev_err(dev, "Failed to get a INTx IRQ domain\n");
		return -ENODEV;
	}

	return 0;
}

static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{
	struct dra7xx_pcie *dra7xx = arg;
	struct pcie_port *pp = &dra7xx->pp;
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);

	switch (reg) {
	case MSI:
		dw_handle_msi_irq(pp);
		break;
	case INTA:
	case INTB:
	case INTC:
	case INTD:
		generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
		break;
	}

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);

	return IRQ_HANDLED;
}


static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{
	struct dra7xx_pcie *dra7xx = arg;
	struct device *dev = dra7xx->pp.dev;
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);

	if (reg & ERR_SYS)
		dev_dbg(dev, "System Error\n");

	if (reg & ERR_FATAL)
		dev_dbg(dev, "Fatal Error\n");

	if (reg & ERR_NONFATAL)
		dev_dbg(dev, "Non Fatal Error\n");

	if (reg & ERR_COR)
		dev_dbg(dev, "Correctable Error\n");

	if (reg & ERR_AXI)
		dev_dbg(dev, "AXI tag lookup fatal Error\n");

	if (reg & ERR_ECRC)
		dev_dbg(dev, "ECRC Error\n");

	if (reg & PME_TURN_OFF)
		dev_dbg(dev,
			"Power Management Event Turn-Off message received\n");

	if (reg & PME_TO_ACK)
		dev_dbg(dev,
			"Power Management Turn-Off Ack message received\n");

	if (reg & PM_PME)
		dev_dbg(dev, "PM Power Management Event message received\n");

	if (reg & LINK_REQ_RST)
		dev_dbg(dev, "Link Request Reset\n");

	if (reg & LINK_UP_EVT)
		dev_dbg(dev, "Link-up state change\n");

	if (reg & CFG_BME_EVT)
		dev_dbg(dev, "CFG 'Bus Master Enable' change\n");

	if (reg & CFG_MSE_EVT)
		dev_dbg(dev, "CFG 'Memory Space Enable' change\n");

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);

	return IRQ_HANDLED;
}

static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
				       struct platform_device *pdev)
{
	int ret;
	struct pcie_port *pp = &dra7xx->pp;
	struct device *dev = pp->dev;
	struct resource *res;

	pp->irq = platform_get_irq(pdev, 1);
	if (pp->irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
			       IRQF_SHARED | IRQF_NO_THREAD,
			       "dra7-pcie-msi",	dra7xx);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
		ret = dra7xx_pcie_init_irq_domain(pp);
		if (ret < 0)
			return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	if (!pp->dbi_base)
		return -ENOMEM;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
	u32 reg;
	int ret;
	int irq;
	int i;
	int phy_count;
	struct phy **phy;
	void __iomem *base;
	struct resource *res;
	struct dra7xx_pcie *dra7xx;
	struct pcie_port *pp;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	char name[10];
	struct gpio_desc *reset;

	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	if (!dra7xx)
		return -ENOMEM;

	pp = &dra7xx->pp;
	pp->dev = dev;
	pp->ops = &dra7xx_pcie_host_ops;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!base)
		return -ENOMEM;

	phy_count = of_property_count_strings(np, "phy-names");
	if (phy_count < 0) {
		dev_err(dev, "unable to find the strings\n");
		return phy_count;
	}

	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	for (i = 0; i < phy_count; i++) {
		snprintf(name, sizeof(name), "pcie-phy%d", i);
		phy[i] = devm_phy_get(dev, name);
		if (IS_ERR(phy[i]))
			return PTR_ERR(phy[i]);

		ret = phy_init(phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(phy[i]);
		if (ret < 0) {
			phy_exit(phy[i]);
			goto err_phy;
		}
	}

	dra7xx->base = base;
	dra7xx->phy = phy;
	dra7xx->phy_count = phy_count;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync failed\n");
		goto err_get_sync;
	}

	reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
	if (IS_ERR(reset)) {
		ret = PTR_ERR(reset);
		dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
		goto err_gpio;
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg &= ~LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	dra7xx->link_gen = of_pci_get_max_link_speed(np);
	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
		dra7xx->link_gen = 2;

	ret = dra7xx_add_pcie_port(dra7xx, pdev);
	if (ret < 0)
		goto err_gpio;

	platform_set_drvdata(pdev, dra7xx);
	return 0;

err_gpio:
	pm_runtime_put(dev);

err_get_sync:
	pm_runtime_disable(dev);

err_phy:
	while (--i >= 0) {
		phy_power_off(phy[i]);
		phy_exit(phy[i]);
	}

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int dra7xx_pcie_suspend(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* clear MSE */
	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
	val &= ~PCI_COMMAND_MEMORY;
	dw_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_resume(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* set MSE */
	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
	val |= PCI_COMMAND_MEMORY;
	dw_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_suspend_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int count = dra7xx->phy_count;

	while (count--) {
		phy_power_off(dra7xx->phy[count]);
		phy_exit(dra7xx->phy[count]);
	}

	return 0;
}

static int dra7xx_pcie_resume_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int phy_count = dra7xx->phy_count;
	int ret;
	int i;

	for (i = 0; i < phy_count; i++) {
		ret = phy_init(dra7xx->phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(dra7xx->phy[i]);
		if (ret < 0) {
			phy_exit(dra7xx->phy[i]);
			goto err_phy;
		}
	}

	return 0;

err_phy:
	while (--i >= 0) {
		phy_power_off(dra7xx->phy[i]);
		phy_exit(dra7xx->phy[i]);
	}

	return ret;
}
#endif

static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
				      dra7xx_pcie_resume_noirq)
};

static const struct of_device_id of_dra7xx_pcie_match[] = {
	{ .compatible = "ti,dra7-pcie", },
	{},
};

static struct platform_driver dra7xx_pcie_driver = {
	.driver = {
		.name	= "dra7-pcie",
		.of_match_table = of_dra7xx_pcie_match,
		.suppress_bind_attrs = true,
		.pm	= &dra7xx_pcie_pm_ops,
	},
};
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
Commit	Line	Data
47ff3de9 KVA	1	/*
	2	* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
	3	*
	4	* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
	5	*
	6	* Authors: Kishon Vijay Abraham I <kishon@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
47ff3de9 KVA	13	#include <linux/err.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/kernel.h>
d29438d6	18	#include <linux/init.h>
78bdcad0	19	#include <linux/of_gpio.h>
ab5fe4f4	20	#include <linux/of_pci.h>
47ff3de9 KVA	21	#include <linux/pci.h>
	22	#include <linux/phy/phy.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/pm_runtime.h>
	25	#include <linux/resource.h>
	26	#include <linux/types.h>
	27
	28	#include "pcie-designware.h"
	29
	30	/* PCIe controller wrapper DRA7XX configuration registers */
	31
	32	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
	33	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
	34	#define ERR_SYS BIT(0)
	35	#define ERR_FATAL BIT(1)
	36	#define ERR_NONFATAL BIT(2)
	37	#define ERR_COR BIT(3)
	38	#define ERR_AXI BIT(4)
	39	#define ERR_ECRC BIT(5)
	40	#define PME_TURN_OFF BIT(8)
	41	#define PME_TO_ACK BIT(9)
	42	#define PM_PME BIT(10)
	43	#define LINK_REQ_RST BIT(11)
	44	#define LINK_UP_EVT BIT(12)
	45	#define CFG_BME_EVT BIT(13)
	46	#define CFG_MSE_EVT BIT(14)
	47	#define INTERRUPTS (ERR_SYS \| ERR_FATAL \| ERR_NONFATAL \| ERR_COR \| ERR_AXI \| \
	48	ERR_ECRC \| PME_TURN_OFF \| PME_TO_ACK \| PM_PME \| \
	49	LINK_REQ_RST \| LINK_UP_EVT \| CFG_BME_EVT \| CFG_MSE_EVT)
	50
	51	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
	52	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
	53	#define INTA BIT(0)
	54	#define INTB BIT(1)
	55	#define INTC BIT(2)
	56	#define INTD BIT(3)
	57	#define MSI BIT(4)
	58	#define LEG_EP_INTERRUPTS (INTA \| INTB \| INTC \| INTD)
	59
	60	#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
	61	#define LTSSM_EN 0x1
	62
	63	#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
	64	#define LINK_UP BIT(16)
883cc17c	65	#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
47ff3de9	66
ab5fe4f4 KVA	67	#define EXP_CAP_ID_OFFSET 0x70
ab5fe4f4 KVA	68
47ff3de9	69	struct dra7xx_pcie {
47ff3de9	70	struct pcie_port pp;
8e5ec414 BH	71	void __iomem base; / DT ti_conf */
	72	int phy_count; /* DT phy-names count */
	73	struct phy **phy;
ab5fe4f4	74	int link_gen;
47ff3de9 KVA	75	};
	76
	77	#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
	78
	79	static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
	80	{
	81	return readl(pcie->base + offset);
	82	}
	83
	84	static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
	85	u32 value)
	86	{
	87	writel(value, pcie->base + offset);
	88	}
	89
	90	static int dra7xx_pcie_link_up(struct pcie_port *pp)
	91	{
	92	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	93	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
	94
	95	return !!(reg & LINK_UP);
	96	}
	97
21baa1c4	98	static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
47ff3de9	99	{
21baa1c4	100	struct pcie_port *pp = &dra7xx->pp;
c7f8146b	101	struct device *dev = pp->dev;
6cbb247e	102	u32 reg;
ab5fe4f4	103	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
47ff3de9 KVA	104
47ff3de9 KVA	105	if (dw_pcie_link_up(pp)) {
c7f8146b	106	dev_err(dev, "link is already up\n");
47ff3de9 KVA	107	return 0;
	108	}
	109
ab5fe4f4 KVA	110	if (dra7xx->link_gen == 1) {
	111	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
	112	4, &reg);
	113	if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	114	reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
	115	reg \|= PCI_EXP_LNKCAP_SLS_2_5GB;
	116	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
	117	PCI_EXP_LNKCAP, 4, reg);
	118	}
	119
	120	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
	121	2, &reg);
	122	if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	123	reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
	124	reg \|= PCI_EXP_LNKCAP_SLS_2_5GB;
	125	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
	126	PCI_EXP_LNKCTL2, 2, reg);
	127	}
	128	}
	129
47ff3de9 KVA	130	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	131	reg \|= LTSSM_EN;
	132	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	133
886bc5ce	134	return dw_pcie_wait_for_link(pp);
47ff3de9 KVA	135	}
47ff3de9 KVA	136
21baa1c4	137	static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
47ff3de9	138	{
47ff3de9 KVA	139	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
	140	~INTERRUPTS);
	141	dra7xx_pcie_writel(dra7xx,
	142	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	143	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
	144	~LEG_EP_INTERRUPTS & ~MSI);
	145
	146	if (IS_ENABLED(CONFIG_PCI_MSI))
	147	dra7xx_pcie_writel(dra7xx,
	148	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	149	else
	150	dra7xx_pcie_writel(dra7xx,
	151	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
	152	LEG_EP_INTERRUPTS);
	153	}
	154
	155	static void dra7xx_pcie_host_init(struct pcie_port *pp)
	156	{
21baa1c4 BH	157	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
21baa1c4 BH	158
9cdce1cd ZW	159	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	160	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	161	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	162	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
883cc17c	163
7e57fd14 JZ	164	dw_pcie_setup_rc(pp);
7e57fd14 JZ	165
21baa1c4	166	dra7xx_pcie_establish_link(dra7xx);
47ff3de9 KVA	167	if (IS_ENABLED(CONFIG_PCI_MSI))
47ff3de9 KVA	168	dw_pcie_msi_init(pp);
21baa1c4	169	dra7xx_pcie_enable_interrupts(dra7xx);
47ff3de9 KVA	170	}
	171
	172	static struct pcie_host_ops dra7xx_pcie_host_ops = {
	173	.link_up = dra7xx_pcie_link_up,
	174	.host_init = dra7xx_pcie_host_init,
	175	};
	176
	177	static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
	178	irq_hw_number_t hwirq)
	179	{
	180	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	181	irq_set_chip_data(irq, domain->host_data);
47ff3de9 KVA	182
	183	return 0;
	184	}
	185
	186	static const struct irq_domain_ops intx_domain_ops = {
	187	.map = dra7xx_pcie_intx_map,
	188	};
	189
	190	static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
	191	{
	192	struct device *dev = pp->dev;
	193	struct device_node *node = dev->of_node;
	194	struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
	195
	196	if (!pcie_intc_node) {
	197	dev_err(dev, "No PCIe Intc node found\n");
991bfef8	198	return -ENODEV;
47ff3de9 KVA	199	}
	200
	201	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
	202	&intx_domain_ops, pp);
	203	if (!pp->irq_domain) {
	204	dev_err(dev, "Failed to get a INTx IRQ domain\n");
991bfef8	205	return -ENODEV;
47ff3de9 KVA	206	}
	207
	208	return 0;
	209	}
	210
	211	static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
	212	{
21baa1c4 BH	213	struct dra7xx_pcie *dra7xx = arg;
21baa1c4 BH	214	struct pcie_port *pp = &dra7xx->pp;
47ff3de9 KVA	215	u32 reg;
	216
	217	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
	218
	219	switch (reg) {
	220	case MSI:
	221	dw_handle_msi_irq(pp);
	222	break;
	223	case INTA:
	224	case INTB:
	225	case INTC:
	226	case INTD:
	227	generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
	228	break;
	229	}
	230
	231	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
	232
	233	return IRQ_HANDLED;
	234	}
	235
	236
	237	static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
	238	{
	239	struct dra7xx_pcie *dra7xx = arg;
c7f8146b	240	struct device *dev = dra7xx->pp.dev;
47ff3de9 KVA	241	u32 reg;
	242
	243	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
	244
	245	if (reg & ERR_SYS)
c7f8146b	246	dev_dbg(dev, "System Error\n");
47ff3de9 KVA	247
47ff3de9 KVA	248	if (reg & ERR_FATAL)
c7f8146b	249	dev_dbg(dev, "Fatal Error\n");
47ff3de9 KVA	250
47ff3de9 KVA	251	if (reg & ERR_NONFATAL)
c7f8146b	252	dev_dbg(dev, "Non Fatal Error\n");
47ff3de9 KVA	253
47ff3de9 KVA	254	if (reg & ERR_COR)
c7f8146b	255	dev_dbg(dev, "Correctable Error\n");
47ff3de9 KVA	256
47ff3de9 KVA	257	if (reg & ERR_AXI)
c7f8146b	258	dev_dbg(dev, "AXI tag lookup fatal Error\n");
47ff3de9 KVA	259
47ff3de9 KVA	260	if (reg & ERR_ECRC)
c7f8146b	261	dev_dbg(dev, "ECRC Error\n");
47ff3de9 KVA	262
47ff3de9 KVA	263	if (reg & PME_TURN_OFF)
c7f8146b	264	dev_dbg(dev,
47ff3de9 KVA	265	"Power Management Event Turn-Off message received\n");
	266
	267	if (reg & PME_TO_ACK)
c7f8146b	268	dev_dbg(dev,
47ff3de9 KVA	269	"Power Management Turn-Off Ack message received\n");
	270
	271	if (reg & PM_PME)
c7f8146b	272	dev_dbg(dev, "PM Power Management Event message received\n");
47ff3de9 KVA	273
47ff3de9 KVA	274	if (reg & LINK_REQ_RST)
c7f8146b	275	dev_dbg(dev, "Link Request Reset\n");
47ff3de9 KVA	276
47ff3de9 KVA	277	if (reg & LINK_UP_EVT)
c7f8146b	278	dev_dbg(dev, "Link-up state change\n");
47ff3de9 KVA	279
47ff3de9 KVA	280	if (reg & CFG_BME_EVT)
c7f8146b	281	dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
47ff3de9 KVA	282
47ff3de9 KVA	283	if (reg & CFG_MSE_EVT)
c7f8146b	284	dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
47ff3de9 KVA	285
	286	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
	287
	288	return IRQ_HANDLED;
	289	}
	290
e73044a0 JH	291	static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
e73044a0 JH	292	struct platform_device *pdev)
47ff3de9 KVA	293	{
47ff3de9 KVA	294	int ret;
150645b9 BH	295	struct pcie_port *pp = &dra7xx->pp;
150645b9 BH	296	struct device *dev = pp->dev;
47ff3de9	297	struct resource *res;
47ff3de9 KVA	298
	299	pp->irq = platform_get_irq(pdev, 1);
	300	if (pp->irq < 0) {
	301	dev_err(dev, "missing IRQ resource\n");
	302	return -EINVAL;
	303	}
	304
c7f8146b	305	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
8ff0ef99	306	IRQF_SHARED \| IRQF_NO_THREAD,
21baa1c4	307	"dra7-pcie-msi", dra7xx);
47ff3de9	308	if (ret) {
c7f8146b	309	dev_err(dev, "failed to request irq\n");
47ff3de9 KVA	310	return ret;
	311	}
	312
	313	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
	314	ret = dra7xx_pcie_init_irq_domain(pp);
	315	if (ret < 0)
	316	return ret;
	317	}
	318
	319	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	320	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	321	if (!pp->dbi_base)
	322	return -ENOMEM;
	323
	324	ret = dw_pcie_host_init(pp);
	325	if (ret) {
c7f8146b	326	dev_err(dev, "failed to initialize host\n");
47ff3de9 KVA	327	return ret;
	328	}
	329
	330	return 0;
	331	}
	332
	333	static int __init dra7xx_pcie_probe(struct platform_device *pdev)
	334	{
	335	u32 reg;
	336	int ret;
	337	int irq;
	338	int i;
	339	int phy_count;
	340	struct phy **phy;
	341	void __iomem *base;
	342	struct resource *res;
	343	struct dra7xx_pcie *dra7xx;
150645b9	344	struct pcie_port *pp;
47ff3de9 KVA	345	struct device *dev = &pdev->dev;
	346	struct device_node *np = dev->of_node;
	347	char name[10];
602d38bc	348	struct gpio_desc *reset;
47ff3de9 KVA	349
	350	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	351	if (!dra7xx)
	352	return -ENOMEM;
	353
150645b9 BH	354	pp = &dra7xx->pp;
	355	pp->dev = dev;
	356	pp->ops = &dra7xx_pcie_host_ops;
	357
47ff3de9 KVA	358	irq = platform_get_irq(pdev, 0);
	359	if (irq < 0) {
	360	dev_err(dev, "missing IRQ resource\n");
	361	return -EINVAL;
	362	}
	363
	364	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
	365	IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	366	if (ret) {
	367	dev_err(dev, "failed to request irq\n");
	368	return ret;
	369	}
	370
	371	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	372	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	373	if (!base)
	374	return -ENOMEM;
	375
	376	phy_count = of_property_count_strings(np, "phy-names");
	377	if (phy_count < 0) {
	378	dev_err(dev, "unable to find the strings\n");
	379	return phy_count;
	380	}
	381
	382	phy = devm_kzalloc(dev, sizeof(phy) phy_count, GFP_KERNEL);
	383	if (!phy)
	384	return -ENOMEM;
	385
	386	for (i = 0; i < phy_count; i++) {
	387	snprintf(name, sizeof(name), "pcie-phy%d", i);
	388	phy[i] = devm_phy_get(dev, name);
	389	if (IS_ERR(phy[i]))
	390	return PTR_ERR(phy[i]);
	391
	392	ret = phy_init(phy[i]);
	393	if (ret < 0)
	394	goto err_phy;
	395
	396	ret = phy_power_on(phy[i]);
	397	if (ret < 0) {
	398	phy_exit(phy[i]);
	399	goto err_phy;
	400	}
	401	}
	402
	403	dra7xx->base = base;
	404	dra7xx->phy = phy;
47ff3de9 KVA	405	dra7xx->phy_count = phy_count;
	406
	407	pm_runtime_enable(dev);
	408	ret = pm_runtime_get_sync(dev);
d3f4caa3	409	if (ret < 0) {
47ff3de9	410	dev_err(dev, "pm_runtime_get_sync failed\n");
0e2bdb0e	411	goto err_get_sync;
47ff3de9 KVA	412	}
47ff3de9 KVA	413
602d38bc KVA	414	reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
	415	if (IS_ERR(reset)) {
	416	ret = PTR_ERR(reset);
	417	dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
78bdcad0	418	goto err_gpio;
47ff3de9 KVA	419	}
	420
	421	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	422	reg &= ~LTSSM_EN;
	423	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	424
ab5fe4f4 KVA	425	dra7xx->link_gen = of_pci_get_max_link_speed(np);
	426	if (dra7xx->link_gen < 0 \|\| dra7xx->link_gen > 2)
	427	dra7xx->link_gen = 2;
	428
23926c8d	429	ret = dra7xx_add_pcie_port(dra7xx, pdev);
47ff3de9	430	if (ret < 0)
78bdcad0	431	goto err_gpio;
47ff3de9	432
03fa2ae1	433	platform_set_drvdata(pdev, dra7xx);
47ff3de9 KVA	434	return 0;
47ff3de9 KVA	435
78bdcad0	436	err_gpio:
47ff3de9	437	pm_runtime_put(dev);
0e2bdb0e KVA	438
0e2bdb0e KVA	439	err_get_sync:
47ff3de9 KVA	440	pm_runtime_disable(dev);
	441
	442	err_phy:
	443	while (--i >= 0) {
	444	phy_power_off(phy[i]);
	445	phy_exit(phy[i]);
	446	}
	447
	448	return ret;
	449	}
	450
e52eb445	451	#ifdef CONFIG_PM_SLEEP
389c7094 KVA	452	static int dra7xx_pcie_suspend(struct device *dev)
	453	{
	454	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	455	struct pcie_port *pp = &dra7xx->pp;
	456	u32 val;
	457
	458	/* clear MSE */
feeb7201	459	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
389c7094	460	val &= ~PCI_COMMAND_MEMORY;
feeb7201	461	dw_pcie_writel_rc(pp, PCI_COMMAND, val);
389c7094 KVA	462
	463	return 0;
	464	}
	465
	466	static int dra7xx_pcie_resume(struct device *dev)
	467	{
	468	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	469	struct pcie_port *pp = &dra7xx->pp;
	470	u32 val;
	471
	472	/* set MSE */
feeb7201	473	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
389c7094	474	val \|= PCI_COMMAND_MEMORY;
feeb7201	475	dw_pcie_writel_rc(pp, PCI_COMMAND, val);
389c7094 KVA	476
	477	return 0;
	478	}
	479
e52eb445 KVA	480	static int dra7xx_pcie_suspend_noirq(struct device *dev)
	481	{
	482	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	483	int count = dra7xx->phy_count;
	484
	485	while (count--) {
	486	phy_power_off(dra7xx->phy[count]);
	487	phy_exit(dra7xx->phy[count]);
	488	}
	489
	490	return 0;
	491	}
	492
	493	static int dra7xx_pcie_resume_noirq(struct device *dev)
	494	{
	495	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	496	int phy_count = dra7xx->phy_count;
	497	int ret;
	498	int i;
	499
	500	for (i = 0; i < phy_count; i++) {
	501	ret = phy_init(dra7xx->phy[i]);
	502	if (ret < 0)
	503	goto err_phy;
	504
	505	ret = phy_power_on(dra7xx->phy[i]);
	506	if (ret < 0) {
	507	phy_exit(dra7xx->phy[i]);
	508	goto err_phy;
	509	}
	510	}
	511
	512	return 0;
	513
	514	err_phy:
	515	while (--i >= 0) {
	516	phy_power_off(dra7xx->phy[i]);
	517	phy_exit(dra7xx->phy[i]);
	518	}
	519
	520	return ret;
	521	}
	522	#endif
	523
	524	static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
389c7094	525	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
e52eb445 KVA	526	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
	527	dra7xx_pcie_resume_noirq)
	528	};
	529
47ff3de9 KVA	530	static const struct of_device_id of_dra7xx_pcie_match[] = {
	531	{ .compatible = "ti,dra7-pcie", },
	532	{},
	533	};
47ff3de9 KVA	534
47ff3de9 KVA	535	static struct platform_driver dra7xx_pcie_driver = {
47ff3de9 KVA	536	.driver = {
47ff3de9 KVA	537	.name = "dra7-pcie",
47ff3de9	538	.of_match_table = of_dra7xx_pcie_match,
d29438d6	539	.suppress_bind_attrs = true,
e52eb445	540	.pm = &dra7xx_pcie_pm_ops,
47ff3de9 KVA	541	},
47ff3de9 KVA	542	};
d29438d6	543	builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);