Commit | Line | Data |
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47ff3de9 KVA |
1 | /* |
2 | * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs | |
3 | * | |
4 | * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Authors: Kishon Vijay Abraham I <kishon@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
608793e2 | 13 | #include <linux/delay.h> |
7a4db656 | 14 | #include <linux/device.h> |
47ff3de9 KVA |
15 | #include <linux/err.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/irqdomain.h> | |
19 | #include <linux/kernel.h> | |
d29438d6 | 20 | #include <linux/init.h> |
608793e2 | 21 | #include <linux/of_device.h> |
78bdcad0 | 22 | #include <linux/of_gpio.h> |
ab5fe4f4 | 23 | #include <linux/of_pci.h> |
47ff3de9 KVA |
24 | #include <linux/pci.h> |
25 | #include <linux/phy/phy.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/resource.h> | |
29 | #include <linux/types.h> | |
f7a2757f KVA |
30 | #include <linux/mfd/syscon.h> |
31 | #include <linux/regmap.h> | |
47ff3de9 KVA |
32 | |
33 | #include "pcie-designware.h" | |
34 | ||
35 | /* PCIe controller wrapper DRA7XX configuration registers */ | |
36 | ||
37 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 | |
38 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 | |
39 | #define ERR_SYS BIT(0) | |
40 | #define ERR_FATAL BIT(1) | |
41 | #define ERR_NONFATAL BIT(2) | |
42 | #define ERR_COR BIT(3) | |
43 | #define ERR_AXI BIT(4) | |
44 | #define ERR_ECRC BIT(5) | |
45 | #define PME_TURN_OFF BIT(8) | |
46 | #define PME_TO_ACK BIT(9) | |
47 | #define PM_PME BIT(10) | |
48 | #define LINK_REQ_RST BIT(11) | |
49 | #define LINK_UP_EVT BIT(12) | |
50 | #define CFG_BME_EVT BIT(13) | |
51 | #define CFG_MSE_EVT BIT(14) | |
52 | #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ | |
53 | ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ | |
54 | LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) | |
55 | ||
56 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 | |
57 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 | |
58 | #define INTA BIT(0) | |
59 | #define INTB BIT(1) | |
60 | #define INTC BIT(2) | |
61 | #define INTD BIT(3) | |
62 | #define MSI BIT(4) | |
63 | #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) | |
64 | ||
608793e2 KVA |
65 | #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100 |
66 | #define DEVICE_TYPE_EP 0x0 | |
67 | #define DEVICE_TYPE_LEG_EP 0x1 | |
68 | #define DEVICE_TYPE_RC 0x4 | |
69 | ||
47ff3de9 KVA |
70 | #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 |
71 | #define LTSSM_EN 0x1 | |
72 | ||
73 | #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C | |
74 | #define LINK_UP BIT(16) | |
883cc17c | 75 | #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF |
47ff3de9 | 76 | |
ab5fe4f4 KVA |
77 | #define EXP_CAP_ID_OFFSET 0x70 |
78 | ||
608793e2 KVA |
79 | #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 |
80 | #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 | |
81 | ||
82 | #define PCIECTRL_TI_CONF_MSI_XMT 0x012c | |
83 | #define MSI_REQ_GRANT BIT(0) | |
84 | #define MSI_VECTOR_SHIFT 7 | |
85 | ||
47ff3de9 | 86 | struct dra7xx_pcie { |
442ec4c0 | 87 | struct dw_pcie *pci; |
8e5ec414 BH |
88 | void __iomem *base; /* DT ti_conf */ |
89 | int phy_count; /* DT phy-names count */ | |
90 | struct phy **phy; | |
ab5fe4f4 | 91 | int link_gen; |
ebe85a44 | 92 | struct irq_domain *irq_domain; |
608793e2 KVA |
93 | enum dw_pcie_device_mode mode; |
94 | }; | |
95 | ||
96 | struct dra7xx_pcie_of_data { | |
97 | enum dw_pcie_device_mode mode; | |
47ff3de9 KVA |
98 | }; |
99 | ||
442ec4c0 | 100 | #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) |
47ff3de9 KVA |
101 | |
102 | static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) | |
103 | { | |
104 | return readl(pcie->base + offset); | |
105 | } | |
106 | ||
107 | static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, | |
108 | u32 value) | |
109 | { | |
110 | writel(value, pcie->base + offset); | |
111 | } | |
112 | ||
b6900aeb | 113 | static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr) |
2ed6cc71 KVA |
114 | { |
115 | return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; | |
116 | } | |
117 | ||
442ec4c0 | 118 | static int dra7xx_pcie_link_up(struct dw_pcie *pci) |
47ff3de9 | 119 | { |
442ec4c0 | 120 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); |
47ff3de9 KVA |
121 | u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); |
122 | ||
123 | return !!(reg & LINK_UP); | |
124 | } | |
125 | ||
608793e2 | 126 | static void dra7xx_pcie_stop_link(struct dw_pcie *pci) |
47ff3de9 | 127 | { |
608793e2 KVA |
128 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); |
129 | u32 reg; | |
130 | ||
131 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
132 | reg &= ~LTSSM_EN; | |
133 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
134 | } | |
135 | ||
136 | static int dra7xx_pcie_establish_link(struct dw_pcie *pci) | |
137 | { | |
138 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
442ec4c0 | 139 | struct device *dev = pci->dev; |
6cbb247e | 140 | u32 reg; |
ab5fe4f4 | 141 | u32 exp_cap_off = EXP_CAP_ID_OFFSET; |
47ff3de9 | 142 | |
442ec4c0 | 143 | if (dw_pcie_link_up(pci)) { |
c7f8146b | 144 | dev_err(dev, "link is already up\n"); |
47ff3de9 KVA |
145 | return 0; |
146 | } | |
147 | ||
ab5fe4f4 | 148 | if (dra7xx->link_gen == 1) { |
442ec4c0 | 149 | dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, |
19ce01cc | 150 | 4, ®); |
ab5fe4f4 KVA |
151 | if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { |
152 | reg &= ~((u32)PCI_EXP_LNKCAP_SLS); | |
153 | reg |= PCI_EXP_LNKCAP_SLS_2_5GB; | |
442ec4c0 | 154 | dw_pcie_write(pci->dbi_base + exp_cap_off + |
19ce01cc | 155 | PCI_EXP_LNKCAP, 4, reg); |
ab5fe4f4 KVA |
156 | } |
157 | ||
442ec4c0 | 158 | dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, |
19ce01cc | 159 | 2, ®); |
ab5fe4f4 KVA |
160 | if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { |
161 | reg &= ~((u32)PCI_EXP_LNKCAP_SLS); | |
162 | reg |= PCI_EXP_LNKCAP_SLS_2_5GB; | |
442ec4c0 | 163 | dw_pcie_write(pci->dbi_base + exp_cap_off + |
19ce01cc | 164 | PCI_EXP_LNKCTL2, 2, reg); |
ab5fe4f4 KVA |
165 | } |
166 | } | |
167 | ||
47ff3de9 KVA |
168 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); |
169 | reg |= LTSSM_EN; | |
170 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
171 | ||
608793e2 | 172 | return 0; |
47ff3de9 KVA |
173 | } |
174 | ||
5ffd90a0 | 175 | static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) |
47ff3de9 | 176 | { |
47ff3de9 | 177 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, |
40aa52c4 | 178 | LEG_EP_INTERRUPTS | MSI); |
5ffd90a0 KVA |
179 | |
180 | dra7xx_pcie_writel(dra7xx, | |
181 | PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, | |
ebe85a44 | 182 | MSI | LEG_EP_INTERRUPTS); |
47ff3de9 KVA |
183 | } |
184 | ||
5ffd90a0 KVA |
185 | static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) |
186 | { | |
187 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, | |
40aa52c4 | 188 | INTERRUPTS); |
5ffd90a0 KVA |
189 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, |
190 | INTERRUPTS); | |
191 | } | |
192 | ||
193 | static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) | |
194 | { | |
195 | dra7xx_pcie_enable_wrapper_interrupts(dra7xx); | |
196 | dra7xx_pcie_enable_msi_interrupts(dra7xx); | |
197 | } | |
198 | ||
4a301766 | 199 | static int dra7xx_pcie_host_init(struct pcie_port *pp) |
47ff3de9 | 200 | { |
442ec4c0 KVA |
201 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
202 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
21baa1c4 | 203 | |
7e57fd14 JZ |
204 | dw_pcie_setup_rc(pp); |
205 | ||
608793e2 KVA |
206 | dra7xx_pcie_establish_link(pci); |
207 | dw_pcie_wait_for_link(pci); | |
ebe85a44 | 208 | dw_pcie_msi_init(pp); |
21baa1c4 | 209 | dra7xx_pcie_enable_interrupts(dra7xx); |
4a301766 BA |
210 | |
211 | return 0; | |
47ff3de9 KVA |
212 | } |
213 | ||
4ab2e7c0 | 214 | static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { |
47ff3de9 KVA |
215 | .host_init = dra7xx_pcie_host_init, |
216 | }; | |
217 | ||
218 | static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
219 | irq_hw_number_t hwirq) | |
220 | { | |
221 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
222 | irq_set_chip_data(irq, domain->host_data); | |
47ff3de9 KVA |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static const struct irq_domain_ops intx_domain_ops = { | |
228 | .map = dra7xx_pcie_intx_map, | |
229 | }; | |
230 | ||
231 | static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) | |
232 | { | |
442ec4c0 KVA |
233 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
234 | struct device *dev = pci->dev; | |
235 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
47ff3de9 KVA |
236 | struct device_node *node = dev->of_node; |
237 | struct device_node *pcie_intc_node = of_get_next_child(node, NULL); | |
238 | ||
239 | if (!pcie_intc_node) { | |
240 | dev_err(dev, "No PCIe Intc node found\n"); | |
991bfef8 | 241 | return -ENODEV; |
47ff3de9 KVA |
242 | } |
243 | ||
61534d1a | 244 | dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, |
ebe85a44 KVA |
245 | &intx_domain_ops, pp); |
246 | if (!dra7xx->irq_domain) { | |
47ff3de9 | 247 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); |
991bfef8 | 248 | return -ENODEV; |
47ff3de9 KVA |
249 | } |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) | |
255 | { | |
21baa1c4 | 256 | struct dra7xx_pcie *dra7xx = arg; |
442ec4c0 KVA |
257 | struct dw_pcie *pci = dra7xx->pci; |
258 | struct pcie_port *pp = &pci->pp; | |
47ff3de9 KVA |
259 | u32 reg; |
260 | ||
261 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); | |
262 | ||
263 | switch (reg) { | |
264 | case MSI: | |
265 | dw_handle_msi_irq(pp); | |
266 | break; | |
267 | case INTA: | |
268 | case INTB: | |
269 | case INTC: | |
270 | case INTD: | |
ebe85a44 KVA |
271 | generic_handle_irq(irq_find_mapping(dra7xx->irq_domain, |
272 | ffs(reg))); | |
47ff3de9 KVA |
273 | break; |
274 | } | |
275 | ||
276 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); | |
277 | ||
278 | return IRQ_HANDLED; | |
279 | } | |
280 | ||
47ff3de9 KVA |
281 | static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) |
282 | { | |
283 | struct dra7xx_pcie *dra7xx = arg; | |
442ec4c0 KVA |
284 | struct dw_pcie *pci = dra7xx->pci; |
285 | struct device *dev = pci->dev; | |
608793e2 | 286 | struct dw_pcie_ep *ep = &pci->ep; |
47ff3de9 KVA |
287 | u32 reg; |
288 | ||
289 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); | |
290 | ||
291 | if (reg & ERR_SYS) | |
c7f8146b | 292 | dev_dbg(dev, "System Error\n"); |
47ff3de9 KVA |
293 | |
294 | if (reg & ERR_FATAL) | |
c7f8146b | 295 | dev_dbg(dev, "Fatal Error\n"); |
47ff3de9 KVA |
296 | |
297 | if (reg & ERR_NONFATAL) | |
c7f8146b | 298 | dev_dbg(dev, "Non Fatal Error\n"); |
47ff3de9 KVA |
299 | |
300 | if (reg & ERR_COR) | |
c7f8146b | 301 | dev_dbg(dev, "Correctable Error\n"); |
47ff3de9 KVA |
302 | |
303 | if (reg & ERR_AXI) | |
c7f8146b | 304 | dev_dbg(dev, "AXI tag lookup fatal Error\n"); |
47ff3de9 KVA |
305 | |
306 | if (reg & ERR_ECRC) | |
c7f8146b | 307 | dev_dbg(dev, "ECRC Error\n"); |
47ff3de9 KVA |
308 | |
309 | if (reg & PME_TURN_OFF) | |
c7f8146b | 310 | dev_dbg(dev, |
47ff3de9 KVA |
311 | "Power Management Event Turn-Off message received\n"); |
312 | ||
313 | if (reg & PME_TO_ACK) | |
c7f8146b | 314 | dev_dbg(dev, |
47ff3de9 KVA |
315 | "Power Management Turn-Off Ack message received\n"); |
316 | ||
317 | if (reg & PM_PME) | |
c7f8146b | 318 | dev_dbg(dev, "PM Power Management Event message received\n"); |
47ff3de9 KVA |
319 | |
320 | if (reg & LINK_REQ_RST) | |
c7f8146b | 321 | dev_dbg(dev, "Link Request Reset\n"); |
47ff3de9 | 322 | |
608793e2 KVA |
323 | if (reg & LINK_UP_EVT) { |
324 | if (dra7xx->mode == DW_PCIE_EP_TYPE) | |
325 | dw_pcie_ep_linkup(ep); | |
c7f8146b | 326 | dev_dbg(dev, "Link-up state change\n"); |
608793e2 | 327 | } |
47ff3de9 KVA |
328 | |
329 | if (reg & CFG_BME_EVT) | |
c7f8146b | 330 | dev_dbg(dev, "CFG 'Bus Master Enable' change\n"); |
47ff3de9 KVA |
331 | |
332 | if (reg & CFG_MSE_EVT) | |
c7f8146b | 333 | dev_dbg(dev, "CFG 'Memory Space Enable' change\n"); |
47ff3de9 KVA |
334 | |
335 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); | |
336 | ||
337 | return IRQ_HANDLED; | |
338 | } | |
339 | ||
608793e2 KVA |
340 | static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) |
341 | { | |
342 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); | |
343 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
85aa1399 KVA |
344 | enum pci_barno bar; |
345 | ||
346 | for (bar = BAR_0; bar <= BAR_5; bar++) | |
347 | dw_pcie_ep_reset_bar(pci, bar); | |
608793e2 KVA |
348 | |
349 | dra7xx_pcie_enable_wrapper_interrupts(dra7xx); | |
350 | } | |
351 | ||
352 | static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx) | |
353 | { | |
354 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1); | |
355 | mdelay(1); | |
356 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1); | |
357 | } | |
358 | ||
359 | static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, | |
360 | u8 interrupt_num) | |
361 | { | |
362 | u32 reg; | |
363 | ||
364 | reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; | |
365 | reg |= MSI_REQ_GRANT; | |
366 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); | |
367 | } | |
368 | ||
369 | static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, | |
370 | enum pci_epc_irq_type type, u8 interrupt_num) | |
371 | { | |
372 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); | |
373 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
374 | ||
375 | switch (type) { | |
376 | case PCI_EPC_IRQ_LEGACY: | |
377 | dra7xx_pcie_raise_legacy_irq(dra7xx); | |
378 | break; | |
379 | case PCI_EPC_IRQ_MSI: | |
380 | dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num); | |
381 | break; | |
382 | default: | |
383 | dev_err(pci->dev, "UNKNOWN IRQ type\n"); | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static struct dw_pcie_ep_ops pcie_ep_ops = { | |
390 | .ep_init = dra7xx_pcie_ep_init, | |
391 | .raise_irq = dra7xx_pcie_raise_irq, | |
392 | }; | |
393 | ||
394 | static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, | |
395 | struct platform_device *pdev) | |
396 | { | |
397 | int ret; | |
398 | struct dw_pcie_ep *ep; | |
399 | struct resource *res; | |
400 | struct device *dev = &pdev->dev; | |
401 | struct dw_pcie *pci = dra7xx->pci; | |
402 | ||
403 | ep = &pci->ep; | |
404 | ep->ops = &pcie_ep_ops; | |
405 | ||
406 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics"); | |
407 | pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); | |
408 | if (!pci->dbi_base) | |
409 | return -ENOMEM; | |
410 | ||
411 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2"); | |
412 | pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res)); | |
413 | if (!pci->dbi_base2) | |
414 | return -ENOMEM; | |
415 | ||
416 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); | |
417 | if (!res) | |
418 | return -EINVAL; | |
419 | ||
420 | ep->phys_base = res->start; | |
421 | ep->addr_size = resource_size(res); | |
422 | ||
423 | ret = dw_pcie_ep_init(ep); | |
424 | if (ret) { | |
425 | dev_err(dev, "failed to initialize endpoint\n"); | |
426 | return ret; | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
e73044a0 JH |
432 | static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, |
433 | struct platform_device *pdev) | |
47ff3de9 KVA |
434 | { |
435 | int ret; | |
442ec4c0 KVA |
436 | struct dw_pcie *pci = dra7xx->pci; |
437 | struct pcie_port *pp = &pci->pp; | |
438 | struct device *dev = pci->dev; | |
47ff3de9 | 439 | struct resource *res; |
47ff3de9 KVA |
440 | |
441 | pp->irq = platform_get_irq(pdev, 1); | |
442 | if (pp->irq < 0) { | |
443 | dev_err(dev, "missing IRQ resource\n"); | |
2f3ec752 | 444 | return pp->irq; |
47ff3de9 KVA |
445 | } |
446 | ||
c7f8146b | 447 | ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler, |
8ff0ef99 | 448 | IRQF_SHARED | IRQF_NO_THREAD, |
21baa1c4 | 449 | "dra7-pcie-msi", dra7xx); |
47ff3de9 | 450 | if (ret) { |
c7f8146b | 451 | dev_err(dev, "failed to request irq\n"); |
47ff3de9 KVA |
452 | return ret; |
453 | } | |
454 | ||
ebe85a44 KVA |
455 | ret = dra7xx_pcie_init_irq_domain(pp); |
456 | if (ret < 0) | |
457 | return ret; | |
47ff3de9 KVA |
458 | |
459 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics"); | |
442ec4c0 KVA |
460 | pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); |
461 | if (!pci->dbi_base) | |
47ff3de9 KVA |
462 | return -ENOMEM; |
463 | ||
71890ea0 NC |
464 | pp->ops = &dra7xx_pcie_host_ops; |
465 | ||
47ff3de9 KVA |
466 | ret = dw_pcie_host_init(pp); |
467 | if (ret) { | |
c7f8146b | 468 | dev_err(dev, "failed to initialize host\n"); |
47ff3de9 KVA |
469 | return ret; |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
442ec4c0 | 475 | static const struct dw_pcie_ops dw_pcie_ops = { |
2ed6cc71 | 476 | .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, |
608793e2 KVA |
477 | .start_link = dra7xx_pcie_establish_link, |
478 | .stop_link = dra7xx_pcie_stop_link, | |
442ec4c0 KVA |
479 | .link_up = dra7xx_pcie_link_up, |
480 | }; | |
481 | ||
1f6c4501 KVA |
482 | static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) |
483 | { | |
484 | int phy_count = dra7xx->phy_count; | |
485 | ||
486 | while (phy_count--) { | |
487 | phy_power_off(dra7xx->phy[phy_count]); | |
488 | phy_exit(dra7xx->phy[phy_count]); | |
489 | } | |
490 | } | |
491 | ||
492 | static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) | |
493 | { | |
494 | int phy_count = dra7xx->phy_count; | |
495 | int ret; | |
496 | int i; | |
497 | ||
498 | for (i = 0; i < phy_count; i++) { | |
499 | ret = phy_init(dra7xx->phy[i]); | |
500 | if (ret < 0) | |
501 | goto err_phy; | |
502 | ||
503 | ret = phy_power_on(dra7xx->phy[i]); | |
504 | if (ret < 0) { | |
505 | phy_exit(dra7xx->phy[i]); | |
506 | goto err_phy; | |
507 | } | |
508 | } | |
509 | ||
510 | return 0; | |
511 | ||
512 | err_phy: | |
513 | while (--i >= 0) { | |
514 | phy_power_off(dra7xx->phy[i]); | |
515 | phy_exit(dra7xx->phy[i]); | |
516 | } | |
517 | ||
518 | return ret; | |
519 | } | |
520 | ||
608793e2 KVA |
521 | static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = { |
522 | .mode = DW_PCIE_RC_TYPE, | |
523 | }; | |
524 | ||
525 | static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { | |
526 | .mode = DW_PCIE_EP_TYPE, | |
527 | }; | |
528 | ||
529 | static const struct of_device_id of_dra7xx_pcie_match[] = { | |
530 | { | |
531 | .compatible = "ti,dra7-pcie", | |
532 | .data = &dra7xx_pcie_rc_of_data, | |
533 | }, | |
534 | { | |
535 | .compatible = "ti,dra7-pcie-ep", | |
536 | .data = &dra7xx_pcie_ep_of_data, | |
537 | }, | |
538 | {}, | |
539 | }; | |
540 | ||
f7a2757f KVA |
541 | /* |
542 | * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 | |
543 | * @dra7xx: the dra7xx device where the workaround should be applied | |
544 | * | |
545 | * Access to the PCIe slave port that are not 32-bit aligned will result | |
546 | * in incorrect mapping to TLP Address and Byte enable fields. Therefore, | |
547 | * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or | |
548 | * 0x3. | |
549 | * | |
550 | * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. | |
551 | */ | |
552 | static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) | |
553 | { | |
554 | int ret; | |
555 | struct device_node *np = dev->of_node; | |
556 | struct of_phandle_args args; | |
557 | struct regmap *regmap; | |
558 | ||
559 | regmap = syscon_regmap_lookup_by_phandle(np, | |
560 | "ti,syscon-unaligned-access"); | |
561 | if (IS_ERR(regmap)) { | |
562 | dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); | |
563 | return -EINVAL; | |
564 | } | |
565 | ||
566 | ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access", | |
567 | 2, 0, &args); | |
568 | if (ret) { | |
569 | dev_err(dev, "failed to parse ti,syscon-unaligned-access\n"); | |
570 | return ret; | |
571 | } | |
572 | ||
573 | ret = regmap_update_bits(regmap, args.args[0], args.args[1], | |
574 | args.args[1]); | |
575 | if (ret) | |
576 | dev_err(dev, "failed to enable unaligned access\n"); | |
577 | ||
578 | of_node_put(args.np); | |
579 | ||
580 | return ret; | |
581 | } | |
582 | ||
47ff3de9 KVA |
583 | static int __init dra7xx_pcie_probe(struct platform_device *pdev) |
584 | { | |
585 | u32 reg; | |
586 | int ret; | |
587 | int irq; | |
588 | int i; | |
589 | int phy_count; | |
590 | struct phy **phy; | |
7a4db656 | 591 | struct device_link **link; |
47ff3de9 KVA |
592 | void __iomem *base; |
593 | struct resource *res; | |
442ec4c0 | 594 | struct dw_pcie *pci; |
442ec4c0 | 595 | struct dra7xx_pcie *dra7xx; |
47ff3de9 KVA |
596 | struct device *dev = &pdev->dev; |
597 | struct device_node *np = dev->of_node; | |
598 | char name[10]; | |
602d38bc | 599 | struct gpio_desc *reset; |
608793e2 KVA |
600 | const struct of_device_id *match; |
601 | const struct dra7xx_pcie_of_data *data; | |
602 | enum dw_pcie_device_mode mode; | |
603 | ||
604 | match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); | |
605 | if (!match) | |
606 | return -EINVAL; | |
607 | ||
608 | data = (struct dra7xx_pcie_of_data *)match->data; | |
609 | mode = (enum dw_pcie_device_mode)data->mode; | |
47ff3de9 KVA |
610 | |
611 | dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); | |
612 | if (!dra7xx) | |
613 | return -ENOMEM; | |
614 | ||
442ec4c0 KVA |
615 | pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); |
616 | if (!pci) | |
617 | return -ENOMEM; | |
618 | ||
619 | pci->dev = dev; | |
620 | pci->ops = &dw_pcie_ops; | |
621 | ||
47ff3de9 KVA |
622 | irq = platform_get_irq(pdev, 0); |
623 | if (irq < 0) { | |
a0d21ba1 GS |
624 | dev_err(dev, "missing IRQ resource: %d\n", irq); |
625 | return irq; | |
47ff3de9 KVA |
626 | } |
627 | ||
47ff3de9 KVA |
628 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); |
629 | base = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
630 | if (!base) | |
631 | return -ENOMEM; | |
632 | ||
633 | phy_count = of_property_count_strings(np, "phy-names"); | |
634 | if (phy_count < 0) { | |
635 | dev_err(dev, "unable to find the strings\n"); | |
636 | return phy_count; | |
637 | } | |
638 | ||
639 | phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL); | |
640 | if (!phy) | |
641 | return -ENOMEM; | |
642 | ||
7a4db656 KVA |
643 | link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL); |
644 | if (!link) | |
645 | return -ENOMEM; | |
646 | ||
47ff3de9 KVA |
647 | for (i = 0; i < phy_count; i++) { |
648 | snprintf(name, sizeof(name), "pcie-phy%d", i); | |
649 | phy[i] = devm_phy_get(dev, name); | |
650 | if (IS_ERR(phy[i])) | |
651 | return PTR_ERR(phy[i]); | |
7a4db656 KVA |
652 | |
653 | link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); | |
654 | if (!link[i]) { | |
655 | ret = -EINVAL; | |
656 | goto err_link; | |
657 | } | |
47ff3de9 KVA |
658 | } |
659 | ||
660 | dra7xx->base = base; | |
661 | dra7xx->phy = phy; | |
442ec4c0 | 662 | dra7xx->pci = pci; |
47ff3de9 KVA |
663 | dra7xx->phy_count = phy_count; |
664 | ||
1f6c4501 KVA |
665 | ret = dra7xx_pcie_enable_phy(dra7xx); |
666 | if (ret) { | |
667 | dev_err(dev, "failed to enable phy\n"); | |
668 | return ret; | |
669 | } | |
670 | ||
9bcf0a6f KVA |
671 | platform_set_drvdata(pdev, dra7xx); |
672 | ||
47ff3de9 KVA |
673 | pm_runtime_enable(dev); |
674 | ret = pm_runtime_get_sync(dev); | |
d3f4caa3 | 675 | if (ret < 0) { |
47ff3de9 | 676 | dev_err(dev, "pm_runtime_get_sync failed\n"); |
0e2bdb0e | 677 | goto err_get_sync; |
47ff3de9 KVA |
678 | } |
679 | ||
602d38bc KVA |
680 | reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); |
681 | if (IS_ERR(reset)) { | |
682 | ret = PTR_ERR(reset); | |
683 | dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); | |
78bdcad0 | 684 | goto err_gpio; |
47ff3de9 KVA |
685 | } |
686 | ||
687 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
688 | reg &= ~LTSSM_EN; | |
689 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
690 | ||
ab5fe4f4 KVA |
691 | dra7xx->link_gen = of_pci_get_max_link_speed(np); |
692 | if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2) | |
693 | dra7xx->link_gen = 2; | |
694 | ||
608793e2 KVA |
695 | switch (mode) { |
696 | case DW_PCIE_RC_TYPE: | |
f1aba0a0 NC |
697 | if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) { |
698 | ret = -ENODEV; | |
699 | goto err_gpio; | |
700 | } | |
701 | ||
608793e2 KVA |
702 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, |
703 | DEVICE_TYPE_RC); | |
704 | ret = dra7xx_add_pcie_port(dra7xx, pdev); | |
705 | if (ret < 0) | |
706 | goto err_gpio; | |
707 | break; | |
708 | case DW_PCIE_EP_TYPE: | |
f1aba0a0 NC |
709 | if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) { |
710 | ret = -ENODEV; | |
711 | goto err_gpio; | |
712 | } | |
713 | ||
608793e2 KVA |
714 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, |
715 | DEVICE_TYPE_EP); | |
f7a2757f KVA |
716 | |
717 | ret = dra7xx_pcie_ep_unaligned_memaccess(dev); | |
718 | if (ret) | |
719 | goto err_gpio; | |
720 | ||
608793e2 KVA |
721 | ret = dra7xx_add_pcie_ep(dra7xx, pdev); |
722 | if (ret < 0) | |
723 | goto err_gpio; | |
724 | break; | |
725 | default: | |
726 | dev_err(dev, "INVALID device type %d\n", mode); | |
727 | } | |
728 | dra7xx->mode = mode; | |
47ff3de9 | 729 | |
d4c7d1a0 K |
730 | ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, |
731 | IRQF_SHARED, "dra7xx-pcie-main", dra7xx); | |
732 | if (ret) { | |
733 | dev_err(dev, "failed to request irq\n"); | |
734 | goto err_gpio; | |
735 | } | |
736 | ||
47ff3de9 KVA |
737 | return 0; |
738 | ||
78bdcad0 | 739 | err_gpio: |
47ff3de9 | 740 | pm_runtime_put(dev); |
0e2bdb0e KVA |
741 | |
742 | err_get_sync: | |
47ff3de9 | 743 | pm_runtime_disable(dev); |
1f6c4501 | 744 | dra7xx_pcie_disable_phy(dra7xx); |
47ff3de9 | 745 | |
7a4db656 KVA |
746 | err_link: |
747 | while (--i >= 0) | |
748 | device_link_del(link[i]); | |
749 | ||
47ff3de9 KVA |
750 | return ret; |
751 | } | |
752 | ||
e52eb445 | 753 | #ifdef CONFIG_PM_SLEEP |
389c7094 KVA |
754 | static int dra7xx_pcie_suspend(struct device *dev) |
755 | { | |
756 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
442ec4c0 | 757 | struct dw_pcie *pci = dra7xx->pci; |
389c7094 KVA |
758 | u32 val; |
759 | ||
608793e2 KVA |
760 | if (dra7xx->mode != DW_PCIE_RC_TYPE) |
761 | return 0; | |
762 | ||
389c7094 | 763 | /* clear MSE */ |
442ec4c0 | 764 | val = dw_pcie_readl_dbi(pci, PCI_COMMAND); |
389c7094 | 765 | val &= ~PCI_COMMAND_MEMORY; |
442ec4c0 | 766 | dw_pcie_writel_dbi(pci, PCI_COMMAND, val); |
389c7094 KVA |
767 | |
768 | return 0; | |
769 | } | |
770 | ||
771 | static int dra7xx_pcie_resume(struct device *dev) | |
772 | { | |
773 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
442ec4c0 | 774 | struct dw_pcie *pci = dra7xx->pci; |
389c7094 KVA |
775 | u32 val; |
776 | ||
608793e2 KVA |
777 | if (dra7xx->mode != DW_PCIE_RC_TYPE) |
778 | return 0; | |
779 | ||
389c7094 | 780 | /* set MSE */ |
442ec4c0 | 781 | val = dw_pcie_readl_dbi(pci, PCI_COMMAND); |
389c7094 | 782 | val |= PCI_COMMAND_MEMORY; |
442ec4c0 | 783 | dw_pcie_writel_dbi(pci, PCI_COMMAND, val); |
389c7094 KVA |
784 | |
785 | return 0; | |
786 | } | |
787 | ||
e52eb445 KVA |
788 | static int dra7xx_pcie_suspend_noirq(struct device *dev) |
789 | { | |
790 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
e52eb445 | 791 | |
1f6c4501 | 792 | dra7xx_pcie_disable_phy(dra7xx); |
e52eb445 KVA |
793 | |
794 | return 0; | |
795 | } | |
796 | ||
797 | static int dra7xx_pcie_resume_noirq(struct device *dev) | |
798 | { | |
799 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
e52eb445 | 800 | int ret; |
e52eb445 | 801 | |
1f6c4501 KVA |
802 | ret = dra7xx_pcie_enable_phy(dra7xx); |
803 | if (ret) { | |
804 | dev_err(dev, "failed to enable phy\n"); | |
805 | return ret; | |
e52eb445 KVA |
806 | } |
807 | ||
808 | return 0; | |
e52eb445 KVA |
809 | } |
810 | #endif | |
811 | ||
4751fac7 | 812 | static void dra7xx_pcie_shutdown(struct platform_device *pdev) |
9c049bea K |
813 | { |
814 | struct device *dev = &pdev->dev; | |
815 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
816 | int ret; | |
817 | ||
818 | dra7xx_pcie_stop_link(dra7xx->pci); | |
819 | ||
820 | ret = pm_runtime_put_sync(dev); | |
821 | if (ret < 0) | |
822 | dev_dbg(dev, "pm_runtime_put_sync failed\n"); | |
823 | ||
824 | pm_runtime_disable(dev); | |
825 | dra7xx_pcie_disable_phy(dra7xx); | |
826 | } | |
827 | ||
e52eb445 | 828 | static const struct dev_pm_ops dra7xx_pcie_pm_ops = { |
389c7094 | 829 | SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) |
e52eb445 KVA |
830 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, |
831 | dra7xx_pcie_resume_noirq) | |
832 | }; | |
833 | ||
47ff3de9 | 834 | static struct platform_driver dra7xx_pcie_driver = { |
47ff3de9 KVA |
835 | .driver = { |
836 | .name = "dra7-pcie", | |
47ff3de9 | 837 | .of_match_table = of_dra7xx_pcie_match, |
d29438d6 | 838 | .suppress_bind_attrs = true, |
e52eb445 | 839 | .pm = &dra7xx_pcie_pm_ops, |
47ff3de9 | 840 | }, |
9c049bea | 841 | .shutdown = dra7xx_pcie_shutdown, |
47ff3de9 | 842 | }; |
d29438d6 | 843 | builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe); |