[linux-2.6-block.git] / drivers / pci / dwc / pci-dra7xx.c

/*
 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
 *
 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/resource.h>
#include <linux/types.h>

#include "pcie-designware.h"

/* PCIe controller wrapper DRA7XX configuration registers */

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN		0x0024
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN		0x0028
#define	ERR_SYS						BIT(0)
#define	ERR_FATAL					BIT(1)
#define	ERR_NONFATAL					BIT(2)
#define	ERR_COR						BIT(3)
#define	ERR_AXI						BIT(4)
#define	ERR_ECRC					BIT(5)
#define	PME_TURN_OFF					BIT(8)
#define	PME_TO_ACK					BIT(9)
#define	PM_PME						BIT(10)
#define	LINK_REQ_RST					BIT(11)
#define	LINK_UP_EVT					BIT(12)
#define	CFG_BME_EVT					BIT(13)
#define	CFG_MSE_EVT					BIT(14)
#define	INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
			ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
			LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI		0x0034
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI		0x0038
#define	INTA						BIT(0)
#define	INTB						BIT(1)
#define	INTC						BIT(2)
#define	INTD						BIT(3)
#define	MSI						BIT(4)
#define	LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)

#define	PCIECTRL_DRA7XX_CONF_DEVICE_CMD			0x0104
#define	LTSSM_EN					0x1

#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C
#define	LINK_UP						BIT(16)
#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF

struct dra7xx_pcie {
	struct pcie_port	pp;
	void __iomem		*base;		/* DT ti_conf */
	int			phy_count;	/* DT phy-names count */
	struct phy		**phy;
};

#define to_dra7xx_pcie(x)	container_of((x), struct dra7xx_pcie, pp)

static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
{
	return readl(pcie->base + offset);
}

static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
				      u32 value)
{
	writel(value, pcie->base + offset);
}

static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);

	return !!(reg & LINK_UP);
}

static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
{
	struct pcie_port *pp = &dra7xx->pp;
	struct device *dev = pp->dev;
	u32 reg;

	if (dw_pcie_link_up(pp)) {
		dev_err(dev, "link is already up\n");
		return 0;
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg |= LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	return dw_pcie_wait_for_link(pp);
}

static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
{
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
			   ~INTERRUPTS);
	dra7xx_pcie_writel(dra7xx,
			   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
			   ~LEG_EP_INTERRUPTS & ~MSI);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	else
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
				   LEG_EP_INTERRUPTS);
}

static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;

	dw_pcie_setup_rc(pp);

	dra7xx_pcie_establish_link(dra7xx);
	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
	dra7xx_pcie_enable_interrupts(dra7xx);
}

static struct pcie_host_ops dra7xx_pcie_host_ops = {
	.link_up = dra7xx_pcie_link_up,
	.host_init = dra7xx_pcie_host_init,
};

static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops intx_domain_ops = {
	.map = dra7xx_pcie_intx_map,
};

static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
{
	struct device *dev = pp->dev;
	struct device_node *node = dev->of_node;
	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);

	if (!pcie_intc_node) {
		dev_err(dev, "No PCIe Intc node found\n");
		return -ENODEV;
	}

	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
					       &intx_domain_ops, pp);
	if (!pp->irq_domain) {
		dev_err(dev, "Failed to get a INTx IRQ domain\n");
		return -ENODEV;
	}

	return 0;
}

static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{
	struct dra7xx_pcie *dra7xx = arg;
	struct pcie_port *pp = &dra7xx->pp;
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);

	switch (reg) {
	case MSI:
		dw_handle_msi_irq(pp);
		break;
	case INTA:
	case INTB:
	case INTC:
	case INTD:
		generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
		break;
	}

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);

	return IRQ_HANDLED;
}


static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{
	struct dra7xx_pcie *dra7xx = arg;
	struct device *dev = dra7xx->pp.dev;
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);

	if (reg & ERR_SYS)
		dev_dbg(dev, "System Error\n");

	if (reg & ERR_FATAL)
		dev_dbg(dev, "Fatal Error\n");

	if (reg & ERR_NONFATAL)
		dev_dbg(dev, "Non Fatal Error\n");

	if (reg & ERR_COR)
		dev_dbg(dev, "Correctable Error\n");

	if (reg & ERR_AXI)
		dev_dbg(dev, "AXI tag lookup fatal Error\n");

	if (reg & ERR_ECRC)
		dev_dbg(dev, "ECRC Error\n");

	if (reg & PME_TURN_OFF)
		dev_dbg(dev,
			"Power Management Event Turn-Off message received\n");

	if (reg & PME_TO_ACK)
		dev_dbg(dev,
			"Power Management Turn-Off Ack message received\n");

	if (reg & PM_PME)
		dev_dbg(dev, "PM Power Management Event message received\n");

	if (reg & LINK_REQ_RST)
		dev_dbg(dev, "Link Request Reset\n");

	if (reg & LINK_UP_EVT)
		dev_dbg(dev, "Link-up state change\n");

	if (reg & CFG_BME_EVT)
		dev_dbg(dev, "CFG 'Bus Master Enable' change\n");

	if (reg & CFG_MSE_EVT)
		dev_dbg(dev, "CFG 'Memory Space Enable' change\n");

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);

	return IRQ_HANDLED;
}

static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
				       struct platform_device *pdev)
{
	int ret;
	struct pcie_port *pp = &dra7xx->pp;
	struct device *dev = pp->dev;
	struct resource *res;

	pp->irq = platform_get_irq(pdev, 1);
	if (pp->irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
			       IRQF_SHARED | IRQF_NO_THREAD,
			       "dra7-pcie-msi",	dra7xx);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
		ret = dra7xx_pcie_init_irq_domain(pp);
		if (ret < 0)
			return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	if (!pp->dbi_base)
		return -ENOMEM;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
	u32 reg;
	int ret;
	int irq;
	int i;
	int phy_count;
	struct phy **phy;
	void __iomem *base;
	struct resource *res;
	struct dra7xx_pcie *dra7xx;
	struct pcie_port *pp;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	char name[10];
	struct gpio_desc *reset;

	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	if (!dra7xx)
		return -ENOMEM;

	pp = &dra7xx->pp;
	pp->dev = dev;
	pp->ops = &dra7xx_pcie_host_ops;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!base)
		return -ENOMEM;

	phy_count = of_property_count_strings(np, "phy-names");
	if (phy_count < 0) {
		dev_err(dev, "unable to find the strings\n");
		return phy_count;
	}

	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	for (i = 0; i < phy_count; i++) {
		snprintf(name, sizeof(name), "pcie-phy%d", i);
		phy[i] = devm_phy_get(dev, name);
		if (IS_ERR(phy[i]))
			return PTR_ERR(phy[i]);

		ret = phy_init(phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(phy[i]);
		if (ret < 0) {
			phy_exit(phy[i]);
			goto err_phy;
		}
	}

	dra7xx->base = base;
	dra7xx->phy = phy;
	dra7xx->phy_count = phy_count;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync failed\n");
		goto err_get_sync;
	}

	reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
	if (IS_ERR(reset)) {
		ret = PTR_ERR(reset);
		dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
		goto err_gpio;
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg &= ~LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	ret = dra7xx_add_pcie_port(dra7xx, pdev);
	if (ret < 0)
		goto err_gpio;

	platform_set_drvdata(pdev, dra7xx);
	return 0;

err_gpio:
	pm_runtime_put(dev);

err_get_sync:
	pm_runtime_disable(dev);

err_phy:
	while (--i >= 0) {
		phy_power_off(phy[i]);
		phy_exit(phy[i]);
	}

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int dra7xx_pcie_suspend(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* clear MSE */
	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
	val &= ~PCI_COMMAND_MEMORY;
	dw_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_resume(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* set MSE */
	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
	val |= PCI_COMMAND_MEMORY;
	dw_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_suspend_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int count = dra7xx->phy_count;

	while (count--) {
		phy_power_off(dra7xx->phy[count]);
		phy_exit(dra7xx->phy[count]);
	}

	return 0;
}

static int dra7xx_pcie_resume_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int phy_count = dra7xx->phy_count;
	int ret;
	int i;

	for (i = 0; i < phy_count; i++) {
		ret = phy_init(dra7xx->phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(dra7xx->phy[i]);
		if (ret < 0) {
			phy_exit(dra7xx->phy[i]);
			goto err_phy;
		}
	}

	return 0;

err_phy:
	while (--i >= 0) {
		phy_power_off(dra7xx->phy[i]);
		phy_exit(dra7xx->phy[i]);
	}

	return ret;
}
#endif

static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
				      dra7xx_pcie_resume_noirq)
};

static const struct of_device_id of_dra7xx_pcie_match[] = {
	{ .compatible = "ti,dra7-pcie", },
	{},
};

static struct platform_driver dra7xx_pcie_driver = {
	.driver = {
		.name	= "dra7-pcie",
		.of_match_table = of_dra7xx_pcie_match,
		.suppress_bind_attrs = true,
		.pm	= &dra7xx_pcie_pm_ops,
	},
};
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
Commit	Line	Data
47ff3de9 KVA	1	/*
	2	* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
	3	*
	4	* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
	5	*
	6	* Authors: Kishon Vijay Abraham I <kishon@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
47ff3de9 KVA	13	#include <linux/err.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/kernel.h>
d29438d6	18	#include <linux/init.h>
78bdcad0	19	#include <linux/of_gpio.h>
47ff3de9 KVA	20	#include <linux/pci.h>
	21	#include <linux/phy/phy.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/pm_runtime.h>
	24	#include <linux/resource.h>
	25	#include <linux/types.h>
	26
	27	#include "pcie-designware.h"
	28
	29	/* PCIe controller wrapper DRA7XX configuration registers */
	30
	31	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
	32	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
	33	#define ERR_SYS BIT(0)
	34	#define ERR_FATAL BIT(1)
	35	#define ERR_NONFATAL BIT(2)
	36	#define ERR_COR BIT(3)
	37	#define ERR_AXI BIT(4)
	38	#define ERR_ECRC BIT(5)
	39	#define PME_TURN_OFF BIT(8)
	40	#define PME_TO_ACK BIT(9)
	41	#define PM_PME BIT(10)
	42	#define LINK_REQ_RST BIT(11)
	43	#define LINK_UP_EVT BIT(12)
	44	#define CFG_BME_EVT BIT(13)
	45	#define CFG_MSE_EVT BIT(14)
	46	#define INTERRUPTS (ERR_SYS \| ERR_FATAL \| ERR_NONFATAL \| ERR_COR \| ERR_AXI \| \
	47	ERR_ECRC \| PME_TURN_OFF \| PME_TO_ACK \| PM_PME \| \
	48	LINK_REQ_RST \| LINK_UP_EVT \| CFG_BME_EVT \| CFG_MSE_EVT)
	49
	50	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
	51	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
	52	#define INTA BIT(0)
	53	#define INTB BIT(1)
	54	#define INTC BIT(2)
	55	#define INTD BIT(3)
	56	#define MSI BIT(4)
	57	#define LEG_EP_INTERRUPTS (INTA \| INTB \| INTC \| INTD)
	58
	59	#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
	60	#define LTSSM_EN 0x1
	61
	62	#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
	63	#define LINK_UP BIT(16)
883cc17c	64	#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
47ff3de9 KVA	65
47ff3de9 KVA	66	struct dra7xx_pcie {
47ff3de9	67	struct pcie_port pp;
8e5ec414 BH	68	void __iomem base; / DT ti_conf */
	69	int phy_count; /* DT phy-names count */
	70	struct phy **phy;
47ff3de9 KVA	71	};
	72
	73	#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
	74
	75	static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
	76	{
	77	return readl(pcie->base + offset);
	78	}
	79
	80	static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
	81	u32 value)
	82	{
	83	writel(value, pcie->base + offset);
	84	}
	85
	86	static int dra7xx_pcie_link_up(struct pcie_port *pp)
	87	{
	88	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	89	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
	90
	91	return !!(reg & LINK_UP);
	92	}
	93
21baa1c4	94	static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
47ff3de9	95	{
21baa1c4	96	struct pcie_port *pp = &dra7xx->pp;
c7f8146b	97	struct device *dev = pp->dev;
6cbb247e	98	u32 reg;
47ff3de9 KVA	99
47ff3de9 KVA	100	if (dw_pcie_link_up(pp)) {
c7f8146b	101	dev_err(dev, "link is already up\n");
47ff3de9 KVA	102	return 0;
	103	}
	104
	105	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	106	reg \|= LTSSM_EN;
	107	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	108
886bc5ce	109	return dw_pcie_wait_for_link(pp);
47ff3de9 KVA	110	}
47ff3de9 KVA	111
21baa1c4	112	static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
47ff3de9	113	{
47ff3de9 KVA	114	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
	115	~INTERRUPTS);
	116	dra7xx_pcie_writel(dra7xx,
	117	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	118	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
	119	~LEG_EP_INTERRUPTS & ~MSI);
	120
	121	if (IS_ENABLED(CONFIG_PCI_MSI))
	122	dra7xx_pcie_writel(dra7xx,
	123	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	124	else
	125	dra7xx_pcie_writel(dra7xx,
	126	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
	127	LEG_EP_INTERRUPTS);
	128	}
	129
	130	static void dra7xx_pcie_host_init(struct pcie_port *pp)
	131	{
21baa1c4 BH	132	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
21baa1c4 BH	133
9cdce1cd ZW	134	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	135	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	136	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	137	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
883cc17c	138
7e57fd14 JZ	139	dw_pcie_setup_rc(pp);
7e57fd14 JZ	140
21baa1c4	141	dra7xx_pcie_establish_link(dra7xx);
47ff3de9 KVA	142	if (IS_ENABLED(CONFIG_PCI_MSI))
47ff3de9 KVA	143	dw_pcie_msi_init(pp);
21baa1c4	144	dra7xx_pcie_enable_interrupts(dra7xx);
47ff3de9 KVA	145	}
	146
	147	static struct pcie_host_ops dra7xx_pcie_host_ops = {
	148	.link_up = dra7xx_pcie_link_up,
	149	.host_init = dra7xx_pcie_host_init,
	150	};
	151
	152	static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
	153	irq_hw_number_t hwirq)
	154	{
	155	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	156	irq_set_chip_data(irq, domain->host_data);
47ff3de9 KVA	157
	158	return 0;
	159	}
	160
	161	static const struct irq_domain_ops intx_domain_ops = {
	162	.map = dra7xx_pcie_intx_map,
	163	};
	164
	165	static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
	166	{
	167	struct device *dev = pp->dev;
	168	struct device_node *node = dev->of_node;
	169	struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
	170
	171	if (!pcie_intc_node) {
	172	dev_err(dev, "No PCIe Intc node found\n");
991bfef8	173	return -ENODEV;
47ff3de9 KVA	174	}
	175
	176	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
	177	&intx_domain_ops, pp);
	178	if (!pp->irq_domain) {
	179	dev_err(dev, "Failed to get a INTx IRQ domain\n");
991bfef8	180	return -ENODEV;
47ff3de9 KVA	181	}
	182
	183	return 0;
	184	}
	185
	186	static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
	187	{
21baa1c4 BH	188	struct dra7xx_pcie *dra7xx = arg;
21baa1c4 BH	189	struct pcie_port *pp = &dra7xx->pp;
47ff3de9 KVA	190	u32 reg;
	191
	192	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
	193
	194	switch (reg) {
	195	case MSI:
	196	dw_handle_msi_irq(pp);
	197	break;
	198	case INTA:
	199	case INTB:
	200	case INTC:
	201	case INTD:
	202	generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
	203	break;
	204	}
	205
	206	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
	207
	208	return IRQ_HANDLED;
	209	}
	210
	211
	212	static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
	213	{
	214	struct dra7xx_pcie *dra7xx = arg;
c7f8146b	215	struct device *dev = dra7xx->pp.dev;
47ff3de9 KVA	216	u32 reg;
	217
	218	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
	219
	220	if (reg & ERR_SYS)
c7f8146b	221	dev_dbg(dev, "System Error\n");
47ff3de9 KVA	222
47ff3de9 KVA	223	if (reg & ERR_FATAL)
c7f8146b	224	dev_dbg(dev, "Fatal Error\n");
47ff3de9 KVA	225
47ff3de9 KVA	226	if (reg & ERR_NONFATAL)
c7f8146b	227	dev_dbg(dev, "Non Fatal Error\n");
47ff3de9 KVA	228
47ff3de9 KVA	229	if (reg & ERR_COR)
c7f8146b	230	dev_dbg(dev, "Correctable Error\n");
47ff3de9 KVA	231
47ff3de9 KVA	232	if (reg & ERR_AXI)
c7f8146b	233	dev_dbg(dev, "AXI tag lookup fatal Error\n");
47ff3de9 KVA	234
47ff3de9 KVA	235	if (reg & ERR_ECRC)
c7f8146b	236	dev_dbg(dev, "ECRC Error\n");
47ff3de9 KVA	237
47ff3de9 KVA	238	if (reg & PME_TURN_OFF)
c7f8146b	239	dev_dbg(dev,
47ff3de9 KVA	240	"Power Management Event Turn-Off message received\n");
	241
	242	if (reg & PME_TO_ACK)
c7f8146b	243	dev_dbg(dev,
47ff3de9 KVA	244	"Power Management Turn-Off Ack message received\n");
	245
	246	if (reg & PM_PME)
c7f8146b	247	dev_dbg(dev, "PM Power Management Event message received\n");
47ff3de9 KVA	248
47ff3de9 KVA	249	if (reg & LINK_REQ_RST)
c7f8146b	250	dev_dbg(dev, "Link Request Reset\n");
47ff3de9 KVA	251
47ff3de9 KVA	252	if (reg & LINK_UP_EVT)
c7f8146b	253	dev_dbg(dev, "Link-up state change\n");
47ff3de9 KVA	254
47ff3de9 KVA	255	if (reg & CFG_BME_EVT)
c7f8146b	256	dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
47ff3de9 KVA	257
47ff3de9 KVA	258	if (reg & CFG_MSE_EVT)
c7f8146b	259	dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
47ff3de9 KVA	260
	261	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
	262
	263	return IRQ_HANDLED;
	264	}
	265
e73044a0 JH	266	static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
e73044a0 JH	267	struct platform_device *pdev)
47ff3de9 KVA	268	{
47ff3de9 KVA	269	int ret;
150645b9 BH	270	struct pcie_port *pp = &dra7xx->pp;
150645b9 BH	271	struct device *dev = pp->dev;
47ff3de9	272	struct resource *res;
47ff3de9 KVA	273
	274	pp->irq = platform_get_irq(pdev, 1);
	275	if (pp->irq < 0) {
	276	dev_err(dev, "missing IRQ resource\n");
	277	return -EINVAL;
	278	}
	279
c7f8146b	280	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
8ff0ef99	281	IRQF_SHARED \| IRQF_NO_THREAD,
21baa1c4	282	"dra7-pcie-msi", dra7xx);
47ff3de9	283	if (ret) {
c7f8146b	284	dev_err(dev, "failed to request irq\n");
47ff3de9 KVA	285	return ret;
	286	}
	287
	288	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
	289	ret = dra7xx_pcie_init_irq_domain(pp);
	290	if (ret < 0)
	291	return ret;
	292	}
	293
	294	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	295	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	296	if (!pp->dbi_base)
	297	return -ENOMEM;
	298
	299	ret = dw_pcie_host_init(pp);
	300	if (ret) {
c7f8146b	301	dev_err(dev, "failed to initialize host\n");
47ff3de9 KVA	302	return ret;
	303	}
	304
	305	return 0;
	306	}
	307
	308	static int __init dra7xx_pcie_probe(struct platform_device *pdev)
	309	{
	310	u32 reg;
	311	int ret;
	312	int irq;
	313	int i;
	314	int phy_count;
	315	struct phy **phy;
	316	void __iomem *base;
	317	struct resource *res;
	318	struct dra7xx_pcie *dra7xx;
150645b9	319	struct pcie_port *pp;
47ff3de9 KVA	320	struct device *dev = &pdev->dev;
	321	struct device_node *np = dev->of_node;
	322	char name[10];
602d38bc	323	struct gpio_desc *reset;
47ff3de9 KVA	324
	325	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	326	if (!dra7xx)
	327	return -ENOMEM;
	328
150645b9 BH	329	pp = &dra7xx->pp;
	330	pp->dev = dev;
	331	pp->ops = &dra7xx_pcie_host_ops;
	332
47ff3de9 KVA	333	irq = platform_get_irq(pdev, 0);
	334	if (irq < 0) {
	335	dev_err(dev, "missing IRQ resource\n");
	336	return -EINVAL;
	337	}
	338
	339	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
	340	IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	341	if (ret) {
	342	dev_err(dev, "failed to request irq\n");
	343	return ret;
	344	}
	345
	346	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	347	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	348	if (!base)
	349	return -ENOMEM;
	350
	351	phy_count = of_property_count_strings(np, "phy-names");
	352	if (phy_count < 0) {
	353	dev_err(dev, "unable to find the strings\n");
	354	return phy_count;
	355	}
	356
	357	phy = devm_kzalloc(dev, sizeof(phy) phy_count, GFP_KERNEL);
	358	if (!phy)
	359	return -ENOMEM;
	360
	361	for (i = 0; i < phy_count; i++) {
	362	snprintf(name, sizeof(name), "pcie-phy%d", i);
	363	phy[i] = devm_phy_get(dev, name);
	364	if (IS_ERR(phy[i]))
	365	return PTR_ERR(phy[i]);
	366
	367	ret = phy_init(phy[i]);
	368	if (ret < 0)
	369	goto err_phy;
	370
	371	ret = phy_power_on(phy[i]);
	372	if (ret < 0) {
	373	phy_exit(phy[i]);
	374	goto err_phy;
	375	}
	376	}
	377
	378	dra7xx->base = base;
	379	dra7xx->phy = phy;
47ff3de9 KVA	380	dra7xx->phy_count = phy_count;
	381
	382	pm_runtime_enable(dev);
	383	ret = pm_runtime_get_sync(dev);
d3f4caa3	384	if (ret < 0) {
47ff3de9	385	dev_err(dev, "pm_runtime_get_sync failed\n");
0e2bdb0e	386	goto err_get_sync;
47ff3de9 KVA	387	}
47ff3de9 KVA	388
602d38bc KVA	389	reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
	390	if (IS_ERR(reset)) {
	391	ret = PTR_ERR(reset);
	392	dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
78bdcad0	393	goto err_gpio;
47ff3de9 KVA	394	}
	395
	396	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	397	reg &= ~LTSSM_EN;
	398	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	399
23926c8d	400	ret = dra7xx_add_pcie_port(dra7xx, pdev);
47ff3de9	401	if (ret < 0)
78bdcad0	402	goto err_gpio;
47ff3de9	403
03fa2ae1	404	platform_set_drvdata(pdev, dra7xx);
47ff3de9 KVA	405	return 0;
47ff3de9 KVA	406
78bdcad0	407	err_gpio:
47ff3de9	408	pm_runtime_put(dev);
0e2bdb0e KVA	409
0e2bdb0e KVA	410	err_get_sync:
47ff3de9 KVA	411	pm_runtime_disable(dev);
	412
	413	err_phy:
	414	while (--i >= 0) {
	415	phy_power_off(phy[i]);
	416	phy_exit(phy[i]);
	417	}
	418
	419	return ret;
	420	}
	421
e52eb445	422	#ifdef CONFIG_PM_SLEEP
389c7094 KVA	423	static int dra7xx_pcie_suspend(struct device *dev)
	424	{
	425	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	426	struct pcie_port *pp = &dra7xx->pp;
	427	u32 val;
	428
	429	/* clear MSE */
feeb7201	430	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
389c7094	431	val &= ~PCI_COMMAND_MEMORY;
feeb7201	432	dw_pcie_writel_rc(pp, PCI_COMMAND, val);
389c7094 KVA	433
	434	return 0;
	435	}
	436
	437	static int dra7xx_pcie_resume(struct device *dev)
	438	{
	439	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	440	struct pcie_port *pp = &dra7xx->pp;
	441	u32 val;
	442
	443	/* set MSE */
feeb7201	444	val = dw_pcie_readl_rc(pp, PCI_COMMAND);
389c7094	445	val \|= PCI_COMMAND_MEMORY;
feeb7201	446	dw_pcie_writel_rc(pp, PCI_COMMAND, val);
389c7094 KVA	447
	448	return 0;
	449	}
	450
e52eb445 KVA	451	static int dra7xx_pcie_suspend_noirq(struct device *dev)
	452	{
	453	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	454	int count = dra7xx->phy_count;
	455
	456	while (count--) {
	457	phy_power_off(dra7xx->phy[count]);
	458	phy_exit(dra7xx->phy[count]);
	459	}
	460
	461	return 0;
	462	}
	463
	464	static int dra7xx_pcie_resume_noirq(struct device *dev)
	465	{
	466	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	467	int phy_count = dra7xx->phy_count;
	468	int ret;
	469	int i;
	470
	471	for (i = 0; i < phy_count; i++) {
	472	ret = phy_init(dra7xx->phy[i]);
	473	if (ret < 0)
	474	goto err_phy;
	475
	476	ret = phy_power_on(dra7xx->phy[i]);
	477	if (ret < 0) {
	478	phy_exit(dra7xx->phy[i]);
	479	goto err_phy;
	480	}
	481	}
	482
	483	return 0;
	484
	485	err_phy:
	486	while (--i >= 0) {
	487	phy_power_off(dra7xx->phy[i]);
	488	phy_exit(dra7xx->phy[i]);
	489	}
	490
	491	return ret;
	492	}
	493	#endif
	494
	495	static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
389c7094	496	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
e52eb445 KVA	497	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
	498	dra7xx_pcie_resume_noirq)
	499	};
	500
47ff3de9 KVA	501	static const struct of_device_id of_dra7xx_pcie_match[] = {
	502	{ .compatible = "ti,dra7-pcie", },
	503	{},
	504	};
47ff3de9 KVA	505
47ff3de9 KVA	506	static struct platform_driver dra7xx_pcie_driver = {
47ff3de9 KVA	507	.driver = {
47ff3de9 KVA	508	.name = "dra7-pcie",
47ff3de9	509	.of_match_table = of_dra7xx_pcie_match,
d29438d6	510	.suppress_bind_attrs = true,
e52eb445	511	.pm = &dra7xx_pcie_pm_ops,
47ff3de9 KVA	512	},
47ff3de9 KVA	513	};
d29438d6	514	builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);