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e61d98d8 SS |
1 | #ifndef _DMA_REMAPPING_H |
2 | #define _DMA_REMAPPING_H | |
3 | ||
4 | /* | |
5 | * We need a fixed PAGE_SIZE of 4K irrespective of | |
6 | * arch PAGE_SIZE for IOMMU page tables. | |
7 | */ | |
8 | #define PAGE_SHIFT_4K (12) | |
9 | #define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K) | |
10 | #define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K) | |
11 | #define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K) | |
12 | ||
13 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K) | |
14 | #define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK) | |
15 | #define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK) | |
16 | ||
17 | ||
18 | /* | |
19 | * 0: Present | |
20 | * 1-11: Reserved | |
21 | * 12-63: Context Ptr (12 - (haw-1)) | |
22 | * 64-127: Reserved | |
23 | */ | |
24 | struct root_entry { | |
25 | u64 val; | |
26 | u64 rsvd1; | |
27 | }; | |
28 | #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry)) | |
29 | static inline bool root_present(struct root_entry *root) | |
30 | { | |
31 | return (root->val & 1); | |
32 | } | |
33 | static inline void set_root_present(struct root_entry *root) | |
34 | { | |
35 | root->val |= 1; | |
36 | } | |
37 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
38 | { | |
39 | root->val |= value & PAGE_MASK_4K; | |
40 | } | |
41 | ||
42 | struct context_entry; | |
43 | static inline struct context_entry * | |
44 | get_context_addr_from_root(struct root_entry *root) | |
45 | { | |
46 | return (struct context_entry *) | |
47 | (root_present(root)?phys_to_virt( | |
48 | root->val & PAGE_MASK_4K): | |
49 | NULL); | |
50 | } | |
51 | ||
52 | /* | |
53 | * low 64 bits: | |
54 | * 0: present | |
55 | * 1: fault processing disable | |
56 | * 2-3: translation type | |
57 | * 12-63: address space root | |
58 | * high 64 bits: | |
59 | * 0-2: address width | |
60 | * 3-6: aval | |
61 | * 8-23: domain id | |
62 | */ | |
63 | struct context_entry { | |
64 | u64 lo; | |
65 | u64 hi; | |
66 | }; | |
67 | #define context_present(c) ((c).lo & 1) | |
68 | #define context_fault_disable(c) (((c).lo >> 1) & 1) | |
69 | #define context_translation_type(c) (((c).lo >> 2) & 3) | |
70 | #define context_address_root(c) ((c).lo & PAGE_MASK_4K) | |
71 | #define context_address_width(c) ((c).hi & 7) | |
72 | #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1)) | |
73 | ||
74 | #define context_set_present(c) do {(c).lo |= 1;} while (0) | |
75 | #define context_set_fault_enable(c) \ | |
76 | do {(c).lo &= (((u64)-1) << 2) | 1;} while (0) | |
77 | #define context_set_translation_type(c, val) \ | |
78 | do { \ | |
79 | (c).lo &= (((u64)-1) << 4) | 3; \ | |
80 | (c).lo |= ((val) & 3) << 2; \ | |
81 | } while (0) | |
82 | #define CONTEXT_TT_MULTI_LEVEL 0 | |
83 | #define context_set_address_root(c, val) \ | |
84 | do {(c).lo |= (val) & PAGE_MASK_4K;} while (0) | |
85 | #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0) | |
86 | #define context_set_domain_id(c, val) \ | |
87 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) | |
88 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) | |
89 | ||
90 | /* | |
91 | * 0: readable | |
92 | * 1: writable | |
93 | * 2-6: reserved | |
94 | * 7: super page | |
95 | * 8-11: available | |
96 | * 12-63: Host physcial address | |
97 | */ | |
98 | struct dma_pte { | |
99 | u64 val; | |
100 | }; | |
101 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | |
102 | ||
103 | #define DMA_PTE_READ (1) | |
104 | #define DMA_PTE_WRITE (2) | |
105 | ||
106 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | |
107 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | |
108 | #define dma_set_pte_prot(p, prot) \ | |
109 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | |
110 | #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K) | |
111 | #define dma_set_pte_addr(p, addr) do {\ | |
112 | (p).val |= ((addr) & PAGE_MASK_4K); } while (0) | |
113 | #define dma_pte_present(p) (((p).val & 3) != 0) | |
114 | ||
115 | struct intel_iommu; | |
116 | ||
117 | struct dmar_domain { | |
118 | int id; /* domain id */ | |
119 | struct intel_iommu *iommu; /* back pointer to owning iommu */ | |
120 | ||
121 | struct list_head devices; /* all devices' list */ | |
122 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
123 | ||
124 | struct dma_pte *pgd; /* virtual address */ | |
125 | spinlock_t mapping_lock; /* page table lock */ | |
126 | int gaw; /* max guest address width */ | |
127 | ||
128 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
129 | int agaw; | |
130 | ||
131 | #define DOMAIN_FLAG_MULTIPLE_DEVICES 1 | |
132 | int flags; | |
133 | }; | |
134 | ||
135 | /* PCI domain-device relationship */ | |
136 | struct device_domain_info { | |
137 | struct list_head link; /* link to domain siblings */ | |
138 | struct list_head global; /* link to global list */ | |
139 | u8 bus; /* PCI bus numer */ | |
140 | u8 devfn; /* PCI devfn number */ | |
141 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
142 | struct dmar_domain *domain; /* pointer to domain */ | |
143 | }; | |
144 | ||
145 | extern int init_dmars(void); | |
146 | extern void free_dmar_iommu(struct intel_iommu *iommu); | |
147 | ||
2ae21010 SS |
148 | extern int dmar_disabled; |
149 | ||
e61d98d8 SS |
150 | #ifndef CONFIG_DMAR_GFX_WA |
151 | static inline void iommu_prepare_gfx_mapping(void) | |
152 | { | |
153 | return; | |
154 | } | |
155 | #endif /* !CONFIG_DMAR_GFX_WA */ | |
156 | ||
157 | #endif |