Commit | Line | Data |
---|---|---|
7d6bc569 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
335bbd9e SP |
2 | /* |
3 | * BRIEF MODULE DESCRIPTION | |
03f152e3 JC |
4 | * PCI init for Ralink RT2880 solution |
5 | * | |
335bbd9e | 6 | * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw) |
03f152e3 | 7 | * |
03f152e3 JC |
8 | * May 2007 Bruce Chang |
9 | * Initial Release | |
10 | * | |
11 | * May 2009 Bruce Chang | |
12 | * support RT2880/RT3883 PCIe | |
13 | * | |
14 | * May 2011 Bruce Chang | |
15 | * support RT6855/MT7620 PCIe | |
03f152e3 JC |
16 | */ |
17 | ||
cd7d07db | 18 | #include <linux/bitops.h> |
cc4e864a | 19 | #include <linux/clk.h> |
03f152e3 | 20 | #include <linux/delay.h> |
07420a02 | 21 | #include <linux/gpio/consumer.h> |
cd7d07db | 22 | #include <linux/module.h> |
03f152e3 | 23 | #include <linux/of.h> |
8571c62d | 24 | #include <linux/of_address.h> |
cd7d07db SP |
25 | #include <linux/of_pci.h> |
26 | #include <linux/of_platform.h> | |
27 | #include <linux/pci.h> | |
61f9bde6 | 28 | #include <linux/phy/phy.h> |
03f152e3 | 29 | #include <linux/platform_device.h> |
cd7d07db | 30 | #include <linux/reset.h> |
b483b4e4 | 31 | #include <linux/sys_soc.h> |
8571c62d | 32 | |
2301a3e1 PR |
33 | #include "../pci.h" |
34 | ||
2bdd5238 | 35 | /* MediaTek-specific configuration registers */ |
a4b2eb91 SP |
36 | #define PCIE_FTS_NUM 0x70c |
37 | #define PCIE_FTS_NUM_MASK GENMASK(15, 8) | |
0ae0cf50 | 38 | #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8) |
a4b2eb91 | 39 | |
a934d901 | 40 | /* Host-PCI bridge registers */ |
152f3893 | 41 | #define RALINK_PCI_PCICFG_ADDR 0x0000 |
2bdd5238 | 42 | #define RALINK_PCI_PCIMSK_ADDR 0x000c |
a934d901 SP |
43 | #define RALINK_PCI_CONFIG_ADDR 0x0020 |
44 | #define RALINK_PCI_CONFIG_DATA 0x0024 | |
45 | #define RALINK_PCI_MEMBASE 0x0028 | |
2bdd5238 | 46 | #define RALINK_PCI_IOBASE 0x002c |
d4e3a1f6 | 47 | |
a934d901 | 48 | /* PCIe RC control registers */ |
e38bb175 SP |
49 | #define RALINK_PCI_ID 0x0030 |
50 | #define RALINK_PCI_CLASS 0x0034 | |
51 | #define RALINK_PCI_SUBID 0x0038 | |
52 | #define RALINK_PCI_STATUS 0x0050 | |
d4e3a1f6 | 53 | |
a934d901 | 54 | /* Some definition values */ |
301c15be SP |
55 | #define PCIE_REVISION_ID BIT(0) |
56 | #define PCIE_CLASS_CODE (0x60400 << 8) | |
57 | #define PCIE_BAR_MAP_MAX GENMASK(30, 16) | |
58 | #define PCIE_BAR_ENABLE BIT(0) | |
59 | #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) | |
bd1a05bd | 60 | #define PCIE_PORT_LINKUP BIT(0) |
7d761b08 | 61 | #define PCIE_PORT_CNT 3 |
301c15be | 62 | |
0cb2a8f3 | 63 | #define INIT_PORTS_DELAY_MS 100 |
475fe234 | 64 | #define PERST_DELAY_MS 100 |
6b767904 | 65 | |
8571c62d SP |
66 | /** |
67 | * struct mt7621_pcie_port - PCIe port information | |
ad9c87e1 | 68 | * @base: I/O mapped register base |
8571c62d SP |
69 | * @list: port list |
70 | * @pcie: pointer to PCIe host info | |
cc4e864a | 71 | * @clk: pointer to the port clock gate |
61f9bde6 | 72 | * @phy: pointer to PHY control block |
ad9c87e1 | 73 | * @pcie_rst: pointer to port reset control |
b27e35f9 | 74 | * @gpio_rst: gpio reset |
ad9c87e1 | 75 | * @slot: port slot |
a41a1f86 | 76 | * @enabled: indicates if port is enabled |
8571c62d SP |
77 | */ |
78 | struct mt7621_pcie_port { | |
79 | void __iomem *base; | |
80 | struct list_head list; | |
81 | struct mt7621_pcie *pcie; | |
cc4e864a | 82 | struct clk *clk; |
61f9bde6 | 83 | struct phy *phy; |
ad9c87e1 | 84 | struct reset_control *pcie_rst; |
b27e35f9 | 85 | struct gpio_desc *gpio_rst; |
ad9c87e1 | 86 | u32 slot; |
a41a1f86 | 87 | bool enabled; |
8571c62d SP |
88 | }; |
89 | ||
90 | /** | |
91 | * struct mt7621_pcie - PCIe host information | |
92 | * @base: IO Mapped Register Base | |
8571c62d SP |
93 | * @dev: Pointer to PCIe device |
94 | * @ports: pointer to PCIe port information | |
b483b4e4 SP |
95 | * @resets_inverted: depends on chip revision |
96 | * reset lines are inverted. | |
8571c62d SP |
97 | */ |
98 | struct mt7621_pcie { | |
8571c62d | 99 | struct device *dev; |
4793895f | 100 | void __iomem *base; |
8571c62d | 101 | struct list_head ports; |
b483b4e4 | 102 | bool resets_inverted; |
8571c62d SP |
103 | }; |
104 | ||
52ed727c SP |
105 | static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) |
106 | { | |
860bce45 | 107 | return readl_relaxed(pcie->base + reg); |
52ed727c SP |
108 | } |
109 | ||
110 | static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) | |
111 | { | |
860bce45 | 112 | writel_relaxed(val, pcie->base + reg); |
52ed727c SP |
113 | } |
114 | ||
c8242bef SP |
115 | static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) |
116 | { | |
860bce45 | 117 | return readl_relaxed(port->base + reg); |
c8242bef SP |
118 | } |
119 | ||
120 | static inline void pcie_port_write(struct mt7621_pcie_port *port, | |
121 | u32 val, u32 reg) | |
122 | { | |
860bce45 | 123 | writel_relaxed(val, port->base + reg); |
c8242bef SP |
124 | } |
125 | ||
8571c62d SP |
126 | static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, |
127 | unsigned int devfn, int where) | |
128 | { | |
129 | struct mt7621_pcie *pcie = bus->sysdata; | |
2301a3e1 PR |
130 | u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), |
131 | PCI_FUNC(devfn), where); | |
8571c62d | 132 | |
860bce45 | 133 | writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); |
8571c62d | 134 | |
8594351a | 135 | return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); |
8571c62d | 136 | } |
03f152e3 | 137 | |
87c71931 | 138 | static struct pci_ops mt7621_pcie_ops = { |
8571c62d SP |
139 | .map_bus = mt7621_pcie_map_bus, |
140 | .read = pci_generic_config_read, | |
141 | .write = pci_generic_config_write, | |
03f152e3 JC |
142 | }; |
143 | ||
ce3368dc | 144 | static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) |
03f152e3 | 145 | { |
2301a3e1 | 146 | u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); |
9f999b41 SP |
147 | |
148 | pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); | |
8594351a | 149 | return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); |
03f152e3 JC |
150 | } |
151 | ||
ce3368dc SP |
152 | static void write_config(struct mt7621_pcie *pcie, unsigned int dev, |
153 | u32 reg, u32 val) | |
03f152e3 | 154 | { |
2301a3e1 | 155 | u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); |
9f999b41 SP |
156 | |
157 | pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); | |
8594351a | 158 | pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); |
03f152e3 JC |
159 | } |
160 | ||
b27e35f9 | 161 | static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port) |
07420a02 | 162 | { |
b27e35f9 SP |
163 | if (port->gpio_rst) |
164 | gpiod_set_value(port->gpio_rst, 1); | |
07420a02 SP |
165 | } |
166 | ||
b27e35f9 | 167 | static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port) |
07420a02 | 168 | { |
b27e35f9 SP |
169 | if (port->gpio_rst) |
170 | gpiod_set_value(port->gpio_rst, 0); | |
07420a02 SP |
171 | } |
172 | ||
173 | static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port) | |
174 | { | |
175 | return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; | |
176 | } | |
177 | ||
e51844bf SP |
178 | static inline void mt7621_control_assert(struct mt7621_pcie_port *port) |
179 | { | |
b483b4e4 | 180 | struct mt7621_pcie *pcie = port->pcie; |
e51844bf | 181 | |
b483b4e4 | 182 | if (pcie->resets_inverted) |
e51844bf SP |
183 | reset_control_assert(port->pcie_rst); |
184 | else | |
185 | reset_control_deassert(port->pcie_rst); | |
186 | } | |
187 | ||
188 | static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) | |
189 | { | |
b483b4e4 | 190 | struct mt7621_pcie *pcie = port->pcie; |
e51844bf | 191 | |
b483b4e4 | 192 | if (pcie->resets_inverted) |
e51844bf SP |
193 | reset_control_deassert(port->pcie_rst); |
194 | else | |
195 | reset_control_assert(port->pcie_rst); | |
196 | } | |
197 | ||
ad9c87e1 | 198 | static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, |
2d3d288f | 199 | struct device_node *node, |
ad9c87e1 SP |
200 | int slot) |
201 | { | |
202 | struct mt7621_pcie_port *port; | |
203 | struct device *dev = pcie->dev; | |
fab6710e | 204 | struct platform_device *pdev = to_platform_device(dev); |
fd6eb49a | 205 | char name[11]; |
2d3d288f | 206 | int err; |
ad9c87e1 SP |
207 | |
208 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); | |
209 | if (!port) | |
210 | return -ENOMEM; | |
211 | ||
108b2f2a | 212 | port->base = devm_platform_ioremap_resource(pdev, slot + 1); |
ad9c87e1 SP |
213 | if (IS_ERR(port->base)) |
214 | return PTR_ERR(port->base); | |
215 | ||
2d3d288f | 216 | port->clk = devm_get_clk_from_child(dev, node, NULL); |
cc4e864a SP |
217 | if (IS_ERR(port->clk)) { |
218 | dev_err(dev, "failed to get pcie%d clock\n", slot); | |
219 | return PTR_ERR(port->clk); | |
220 | } | |
221 | ||
2d3d288f | 222 | port->pcie_rst = of_reset_control_get_exclusive(node, NULL); |
ad9c87e1 SP |
223 | if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) { |
224 | dev_err(dev, "failed to get pcie%d reset control\n", slot); | |
225 | return PTR_ERR(port->pcie_rst); | |
226 | } | |
227 | ||
61f9bde6 | 228 | snprintf(name, sizeof(name), "pcie-phy%d", slot); |
2d3d288f SP |
229 | port->phy = devm_of_phy_get(dev, node, name); |
230 | if (IS_ERR(port->phy)) { | |
231 | dev_err(dev, "failed to get pcie-phy%d\n", slot); | |
232 | err = PTR_ERR(port->phy); | |
233 | goto remove_reset; | |
234 | } | |
61f9bde6 | 235 | |
b27e35f9 SP |
236 | port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, |
237 | GPIOD_OUT_LOW); | |
825c6f47 | 238 | if (IS_ERR(port->gpio_rst)) { |
2bdd5238 | 239 | dev_err(dev, "failed to get GPIO for PCIe%d\n", slot); |
2d3d288f SP |
240 | err = PTR_ERR(port->gpio_rst); |
241 | goto remove_reset; | |
825c6f47 | 242 | } |
b27e35f9 | 243 | |
ad9c87e1 SP |
244 | port->slot = slot; |
245 | port->pcie = pcie; | |
246 | ||
247 | INIT_LIST_HEAD(&port->list); | |
248 | list_add_tail(&port->list, &pcie->ports); | |
249 | ||
250 | return 0; | |
2d3d288f SP |
251 | |
252 | remove_reset: | |
253 | reset_control_put(port->pcie_rst); | |
254 | return err; | |
ad9c87e1 SP |
255 | } |
256 | ||
8571c62d SP |
257 | static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) |
258 | { | |
259 | struct device *dev = pcie->dev; | |
108b2f2a | 260 | struct platform_device *pdev = to_platform_device(dev); |
ad9c87e1 | 261 | struct device_node *node = dev->of_node, *child; |
8571c62d SP |
262 | int err; |
263 | ||
108b2f2a | 264 | pcie->base = devm_platform_ioremap_resource(pdev, 0); |
8571c62d SP |
265 | if (IS_ERR(pcie->base)) |
266 | return PTR_ERR(pcie->base); | |
267 | ||
ad9c87e1 SP |
268 | for_each_available_child_of_node(node, child) { |
269 | int slot; | |
270 | ||
271 | err = of_pci_get_devfn(child); | |
272 | if (err < 0) { | |
2125a441 | 273 | of_node_put(child); |
ad9c87e1 SP |
274 | dev_err(dev, "failed to parse devfn: %d\n", err); |
275 | return err; | |
276 | } | |
277 | ||
278 | slot = PCI_SLOT(err); | |
279 | ||
2d3d288f | 280 | err = mt7621_pcie_parse_port(pcie, child, slot); |
2125a441 ND |
281 | if (err) { |
282 | of_node_put(child); | |
ad9c87e1 | 283 | return err; |
2125a441 | 284 | } |
ad9c87e1 SP |
285 | } |
286 | ||
8571c62d SP |
287 | return 0; |
288 | } | |
289 | ||
4fdf3abc | 290 | static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) |
745eeeac SP |
291 | { |
292 | struct mt7621_pcie *pcie = port->pcie; | |
293 | struct device *dev = pcie->dev; | |
294 | u32 slot = port->slot; | |
61f9bde6 | 295 | int err; |
745eeeac | 296 | |
61f9bde6 SP |
297 | err = phy_init(port->phy); |
298 | if (err) { | |
299 | dev_err(dev, "failed to initialize port%d phy\n", slot); | |
07420a02 | 300 | return err; |
61f9bde6 SP |
301 | } |
302 | ||
303 | err = phy_power_on(port->phy); | |
304 | if (err) { | |
305 | dev_err(dev, "failed to power on port%d phy\n", slot); | |
cdf6f83b | 306 | phy_exit(port->phy); |
07420a02 | 307 | return err; |
745eeeac SP |
308 | } |
309 | ||
61f9bde6 | 310 | port->enabled = true; |
3beb6da5 | 311 | |
745eeeac SP |
312 | return 0; |
313 | } | |
314 | ||
b27e35f9 SP |
315 | static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) |
316 | { | |
317 | struct mt7621_pcie_port *port; | |
318 | ||
319 | list_for_each_entry(port, &pcie->ports, list) { | |
320 | /* PCIe RC reset assert */ | |
321 | mt7621_control_assert(port); | |
322 | ||
323 | /* PCIe EP reset assert */ | |
324 | mt7621_rst_gpio_pcie_assert(port); | |
325 | } | |
326 | ||
4ab4ca20 | 327 | msleep(PERST_DELAY_MS); |
b27e35f9 SP |
328 | } |
329 | ||
330 | static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) | |
331 | { | |
332 | struct mt7621_pcie_port *port; | |
333 | ||
334 | list_for_each_entry(port, &pcie->ports, list) | |
335 | mt7621_control_deassert(port); | |
336 | } | |
337 | ||
338 | static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) | |
339 | { | |
340 | struct mt7621_pcie_port *port; | |
341 | ||
342 | list_for_each_entry(port, &pcie->ports, list) | |
343 | mt7621_rst_gpio_pcie_deassert(port); | |
344 | ||
4ab4ca20 | 345 | msleep(PERST_DELAY_MS); |
b27e35f9 SP |
346 | } |
347 | ||
7d761b08 | 348 | static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie) |
cd910f19 SP |
349 | { |
350 | struct device *dev = pcie->dev; | |
351 | struct mt7621_pcie_port *port, *tmp; | |
7d761b08 | 352 | u8 num_disabled = 0; |
cd910f19 SP |
353 | int err; |
354 | ||
b27e35f9 SP |
355 | mt7621_pcie_reset_assert(pcie); |
356 | mt7621_pcie_reset_rc_deassert(pcie); | |
07420a02 | 357 | |
cd910f19 SP |
358 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { |
359 | u32 slot = port->slot; | |
360 | ||
bf516f41 SP |
361 | if (slot == 1) { |
362 | port->enabled = true; | |
363 | continue; | |
364 | } | |
365 | ||
cd910f19 SP |
366 | err = mt7621_pcie_init_port(port); |
367 | if (err) { | |
2bdd5238 | 368 | dev_err(dev, "initializing port %d failed\n", slot); |
cd910f19 SP |
369 | list_del(&port->list); |
370 | } | |
371 | } | |
b8d97d43 | 372 | |
0cb2a8f3 | 373 | msleep(INIT_PORTS_DELAY_MS); |
b27e35f9 | 374 | mt7621_pcie_reset_ep_deassert(pcie); |
07420a02 | 375 | |
5fcded5e | 376 | tmp = NULL; |
07420a02 SP |
377 | list_for_each_entry(port, &pcie->ports, list) { |
378 | u32 slot = port->slot; | |
379 | ||
380 | if (!mt7621_pcie_port_is_linkup(port)) { | |
50233e10 SP |
381 | dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n", |
382 | slot); | |
07420a02 SP |
383 | mt7621_control_assert(port); |
384 | port->enabled = false; | |
7d761b08 | 385 | num_disabled++; |
5fcded5e SP |
386 | |
387 | if (slot == 0) { | |
388 | tmp = port; | |
389 | continue; | |
390 | } | |
391 | ||
392 | if (slot == 1 && tmp && !tmp->enabled) | |
393 | phy_power_off(tmp->phy); | |
07420a02 SP |
394 | } |
395 | } | |
7d761b08 SP |
396 | |
397 | return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV; | |
cd910f19 SP |
398 | } |
399 | ||
07420a02 | 400 | static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) |
802a2f7b SP |
401 | { |
402 | struct mt7621_pcie *pcie = port->pcie; | |
403 | u32 slot = port->slot; | |
802a2f7b | 404 | u32 val; |
802a2f7b SP |
405 | |
406 | /* enable pcie interrupt */ | |
407 | val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); | |
408 | val |= PCIE_PORT_INT_EN(slot); | |
409 | pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); | |
410 | ||
411 | /* map 2G DDR region */ | |
25203e32 SP |
412 | pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, |
413 | PCI_BASE_ADDRESS_0); | |
802a2f7b SP |
414 | |
415 | /* configure class code and revision ID */ | |
25203e32 SP |
416 | pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID, |
417 | RALINK_PCI_CLASS); | |
a3bb1d05 SP |
418 | |
419 | /* configure RC FTS number to 250 when it leaves L0s */ | |
420 | val = read_config(pcie, slot, PCIE_FTS_NUM); | |
421 | val &= ~PCIE_FTS_NUM_MASK; | |
422 | val |= PCIE_FTS_NUM_L0(0x50); | |
423 | write_config(pcie, slot, PCIE_FTS_NUM, val); | |
802a2f7b SP |
424 | } |
425 | ||
b15606e6 | 426 | static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) |
a41a1f86 | 427 | { |
b15606e6 | 428 | struct mt7621_pcie *pcie = pci_host_bridge_priv(host); |
a41a1f86 SP |
429 | struct device *dev = pcie->dev; |
430 | struct mt7621_pcie_port *port; | |
b15606e6 | 431 | struct resource_entry *entry; |
cc4e864a | 432 | int err; |
a41a1f86 | 433 | |
b15606e6 SP |
434 | entry = resource_list_first_type(&host->windows, IORESOURCE_IO); |
435 | if (!entry) { | |
2bdd5238 | 436 | dev_err(dev, "cannot get io resource\n"); |
b15606e6 SP |
437 | return -EINVAL; |
438 | } | |
439 | ||
09dd629e SP |
440 | /* Setup MEMWIN and IOWIN */ |
441 | pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); | |
e0b91381 | 442 | pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); |
09dd629e | 443 | |
a41a1f86 | 444 | list_for_each_entry(port, &pcie->ports, list) { |
a41a1f86 | 445 | if (port->enabled) { |
cc4e864a SP |
446 | err = clk_prepare_enable(port->clk); |
447 | if (err) { | |
a3bb1d05 SP |
448 | dev_err(dev, "enabling clk pcie%d\n", |
449 | port->slot); | |
cc4e864a SP |
450 | return err; |
451 | } | |
452 | ||
07420a02 | 453 | mt7621_pcie_enable_port(port); |
7846a982 | 454 | dev_info(dev, "PCIE%d enabled\n", port->slot); |
a41a1f86 SP |
455 | } |
456 | } | |
457 | ||
cc4e864a | 458 | return 0; |
a41a1f86 SP |
459 | } |
460 | ||
2fc0898b | 461 | static int mt7621_pcie_register_host(struct pci_host_bridge *host) |
8571c62d SP |
462 | { |
463 | struct mt7621_pcie *pcie = pci_host_bridge_priv(host); | |
464 | ||
4793895f | 465 | host->ops = &mt7621_pcie_ops; |
8571c62d | 466 | host->sysdata = pcie; |
8571c62d SP |
467 | return pci_host_probe(host); |
468 | } | |
469 | ||
4793895f | 470 | static const struct soc_device_attribute mt7621_pcie_quirks_match[] = { |
19098934 JT |
471 | { .soc_id = "mt7621", .revision = "E2" }, |
472 | { /* sentinel */ } | |
b483b4e4 SP |
473 | }; |
474 | ||
4793895f | 475 | static int mt7621_pcie_probe(struct platform_device *pdev) |
03f152e3 | 476 | { |
8571c62d | 477 | struct device *dev = &pdev->dev; |
b483b4e4 | 478 | const struct soc_device_attribute *attr; |
2d3d288f | 479 | struct mt7621_pcie_port *port; |
8571c62d SP |
480 | struct mt7621_pcie *pcie; |
481 | struct pci_host_bridge *bridge; | |
482 | int err; | |
8571c62d SP |
483 | |
484 | if (!dev->of_node) | |
485 | return -ENODEV; | |
486 | ||
487 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); | |
488 | if (!bridge) | |
a80775d6 | 489 | return -ENOMEM; |
03f152e3 | 490 | |
8571c62d SP |
491 | pcie = pci_host_bridge_priv(bridge); |
492 | pcie->dev = dev; | |
493 | platform_set_drvdata(pdev, pcie); | |
494 | INIT_LIST_HEAD(&pcie->ports); | |
495 | ||
4793895f | 496 | attr = soc_device_match(mt7621_pcie_quirks_match); |
b483b4e4 SP |
497 | if (attr) |
498 | pcie->resets_inverted = true; | |
499 | ||
8571c62d SP |
500 | err = mt7621_pcie_parse_dt(pcie); |
501 | if (err) { | |
2bdd5238 | 502 | dev_err(dev, "parsing DT failed\n"); |
8571c62d SP |
503 | return err; |
504 | } | |
505 | ||
7d761b08 SP |
506 | err = mt7621_pcie_init_ports(pcie); |
507 | if (err) { | |
2bdd5238 | 508 | dev_err(dev, "nothing connected in virtual bridges\n"); |
7d761b08 SP |
509 | return 0; |
510 | } | |
03f152e3 | 511 | |
b15606e6 | 512 | err = mt7621_pcie_enable_ports(bridge); |
cc4e864a | 513 | if (err) { |
2bdd5238 | 514 | dev_err(dev, "error enabling pcie ports\n"); |
2d3d288f | 515 | goto remove_resets; |
cc4e864a | 516 | } |
03f152e3 | 517 | |
35d96b88 | 518 | return mt7621_pcie_register_host(bridge); |
2d3d288f SP |
519 | |
520 | remove_resets: | |
521 | list_for_each_entry(port, &pcie->ports, list) | |
522 | reset_control_put(port->pcie_rst); | |
523 | ||
524 | return err; | |
525 | } | |
526 | ||
8c47ac2a | 527 | static void mt7621_pcie_remove(struct platform_device *pdev) |
2d3d288f SP |
528 | { |
529 | struct mt7621_pcie *pcie = platform_get_drvdata(pdev); | |
530 | struct mt7621_pcie_port *port; | |
531 | ||
532 | list_for_each_entry(port, &pcie->ports, list) | |
533 | reset_control_put(port->pcie_rst); | |
03f152e3 JC |
534 | } |
535 | ||
4793895f | 536 | static const struct of_device_id mt7621_pcie_ids[] = { |
03f152e3 JC |
537 | { .compatible = "mediatek,mt7621-pci" }, |
538 | {}, | |
539 | }; | |
4793895f | 540 | MODULE_DEVICE_TABLE(of, mt7621_pcie_ids); |
03f152e3 | 541 | |
4793895f BH |
542 | static struct platform_driver mt7621_pcie_driver = { |
543 | .probe = mt7621_pcie_probe, | |
8c47ac2a | 544 | .remove_new = mt7621_pcie_remove, |
03f152e3 JC |
545 | .driver = { |
546 | .name = "mt7621-pci", | |
4b77e4ab | 547 | .of_match_table = mt7621_pcie_ids, |
03f152e3 JC |
548 | }, |
549 | }; | |
4793895f | 550 | builtin_platform_driver(mt7621_pcie_driver); |
e4b1cd02 SP |
551 | |
552 | MODULE_LICENSE("GPL v2"); |