[linux-2.6-block.git] / drivers / pci / controller / pcie-cadence-ep.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017 Cadence
// Cadence PCIe endpoint controller driver.
// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pci-epc.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>

#include "pcie-cadence.h"

#define CDNS_PCIE_EP_MIN_APERTURE		128	/* 128 bytes */
#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE		0x1
#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY	0x3

/**
 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
 * @pcie: Cadence PCIe controller
 * @max_regions: maximum number of regions supported by hardware
 * @ob_region_map: bitmask of mapped outbound regions
 * @ob_addr: base addresses in the AXI bus where the outbound regions start
 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
 *		   dedicated outbound regions is mapped.
 * @irq_cpu_addr: base address in the CPU space where a write access triggers
 *		  the sending of a memory write (MSI) / normal message (legacy
 *		  IRQ) TLP through the PCIe bus.
 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
 *		  dedicated outbound region.
 * @irq_pci_fn: the latest PCI function that has updated the mapping of
 *		the MSI/legacy IRQ dedicated outbound region.
 * @irq_pending: bitmask of asserted legacy IRQs.
 */
struct cdns_pcie_ep {
	struct cdns_pcie		pcie;
	u32				max_regions;
	unsigned long			ob_region_map;
	phys_addr_t			*ob_addr;
	phys_addr_t			irq_phys_addr;
	void __iomem			*irq_cpu_addr;
	u64				irq_pci_addr;
	u8				irq_pci_fn;
	u8				irq_pending;
};

static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
				     struct pci_epf_header *hdr)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;

	cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
	cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
			       hdr->subclass_code | hdr->baseclass_code << 8);
	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
			       hdr->cache_line_size);
	cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);

	/*
	 * Vendor ID can only be modified from function 0, all other functions
	 * use the same vendor ID as function 0.
	 */
	if (fn == 0) {
		/* Update the vendor IDs. */
		u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
			 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);

		cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
	}

	return 0;
}

static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
				struct pci_epf_bar *epf_bar)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	dma_addr_t bar_phys = epf_bar->phys_addr;
	enum pci_barno bar = epf_bar->barno;
	int flags = epf_bar->flags;
	u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
	u64 sz;

	/* BAR size is 2^(aperture + 7) */
	sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
	/*
	 * roundup_pow_of_two() returns an unsigned long, which is not suited
	 * for 64bit values.
	 */
	sz = 1ULL << fls64(sz - 1);
	aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */

	if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
		ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
	} else {
		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
		bool is_64bits = sz > SZ_2G;

		if (is_64bits && (bar & 1))
			return -EINVAL;

		if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
			epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;

		if (is_64bits && is_prefetch)
			ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
		else if (is_prefetch)
			ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
		else if (is_64bits)
			ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
		else
			ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
	}

	addr0 = lower_32_bits(bar_phys);
	addr1 = upper_32_bits(bar_phys);
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
			 addr0);
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
			 addr1);

	if (bar < BAR_4) {
		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
		b = bar;
	} else {
		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
		b = bar - BAR_4;
	}

	cfg = cdns_pcie_readl(pcie, reg);
	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
		 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
	cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
		CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
	cdns_pcie_writel(pcie, reg, cfg);

	return 0;
}

static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
				   struct pci_epf_bar *epf_bar)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	enum pci_barno bar = epf_bar->barno;
	u32 reg, cfg, b, ctrl;

	if (bar < BAR_4) {
		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
		b = bar;
	} else {
		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
		b = bar - BAR_4;
	}

	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
	cfg = cdns_pcie_readl(pcie, reg);
	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
		 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
	cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
	cdns_pcie_writel(pcie, reg, cfg);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
}

static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
				 u64 pci_addr, size_t size)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	u32 r;

	r = find_first_zero_bit(&ep->ob_region_map,
				sizeof(ep->ob_region_map) * BITS_PER_LONG);
	if (r >= ep->max_regions - 1) {
		dev_err(&epc->dev, "no free outbound region\n");
		return -EINVAL;
	}

	cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);

	set_bit(r, &ep->ob_region_map);
	ep->ob_addr[r] = addr;

	return 0;
}

static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
				    phys_addr_t addr)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	u32 r;

	for (r = 0; r < ep->max_regions - 1; r++)
		if (ep->ob_addr[r] == addr)
			break;

	if (r == ep->max_regions - 1)
		return;

	cdns_pcie_reset_outbound_region(pcie, r);

	ep->ob_addr[r] = 0;
	clear_bit(r, &ep->ob_region_map);
}

static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
	u16 flags;

	/*
	 * Set the Multiple Message Capable bitfield into the Message Control
	 * register.
	 */
	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
	flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
	flags |= PCI_MSI_FLAGS_64BIT;
	flags &= ~PCI_MSI_FLAGS_MASKBIT;
	cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);

	return 0;
}

static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
	u16 flags, mme;

	/* Validate that the MSI feature is actually enabled. */
	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
	if (!(flags & PCI_MSI_FLAGS_ENABLE))
		return -EINVAL;

	/*
	 * Get the Multiple Message Enable bitfield from the Message Control
	 * register.
	 */
	mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;

	return mme;
}

static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
				     u8 intx, bool is_asserted)
{
	struct cdns_pcie *pcie = &ep->pcie;
	u32 offset;
	u16 status;
	u8 msg_code;

	intx &= 3;

	/* Set the outbound region if needed. */
	if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
		     ep->irq_pci_fn != fn)) {
		/* First region was reserved for IRQ writes. */
		cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
							     ep->irq_phys_addr);
		ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
		ep->irq_pci_fn = fn;
	}

	if (is_asserted) {
		ep->irq_pending |= BIT(intx);
		msg_code = MSG_CODE_ASSERT_INTA + intx;
	} else {
		ep->irq_pending &= ~BIT(intx);
		msg_code = MSG_CODE_DEASSERT_INTA + intx;
	}

	status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
	if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
		status ^= PCI_STATUS_INTERRUPT;
		cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
	}

	offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
		 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
		 CDNS_PCIE_MSG_NO_DATA;
	writel(0, ep->irq_cpu_addr + offset);
}

static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
{
	u16 cmd;

	cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
	if (cmd & PCI_COMMAND_INTX_DISABLE)
		return -EINVAL;

	cdns_pcie_ep_assert_intx(ep, fn, intx, true);
	/*
	 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
	 * from drivers/pci/dwc/pci-dra7xx.c
	 */
	mdelay(1);
	cdns_pcie_ep_assert_intx(ep, fn, intx, false);
	return 0;
}

static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
				     u8 interrupt_num)
{
	struct cdns_pcie *pcie = &ep->pcie;
	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
	u16 flags, mme, data, data_mask;
	u8 msi_count;
	u64 pci_addr, pci_addr_mask = 0xff;

	/* Check whether the MSI feature has been enabled by the PCI host. */
	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
	if (!(flags & PCI_MSI_FLAGS_ENABLE))
		return -EINVAL;

	/* Get the number of enabled MSIs */
	mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
	msi_count = 1 << mme;
	if (!interrupt_num || interrupt_num > msi_count)
		return -EINVAL;

	/* Compute the data value to be written. */
	data_mask = msi_count - 1;
	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
	data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);

	/* Get the PCI address where to write the data into. */
	pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
	pci_addr <<= 32;
	pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
	pci_addr &= GENMASK_ULL(63, 2);

	/* Set the outbound region if needed. */
	if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
		     ep->irq_pci_fn != fn)) {
		/* First region was reserved for IRQ writes. */
		cdns_pcie_set_outbound_region(pcie, fn, 0,
					      false,
					      ep->irq_phys_addr,
					      pci_addr & ~pci_addr_mask,
					      pci_addr_mask + 1);
		ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
		ep->irq_pci_fn = fn;
	}
	writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));

	return 0;
}

static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
				  enum pci_epc_irq_type type,
				  u16 interrupt_num)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	switch (type) {
	case PCI_EPC_IRQ_LEGACY:
		return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);

	case PCI_EPC_IRQ_MSI:
		return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);

	default:
		break;
	}

	return -EINVAL;
}

static int cdns_pcie_ep_start(struct pci_epc *epc)
{
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	struct cdns_pcie *pcie = &ep->pcie;
	struct pci_epf *epf;
	u32 cfg;

	/*
	 * BIT(0) is hardwired to 1, hence function 0 is always enabled
	 * and can't be disabled anyway.
	 */
	cfg = BIT(0);
	list_for_each_entry(epf, &epc->pci_epf, list)
		cfg |= BIT(epf->func_no);
	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);

	/*
	 * The PCIe links are automatically established by the controller
	 * once for all at powerup: the software can neither start nor stop
	 * those links later at runtime.
	 *
	 * Then we only have to notify the EP core that our links are already
	 * established. However we don't call directly pci_epc_linkup() because
	 * we've already locked the epc->lock.
	 */
	list_for_each_entry(epf, &epc->pci_epf, list)
		pci_epf_linkup(epf);

	return 0;
}

static const struct pci_epc_ops cdns_pcie_epc_ops = {
	.write_header	= cdns_pcie_ep_write_header,
	.set_bar	= cdns_pcie_ep_set_bar,
	.clear_bar	= cdns_pcie_ep_clear_bar,
	.map_addr	= cdns_pcie_ep_map_addr,
	.unmap_addr	= cdns_pcie_ep_unmap_addr,
	.set_msi	= cdns_pcie_ep_set_msi,
	.get_msi	= cdns_pcie_ep_get_msi,
	.raise_irq	= cdns_pcie_ep_raise_irq,
	.start		= cdns_pcie_ep_start,
};

static const struct of_device_id cdns_pcie_ep_of_match[] = {
	{ .compatible = "cdns,cdns-pcie-ep" },

	{ },
};

static int cdns_pcie_ep_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct cdns_pcie_ep *ep;
	struct cdns_pcie *pcie;
	struct pci_epc *epc;
	struct resource *res;
	int ret;
	int phy_count;

	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
	if (!ep)
		return -ENOMEM;

	pcie = &ep->pcie;
	pcie->is_rc = false;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	pcie->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(pcie->reg_base)) {
		dev_err(dev, "missing \"reg\"\n");
		return PTR_ERR(pcie->reg_base);
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	if (!res) {
		dev_err(dev, "missing \"mem\"\n");
		return -EINVAL;
	}
	pcie->mem_res = res;

	ret = of_property_read_u32(np, "cdns,max-outbound-regions",
				   &ep->max_regions);
	if (ret < 0) {
		dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
		return ret;
	}
	ep->ob_addr = devm_kcalloc(dev,
				   ep->max_regions, sizeof(*ep->ob_addr),
				   GFP_KERNEL);
	if (!ep->ob_addr)
		return -ENOMEM;

	ret = cdns_pcie_init_phy(dev, pcie);
	if (ret) {
		dev_err(dev, "failed to init phy\n");
		return ret;
	}
	platform_set_drvdata(pdev, pcie);
	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync() failed\n");
		goto err_get_sync;
	}

	/* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));

	epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
	if (IS_ERR(epc)) {
		dev_err(dev, "failed to create epc device\n");
		ret = PTR_ERR(epc);
		goto err_init;
	}

	epc_set_drvdata(epc, ep);

	if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
		epc->max_functions = 1;

	ret = pci_epc_mem_init(epc, pcie->mem_res->start,
			       resource_size(pcie->mem_res));
	if (ret < 0) {
		dev_err(dev, "failed to initialize the memory space\n");
		goto err_init;
	}

	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
						  SZ_128K);
	if (!ep->irq_cpu_addr) {
		dev_err(dev, "failed to reserve memory space for MSI\n");
		ret = -ENOMEM;
		goto free_epc_mem;
	}
	ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
	/* Reserve region 0 for IRQs */
	set_bit(0, &ep->ob_region_map);

	return 0;

 free_epc_mem:
	pci_epc_mem_exit(epc);

 err_init:
	pm_runtime_put_sync(dev);

 err_get_sync:
	pm_runtime_disable(dev);
	cdns_pcie_disable_phy(pcie);
	phy_count = pcie->phy_count;
	while (phy_count--)
		device_link_del(pcie->link[phy_count]);

	return ret;
}

static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct cdns_pcie *pcie = dev_get_drvdata(dev);
	int ret;

	ret = pm_runtime_put_sync(dev);
	if (ret < 0)
		dev_dbg(dev, "pm_runtime_put_sync failed\n");

	pm_runtime_disable(dev);

	cdns_pcie_disable_phy(pcie);
}

static struct platform_driver cdns_pcie_ep_driver = {
	.driver = {
		.name = "cdns-pcie-ep",
		.of_match_table = cdns_pcie_ep_of_match,
		.pm	= &cdns_pcie_pm_ops,
	},
	.probe = cdns_pcie_ep_probe,
	.shutdown = cdns_pcie_ep_shutdown,
};
builtin_platform_driver(cdns_pcie_ep_driver);
Commit	Line	Data
37dddf14 CP	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2017 Cadence
	3	// Cadence PCIe endpoint controller driver.
	4	// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
	5
	6	#include <linux/delay.h>
	7	#include <linux/kernel.h>
	8	#include <linux/of.h>
	9	#include <linux/pci-epc.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/pm_runtime.h>
	12	#include <linux/sizes.h>
	13
	14	#include "pcie-cadence.h"
	15
	16	#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
	17	#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
	18	#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
	19
	20	/**
	21	* struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
	22	* @pcie: Cadence PCIe controller
	23	* @max_regions: maximum number of regions supported by hardware
	24	* @ob_region_map: bitmask of mapped outbound regions
	25	* @ob_addr: base addresses in the AXI bus where the outbound regions start
	26	* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
	27	* dedicated outbound regions is mapped.
	28	* @irq_cpu_addr: base address in the CPU space where a write access triggers
	29	* the sending of a memory write (MSI) / normal message (legacy
	30	* IRQ) TLP through the PCIe bus.
	31	* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
	32	* dedicated outbound region.
	33	* @irq_pci_fn: the latest PCI function that has updated the mapping of
	34	* the MSI/legacy IRQ dedicated outbound region.
	35	* @irq_pending: bitmask of asserted legacy IRQs.
	36	*/
	37	struct cdns_pcie_ep {
	38	struct cdns_pcie pcie;
	39	u32 max_regions;
	40	unsigned long ob_region_map;
	41	phys_addr_t *ob_addr;
	42	phys_addr_t irq_phys_addr;
	43	void __iomem *irq_cpu_addr;
	44	u64 irq_pci_addr;
	45	u8 irq_pci_fn;
	46	u8 irq_pending;
	47	};
	48
	49	static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
	50	struct pci_epf_header *hdr)
	51	{
	52	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	53	struct cdns_pcie *pcie = &ep->pcie;
	54
	55	cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
	56	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
	57	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
	58	cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
	59	hdr->subclass_code \| hdr->baseclass_code << 8);
	60	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
	61	hdr->cache_line_size);
	62	cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
	63	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
	64
65	/*
66	* Vendor ID can only be modified from function 0, all other functions
67	* use the same vendor ID as function 0.
68	*/
69	if (fn == 0) {
70	/* Update the vendor IDs. */
71	u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) \|
72	CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
73
74	cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
75	}
76
77	return 0;
78	}
79
bc4a4897 NC	80	static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
bc4a4897 NC	81	struct pci_epf_bar *epf_bar)
37dddf14 CP	82	{
	83	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	84	struct cdns_pcie *pcie = &ep->pcie;
bc4a4897 NC	85	dma_addr_t bar_phys = epf_bar->phys_addr;
	86	enum pci_barno bar = epf_bar->barno;
	87	int flags = epf_bar->flags;
37dddf14 CP	88	u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
	89	u64 sz;
	90
	91	/* BAR size is 2^(aperture + 7) */
bc4a4897	92	sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
37dddf14 CP	93	/*
	94	* roundup_pow_of_two() returns an unsigned long, which is not suited
	95	* for 64bit values.
	96	*/
	97	sz = 1ULL << fls64(sz - 1);
	98	aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
	99
	100	if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
	101	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
	102	} else {
	103	bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
	104	bool is_64bits = sz > SZ_2G;
	105
	106	if (is_64bits && (bar & 1))
	107	return -EINVAL;
	108
a2ea8ac4 NC	109	if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
	110	epf_bar->flags \|= PCI_BASE_ADDRESS_MEM_TYPE_64;
	111
37dddf14 CP	112	if (is_64bits && is_prefetch)
	113	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
	114	else if (is_prefetch)
	115	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
	116	else if (is_64bits)
	117	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
	118	else
	119	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
	120	}
	121
	122	addr0 = lower_32_bits(bar_phys);
	123	addr1 = upper_32_bits(bar_phys);
	124	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
	125	addr0);
	126	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
	127	addr1);
	128
	129	if (bar < BAR_4) {
	130	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
	131	b = bar;
	132	} else {
	133	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
	134	b = bar - BAR_4;
	135	}
	136
	137	cfg = cdns_pcie_readl(pcie, reg);
	138	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \|
	139	CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
	140	cfg \|= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) \|
	141	CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
	142	cdns_pcie_writel(pcie, reg, cfg);
	143
	144	return 0;
	145	}
	146
	147	static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
77d08dbd	148	struct pci_epf_bar *epf_bar)
37dddf14 CP	149	{
	150	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	151	struct cdns_pcie *pcie = &ep->pcie;
77d08dbd	152	enum pci_barno bar = epf_bar->barno;
37dddf14 CP	153	u32 reg, cfg, b, ctrl;
	154
	155	if (bar < BAR_4) {
	156	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
	157	b = bar;
	158	} else {
	159	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
	160	b = bar - BAR_4;
	161	}
	162
	163	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
	164	cfg = cdns_pcie_readl(pcie, reg);
	165	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \|
	166	CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
	167	cfg \|= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
	168	cdns_pcie_writel(pcie, reg, cfg);
	169
	170	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
	171	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
	172	}
	173
	174	static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
	175	u64 pci_addr, size_t size)
	176	{
	177	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	178	struct cdns_pcie *pcie = &ep->pcie;
	179	u32 r;
	180
	181	r = find_first_zero_bit(&ep->ob_region_map,
	182	sizeof(ep->ob_region_map) * BITS_PER_LONG);
	183	if (r >= ep->max_regions - 1) {
	184	dev_err(&epc->dev, "no free outbound region\n");
	185	return -EINVAL;
	186	}
	187
	188	cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
	189
	190	set_bit(r, &ep->ob_region_map);
	191	ep->ob_addr[r] = addr;
	192
	193	return 0;
	194	}
	195
	196	static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
	197	phys_addr_t addr)
	198	{
	199	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	200	struct cdns_pcie *pcie = &ep->pcie;
	201	u32 r;
	202
	203	for (r = 0; r < ep->max_regions - 1; r++)
	204	if (ep->ob_addr[r] == addr)
	205	break;
	206
	207	if (r == ep->max_regions - 1)
	208	return;
	209
	210	cdns_pcie_reset_outbound_region(pcie, r);
	211
	212	ep->ob_addr[r] = 0;
	213	clear_bit(r, &ep->ob_region_map);
	214	}
	215
	216	static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
217	{
218	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
219	struct cdns_pcie *pcie = &ep->pcie;
220	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
221	u16 flags;
222
223	/*
224	* Set the Multiple Message Capable bitfield into the Message Control
225	* register.
226	*/
227	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
228	flags = (flags & ~PCI_MSI_FLAGS_QMASK) \| (mmc << 1);
229	flags \|= PCI_MSI_FLAGS_64BIT;
230	flags &= ~PCI_MSI_FLAGS_MASKBIT;
231	cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
232
233	return 0;
234	}
235
236	static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
237	{
238	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
239	struct cdns_pcie *pcie = &ep->pcie;
240	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
eb1e39f7	241	u16 flags, mme;
37dddf14 CP	242
	243	/* Validate that the MSI feature is actually enabled. */
	244	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
	245	if (!(flags & PCI_MSI_FLAGS_ENABLE))
	246	return -EINVAL;
	247
	248	/*
	249	* Get the Multiple Message Enable bitfield from the Message Control
	250	* register.
	251	*/
37dddf14 CP	252	mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
	253
	254	return mme;
	255	}
	256
	257	static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
	258	u8 intx, bool is_asserted)
	259	{
	260	struct cdns_pcie *pcie = &ep->pcie;
37dddf14 CP	261	u32 offset;
	262	u16 status;
	263	u8 msg_code;
	264
	265	intx &= 3;
	266
	267	/* Set the outbound region if needed. */
	268	if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY \|\|
	269	ep->irq_pci_fn != fn)) {
0652d4b6 AD	270	/* First region was reserved for IRQ writes. */
0652d4b6 AD	271	cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
37dddf14 CP	272	ep->irq_phys_addr);
	273	ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
	274	ep->irq_pci_fn = fn;
	275	}
	276
	277	if (is_asserted) {
	278	ep->irq_pending \|= BIT(intx);
	279	msg_code = MSG_CODE_ASSERT_INTA + intx;
	280	} else {
	281	ep->irq_pending &= ~BIT(intx);
	282	msg_code = MSG_CODE_DEASSERT_INTA + intx;
	283	}
	284
	285	status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
	286	if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
	287	status ^= PCI_STATUS_INTERRUPT;
	288	cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
	289	}
	290
	291	offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) \|
	292	CDNS_PCIE_NORMAL_MSG_CODE(msg_code) \|
	293	CDNS_PCIE_MSG_NO_DATA;
	294	writel(0, ep->irq_cpu_addr + offset);
	295	}
	296
	297	static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
	298	{
	299	u16 cmd;
	300
	301	cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
	302	if (cmd & PCI_COMMAND_INTX_DISABLE)
	303	return -EINVAL;
	304
	305	cdns_pcie_ep_assert_intx(ep, fn, intx, true);
	306	/*
	307	* The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
	308	* from drivers/pci/dwc/pci-dra7xx.c
	309	*/
	310	mdelay(1);
	311	cdns_pcie_ep_assert_intx(ep, fn, intx, false);
	312	return 0;
	313	}
	314
	315	static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
	316	u8 interrupt_num)
	317	{
	318	struct cdns_pcie *pcie = &ep->pcie;
	319	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
	320	u16 flags, mme, data, data_mask;
	321	u8 msi_count;
	322	u64 pci_addr, pci_addr_mask = 0xff;
	323
	324	/* Check whether the MSI feature has been enabled by the PCI host. */
	325	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
	326	if (!(flags & PCI_MSI_FLAGS_ENABLE))
	327	return -EINVAL;
	328
	329	/* Get the number of enabled MSIs */
	330	mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
	331	msi_count = 1 << mme;
	332	if (!interrupt_num \|\| interrupt_num > msi_count)
	333	return -EINVAL;
	334
	335	/* Compute the data value to be written. */
336	data_mask = msi_count - 1;
337	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
338	data = (data & ~data_mask) \| ((interrupt_num - 1) & data_mask);
339
340	/* Get the PCI address where to write the data into. */
341	pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
342	pci_addr <<= 32;
343	pci_addr \|= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
344	pci_addr &= GENMASK_ULL(63, 2);
345
346	/* Set the outbound region if needed. */
347	if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) \|\|
348	ep->irq_pci_fn != fn)) {
0652d4b6 AD	349	/* First region was reserved for IRQ writes. */
0652d4b6 AD	350	cdns_pcie_set_outbound_region(pcie, fn, 0,
37dddf14 CP	351	false,
	352	ep->irq_phys_addr,
	353	pci_addr & ~pci_addr_mask,
	354	pci_addr_mask + 1);
	355	ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
	356	ep->irq_pci_fn = fn;
	357	}
e81e36a9	358	writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
37dddf14 CP	359
	360	return 0;
	361	}
	362
	363	static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
d3c70a98 GP	364	enum pci_epc_irq_type type,
d3c70a98 GP	365	u16 interrupt_num)
37dddf14 CP	366	{
	367	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	368
	369	switch (type) {
	370	case PCI_EPC_IRQ_LEGACY:
	371	return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
	372
	373	case PCI_EPC_IRQ_MSI:
	374	return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
	375
	376	default:
	377	break;
	378	}
	379
	380	return -EINVAL;
	381	}
	382
	383	static int cdns_pcie_ep_start(struct pci_epc *epc)
	384	{
	385	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
	386	struct cdns_pcie *pcie = &ep->pcie;
	387	struct pci_epf *epf;
	388	u32 cfg;
	389
	390	/*
	391	* BIT(0) is hardwired to 1, hence function 0 is always enabled
	392	* and can't be disabled anyway.
	393	*/
	394	cfg = BIT(0);
	395	list_for_each_entry(epf, &epc->pci_epf, list)
	396	cfg \|= BIT(epf->func_no);
	397	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
	398
	399	/*
	400	* The PCIe links are automatically established by the controller
	401	* once for all at powerup: the software can neither start nor stop
	402	* those links later at runtime.
	403	*
	404	* Then we only have to notify the EP core that our links are already
	405	* established. However we don't call directly pci_epc_linkup() because
	406	* we've already locked the epc->lock.
	407	*/
	408	list_for_each_entry(epf, &epc->pci_epf, list)
	409	pci_epf_linkup(epf);
	410
	411	return 0;
	412	}
	413
	414	static const struct pci_epc_ops cdns_pcie_epc_ops = {
	415	.write_header = cdns_pcie_ep_write_header,
	416	.set_bar = cdns_pcie_ep_set_bar,
	417	.clear_bar = cdns_pcie_ep_clear_bar,
	418	.map_addr = cdns_pcie_ep_map_addr,
	419	.unmap_addr = cdns_pcie_ep_unmap_addr,
	420	.set_msi = cdns_pcie_ep_set_msi,
	421	.get_msi = cdns_pcie_ep_get_msi,
	422	.raise_irq = cdns_pcie_ep_raise_irq,
	423	.start = cdns_pcie_ep_start,
	424	};
	425
	426	static const struct of_device_id cdns_pcie_ep_of_match[] = {
	427	{ .compatible = "cdns,cdns-pcie-ep" },
	428
	429	{ },
430	};
431
432	static int cdns_pcie_ep_probe(struct platform_device *pdev)
433	{
434	struct device *dev = &pdev->dev;
435	struct device_node *np = dev->of_node;
436	struct cdns_pcie_ep *ep;
437	struct cdns_pcie *pcie;
438	struct pci_epc *epc;
439	struct resource *res;
440	int ret;
dfb80534	441	int phy_count;
37dddf14 CP	442
	443	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
	444	if (!ep)
	445	return -ENOMEM;
	446
	447	pcie = &ep->pcie;
	448	pcie->is_rc = false;
	449
	450	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	451	pcie->reg_base = devm_ioremap_resource(dev, res);
	452	if (IS_ERR(pcie->reg_base)) {
	453	dev_err(dev, "missing \"reg\"\n");
	454	return PTR_ERR(pcie->reg_base);
	455	}
	456
	457	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	458	if (!res) {
	459	dev_err(dev, "missing \"mem\"\n");
	460	return -EINVAL;
	461	}
	462	pcie->mem_res = res;
	463
	464	ret = of_property_read_u32(np, "cdns,max-outbound-regions",
	465	&ep->max_regions);
	466	if (ret < 0) {
	467	dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
	468	return ret;
	469	}
a86854d0 KC	470	ep->ob_addr = devm_kcalloc(dev,
a86854d0 KC	471	ep->max_regions, sizeof(*ep->ob_addr),
37dddf14 CP	472	GFP_KERNEL);
	473	if (!ep->ob_addr)
	474	return -ENOMEM;
	475
dfb80534 AD	476	ret = cdns_pcie_init_phy(dev, pcie);
	477	if (ret) {
	478	dev_err(dev, "failed to init phy\n");
	479	return ret;
	480	}
	481	platform_set_drvdata(pdev, pcie);
37dddf14 CP	482	pm_runtime_enable(dev);
	483	ret = pm_runtime_get_sync(dev);
	484	if (ret < 0) {
	485	dev_err(dev, "pm_runtime_get_sync() failed\n");
	486	goto err_get_sync;
	487	}
	488
	489	/* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
	490	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
	491
	492	epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
	493	if (IS_ERR(epc)) {
	494	dev_err(dev, "failed to create epc device\n");
	495	ret = PTR_ERR(epc);
	496	goto err_init;
	497	}
	498
	499	epc_set_drvdata(epc, ep);
	500
	501	if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
	502	epc->max_functions = 1;
	503
	504	ret = pci_epc_mem_init(epc, pcie->mem_res->start,
	505	resource_size(pcie->mem_res));
	506	if (ret < 0) {
	507	dev_err(dev, "failed to initialize the memory space\n");
	508	goto err_init;
	509	}
	510
	511	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
	512	SZ_128K);
	513	if (!ep->irq_cpu_addr) {
	514	dev_err(dev, "failed to reserve memory space for MSI\n");
	515	ret = -ENOMEM;
	516	goto free_epc_mem;
	517	}
	518	ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
0652d4b6 AD	519	/* Reserve region 0 for IRQs */
0652d4b6 AD	520	set_bit(0, &ep->ob_region_map);
37dddf14 CP	521
	522	return 0;
	523
	524	free_epc_mem:
	525	pci_epc_mem_exit(epc);
	526
	527	err_init:
	528	pm_runtime_put_sync(dev);
	529
	530	err_get_sync:
	531	pm_runtime_disable(dev);
dfb80534 AD	532	cdns_pcie_disable_phy(pcie);
	533	phy_count = pcie->phy_count;
	534	while (phy_count--)
	535	device_link_del(pcie->link[phy_count]);
37dddf14 CP	536
	537	return ret;
	538	}
	539
	540	static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
	541	{
	542	struct device *dev = &pdev->dev;
dfb80534	543	struct cdns_pcie *pcie = dev_get_drvdata(dev);
37dddf14 CP	544	int ret;
	545
	546	ret = pm_runtime_put_sync(dev);
	547	if (ret < 0)
	548	dev_dbg(dev, "pm_runtime_put_sync failed\n");
	549
	550	pm_runtime_disable(dev);
	551
dfb80534	552	cdns_pcie_disable_phy(pcie);
37dddf14 CP	553	}
	554
	555	static struct platform_driver cdns_pcie_ep_driver = {
	556	.driver = {
	557	.name = "cdns-pcie-ep",
	558	.of_match_table = cdns_pcie_ep_of_match,
ee12c9ef	559	.pm = &cdns_pcie_pm_ops,
37dddf14 CP	560	},
	561	.probe = cdns_pcie_ep_probe,
	562	.shutdown = cdns_pcie_ep_shutdown,
	563	};
	564	builtin_platform_driver(cdns_pcie_ep_driver);