[linux-2.6-block.git] / drivers / pci / controller / pci-ftpci100.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Support for Faraday Technology FTPC100 PCI Controller
 *
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 * Based on SL2312 PCI controller code
 * Storlink (C) 2003
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>

#include "../pci.h"

/*
 * Special configuration registers directly in the first few words
 * in I/O space.
 */
#define PCI_IOSIZE	0x00
#define PCI_PROT	0x04 /* AHB protection */
#define PCI_CTRL	0x08 /* PCI control signal */
#define PCI_SOFTRST	0x10 /* Soft reset counter and response error enable */
#define PCI_CONFIG	0x28 /* PCI configuration command register */
#define PCI_DATA	0x2C

#define FARADAY_PCI_STATUS_CMD		0x04 /* Status and command */
#define FARADAY_PCI_PMC			0x40 /* Power management control */
#define FARADAY_PCI_PMCSR		0x44 /* Power management status */
#define FARADAY_PCI_CTRL1		0x48 /* Control register 1 */
#define FARADAY_PCI_CTRL2		0x4C /* Control register 2 */
#define FARADAY_PCI_MEM1_BASE_SIZE	0x50 /* Memory base and size #1 */
#define FARADAY_PCI_MEM2_BASE_SIZE	0x54 /* Memory base and size #2 */
#define FARADAY_PCI_MEM3_BASE_SIZE	0x58 /* Memory base and size #3 */

#define PCI_STATUS_66MHZ_CAPABLE	BIT(21)

/* Bits 31..28 gives INTD..INTA status */
#define PCI_CTRL2_INTSTS_SHIFT		28
#define PCI_CTRL2_INTMASK_CMDERR	BIT(27)
#define PCI_CTRL2_INTMASK_PARERR	BIT(26)
/* Bits 25..22 masks INTD..INTA */
#define PCI_CTRL2_INTMASK_SHIFT		22
#define PCI_CTRL2_INTMASK_MABRT_RX	BIT(21)
#define PCI_CTRL2_INTMASK_TABRT_RX	BIT(20)
#define PCI_CTRL2_INTMASK_TABRT_TX	BIT(19)
#define PCI_CTRL2_INTMASK_RETRY4	BIT(18)
#define PCI_CTRL2_INTMASK_SERR_RX	BIT(17)
#define PCI_CTRL2_INTMASK_PERR_RX	BIT(16)
/* Bit 15 reserved */
#define PCI_CTRL2_MSTPRI_REQ6		BIT(14)
#define PCI_CTRL2_MSTPRI_REQ5		BIT(13)
#define PCI_CTRL2_MSTPRI_REQ4		BIT(12)
#define PCI_CTRL2_MSTPRI_REQ3		BIT(11)
#define PCI_CTRL2_MSTPRI_REQ2		BIT(10)
#define PCI_CTRL2_MSTPRI_REQ1		BIT(9)
#define PCI_CTRL2_MSTPRI_REQ0		BIT(8)
/* Bits 7..4 reserved */
/* Bits 3..0 TRDYW */

/*
 * Memory configs:
 * Bit 31..20 defines the PCI side memory base
 * Bit 19..16 (4 bits) defines the size per below
 */
#define FARADAY_PCI_MEMBASE_MASK	0xfff00000
#define FARADAY_PCI_MEMSIZE_1MB		0x0
#define FARADAY_PCI_MEMSIZE_2MB		0x1
#define FARADAY_PCI_MEMSIZE_4MB		0x2
#define FARADAY_PCI_MEMSIZE_8MB		0x3
#define FARADAY_PCI_MEMSIZE_16MB	0x4
#define FARADAY_PCI_MEMSIZE_32MB	0x5
#define FARADAY_PCI_MEMSIZE_64MB	0x6
#define FARADAY_PCI_MEMSIZE_128MB	0x7
#define FARADAY_PCI_MEMSIZE_256MB	0x8
#define FARADAY_PCI_MEMSIZE_512MB	0x9
#define FARADAY_PCI_MEMSIZE_1GB		0xa
#define FARADAY_PCI_MEMSIZE_2GB		0xb
#define FARADAY_PCI_MEMSIZE_SHIFT	16

/*
 * The DMA base is set to 0x0 for all memory segments, it reflects the
 * fact that the memory of the host system starts at 0x0.
 */
#define FARADAY_PCI_DMA_MEM1_BASE	0x00000000
#define FARADAY_PCI_DMA_MEM2_BASE	0x00000000
#define FARADAY_PCI_DMA_MEM3_BASE	0x00000000

/* Defines for PCI configuration command register */
#define PCI_CONF_ENABLE		BIT(31)
#define PCI_CONF_WHERE(r)	((r) & 0xFC)
#define PCI_CONF_BUS(b)		(((b) & 0xFF) << 16)
#define PCI_CONF_DEVICE(d)	(((d) & 0x1F) << 11)
#define PCI_CONF_FUNCTION(f)	(((f) & 0x07) << 8)

/**
 * struct faraday_pci_variant - encodes IP block differences
 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
 *	embedded in the host bridge.
 */
struct faraday_pci_variant {
	bool cascaded_irq;
};

struct faraday_pci {
	struct device *dev;
	void __iomem *base;
	struct irq_domain *irqdomain;
	struct pci_bus *bus;
	struct clk *bus_clk;
};

static int faraday_res_to_memcfg(resource_size_t mem_base,
				 resource_size_t mem_size, u32 *val)
{
	u32 outval;

	switch (mem_size) {
	case SZ_1M:
		outval = FARADAY_PCI_MEMSIZE_1MB;
		break;
	case SZ_2M:
		outval = FARADAY_PCI_MEMSIZE_2MB;
		break;
	case SZ_4M:
		outval = FARADAY_PCI_MEMSIZE_4MB;
		break;
	case SZ_8M:
		outval = FARADAY_PCI_MEMSIZE_8MB;
		break;
	case SZ_16M:
		outval = FARADAY_PCI_MEMSIZE_16MB;
		break;
	case SZ_32M:
		outval = FARADAY_PCI_MEMSIZE_32MB;
		break;
	case SZ_64M:
		outval = FARADAY_PCI_MEMSIZE_64MB;
		break;
	case SZ_128M:
		outval = FARADAY_PCI_MEMSIZE_128MB;
		break;
	case SZ_256M:
		outval = FARADAY_PCI_MEMSIZE_256MB;
		break;
	case SZ_512M:
		outval = FARADAY_PCI_MEMSIZE_512MB;
		break;
	case SZ_1G:
		outval = FARADAY_PCI_MEMSIZE_1GB;
		break;
	case SZ_2G:
		outval = FARADAY_PCI_MEMSIZE_2GB;
		break;
	default:
		return -EINVAL;
	}
	outval <<= FARADAY_PCI_MEMSIZE_SHIFT;

	/* This is probably not good */
	if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
		pr_warn("truncated PCI memory base\n");
	/* Translate to bridge side address space */
	outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
	pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
		 &mem_base, &mem_size, outval);

	*val = outval;
	return 0;
}

static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
				       unsigned int fn, int config, int size,
				       u32 *value)
{
	writel(PCI_CONF_BUS(bus_number) |
			PCI_CONF_DEVICE(PCI_SLOT(fn)) |
			PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
			PCI_CONF_WHERE(config) |
			PCI_CONF_ENABLE,
			p->base + PCI_CONFIG);

	*value = readl(p->base + PCI_DATA);

	if (size == 1)
		*value = (*value >> (8 * (config & 3))) & 0xFF;
	else if (size == 2)
		*value = (*value >> (8 * (config & 3))) & 0xFFFF;

	return PCIBIOS_SUCCESSFUL;
}

static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
				   int config, int size, u32 *value)
{
	struct faraday_pci *p = bus->sysdata;

	dev_dbg(&bus->dev,
		"[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
		PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);

	return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
}

static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
					 unsigned int fn, int config, int size,
					 u32 value)
{
	int ret = PCIBIOS_SUCCESSFUL;

	writel(PCI_CONF_BUS(bus_number) |
			PCI_CONF_DEVICE(PCI_SLOT(fn)) |
			PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
			PCI_CONF_WHERE(config) |
			PCI_CONF_ENABLE,
			p->base + PCI_CONFIG);

	switch (size) {
	case 4:
		writel(value, p->base + PCI_DATA);
		break;
	case 2:
		writew(value, p->base + PCI_DATA + (config & 3));
		break;
	case 1:
		writeb(value, p->base + PCI_DATA + (config & 3));
		break;
	default:
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	return ret;
}

static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
				    int config, int size, u32 value)
{
	struct faraday_pci *p = bus->sysdata;

	dev_dbg(&bus->dev,
		"[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
		PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);

	return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
					    value);
}

static struct pci_ops faraday_pci_ops = {
	.read	= faraday_pci_read_config,
	.write	= faraday_pci_write_config,
};

static void faraday_pci_ack_irq(struct irq_data *d)
{
	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	unsigned int reg;

	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
	reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
	reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
}

static void faraday_pci_mask_irq(struct irq_data *d)
{
	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	unsigned int reg;

	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
	reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
		 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
}

static void faraday_pci_unmask_irq(struct irq_data *d)
{
	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	unsigned int reg;

	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
	reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
	reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
}

static void faraday_pci_irq_handler(struct irq_desc *desc)
{
	struct faraday_pci *p = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	unsigned int irq_stat, reg, i;

	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
	irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;

	chained_irq_enter(irqchip, desc);

	for (i = 0; i < 4; i++) {
		if ((irq_stat & BIT(i)) == 0)
			continue;
		generic_handle_irq(irq_find_mapping(p->irqdomain, i));
	}

	chained_irq_exit(irqchip, desc);
}

static struct irq_chip faraday_pci_irq_chip = {
	.name = "PCI",
	.irq_ack = faraday_pci_ack_irq,
	.irq_mask = faraday_pci_mask_irq,
	.irq_unmask = faraday_pci_unmask_irq,
};

static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
			       irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
	.map = faraday_pci_irq_map,
};

static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
{
	struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
	int irq;
	int i;

	if (!intc) {
		dev_err(p->dev, "missing child interrupt-controller node\n");
		return -EINVAL;
	}

	/* All PCI IRQs cascade off this one */
	irq = of_irq_get(intc, 0);
	if (irq <= 0) {
		dev_err(p->dev, "failed to get parent IRQ\n");
		of_node_put(intc);
		return irq ?: -EINVAL;
	}

	p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
					     &faraday_pci_irqdomain_ops, p);
	of_node_put(intc);
	if (!p->irqdomain) {
		dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
		return -EINVAL;
	}

	irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);

	for (i = 0; i < 4; i++)
		irq_create_mapping(p->irqdomain, i);

	return 0;
}

static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
					    struct device_node *np)
{
	struct of_pci_range range;
	struct of_pci_range_parser parser;
	struct device *dev = p->dev;
	u32 confreg[3] = {
		FARADAY_PCI_MEM1_BASE_SIZE,
		FARADAY_PCI_MEM2_BASE_SIZE,
		FARADAY_PCI_MEM3_BASE_SIZE,
	};
	int i = 0;
	u32 val;

	if (of_pci_dma_range_parser_init(&parser, np)) {
		dev_err(dev, "missing dma-ranges property\n");
		return -EINVAL;
	}

	/*
	 * Get the dma-ranges from the device tree
	 */
	for_each_of_pci_range(&parser, &range) {
		u64 end = range.pci_addr + range.size - 1;
		int ret;

		ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
		if (ret) {
			dev_err(dev,
				"DMA range %d: illegal MEM resource size\n", i);
			return -EINVAL;
		}

		dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
			 i + 1, range.pci_addr, end, val);
		if (i <= 2) {
			faraday_raw_pci_write_config(p, 0, 0, confreg[i],
						     4, val);
		} else {
			dev_err(dev, "ignore extraneous dma-range %d\n", i);
			break;
		}

		i++;
	}

	return 0;
}

static int faraday_pci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct faraday_pci_variant *variant =
		of_device_get_match_data(dev);
	struct resource *regs;
	resource_size_t io_base;
	struct resource_entry *win;
	struct faraday_pci *p;
	struct resource *mem;
	struct resource *io;
	struct pci_host_bridge *host;
	struct clk *clk;
	unsigned char max_bus_speed = PCI_SPEED_33MHz;
	unsigned char cur_bus_speed = PCI_SPEED_33MHz;
	int ret;
	u32 val;
	LIST_HEAD(res);

	host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
	if (!host)
		return -ENOMEM;

	host->dev.parent = dev;
	host->ops = &faraday_pci_ops;
	host->busnr = 0;
	host->msi = NULL;
	host->map_irq = of_irq_parse_and_map_pci;
	host->swizzle_irq = pci_common_swizzle;
	p = pci_host_bridge_priv(host);
	host->sysdata = p;
	p->dev = dev;

	/* Retrieve and enable optional clocks */
	clk = devm_clk_get(dev, "PCLK");
	if (IS_ERR(clk))
		return PTR_ERR(clk);
	ret = clk_prepare_enable(clk);
	if (ret) {
		dev_err(dev, "could not prepare PCLK\n");
		return ret;
	}
	p->bus_clk = devm_clk_get(dev, "PCICLK");
	if (IS_ERR(p->bus_clk))
		return PTR_ERR(p->bus_clk);
	ret = clk_prepare_enable(p->bus_clk);
	if (ret) {
		dev_err(dev, "could not prepare PCICLK\n");
		return ret;
	}

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	p->base = devm_ioremap_resource(dev, regs);
	if (IS_ERR(p->base))
		return PTR_ERR(p->base);

	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
						    &res, &io_base);
	if (ret)
		return ret;

	ret = devm_request_pci_bus_resources(dev, &res);
	if (ret)
		return ret;

	/* Get the I/O and memory ranges from DT */
	resource_list_for_each_entry(win, &res) {
		switch (resource_type(win->res)) {
		case IORESOURCE_IO:
			io = win->res;
			io->name = "Gemini PCI I/O";
			if (!faraday_res_to_memcfg(io->start - win->offset,
						   resource_size(io), &val)) {
				/* setup I/O space size */
				writel(val, p->base + PCI_IOSIZE);
			} else {
				dev_err(dev, "illegal IO mem size\n");
				return -EINVAL;
			}
			ret = devm_pci_remap_iospace(dev, io, io_base);
			if (ret) {
				dev_warn(dev, "error %d: failed to map resource %pR\n",
					 ret, io);
				continue;
			}
			break;
		case IORESOURCE_MEM:
			mem = win->res;
			mem->name = "Gemini PCI MEM";
			break;
		case IORESOURCE_BUS:
			break;
		default:
			break;
		}
	}

	/* Setup hostbridge */
	val = readl(p->base + PCI_CTRL);
	val |= PCI_COMMAND_IO;
	val |= PCI_COMMAND_MEMORY;
	val |= PCI_COMMAND_MASTER;
	writel(val, p->base + PCI_CTRL);
	/* Mask and clear all interrupts */
	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
	if (variant->cascaded_irq) {
		ret = faraday_pci_setup_cascaded_irq(p);
		if (ret) {
			dev_err(dev, "failed to setup cascaded IRQ\n");
			return ret;
		}
	}

	/* Check bus clock if we can gear up to 66 MHz */
	if (!IS_ERR(p->bus_clk)) {
		unsigned long rate;
		u32 val;

		faraday_raw_pci_read_config(p, 0, 0,
					    FARADAY_PCI_STATUS_CMD, 4, &val);
		rate = clk_get_rate(p->bus_clk);

		if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
			dev_info(dev, "33MHz bus is 66MHz capable\n");
			max_bus_speed = PCI_SPEED_66MHz;
			ret = clk_set_rate(p->bus_clk, 66000000);
			if (ret)
				dev_err(dev, "failed to set bus clock\n");
		} else {
			dev_info(dev, "33MHz only bus\n");
			max_bus_speed = PCI_SPEED_33MHz;
		}

		/* Bumping the clock may fail so read back the rate */
		rate = clk_get_rate(p->bus_clk);
		if (rate == 33000000)
			cur_bus_speed = PCI_SPEED_33MHz;
		if (rate == 66000000)
			cur_bus_speed = PCI_SPEED_66MHz;
	}

	ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
	if (ret)
		return ret;

	list_splice_init(&res, &host->windows);
	ret = pci_scan_root_bus_bridge(host);
	if (ret) {
		dev_err(dev, "failed to scan host: %d\n", ret);
		return ret;
	}
	p->bus = host->bus;
	p->bus->max_bus_speed = max_bus_speed;
	p->bus->cur_bus_speed = cur_bus_speed;

	pci_bus_assign_resources(p->bus);
	pci_bus_add_devices(p->bus);
	pci_free_resource_list(&res);

	return 0;
}

/*
 * We encode bridge variants here, we have at least two so it doesn't
 * hurt to have infrastructure to encompass future variants as well.
 */
static const struct faraday_pci_variant faraday_regular = {
	.cascaded_irq = true,
};

static const struct faraday_pci_variant faraday_dual = {
	.cascaded_irq = false,
};

static const struct of_device_id faraday_pci_of_match[] = {
	{
		.compatible = "faraday,ftpci100",
		.data = &faraday_regular,
	},
	{
		.compatible = "faraday,ftpci100-dual",
		.data = &faraday_dual,
	},
	{},
};

static struct platform_driver faraday_pci_driver = {
	.driver = {
		.name = "ftpci100",
		.of_match_table = of_match_ptr(faraday_pci_of_match),
		.suppress_bind_attrs = true,
	},
	.probe  = faraday_pci_probe,
};
builtin_platform_driver(faraday_pci_driver);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
d3c68e0a LW	2	/*
	3	* Support for Faraday Technology FTPC100 PCI Controller
	4	*
	5	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	6	*
	7	* Based on the out-of-tree OpenWRT patch for Cortina Gemini:
	8	* Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
	9	* Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	10	* Based on SL2312 PCI controller code
	11	* Storlink (C) 2003
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of_device.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_pci.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/slab.h>
	25	#include <linux/irqdomain.h>
	26	#include <linux/irqchip/chained_irq.h>
	27	#include <linux/bitops.h>
	28	#include <linux/irq.h>
2eeb02b2	29	#include <linux/clk.h>
d3c68e0a	30
9e2aee80 RH	31	#include "../pci.h"
9e2aee80 RH	32
d3c68e0a LW	33	/*
	34	* Special configuration registers directly in the first few words
	35	* in I/O space.
	36	*/
	37	#define PCI_IOSIZE 0x00
	38	#define PCI_PROT 0x04 /* AHB protection */
	39	#define PCI_CTRL 0x08 /* PCI control signal */
	40	#define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
	41	#define PCI_CONFIG 0x28 /* PCI configuration command register */
	42	#define PCI_DATA 0x2C
	43
2eeb02b2	44	#define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
d3c68e0a LW	45	#define FARADAY_PCI_PMC 0x40 /* Power management control */
	46	#define FARADAY_PCI_PMCSR 0x44 /* Power management status */
	47	#define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
	48	#define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
	49	#define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
	50	#define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
	51	#define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
	52
2eeb02b2 LW	53	#define PCI_STATUS_66MHZ_CAPABLE BIT(21)
2eeb02b2 LW	54
d3c68e0a LW	55	/* Bits 31..28 gives INTD..INTA status */
	56	#define PCI_CTRL2_INTSTS_SHIFT 28
	57	#define PCI_CTRL2_INTMASK_CMDERR BIT(27)
	58	#define PCI_CTRL2_INTMASK_PARERR BIT(26)
	59	/* Bits 25..22 masks INTD..INTA */
	60	#define PCI_CTRL2_INTMASK_SHIFT 22
	61	#define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
	62	#define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
	63	#define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
	64	#define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
	65	#define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
	66	#define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
	67	/* Bit 15 reserved */
	68	#define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
	69	#define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
	70	#define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
	71	#define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
	72	#define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
	73	#define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
	74	#define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
	75	/* Bits 7..4 reserved */
	76	/* Bits 3..0 TRDYW */
	77
	78	/*
	79	* Memory configs:
	80	* Bit 31..20 defines the PCI side memory base
	81	* Bit 19..16 (4 bits) defines the size per below
	82	*/
	83	#define FARADAY_PCI_MEMBASE_MASK 0xfff00000
	84	#define FARADAY_PCI_MEMSIZE_1MB 0x0
	85	#define FARADAY_PCI_MEMSIZE_2MB 0x1
	86	#define FARADAY_PCI_MEMSIZE_4MB 0x2
	87	#define FARADAY_PCI_MEMSIZE_8MB 0x3
	88	#define FARADAY_PCI_MEMSIZE_16MB 0x4
	89	#define FARADAY_PCI_MEMSIZE_32MB 0x5
	90	#define FARADAY_PCI_MEMSIZE_64MB 0x6
	91	#define FARADAY_PCI_MEMSIZE_128MB 0x7
	92	#define FARADAY_PCI_MEMSIZE_256MB 0x8
	93	#define FARADAY_PCI_MEMSIZE_512MB 0x9
	94	#define FARADAY_PCI_MEMSIZE_1GB 0xa
	95	#define FARADAY_PCI_MEMSIZE_2GB 0xb
	96	#define FARADAY_PCI_MEMSIZE_SHIFT 16
	97
	98	/*
	99	* The DMA base is set to 0x0 for all memory segments, it reflects the
	100	* fact that the memory of the host system starts at 0x0.
	101	*/
	102	#define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
	103	#define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
	104	#define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
	105
	106	/* Defines for PCI configuration command register */
	107	#define PCI_CONF_ENABLE BIT(31)
	108	#define PCI_CONF_WHERE(r) ((r) & 0xFC)
	109	#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
	110	#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
	111	#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
	112
	113	/**
	114	* struct faraday_pci_variant - encodes IP block differences
	115	* @cascaded_irq: this host has cascaded IRQs from an interrupt controller
	116	* embedded in the host bridge.
	117	*/
	118	struct faraday_pci_variant {
119	bool cascaded_irq;
120	};
121
122	struct faraday_pci {
123	struct device *dev;
124	void __iomem *base;
125	struct irq_domain *irqdomain;
126	struct pci_bus *bus;
2eeb02b2	127	struct clk *bus_clk;
d3c68e0a LW	128	};
	129
	130	static int faraday_res_to_memcfg(resource_size_t mem_base,
	131	resource_size_t mem_size, u32 *val)
	132	{
	133	u32 outval;
	134
	135	switch (mem_size) {
	136	case SZ_1M:
	137	outval = FARADAY_PCI_MEMSIZE_1MB;
	138	break;
	139	case SZ_2M:
	140	outval = FARADAY_PCI_MEMSIZE_2MB;
	141	break;
	142	case SZ_4M:
	143	outval = FARADAY_PCI_MEMSIZE_4MB;
	144	break;
	145	case SZ_8M:
	146	outval = FARADAY_PCI_MEMSIZE_8MB;
	147	break;
	148	case SZ_16M:
	149	outval = FARADAY_PCI_MEMSIZE_16MB;
	150	break;
	151	case SZ_32M:
	152	outval = FARADAY_PCI_MEMSIZE_32MB;
	153	break;
	154	case SZ_64M:
	155	outval = FARADAY_PCI_MEMSIZE_64MB;
	156	break;
	157	case SZ_128M:
	158	outval = FARADAY_PCI_MEMSIZE_128MB;
	159	break;
	160	case SZ_256M:
	161	outval = FARADAY_PCI_MEMSIZE_256MB;
	162	break;
	163	case SZ_512M:
	164	outval = FARADAY_PCI_MEMSIZE_512MB;
	165	break;
	166	case SZ_1G:
	167	outval = FARADAY_PCI_MEMSIZE_1GB;
	168	break;
	169	case SZ_2G:
	170	outval = FARADAY_PCI_MEMSIZE_2GB;
	171	break;
	172	default:
	173	return -EINVAL;
	174	}
	175	outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
	176
	177	/* This is probably not good */
	178	if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
	179	pr_warn("truncated PCI memory base\n");
	180	/* Translate to bridge side address space */
	181	outval \|= (mem_base & FARADAY_PCI_MEMBASE_MASK);
	182	pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
	183	&mem_base, &mem_size, outval);
	184
	185	*val = outval;
	186	return 0;
	187	}
	188
f1e8bd21 LP	189	static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
	190	unsigned int fn, int config, int size,
	191	u32 *value)
d3c68e0a	192	{
f1e8bd21	193	writel(PCI_CONF_BUS(bus_number) \|
d3c68e0a LW	194	PCI_CONF_DEVICE(PCI_SLOT(fn)) \|
	195	PCI_CONF_FUNCTION(PCI_FUNC(fn)) \|
	196	PCI_CONF_WHERE(config) \|
	197	PCI_CONF_ENABLE,
	198	p->base + PCI_CONFIG);
	199
	200	*value = readl(p->base + PCI_DATA);
	201
	202	if (size == 1)
	203	value = (value >> (8 * (config & 3))) & 0xFF;
	204	else if (size == 2)
	205	value = (value >> (8 * (config & 3))) & 0xFFFF;
	206
f1e8bd21 LP	207	return PCIBIOS_SUCCESSFUL;
	208	}
	209
	210	static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
	211	int config, int size, u32 *value)
	212	{
	213	struct faraday_pci *p = bus->sysdata;
	214
d3c68e0a LW	215	dev_dbg(&bus->dev,
	216	"[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
	217	PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
	218
f1e8bd21	219	return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
d3c68e0a LW	220	}
d3c68e0a LW	221
f1e8bd21 LP	222	static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
	223	unsigned int fn, int config, int size,
	224	u32 value)
d3c68e0a	225	{
d3c68e0a LW	226	int ret = PCIBIOS_SUCCESSFUL;
d3c68e0a LW	227
f1e8bd21	228	writel(PCI_CONF_BUS(bus_number) \|
d3c68e0a LW	229	PCI_CONF_DEVICE(PCI_SLOT(fn)) \|
	230	PCI_CONF_FUNCTION(PCI_FUNC(fn)) \|
	231	PCI_CONF_WHERE(config) \|
	232	PCI_CONF_ENABLE,
	233	p->base + PCI_CONFIG);
	234
	235	switch (size) {
	236	case 4:
	237	writel(value, p->base + PCI_DATA);
	238	break;
	239	case 2:
	240	writew(value, p->base + PCI_DATA + (config & 3));
	241	break;
	242	case 1:
	243	writeb(value, p->base + PCI_DATA + (config & 3));
	244	break;
	245	default:
	246	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	247	}
	248
	249	return ret;
	250	}
	251
f1e8bd21 LP	252	static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
	253	int config, int size, u32 value)
	254	{
	255	struct faraday_pci *p = bus->sysdata;
	256
	257	dev_dbg(&bus->dev,
	258	"[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
	259	PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
	260
	261	return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
	262	value);
	263	}
	264
d3c68e0a LW	265	static struct pci_ops faraday_pci_ops = {
	266	.read = faraday_pci_read_config,
	267	.write = faraday_pci_write_config,
	268	};
	269
	270	static void faraday_pci_ack_irq(struct irq_data *d)
	271	{
	272	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	273	unsigned int reg;
	274
f1e8bd21	275	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
d3c68e0a LW	276	reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
d3c68e0a LW	277	reg \|= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
f1e8bd21	278	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
d3c68e0a LW	279	}
	280
	281	static void faraday_pci_mask_irq(struct irq_data *d)
	282	{
	283	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	284	unsigned int reg;
	285
f1e8bd21	286	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
d3c68e0a LW	287	reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
d3c68e0a LW	288	\| BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
f1e8bd21	289	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
d3c68e0a LW	290	}
	291
	292	static void faraday_pci_unmask_irq(struct irq_data *d)
	293	{
	294	struct faraday_pci *p = irq_data_get_irq_chip_data(d);
	295	unsigned int reg;
	296
f1e8bd21	297	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
d3c68e0a LW	298	reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
d3c68e0a LW	299	reg \|= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
f1e8bd21	300	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
d3c68e0a LW	301	}
	302
	303	static void faraday_pci_irq_handler(struct irq_desc *desc)
	304	{
	305	struct faraday_pci *p = irq_desc_get_handler_data(desc);
	306	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	307	unsigned int irq_stat, reg, i;
	308
f1e8bd21	309	faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
d3c68e0a LW	310	irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
	311
	312	chained_irq_enter(irqchip, desc);
	313
	314	for (i = 0; i < 4; i++) {
	315	if ((irq_stat & BIT(i)) == 0)
	316	continue;
	317	generic_handle_irq(irq_find_mapping(p->irqdomain, i));
	318	}
	319
	320	chained_irq_exit(irqchip, desc);
	321	}
	322
	323	static struct irq_chip faraday_pci_irq_chip = {
	324	.name = "PCI",
	325	.irq_ack = faraday_pci_ack_irq,
	326	.irq_mask = faraday_pci_mask_irq,
	327	.irq_unmask = faraday_pci_unmask_irq,
	328	};
	329
	330	static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
	331	irq_hw_number_t hwirq)
	332	{
	333	irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
	334	irq_set_chip_data(irq, domain->host_data);
	335
	336	return 0;
	337	}
	338
	339	static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
	340	.map = faraday_pci_irq_map,
	341	};
	342
	343	static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
	344	{
	345	struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
	346	int irq;
	347	int i;
	348
	349	if (!intc) {
	350	dev_err(p->dev, "missing child interrupt-controller node\n");
	351	return -EINVAL;
	352	}
	353
	354	/* All PCI IRQs cascade off this one */
	355	irq = of_irq_get(intc, 0);
b9f27afb	356	if (irq <= 0) {
d3c68e0a	357	dev_err(p->dev, "failed to get parent IRQ\n");
3dc6ddfe	358	of_node_put(intc);
b9f27afb	359	return irq ?: -EINVAL;
d3c68e0a LW	360	}
d3c68e0a LW	361
341d3299	362	p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
d3c68e0a	363	&faraday_pci_irqdomain_ops, p);
3dc6ddfe	364	of_node_put(intc);
d3c68e0a LW	365	if (!p->irqdomain) {
	366	dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
	367	return -EINVAL;
	368	}
	369
	370	irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
	371
	372	for (i = 0; i < 4; i++)
	373	irq_create_mapping(p->irqdomain, i);
	374
	375	return 0;
	376	}
	377
d3c68e0a LW	378	static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
	379	struct device_node *np)
	380	{
	381	struct of_pci_range range;
	382	struct of_pci_range_parser parser;
	383	struct device *dev = p->dev;
	384	u32 confreg[3] = {
	385	FARADAY_PCI_MEM1_BASE_SIZE,
	386	FARADAY_PCI_MEM2_BASE_SIZE,
	387	FARADAY_PCI_MEM3_BASE_SIZE,
	388	};
	389	int i = 0;
	390	u32 val;
	391
1e61a57c	392	if (of_pci_dma_range_parser_init(&parser, np)) {
d3c68e0a LW	393	dev_err(dev, "missing dma-ranges property\n");
	394	return -EINVAL;
	395	}
	396
	397	/*
	398	* Get the dma-ranges from the device tree
	399	*/
	400	for_each_of_pci_range(&parser, &range) {
	401	u64 end = range.pci_addr + range.size - 1;
	402	int ret;
	403
	404	ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
	405	if (ret) {
	406	dev_err(dev,
	407	"DMA range %d: illegal MEM resource size\n", i);
	408	return -EINVAL;
	409	}
	410
	411	dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
	412	i + 1, range.pci_addr, end, val);
	413	if (i <= 2) {
f1e8bd21 LP	414	faraday_raw_pci_write_config(p, 0, 0, confreg[i],
f1e8bd21 LP	415	4, val);
d3c68e0a LW	416	} else {
	417	dev_err(dev, "ignore extraneous dma-range %d\n", i);
	418	break;
	419	}
	420
	421	i++;
	422	}
	423
	424	return 0;
	425	}
	426
	427	static int faraday_pci_probe(struct platform_device *pdev)
	428	{
	429	struct device *dev = &pdev->dev;
	430	const struct faraday_pci_variant *variant =
	431	of_device_get_match_data(dev);
	432	struct resource *regs;
	433	resource_size_t io_base;
	434	struct resource_entry *win;
	435	struct faraday_pci *p;
	436	struct resource *mem;
	437	struct resource *io;
	438	struct pci_host_bridge *host;
2eeb02b2 LW	439	struct clk *clk;
	440	unsigned char max_bus_speed = PCI_SPEED_33MHz;
	441	unsigned char cur_bus_speed = PCI_SPEED_33MHz;
d3c68e0a LW	442	int ret;
	443	u32 val;
	444	LIST_HEAD(res);
	445
9aa17a77	446	host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
d3c68e0a LW	447	if (!host)
	448	return -ENOMEM;
	449
	450	host->dev.parent = dev;
	451	host->ops = &faraday_pci_ops;
	452	host->busnr = 0;
	453	host->msi = NULL;
f7c2e69b LP	454	host->map_irq = of_irq_parse_and_map_pci;
f7c2e69b LP	455	host->swizzle_irq = pci_common_swizzle;
d3c68e0a LW	456	p = pci_host_bridge_priv(host);
	457	host->sysdata = p;
	458	p->dev = dev;
	459
2eeb02b2 LW	460	/* Retrieve and enable optional clocks */
	461	clk = devm_clk_get(dev, "PCLK");
	462	if (IS_ERR(clk))
	463	return PTR_ERR(clk);
	464	ret = clk_prepare_enable(clk);
	465	if (ret) {
	466	dev_err(dev, "could not prepare PCLK\n");
	467	return ret;
	468	}
	469	p->bus_clk = devm_clk_get(dev, "PCICLK");
	470	if (IS_ERR(p->bus_clk))
b3c433ef	471	return PTR_ERR(p->bus_clk);
2eeb02b2 LW	472	ret = clk_prepare_enable(p->bus_clk);
	473	if (ret) {
	474	dev_err(dev, "could not prepare PCICLK\n");
	475	return ret;
	476	}
	477
d3c68e0a LW	478	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	479	p->base = devm_ioremap_resource(dev, regs);
	480	if (IS_ERR(p->base))
	481	return PTR_ERR(p->base);
	482
5bd51b35	483	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
055f87a2	484	&res, &io_base);
d3c68e0a LW	485	if (ret)
	486	return ret;
	487
	488	ret = devm_request_pci_bus_resources(dev, &res);
	489	if (ret)
	490	return ret;
	491
	492	/* Get the I/O and memory ranges from DT */
	493	resource_list_for_each_entry(win, &res) {
	494	switch (resource_type(win->res)) {
	495	case IORESOURCE_IO:
	496	io = win->res;
	497	io->name = "Gemini PCI I/O";
	498	if (!faraday_res_to_memcfg(io->start - win->offset,
	499	resource_size(io), &val)) {
	500	/* setup I/O space size */
	501	writel(val, p->base + PCI_IOSIZE);
	502	} else {
	503	dev_err(dev, "illegal IO mem size\n");
	504	return -EINVAL;
	505	}
e3060945	506	ret = devm_pci_remap_iospace(dev, io, io_base);
d3c68e0a LW	507	if (ret) {
	508	dev_warn(dev, "error %d: failed to map resource %pR\n",
	509	ret, io);
	510	continue;
	511	}
	512	break;
	513	case IORESOURCE_MEM:
	514	mem = win->res;
	515	mem->name = "Gemini PCI MEM";
	516	break;
	517	case IORESOURCE_BUS:
	518	break;
	519	default:
	520	break;
	521	}
	522	}
	523
	524	/* Setup hostbridge */
	525	val = readl(p->base + PCI_CTRL);
	526	val \|= PCI_COMMAND_IO;
	527	val \|= PCI_COMMAND_MEMORY;
	528	val \|= PCI_COMMAND_MASTER;
	529	writel(val, p->base + PCI_CTRL);
d3c68e0a	530	/* Mask and clear all interrupts */
f1e8bd21	531	faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
d3c68e0a LW	532	if (variant->cascaded_irq) {
	533	ret = faraday_pci_setup_cascaded_irq(p);
	534	if (ret) {
	535	dev_err(dev, "failed to setup cascaded IRQ\n");
	536	return ret;
	537	}
	538	}
	539
2eeb02b2 LW	540	/* Check bus clock if we can gear up to 66 MHz */
	541	if (!IS_ERR(p->bus_clk)) {
	542	unsigned long rate;
	543	u32 val;
	544
	545	faraday_raw_pci_read_config(p, 0, 0,
	546	FARADAY_PCI_STATUS_CMD, 4, &val);
	547	rate = clk_get_rate(p->bus_clk);
	548
	549	if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
	550	dev_info(dev, "33MHz bus is 66MHz capable\n");
	551	max_bus_speed = PCI_SPEED_66MHz;
	552	ret = clk_set_rate(p->bus_clk, 66000000);
	553	if (ret)
	554	dev_err(dev, "failed to set bus clock\n");
	555	} else {
	556	dev_info(dev, "33MHz only bus\n");
	557	max_bus_speed = PCI_SPEED_33MHz;
	558	}
	559
	560	/* Bumping the clock may fail so read back the rate */
	561	rate = clk_get_rate(p->bus_clk);
	562	if (rate == 33000000)
	563	cur_bus_speed = PCI_SPEED_33MHz;
	564	if (rate == 66000000)
	565	cur_bus_speed = PCI_SPEED_66MHz;
	566	}
	567
d3c68e0a LW	568	ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
	569	if (ret)
	570	return ret;
	571
f1e8bd21	572	list_splice_init(&res, &host->windows);
cea9bc0b	573	ret = pci_scan_root_bus_bridge(host);
f1e8bd21	574	if (ret) {
cea9bc0b	575	dev_err(dev, "failed to scan host: %d\n", ret);
f1e8bd21 LP	576	return ret;
	577	}
	578	p->bus = host->bus;
2eeb02b2 LW	579	p->bus->max_bus_speed = max_bus_speed;
2eeb02b2 LW	580	p->bus->cur_bus_speed = cur_bus_speed;
f1e8bd21	581
d3c68e0a LW	582	pci_bus_assign_resources(p->bus);
	583	pci_bus_add_devices(p->bus);
	584	pci_free_resource_list(&res);
	585
	586	return 0;
	587	}
	588
	589	/*
	590	* We encode bridge variants here, we have at least two so it doesn't
	591	* hurt to have infrastructure to encompass future variants as well.
	592	*/
492d98e4	593	static const struct faraday_pci_variant faraday_regular = {
d3c68e0a LW	594	.cascaded_irq = true,
	595	};
	596
492d98e4	597	static const struct faraday_pci_variant faraday_dual = {
d3c68e0a LW	598	.cascaded_irq = false,
	599	};
	600
	601	static const struct of_device_id faraday_pci_of_match[] = {
	602	{
	603	.compatible = "faraday,ftpci100",
	604	.data = &faraday_regular,
	605	},
	606	{
	607	.compatible = "faraday,ftpci100-dual",
	608	.data = &faraday_dual,
	609	},
	610	{},
	611	};
	612
	613	static struct platform_driver faraday_pci_driver = {
	614	.driver = {
	615	.name = "ftpci100",
	616	.of_match_table = of_match_ptr(faraday_pci_of_match),
a5f40e80	617	.suppress_bind_attrs = true,
d3c68e0a LW	618	},
	619	.probe = faraday_pci_probe,
	620	};
	621	builtin_platform_driver(faraday_pci_driver);