Commit | Line | Data |
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8cfab3cf | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
4b1ced84 | 2 | /* |
96291d56 | 3 | * Synopsys DesignWare PCIe host controller driver |
4b1ced84 JH |
4 | * |
5 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * | |
8 | * Author: Jingoo Han <jg1.han@samsung.com> | |
4b1ced84 JH |
9 | */ |
10 | ||
18edf451 SJ |
11 | #ifndef _PCIE_DESIGNWARE_H |
12 | #define _PCIE_DESIGNWARE_H | |
13 | ||
a991f748 | 14 | #include <linux/bitfield.h> |
111111a7 | 15 | #include <linux/dma-mapping.h> |
feb85d9b KVA |
16 | #include <linux/irq.h> |
17 | #include <linux/msi.h> | |
18 | #include <linux/pci.h> | |
19 | ||
f8aed6ec KVA |
20 | #include <linux/pci-epc.h> |
21 | #include <linux/pci-epf.h> | |
22 | ||
b90dc392 KVA |
23 | /* Parameters for the waiting for link up routine */ |
24 | #define LINK_WAIT_MAX_RETRIES 10 | |
25 | #define LINK_WAIT_USLEEP_MIN 90000 | |
26 | #define LINK_WAIT_USLEEP_MAX 100000 | |
27 | ||
28 | /* Parameters for the waiting for iATU enabled routine */ | |
29 | #define LINK_WAIT_MAX_IATU_RETRIES 5 | |
9024143e | 30 | #define LINK_WAIT_IATU 9 |
b90dc392 KVA |
31 | |
32 | /* Synopsys-specific PCIe configuration registers */ | |
33 | #define PCIE_PORT_LINK_CONTROL 0x710 | |
a991f748 AS |
34 | #define PORT_LINK_MODE_MASK GENMASK(21, 16) |
35 | #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) | |
36 | #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) | |
37 | #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) | |
38 | #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) | |
39 | #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) | |
b90dc392 | 40 | |
23fe5bd4 KVA |
41 | #define PCIE_PORT_DEBUG0 0x728 |
42 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f | |
43 | #define PORT_LOGIC_LTSSM_STATE_L0 0x11 | |
44 | ||
b90dc392 | 45 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
0e11faa4 | 46 | #define PORT_LOGIC_SPEED_CHANGE BIT(17) |
a991f748 AS |
47 | #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) |
48 | #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) | |
49 | #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) | |
50 | #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) | |
51 | #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) | |
52 | #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) | |
b90dc392 KVA |
53 | |
54 | #define PCIE_MSI_ADDR_LO 0x820 | |
55 | #define PCIE_MSI_ADDR_HI 0x824 | |
56 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
57 | #define PCIE_MSI_INTR0_MASK 0x82C | |
58 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
59 | ||
60 | #define PCIE_ATU_VIEWPORT 0x900 | |
0e11faa4 AS |
61 | #define PCIE_ATU_REGION_INBOUND BIT(31) |
62 | #define PCIE_ATU_REGION_OUTBOUND 0 | |
44ddb77b AS |
63 | #define PCIE_ATU_REGION_INDEX2 0x2 |
64 | #define PCIE_ATU_REGION_INDEX1 0x1 | |
65 | #define PCIE_ATU_REGION_INDEX0 0x0 | |
b90dc392 | 66 | #define PCIE_ATU_CR1 0x904 |
44ddb77b AS |
67 | #define PCIE_ATU_TYPE_MEM 0x0 |
68 | #define PCIE_ATU_TYPE_IO 0x2 | |
69 | #define PCIE_ATU_TYPE_CFG0 0x4 | |
70 | #define PCIE_ATU_TYPE_CFG1 0x5 | |
b90dc392 | 71 | #define PCIE_ATU_CR2 0x908 |
0e11faa4 AS |
72 | #define PCIE_ATU_ENABLE BIT(31) |
73 | #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) | |
b90dc392 KVA |
74 | #define PCIE_ATU_LOWER_BASE 0x90C |
75 | #define PCIE_ATU_UPPER_BASE 0x910 | |
76 | #define PCIE_ATU_LIMIT 0x914 | |
77 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
a991f748 AS |
78 | #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) |
79 | #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) | |
80 | #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) | |
b90dc392 KVA |
81 | #define PCIE_ATU_UPPER_TARGET 0x91C |
82 | ||
e44abfed | 83 | #define PCIE_MISC_CONTROL_1_OFF 0x8BC |
0e11faa4 | 84 | #define PCIE_DBI_RO_WR_EN BIT(0) |
e44abfed | 85 | |
b90dc392 KVA |
86 | /* |
87 | * iATU Unroll-specific register definitions | |
88 | * From 4.80 core version the address translation will be made by unroll | |
89 | */ | |
90 | #define PCIE_ATU_UNR_REGION_CTRL1 0x00 | |
91 | #define PCIE_ATU_UNR_REGION_CTRL2 0x04 | |
92 | #define PCIE_ATU_UNR_LOWER_BASE 0x08 | |
93 | #define PCIE_ATU_UNR_UPPER_BASE 0x0C | |
94 | #define PCIE_ATU_UNR_LIMIT 0x10 | |
95 | #define PCIE_ATU_UNR_LOWER_TARGET 0x14 | |
96 | #define PCIE_ATU_UNR_UPPER_TARGET 0x18 | |
97 | ||
6d6b05e3 SW |
98 | /* |
99 | * The default address offset between dbi_base and atu_base. Root controller | |
100 | * drivers are not required to initialize atu_base if the offset matches this | |
101 | * default; the driver core automatically derives atu_base from dbi_base using | |
102 | * this offset, if atu_base not set. | |
103 | */ | |
104 | #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20) | |
105 | ||
b90dc392 | 106 | /* Register address builder */ |
6d6b05e3 SW |
107 | #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ |
108 | ((region) << 9) | |
b90dc392 | 109 | |
6d6b05e3 | 110 | #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ |
0e11faa4 | 111 | (((region) << 9) | BIT(8)) |
f8aed6ec | 112 | |
1f319cb0 GP |
113 | #define MAX_MSI_IRQS 256 |
114 | #define MAX_MSI_IRQS_PER_CTRL 32 | |
115 | #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) | |
76cbf066 | 116 | #define MSI_REG_CTRL_BLOCK_SIZE 12 |
7c5925af | 117 | #define MSI_DEF_NUM_VECTORS 32 |
f342d940 | 118 | |
ad4a5bec NC |
119 | /* Maximum number of inbound/outbound iATUs */ |
120 | #define MAX_IATU_IN 256 | |
121 | #define MAX_IATU_OUT 256 | |
122 | ||
442ec4c0 KVA |
123 | struct pcie_port; |
124 | struct dw_pcie; | |
f8aed6ec KVA |
125 | struct dw_pcie_ep; |
126 | ||
127 | enum dw_pcie_region_type { | |
128 | DW_PCIE_REGION_UNKNOWN, | |
129 | DW_PCIE_REGION_INBOUND, | |
130 | DW_PCIE_REGION_OUTBOUND, | |
131 | }; | |
442ec4c0 | 132 | |
608793e2 KVA |
133 | enum dw_pcie_device_mode { |
134 | DW_PCIE_UNKNOWN_TYPE, | |
135 | DW_PCIE_EP_TYPE, | |
136 | DW_PCIE_LEG_EP_TYPE, | |
137 | DW_PCIE_RC_TYPE, | |
138 | }; | |
139 | ||
442ec4c0 KVA |
140 | struct dw_pcie_host_ops { |
141 | int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); | |
142 | int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); | |
143 | int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, | |
144 | unsigned int devfn, int where, int size, u32 *val); | |
145 | int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, | |
146 | unsigned int devfn, int where, int size, u32 val); | |
4a301766 | 147 | int (*host_init)(struct pcie_port *pp); |
442ec4c0 | 148 | void (*scan_bus)(struct pcie_port *pp); |
7c5925af | 149 | void (*set_num_vectors)(struct pcie_port *pp); |
3f43ccc4 | 150 | int (*msi_host_init)(struct pcie_port *pp); |
442ec4c0 KVA |
151 | }; |
152 | ||
4b1ced84 | 153 | struct pcie_port { |
4b1ced84 | 154 | u8 root_bus_nr; |
4b1ced84 JH |
155 | u64 cfg0_base; |
156 | void __iomem *va_cfg0_base; | |
adf70fc0 | 157 | u32 cfg0_size; |
4b1ced84 JH |
158 | u64 cfg1_base; |
159 | void __iomem *va_cfg1_base; | |
adf70fc0 | 160 | u32 cfg1_size; |
0021d22b | 161 | resource_size_t io_base; |
adf70fc0 PA |
162 | phys_addr_t io_bus_addr; |
163 | u32 io_size; | |
4b1ced84 | 164 | u64 mem_base; |
adf70fc0 PA |
165 | phys_addr_t mem_bus_addr; |
166 | u32 mem_size; | |
0021d22b ZW |
167 | struct resource *cfg; |
168 | struct resource *io; | |
169 | struct resource *mem; | |
170 | struct resource *busn; | |
4b1ced84 | 171 | int irq; |
4ab2e7c0 | 172 | const struct dw_pcie_host_ops *ops; |
f342d940 | 173 | int msi_irq; |
904d0e78 | 174 | struct irq_domain *irq_domain; |
7c5925af | 175 | struct irq_domain *msi_domain; |
111111a7 | 176 | dma_addr_t msi_data; |
9f67437b | 177 | struct irq_chip *msi_irq_chip; |
7c5925af | 178 | u32 num_vectors; |
a348d015 | 179 | u32 irq_mask[MAX_MSI_CTRLS]; |
7c5925af | 180 | raw_spinlock_t lock; |
f342d940 | 181 | DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); |
4b1ced84 JH |
182 | }; |
183 | ||
f8aed6ec KVA |
184 | enum dw_pcie_as_type { |
185 | DW_PCIE_AS_UNKNOWN, | |
186 | DW_PCIE_AS_MEM, | |
187 | DW_PCIE_AS_IO, | |
188 | }; | |
189 | ||
190 | struct dw_pcie_ep_ops { | |
191 | void (*ep_init)(struct dw_pcie_ep *ep); | |
16093362 | 192 | int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, |
d3c70a98 | 193 | enum pci_epc_irq_type type, u16 interrupt_num); |
fee35cb7 | 194 | const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); |
f8aed6ec KVA |
195 | }; |
196 | ||
197 | struct dw_pcie_ep { | |
198 | struct pci_epc *epc; | |
199 | struct dw_pcie_ep_ops *ops; | |
200 | phys_addr_t phys_base; | |
201 | size_t addr_size; | |
a937fe08 | 202 | size_t page_size; |
f8aed6ec KVA |
203 | u8 bar_to_atu[6]; |
204 | phys_addr_t *outbound_addr; | |
ad4a5bec NC |
205 | unsigned long *ib_window_map; |
206 | unsigned long *ob_window_map; | |
f8aed6ec KVA |
207 | u32 num_ib_windows; |
208 | u32 num_ob_windows; | |
2fd0c9d9 NC |
209 | void __iomem *msi_mem; |
210 | phys_addr_t msi_mem_phys; | |
beb4641a GP |
211 | u8 msi_cap; /* MSI capability offset */ |
212 | u8 msix_cap; /* MSI-X capability offset */ | |
f8aed6ec KVA |
213 | }; |
214 | ||
442ec4c0 | 215 | struct dw_pcie_ops { |
b6900aeb | 216 | u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr); |
a509d7d9 KVA |
217 | u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, |
218 | size_t size); | |
219 | void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, | |
220 | size_t size, u32 val); | |
442ec4c0 | 221 | int (*link_up)(struct dw_pcie *pcie); |
f8aed6ec KVA |
222 | int (*start_link)(struct dw_pcie *pcie); |
223 | void (*stop_link)(struct dw_pcie *pcie); | |
4b1ced84 JH |
224 | }; |
225 | ||
442ec4c0 KVA |
226 | struct dw_pcie { |
227 | struct device *dev; | |
228 | void __iomem *dbi_base; | |
f8aed6ec | 229 | void __iomem *dbi_base2; |
6d6b05e3 SW |
230 | /* Used when iatu_unroll_enabled is true */ |
231 | void __iomem *atu_base; | |
442ec4c0 KVA |
232 | u32 num_viewport; |
233 | u8 iatu_unroll_enabled; | |
234 | struct pcie_port pp; | |
f8aed6ec | 235 | struct dw_pcie_ep ep; |
442ec4c0 | 236 | const struct dw_pcie_ops *ops; |
2aadcb0c | 237 | unsigned int version; |
442ec4c0 KVA |
238 | }; |
239 | ||
240 | #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) | |
241 | ||
f8aed6ec KVA |
242 | #define to_dw_pcie_from_ep(endpoint) \ |
243 | container_of((endpoint), struct dw_pcie, ep) | |
244 | ||
19ce01cc KVA |
245 | int dw_pcie_read(void __iomem *addr, int size, u32 *val); |
246 | int dw_pcie_write(void __iomem *addr, int size, u32 val); | |
18edf451 | 247 | |
a509d7d9 KVA |
248 | u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, |
249 | size_t size); | |
250 | void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, | |
251 | size_t size, u32 val); | |
442ec4c0 KVA |
252 | int dw_pcie_link_up(struct dw_pcie *pci); |
253 | int dw_pcie_wait_for_link(struct dw_pcie *pci); | |
feb85d9b KVA |
254 | void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, |
255 | int type, u64 cpu_addr, u64 pci_addr, | |
256 | u32 size); | |
f8aed6ec KVA |
257 | int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, |
258 | u64 cpu_addr, enum dw_pcie_as_type as_type); | |
259 | void dw_pcie_disable_atu(struct dw_pcie *pci, int index, | |
260 | enum dw_pcie_region_type type); | |
feb85d9b | 261 | void dw_pcie_setup(struct dw_pcie *pci); |
a0560209 | 262 | |
b50b2db2 KVA |
263 | static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) |
264 | { | |
a509d7d9 | 265 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); |
b50b2db2 KVA |
266 | } |
267 | ||
268 | static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) | |
269 | { | |
a509d7d9 | 270 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); |
b50b2db2 KVA |
271 | } |
272 | ||
f8aed6ec KVA |
273 | static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) |
274 | { | |
275 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); | |
276 | } | |
277 | ||
278 | static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) | |
279 | { | |
280 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); | |
281 | } | |
282 | ||
283 | static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) | |
284 | { | |
285 | __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); | |
286 | } | |
287 | ||
288 | static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) | |
289 | { | |
290 | return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); | |
291 | } | |
292 | ||
293 | static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) | |
294 | { | |
295 | __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); | |
296 | } | |
297 | ||
298 | static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) | |
299 | { | |
300 | return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); | |
301 | } | |
302 | ||
6d6b05e3 SW |
303 | static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) |
304 | { | |
305 | __dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val); | |
306 | } | |
307 | ||
308 | static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) | |
309 | { | |
310 | return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4); | |
311 | } | |
312 | ||
e44abfed HZ |
313 | static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) |
314 | { | |
315 | u32 reg; | |
316 | u32 val; | |
317 | ||
318 | reg = PCIE_MISC_CONTROL_1_OFF; | |
319 | val = dw_pcie_readl_dbi(pci, reg); | |
320 | val |= PCIE_DBI_RO_WR_EN; | |
321 | dw_pcie_writel_dbi(pci, reg, val); | |
322 | } | |
323 | ||
324 | static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) | |
325 | { | |
326 | u32 reg; | |
327 | u32 val; | |
328 | ||
329 | reg = PCIE_MISC_CONTROL_1_OFF; | |
330 | val = dw_pcie_readl_dbi(pci, reg); | |
331 | val &= ~PCIE_DBI_RO_WR_EN; | |
332 | dw_pcie_writel_dbi(pci, reg, val); | |
333 | } | |
334 | ||
a0560209 KVA |
335 | #ifdef CONFIG_PCIE_DW_HOST |
336 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); | |
337 | void dw_pcie_msi_init(struct pcie_port *pp); | |
7c5925af | 338 | void dw_pcie_free_msi(struct pcie_port *pp); |
a0560209 KVA |
339 | void dw_pcie_setup_rc(struct pcie_port *pp); |
340 | int dw_pcie_host_init(struct pcie_port *pp); | |
7c5925af | 341 | int dw_pcie_allocate_domains(struct pcie_port *pp); |
a0560209 KVA |
342 | #else |
343 | static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) | |
344 | { | |
345 | return IRQ_NONE; | |
346 | } | |
347 | ||
348 | static inline void dw_pcie_msi_init(struct pcie_port *pp) | |
349 | { | |
350 | } | |
351 | ||
7c5925af GP |
352 | static inline void dw_pcie_free_msi(struct pcie_port *pp) |
353 | { | |
354 | } | |
355 | ||
a0560209 KVA |
356 | static inline void dw_pcie_setup_rc(struct pcie_port *pp) |
357 | { | |
358 | } | |
359 | ||
360 | static inline int dw_pcie_host_init(struct pcie_port *pp) | |
361 | { | |
362 | return 0; | |
363 | } | |
7c5925af GP |
364 | |
365 | static inline int dw_pcie_allocate_domains(struct pcie_port *pp) | |
366 | { | |
367 | return 0; | |
368 | } | |
a0560209 | 369 | #endif |
f8aed6ec KVA |
370 | |
371 | #ifdef CONFIG_PCIE_DW_EP | |
372 | void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); | |
373 | int dw_pcie_ep_init(struct dw_pcie_ep *ep); | |
374 | void dw_pcie_ep_exit(struct dw_pcie_ep *ep); | |
cb22d40b | 375 | int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); |
16093362 BH |
376 | int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
377 | u8 interrupt_num); | |
beb4641a GP |
378 | int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
379 | u16 interrupt_num); | |
9e718119 | 380 | void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); |
f8aed6ec KVA |
381 | #else |
382 | static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) | |
383 | { | |
384 | } | |
385 | ||
386 | static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) | |
387 | { | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) | |
392 | { | |
393 | } | |
9e718119 | 394 | |
cb22d40b GP |
395 | static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) |
396 | { | |
397 | return 0; | |
398 | } | |
399 | ||
16093362 | 400 | static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
6f6d7873 NC |
401 | u8 interrupt_num) |
402 | { | |
403 | return 0; | |
404 | } | |
405 | ||
beb4641a GP |
406 | static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
407 | u16 interrupt_num) | |
408 | { | |
409 | return 0; | |
410 | } | |
411 | ||
9e718119 NC |
412 | static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) |
413 | { | |
414 | } | |
f8aed6ec | 415 | #endif |
18edf451 | 416 | #endif /* _PCIE_DESIGNWARE_H */ |