Commit | Line | Data |
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8cfab3cf | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
4b1ced84 | 2 | /* |
96291d56 | 3 | * Synopsys DesignWare PCIe host controller driver |
4b1ced84 JH |
4 | * |
5 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
7ecd4a81 | 6 | * https://www.samsung.com |
4b1ced84 JH |
7 | * |
8 | * Author: Jingoo Han <jg1.han@samsung.com> | |
4b1ced84 JH |
9 | */ |
10 | ||
18edf451 SJ |
11 | #ifndef _PCIE_DESIGNWARE_H |
12 | #define _PCIE_DESIGNWARE_H | |
13 | ||
a991f748 | 14 | #include <linux/bitfield.h> |
111111a7 | 15 | #include <linux/dma-mapping.h> |
feb85d9b KVA |
16 | #include <linux/irq.h> |
17 | #include <linux/msi.h> | |
18 | #include <linux/pci.h> | |
19 | ||
f8aed6ec KVA |
20 | #include <linux/pci-epc.h> |
21 | #include <linux/pci-epf.h> | |
22 | ||
afe1c6d5 SS |
23 | /* DWC PCIe IP-core versions (native support since v4.70a) */ |
24 | #define DW_PCIE_VER_365A 0x3336352a | |
25 | #define DW_PCIE_VER_460A 0x3436302a | |
26 | #define DW_PCIE_VER_470A 0x3437302a | |
27 | #define DW_PCIE_VER_480A 0x3438302a | |
28 | #define DW_PCIE_VER_490A 0x3439302a | |
29 | #define DW_PCIE_VER_520A 0x3532302a | |
30 | ||
0b0a780d SS |
31 | #define __dw_pcie_ver_cmp(_pci, _ver, _op) \ |
32 | ((_pci)->version _op DW_PCIE_VER_ ## _ver) | |
33 | ||
34 | #define dw_pcie_ver_is(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, ==) | |
35 | ||
36 | #define dw_pcie_ver_is_ge(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, >=) | |
37 | ||
38 | #define dw_pcie_ver_type_is(_pci, _ver, _type) \ | |
39 | (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ | |
40 | __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, ==)) | |
41 | ||
42 | #define dw_pcie_ver_type_is_ge(_pci, _ver, _type) \ | |
43 | (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ | |
44 | __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=)) | |
45 | ||
b90dc392 KVA |
46 | /* Parameters for the waiting for link up routine */ |
47 | #define LINK_WAIT_MAX_RETRIES 10 | |
48 | #define LINK_WAIT_USLEEP_MIN 90000 | |
49 | #define LINK_WAIT_USLEEP_MAX 100000 | |
50 | ||
51 | /* Parameters for the waiting for iATU enabled routine */ | |
52 | #define LINK_WAIT_MAX_IATU_RETRIES 5 | |
9024143e | 53 | #define LINK_WAIT_IATU 9 |
b90dc392 KVA |
54 | |
55 | /* Synopsys-specific PCIe configuration registers */ | |
ed22aaae DK |
56 | #define PCIE_PORT_AFR 0x70C |
57 | #define PORT_AFR_N_FTS_MASK GENMASK(15, 8) | |
84667a41 | 58 | #define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) |
ed22aaae | 59 | #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) |
aeaa0bfe | 60 | #define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n) |
84667a41 RH |
61 | #define PORT_AFR_ENTER_ASPM BIT(30) |
62 | #define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 | |
63 | #define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) | |
64 | #define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 | |
65 | #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) | |
ed22aaae | 66 | |
b90dc392 | 67 | #define PCIE_PORT_LINK_CONTROL 0x710 |
ed22aaae | 68 | #define PORT_LINK_DLL_LINK_EN BIT(5) |
cff92444 | 69 | #define PORT_LINK_FAST_LINK_MODE BIT(7) |
a991f748 AS |
70 | #define PORT_LINK_MODE_MASK GENMASK(21, 16) |
71 | #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) | |
72 | #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) | |
73 | #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) | |
74 | #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) | |
75 | #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) | |
b90dc392 | 76 | |
23fe5bd4 KVA |
77 | #define PCIE_PORT_DEBUG0 0x728 |
78 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f | |
79 | #define PORT_LOGIC_LTSSM_STATE_L0 0x11 | |
60ef4b07 AS |
80 | #define PCIE_PORT_DEBUG1 0x72C |
81 | #define PCIE_PORT_DEBUG1_LINK_UP BIT(4) | |
82 | #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) | |
23fe5bd4 | 83 | |
b90dc392 | 84 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
ed22aaae | 85 | #define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0) |
0e11faa4 | 86 | #define PORT_LOGIC_SPEED_CHANGE BIT(17) |
a991f748 AS |
87 | #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) |
88 | #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) | |
89 | #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) | |
90 | #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) | |
91 | #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) | |
92 | #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) | |
b90dc392 KVA |
93 | |
94 | #define PCIE_MSI_ADDR_LO 0x820 | |
95 | #define PCIE_MSI_ADDR_HI 0x824 | |
96 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
97 | #define PCIE_MSI_INTR0_MASK 0x82C | |
98 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
99 | ||
ed22aaae DK |
100 | #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 |
101 | #define PORT_MLTI_UPCFG_SUPPORT BIT(7) | |
102 | ||
13e9d390 SS |
103 | #define PCIE_VERSION_NUMBER 0x8F8 |
104 | #define PCIE_VERSION_TYPE 0x8FC | |
105 | ||
5a163f59 SS |
106 | /* |
107 | * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each | |
108 | * iATU region CSRs had been indirectly accessible by means of the dedicated | |
109 | * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe | |
110 | * v4.80a in a way so the viewport was unrolled into the directly accessible | |
111 | * iATU/eDMA CSRs space. | |
112 | */ | |
b90dc392 | 113 | #define PCIE_ATU_VIEWPORT 0x900 |
38fe2723 SS |
114 | #define PCIE_ATU_REGION_DIR_IB BIT(31) |
115 | #define PCIE_ATU_REGION_DIR_OB 0 | |
5a163f59 SS |
116 | #define PCIE_ATU_VIEWPORT_BASE 0x904 |
117 | #define PCIE_ATU_UNROLL_BASE(dir, index) \ | |
118 | (((index) << 9) | ((dir == PCIE_ATU_REGION_DIR_IB) ? BIT(8) : 0)) | |
119 | #define PCIE_ATU_VIEWPORT_SIZE 0x2C | |
120 | #define PCIE_ATU_REGION_CTRL1 0x000 | |
74081de4 | 121 | #define PCIE_ATU_INCREASE_REGION_SIZE BIT(13) |
44ddb77b AS |
122 | #define PCIE_ATU_TYPE_MEM 0x0 |
123 | #define PCIE_ATU_TYPE_IO 0x2 | |
124 | #define PCIE_ATU_TYPE_CFG0 0x4 | |
125 | #define PCIE_ATU_TYPE_CFG1 0x5 | |
6104033b | 126 | #define PCIE_ATU_TD BIT(8) |
24ede430 | 127 | #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) |
5a163f59 | 128 | #define PCIE_ATU_REGION_CTRL2 0x004 |
0e11faa4 AS |
129 | #define PCIE_ATU_ENABLE BIT(31) |
130 | #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) | |
24ede430 | 131 | #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) |
5a163f59 SS |
132 | #define PCIE_ATU_LOWER_BASE 0x008 |
133 | #define PCIE_ATU_UPPER_BASE 0x00C | |
134 | #define PCIE_ATU_LIMIT 0x010 | |
135 | #define PCIE_ATU_LOWER_TARGET 0x014 | |
a991f748 AS |
136 | #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) |
137 | #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) | |
138 | #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) | |
5a163f59 SS |
139 | #define PCIE_ATU_UPPER_TARGET 0x018 |
140 | #define PCIE_ATU_UPPER_LIMIT 0x020 | |
b90dc392 | 141 | |
e44abfed | 142 | #define PCIE_MISC_CONTROL_1_OFF 0x8BC |
0e11faa4 | 143 | #define PCIE_DBI_RO_WR_EN BIT(0) |
e44abfed | 144 | |
2f7f7001 XB |
145 | #define PCIE_MSIX_DOORBELL 0x948 |
146 | #define PCIE_MSIX_DOORBELL_PF_SHIFT 24 | |
147 | ||
07f123de VS |
148 | #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 |
149 | #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) | |
150 | #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) | |
151 | #define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16) | |
152 | #define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) | |
153 | #define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) | |
154 | ||
155 | #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 | |
156 | ||
6d6b05e3 SW |
157 | /* |
158 | * The default address offset between dbi_base and atu_base. Root controller | |
159 | * drivers are not required to initialize atu_base if the offset matches this | |
160 | * default; the driver core automatically derives atu_base from dbi_base using | |
161 | * this offset, if atu_base not set. | |
162 | */ | |
163 | #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20) | |
164 | ||
1f319cb0 GP |
165 | #define MAX_MSI_IRQS 256 |
166 | #define MAX_MSI_IRQS_PER_CTRL 32 | |
167 | #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) | |
76cbf066 | 168 | #define MSI_REG_CTRL_BLOCK_SIZE 12 |
7c5925af | 169 | #define MSI_DEF_NUM_VECTORS 32 |
f342d940 | 170 | |
ad4a5bec NC |
171 | /* Maximum number of inbound/outbound iATUs */ |
172 | #define MAX_IATU_IN 256 | |
173 | #define MAX_IATU_OUT 256 | |
174 | ||
442ec4c0 | 175 | struct dw_pcie; |
60b3c27f | 176 | struct dw_pcie_rp; |
f8aed6ec KVA |
177 | struct dw_pcie_ep; |
178 | ||
608793e2 KVA |
179 | enum dw_pcie_device_mode { |
180 | DW_PCIE_UNKNOWN_TYPE, | |
181 | DW_PCIE_EP_TYPE, | |
182 | DW_PCIE_LEG_EP_TYPE, | |
183 | DW_PCIE_RC_TYPE, | |
184 | }; | |
185 | ||
442ec4c0 | 186 | struct dw_pcie_host_ops { |
60b3c27f | 187 | int (*host_init)(struct dw_pcie_rp *pp); |
c6481d51 | 188 | void (*host_deinit)(struct dw_pcie_rp *pp); |
60b3c27f | 189 | int (*msi_host_init)(struct dw_pcie_rp *pp); |
442ec4c0 KVA |
190 | }; |
191 | ||
60b3c27f | 192 | struct dw_pcie_rp { |
f78f0263 | 193 | bool has_msi_ctrl:1; |
d6bdbcd8 | 194 | bool cfg0_io_shared:1; |
4b1ced84 JH |
195 | u64 cfg0_base; |
196 | void __iomem *va_cfg0_base; | |
adf70fc0 | 197 | u32 cfg0_size; |
0021d22b | 198 | resource_size_t io_base; |
adf70fc0 PA |
199 | phys_addr_t io_bus_addr; |
200 | u32 io_size; | |
4b1ced84 | 201 | int irq; |
4ab2e7c0 | 202 | const struct dw_pcie_host_ops *ops; |
f342d940 | 203 | int msi_irq; |
904d0e78 | 204 | struct irq_domain *irq_domain; |
7c5925af | 205 | struct irq_domain *msi_domain; |
111111a7 | 206 | dma_addr_t msi_data; |
35797e67 | 207 | struct page *msi_page; |
9f67437b | 208 | struct irq_chip *msi_irq_chip; |
7c5925af | 209 | u32 num_vectors; |
a348d015 | 210 | u32 irq_mask[MAX_MSI_CTRLS]; |
444ddca5 | 211 | struct pci_host_bridge *bridge; |
7c5925af | 212 | raw_spinlock_t lock; |
f342d940 | 213 | DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); |
4b1ced84 JH |
214 | }; |
215 | ||
f8aed6ec KVA |
216 | struct dw_pcie_ep_ops { |
217 | void (*ep_init)(struct dw_pcie_ep *ep); | |
16093362 | 218 | int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, |
d3c70a98 | 219 | enum pci_epc_irq_type type, u16 interrupt_num); |
fee35cb7 | 220 | const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); |
24ede430 XB |
221 | /* |
222 | * Provide a method to implement the different func config space | |
223 | * access for different platform, if different func have different | |
224 | * offset, return the offset of func. if use write a register way | |
225 | * return a 0, and implement code in callback function of platform | |
226 | * driver. | |
227 | */ | |
228 | unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no); | |
f8aed6ec KVA |
229 | }; |
230 | ||
47a06260 XB |
231 | struct dw_pcie_ep_func { |
232 | struct list_head list; | |
233 | u8 func_no; | |
234 | u8 msi_cap; /* MSI capability offset */ | |
235 | u8 msix_cap; /* MSI-X capability offset */ | |
236 | }; | |
237 | ||
f8aed6ec KVA |
238 | struct dw_pcie_ep { |
239 | struct pci_epc *epc; | |
47a06260 | 240 | struct list_head func_list; |
626961dd | 241 | const struct dw_pcie_ep_ops *ops; |
f8aed6ec KVA |
242 | phys_addr_t phys_base; |
243 | size_t addr_size; | |
a937fe08 | 244 | size_t page_size; |
c9c13ba4 | 245 | u8 bar_to_atu[PCI_STD_NUM_BARS]; |
f8aed6ec | 246 | phys_addr_t *outbound_addr; |
ad4a5bec NC |
247 | unsigned long *ib_window_map; |
248 | unsigned long *ob_window_map; | |
2fd0c9d9 NC |
249 | void __iomem *msi_mem; |
250 | phys_addr_t msi_mem_phys; | |
6f5e193b | 251 | struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; |
f8aed6ec KVA |
252 | }; |
253 | ||
442ec4c0 | 254 | struct dw_pcie_ops { |
b6900aeb | 255 | u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr); |
a509d7d9 KVA |
256 | u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, |
257 | size_t size); | |
258 | void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, | |
259 | size_t size, u32 val); | |
ddf567e3 KVA |
260 | void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, |
261 | size_t size, u32 val); | |
442ec4c0 | 262 | int (*link_up)(struct dw_pcie *pcie); |
f8aed6ec KVA |
263 | int (*start_link)(struct dw_pcie *pcie); |
264 | void (*stop_link)(struct dw_pcie *pcie); | |
4b1ced84 JH |
265 | }; |
266 | ||
442ec4c0 KVA |
267 | struct dw_pcie { |
268 | struct device *dev; | |
269 | void __iomem *dbi_base; | |
f8aed6ec | 270 | void __iomem *dbi_base2; |
6d6b05e3 | 271 | void __iomem *atu_base; |
281f1f99 | 272 | size_t atu_size; |
9ca17af5 RH |
273 | u32 num_ib_windows; |
274 | u32 num_ob_windows; | |
89473aa9 SS |
275 | u32 region_align; |
276 | u64 region_limit; | |
60b3c27f | 277 | struct dw_pcie_rp pp; |
f8aed6ec | 278 | struct dw_pcie_ep ep; |
442ec4c0 | 279 | const struct dw_pcie_ops *ops; |
afe1c6d5 | 280 | u32 version; |
13e9d390 | 281 | u32 type; |
6ffc02d2 | 282 | int num_lanes; |
39bc5006 | 283 | int link_gen; |
aeaa0bfe | 284 | u8 n_fts[2]; |
9f9e59a4 | 285 | bool iatu_unroll_enabled: 1; |
442ec4c0 KVA |
286 | }; |
287 | ||
288 | #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) | |
289 | ||
f8aed6ec KVA |
290 | #define to_dw_pcie_from_ep(endpoint) \ |
291 | container_of((endpoint), struct dw_pcie, ep) | |
292 | ||
13e9d390 SS |
293 | void dw_pcie_version_detect(struct dw_pcie *pci); |
294 | ||
7a6854f6 | 295 | u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); |
5b0841fa | 296 | u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); |
7a6854f6 | 297 | |
19ce01cc KVA |
298 | int dw_pcie_read(void __iomem *addr, int size, u32 *val); |
299 | int dw_pcie_write(void __iomem *addr, int size, u32 val); | |
18edf451 | 300 | |
7bc082d7 VS |
301 | u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); |
302 | void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); | |
7bc082d7 | 303 | void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); |
442ec4c0 | 304 | int dw_pcie_link_up(struct dw_pcie *pci); |
ed22aaae | 305 | void dw_pcie_upconfig_setup(struct dw_pcie *pci); |
442ec4c0 | 306 | int dw_pcie_wait_for_link(struct dw_pcie *pci); |
edf408b9 SS |
307 | int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, |
308 | u64 cpu_addr, u64 pci_addr, u64 size); | |
309 | int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, | |
310 | int type, u64 cpu_addr, u64 pci_addr, u64 size); | |
24ede430 | 311 | int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, |
4859db9b | 312 | int type, u64 cpu_addr, u8 bar); |
38fe2723 | 313 | void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); |
feb85d9b | 314 | void dw_pcie_setup(struct dw_pcie *pci); |
8bcca265 | 315 | void dw_pcie_iatu_detect(struct dw_pcie *pci); |
a0560209 | 316 | |
b50b2db2 KVA |
317 | static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) |
318 | { | |
7bc082d7 | 319 | dw_pcie_write_dbi(pci, reg, 0x4, val); |
b50b2db2 KVA |
320 | } |
321 | ||
322 | static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) | |
323 | { | |
7bc082d7 | 324 | return dw_pcie_read_dbi(pci, reg, 0x4); |
b50b2db2 KVA |
325 | } |
326 | ||
f8aed6ec KVA |
327 | static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) |
328 | { | |
7bc082d7 | 329 | dw_pcie_write_dbi(pci, reg, 0x2, val); |
f8aed6ec KVA |
330 | } |
331 | ||
332 | static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) | |
333 | { | |
7bc082d7 | 334 | return dw_pcie_read_dbi(pci, reg, 0x2); |
f8aed6ec KVA |
335 | } |
336 | ||
337 | static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) | |
338 | { | |
7bc082d7 | 339 | dw_pcie_write_dbi(pci, reg, 0x1, val); |
f8aed6ec KVA |
340 | } |
341 | ||
342 | static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) | |
343 | { | |
7bc082d7 | 344 | return dw_pcie_read_dbi(pci, reg, 0x1); |
f8aed6ec KVA |
345 | } |
346 | ||
347 | static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) | |
348 | { | |
7bc082d7 | 349 | dw_pcie_write_dbi2(pci, reg, 0x4, val); |
f8aed6ec KVA |
350 | } |
351 | ||
e44abfed HZ |
352 | static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) |
353 | { | |
354 | u32 reg; | |
355 | u32 val; | |
356 | ||
357 | reg = PCIE_MISC_CONTROL_1_OFF; | |
358 | val = dw_pcie_readl_dbi(pci, reg); | |
359 | val |= PCIE_DBI_RO_WR_EN; | |
360 | dw_pcie_writel_dbi(pci, reg, val); | |
361 | } | |
362 | ||
363 | static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) | |
364 | { | |
365 | u32 reg; | |
366 | u32 val; | |
367 | ||
368 | reg = PCIE_MISC_CONTROL_1_OFF; | |
369 | val = dw_pcie_readl_dbi(pci, reg); | |
370 | val &= ~PCIE_DBI_RO_WR_EN; | |
371 | dw_pcie_writel_dbi(pci, reg, val); | |
372 | } | |
373 | ||
a37beefb SS |
374 | static inline int dw_pcie_start_link(struct dw_pcie *pci) |
375 | { | |
376 | if (pci->ops && pci->ops->start_link) | |
377 | return pci->ops->start_link(pci); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static inline void dw_pcie_stop_link(struct dw_pcie *pci) | |
383 | { | |
384 | if (pci->ops && pci->ops->stop_link) | |
385 | pci->ops->stop_link(pci); | |
386 | } | |
387 | ||
a0560209 | 388 | #ifdef CONFIG_PCIE_DW_HOST |
60b3c27f | 389 | irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); |
ce06bf57 | 390 | int dw_pcie_setup_rc(struct dw_pcie_rp *pp); |
60b3c27f SS |
391 | int dw_pcie_host_init(struct dw_pcie_rp *pp); |
392 | void dw_pcie_host_deinit(struct dw_pcie_rp *pp); | |
393 | int dw_pcie_allocate_domains(struct dw_pcie_rp *pp); | |
27e7ed01 RH |
394 | void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, |
395 | int where); | |
a0560209 | 396 | #else |
60b3c27f | 397 | static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) |
a0560209 KVA |
398 | { |
399 | return IRQ_NONE; | |
400 | } | |
401 | ||
ce06bf57 | 402 | static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) |
a0560209 | 403 | { |
ce06bf57 | 404 | return 0; |
a0560209 KVA |
405 | } |
406 | ||
60b3c27f | 407 | static inline int dw_pcie_host_init(struct dw_pcie_rp *pp) |
a0560209 KVA |
408 | { |
409 | return 0; | |
410 | } | |
7c5925af | 411 | |
60b3c27f | 412 | static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp) |
9d071cad VS |
413 | { |
414 | } | |
415 | ||
60b3c27f | 416 | static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) |
7c5925af GP |
417 | { |
418 | return 0; | |
419 | } | |
27e7ed01 RH |
420 | static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, |
421 | unsigned int devfn, | |
422 | int where) | |
423 | { | |
424 | return NULL; | |
425 | } | |
a0560209 | 426 | #endif |
f8aed6ec KVA |
427 | |
428 | #ifdef CONFIG_PCIE_DW_EP | |
429 | void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); | |
430 | int dw_pcie_ep_init(struct dw_pcie_ep *ep); | |
e966f739 | 431 | int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); |
ac37dde7 | 432 | void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); |
f8aed6ec | 433 | void dw_pcie_ep_exit(struct dw_pcie_ep *ep); |
cb22d40b | 434 | int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); |
16093362 BH |
435 | int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
436 | u8 interrupt_num); | |
beb4641a GP |
437 | int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
438 | u16 interrupt_num); | |
2f7f7001 XB |
439 | int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, |
440 | u16 interrupt_num); | |
9e718119 | 441 | void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); |
47a06260 XB |
442 | struct dw_pcie_ep_func * |
443 | dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no); | |
f8aed6ec KVA |
444 | #else |
445 | static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) | |
446 | { | |
447 | } | |
448 | ||
449 | static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) | |
450 | { | |
451 | return 0; | |
452 | } | |
453 | ||
e966f739 VS |
454 | static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) |
455 | { | |
456 | return 0; | |
457 | } | |
458 | ||
ac37dde7 VS |
459 | static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) |
460 | { | |
461 | } | |
462 | ||
f8aed6ec KVA |
463 | static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) |
464 | { | |
465 | } | |
9e718119 | 466 | |
cb22d40b GP |
467 | static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) |
468 | { | |
469 | return 0; | |
470 | } | |
471 | ||
16093362 | 472 | static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, |
6f6d7873 NC |
473 | u8 interrupt_num) |
474 | { | |
475 | return 0; | |
476 | } | |
477 | ||
beb4641a GP |
478 | static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, |
479 | u16 interrupt_num) | |
480 | { | |
481 | return 0; | |
482 | } | |
483 | ||
2f7f7001 XB |
484 | static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, |
485 | u8 func_no, | |
486 | u16 interrupt_num) | |
487 | { | |
488 | return 0; | |
489 | } | |
490 | ||
9e718119 NC |
491 | static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) |
492 | { | |
493 | } | |
47a06260 XB |
494 | |
495 | static inline struct dw_pcie_ep_func * | |
496 | dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) | |
497 | { | |
498 | return NULL; | |
499 | } | |
f8aed6ec | 500 | #endif |
18edf451 | 501 | #endif /* _PCIE_DESIGNWARE_H */ |