[linux-block.git] / drivers / pci / controller / dwc / pcie-designware.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Synopsys DesignWare PCIe host controller driver
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: Jingoo Han <jg1.han@samsung.com>
 */

#include <linux/delay.h>
#include <linux/of.h>
#include <linux/types.h>

#include "pcie-designware.h"

/* PCIe Port Logic registers */
#define PLR_OFFSET			0x700
#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)
#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)

int dw_pcie_read(void __iomem *addr, int size, u32 *val)
{
	if ((uintptr_t)addr & (size - 1)) {
		*val = 0;
		return PCIBIOS_BAD_REGISTER_NUMBER;
	}

	if (size == 4) {
		*val = readl(addr);
	} else if (size == 2) {
		*val = readw(addr);
	} else if (size == 1) {
		*val = readb(addr);
	} else {
		*val = 0;
		return PCIBIOS_BAD_REGISTER_NUMBER;
	}

	return PCIBIOS_SUCCESSFUL;
}

int dw_pcie_write(void __iomem *addr, int size, u32 val)
{
	if ((uintptr_t)addr & (size - 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (size == 4)
		writel(val, addr);
	else if (size == 2)
		writew(val, addr);
	else if (size == 1)
		writeb(val, addr);
	else
		return PCIBIOS_BAD_REGISTER_NUMBER;

	return PCIBIOS_SUCCESSFUL;
}

u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
		       size_t size)
{
	int ret;
	u32 val;

	if (pci->ops->read_dbi)
		return pci->ops->read_dbi(pci, base, reg, size);

	ret = dw_pcie_read(base + reg, size, &val);
	if (ret)
		dev_err(pci->dev, "Read DBI address failed\n");

	return val;
}

void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
			 size_t size, u32 val)
{
	int ret;

	if (pci->ops->write_dbi) {
		pci->ops->write_dbi(pci, base, reg, size, val);
		return;
	}

	ret = dw_pcie_write(base + reg, size, val);
	if (ret)
		dev_err(pci->dev, "Write DBI address failed\n");
}

static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
{
	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

	return dw_pcie_readl_dbi(pci, offset + reg);
}

static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
				     u32 val)
{
	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

	dw_pcie_writel_dbi(pci, offset + reg, val);
}

static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
					     int type, u64 cpu_addr,
					     u64 pci_addr, u32 size)
{
	u32 retries, val;

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
				 lower_32_bits(cpu_addr));
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
				 upper_32_bits(cpu_addr));
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
				 lower_32_bits(cpu_addr + size - 1));
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
				 lower_32_bits(pci_addr));
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
				 upper_32_bits(pci_addr));
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
				 type);
	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
				 PCIE_ATU_ENABLE);

	/*
	 * Make sure ATU enable takes effect before any subsequent config
	 * and I/O accesses.
	 */
	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
		val = dw_pcie_readl_ob_unroll(pci, index,
					      PCIE_ATU_UNR_REGION_CTRL2);
		if (val & PCIE_ATU_ENABLE)
			return;

		mdelay(LINK_WAIT_IATU);
	}
	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
}

void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
			       u64 cpu_addr, u64 pci_addr, u32 size)
{
	u32 retries, val;

	if (pci->ops->cpu_addr_fixup)
		cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);

	if (pci->iatu_unroll_enabled) {
		dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
						 pci_addr, size);
		return;
	}

	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
			   PCIE_ATU_REGION_OUTBOUND | index);
	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
			   lower_32_bits(cpu_addr));
	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
			   upper_32_bits(cpu_addr));
	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
			   lower_32_bits(cpu_addr + size - 1));
	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
			   lower_32_bits(pci_addr));
	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
			   upper_32_bits(pci_addr));
	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);

	/*
	 * Make sure ATU enable takes effect before any subsequent config
	 * and I/O accesses.
	 */
	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
		if (val & PCIE_ATU_ENABLE)
			return;

		mdelay(LINK_WAIT_IATU);
	}
	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
}

static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
{
	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);

	return dw_pcie_readl_dbi(pci, offset + reg);
}

static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
				     u32 val)
{
	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);

	dw_pcie_writel_dbi(pci, offset + reg, val);
}

static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
					   int bar, u64 cpu_addr,
					   enum dw_pcie_as_type as_type)
{
	int type;
	u32 retries, val;

	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
				 lower_32_bits(cpu_addr));
	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
				 upper_32_bits(cpu_addr));

	switch (as_type) {
	case DW_PCIE_AS_MEM:
		type = PCIE_ATU_TYPE_MEM;
		break;
	case DW_PCIE_AS_IO:
		type = PCIE_ATU_TYPE_IO;
		break;
	default:
		return -EINVAL;
	}

	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
				 PCIE_ATU_ENABLE |
				 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));

	/*
	 * Make sure ATU enable takes effect before any subsequent config
	 * and I/O accesses.
	 */
	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
		val = dw_pcie_readl_ib_unroll(pci, index,
					      PCIE_ATU_UNR_REGION_CTRL2);
		if (val & PCIE_ATU_ENABLE)
			return 0;

		mdelay(LINK_WAIT_IATU);
	}
	dev_err(pci->dev, "Inbound iATU is not being enabled\n");

	return -EBUSY;
}

int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
			     u64 cpu_addr, enum dw_pcie_as_type as_type)
{
	int type;
	u32 retries, val;

	if (pci->iatu_unroll_enabled)
		return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
						       cpu_addr, as_type);

	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
			   index);
	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));

	switch (as_type) {
	case DW_PCIE_AS_MEM:
		type = PCIE_ATU_TYPE_MEM;
		break;
	case DW_PCIE_AS_IO:
		type = PCIE_ATU_TYPE_IO;
		break;
	default:
		return -EINVAL;
	}

	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
			   | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));

	/*
	 * Make sure ATU enable takes effect before any subsequent config
	 * and I/O accesses.
	 */
	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
		if (val & PCIE_ATU_ENABLE)
			return 0;

		mdelay(LINK_WAIT_IATU);
	}
	dev_err(pci->dev, "Inbound iATU is not being enabled\n");

	return -EBUSY;
}

void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
			 enum dw_pcie_region_type type)
{
	int region;

	switch (type) {
	case DW_PCIE_REGION_INBOUND:
		region = PCIE_ATU_REGION_INBOUND;
		break;
	case DW_PCIE_REGION_OUTBOUND:
		region = PCIE_ATU_REGION_OUTBOUND;
		break;
	default:
		return;
	}

	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
}

int dw_pcie_wait_for_link(struct dw_pcie *pci)
{
	int retries;

	/* Check if the link is up or not */
	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
		if (dw_pcie_link_up(pci)) {
			dev_info(pci->dev, "Link up\n");
			return 0;
		}
		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
	}

	dev_err(pci->dev, "Phy link never came up\n");

	return -ETIMEDOUT;
}

int dw_pcie_link_up(struct dw_pcie *pci)
{
	u32 val;

	if (pci->ops->link_up)
		return pci->ops->link_up(pci);

	val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
		(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
}

void dw_pcie_setup(struct dw_pcie *pci)
{
	int ret;
	u32 val;
	u32 lanes;
	struct device *dev = pci->dev;
	struct device_node *np = dev->of_node;

	ret = of_property_read_u32(np, "num-lanes", &lanes);
	if (ret)
		lanes = 0;

	/* Set the number of lanes */
	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
	val &= ~PORT_LINK_MODE_MASK;
	switch (lanes) {
	case 1:
		val |= PORT_LINK_MODE_1_LANES;
		break;
	case 2:
		val |= PORT_LINK_MODE_2_LANES;
		break;
	case 4:
		val |= PORT_LINK_MODE_4_LANES;
		break;
	case 8:
		val |= PORT_LINK_MODE_8_LANES;
		break;
	default:
		dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
		return;
	}
	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);

	/* Set link width speed control register */
	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
	switch (lanes) {
	case 1:
		val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
		break;
	case 2:
		val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
		break;
	case 4:
		val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
		break;
	case 8:
		val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
		break;
	}
	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
}
Commit	Line	Data
8cfab3cf	1	// SPDX-License-Identifier: GPL-2.0
340cba60	2	/*
96291d56	3	* Synopsys DesignWare PCIe host controller driver
340cba60 JH	4	*
	5	* Copyright (C) 2013 Samsung Electronics Co., Ltd.
	6	* http://www.samsung.com
	7	*
	8	* Author: Jingoo Han <jg1.han@samsung.com>
340cba60 JH	9	*/
340cba60 JH	10
886bc5ce	11	#include <linux/delay.h>
feb85d9b KVA	12	#include <linux/of.h>
feb85d9b KVA	13	#include <linux/types.h>
340cba60	14
4b1ced84	15	#include "pcie-designware.h"
340cba60	16
dac29e6c JP	17	/* PCIe Port Logic registers */
	18	#define PLR_OFFSET 0x700
	19	#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
01c07673 JZ	20	#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
01c07673 JZ	21	#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
dac29e6c	22
19ce01cc	23	int dw_pcie_read(void __iomem addr, int size, u32 val)
340cba60	24	{
b6b18f58 GP	25	if ((uintptr_t)addr & (size - 1)) {
	26	*val = 0;
	27	return PCIBIOS_BAD_REGISTER_NUMBER;
	28	}
	29
314fc854	30	if (size == 4) {
c003ca99	31	*val = readl(addr);
314fc854	32	} else if (size == 2) {
4c45852f	33	*val = readw(addr);
314fc854	34	} else if (size == 1) {
4c45852f	35	*val = readb(addr);
314fc854	36	} else {
c003ca99	37	*val = 0;
340cba60	38	return PCIBIOS_BAD_REGISTER_NUMBER;
c003ca99	39	}
340cba60 JH	40
	41	return PCIBIOS_SUCCESSFUL;
	42	}
	43
19ce01cc	44	int dw_pcie_write(void __iomem *addr, int size, u32 val)
340cba60	45	{
b6b18f58 GP	46	if ((uintptr_t)addr & (size - 1))
	47	return PCIBIOS_BAD_REGISTER_NUMBER;
	48
340cba60 JH	49	if (size == 4)
	50	writel(val, addr);
	51	else if (size == 2)
4c45852f	52	writew(val, addr);
340cba60	53	else if (size == 1)
4c45852f	54	writeb(val, addr);
340cba60 JH	55	else
	56	return PCIBIOS_BAD_REGISTER_NUMBER;
	57
	58	return PCIBIOS_SUCCESSFUL;
	59	}
	60
a509d7d9 KVA	61	u32 __dw_pcie_read_dbi(struct dw_pcie pci, void __iomem base, u32 reg,
a509d7d9 KVA	62	size_t size)
340cba60	63	{
a509d7d9 KVA	64	int ret;
a509d7d9 KVA	65	u32 val;
446fc23f	66
a509d7d9 KVA	67	if (pci->ops->read_dbi)
	68	return pci->ops->read_dbi(pci, base, reg, size);
	69
	70	ret = dw_pcie_read(base + reg, size, &val);
	71	if (ret)
b4a8a51c	72	dev_err(pci->dev, "Read DBI address failed\n");
a509d7d9 KVA	73
a509d7d9 KVA	74	return val;
340cba60 JH	75	}
340cba60 JH	76
a509d7d9 KVA	77	void __dw_pcie_write_dbi(struct dw_pcie pci, void __iomem base, u32 reg,
a509d7d9 KVA	78	size_t size, u32 val)
340cba60	79	{
a509d7d9 KVA	80	int ret;
	81
	82	if (pci->ops->write_dbi) {
	83	pci->ops->write_dbi(pci, base, reg, size, val);
	84	return;
	85	}
	86
	87	ret = dw_pcie_write(base + reg, size, val);
	88	if (ret)
b4a8a51c	89	dev_err(pci->dev, "Write DBI address failed\n");
340cba60 JH	90	}
340cba60 JH	91
edd45e39	92	static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
a0601a47 JP	93	{
	94	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
	95
442ec4c0	96	return dw_pcie_readl_dbi(pci, offset + reg);
a0601a47 JP	97	}
a0601a47 JP	98
edd45e39 KVA	99	static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
edd45e39 KVA	100	u32 val)
a0601a47 JP	101	{
	102	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
	103
442ec4c0	104	dw_pcie_writel_dbi(pci, offset + reg, val);
a0601a47 JP	105	}
a0601a47 JP	106
684a3a91 CP	107	static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
	108	int type, u64 cpu_addr,
	109	u64 pci_addr, u32 size)
edd45e39 KVA	110	{
	111	u32 retries, val;
	112
	113	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
	114	lower_32_bits(cpu_addr));
	115	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
	116	upper_32_bits(cpu_addr));
	117	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
	118	lower_32_bits(cpu_addr + size - 1));
	119	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
	120	lower_32_bits(pci_addr));
	121	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
	122	upper_32_bits(pci_addr));
	123	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
	124	type);
	125	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
	126	PCIE_ATU_ENABLE);
	127
	128	/*
	129	* Make sure ATU enable takes effect before any subsequent config
	130	* and I/O accesses.
	131	*/
	132	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
	133	val = dw_pcie_readl_ob_unroll(pci, index,
	134	PCIE_ATU_UNR_REGION_CTRL2);
	135	if (val & PCIE_ATU_ENABLE)
	136	return;
	137
9024143e	138	mdelay(LINK_WAIT_IATU);
edd45e39	139	}
b4a8a51c	140	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
edd45e39 KVA	141	}
edd45e39 KVA	142
feb85d9b KVA	143	void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
feb85d9b KVA	144	u64 cpu_addr, u64 pci_addr, u32 size)
63503c87	145	{
d8bbeb39	146	u32 retries, val;
17209dfb	147
a660083e	148	if (pci->ops->cpu_addr_fixup)
b6900aeb	149	cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
a660083e	150
442ec4c0	151	if (pci->iatu_unroll_enabled) {
edd45e39 KVA	152	dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
	153	pci_addr, size);
	154	return;
a0601a47	155	}
17209dfb	156
edd45e39 KVA	157	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
	158	PCIE_ATU_REGION_OUTBOUND \| index);
	159	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
	160	lower_32_bits(cpu_addr));
	161	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
	162	upper_32_bits(cpu_addr));
	163	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
	164	lower_32_bits(cpu_addr + size - 1));
	165	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
	166	lower_32_bits(pci_addr));
	167	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
	168	upper_32_bits(pci_addr));
	169	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
	170	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
	171
17209dfb SV	172	/*
	173	* Make sure ATU enable takes effect before any subsequent config
	174	* and I/O accesses.
	175	*/
d8bbeb39	176	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
edd45e39	177	val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
e9be4d78	178	if (val & PCIE_ATU_ENABLE)
d8bbeb39 JP	179	return;
d8bbeb39 JP	180
9024143e	181	mdelay(LINK_WAIT_IATU);
d8bbeb39	182	}
b4a8a51c	183	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
63503c87 JZ	184	}
63503c87 JZ	185
f8aed6ec KVA	186	static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
	187	{
	188	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
	189
	190	return dw_pcie_readl_dbi(pci, offset + reg);
	191	}
	192
	193	static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
	194	u32 val)
	195	{
	196	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
	197
	198	dw_pcie_writel_dbi(pci, offset + reg, val);
	199	}
	200
684a3a91 CP	201	static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
	202	int bar, u64 cpu_addr,
	203	enum dw_pcie_as_type as_type)
f8aed6ec KVA	204	{
	205	int type;
	206	u32 retries, val;
	207
	208	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
	209	lower_32_bits(cpu_addr));
	210	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
	211	upper_32_bits(cpu_addr));
	212
	213	switch (as_type) {
	214	case DW_PCIE_AS_MEM:
	215	type = PCIE_ATU_TYPE_MEM;
	216	break;
	217	case DW_PCIE_AS_IO:
	218	type = PCIE_ATU_TYPE_IO;
	219	break;
	220	default:
	221	return -EINVAL;
	222	}
	223
	224	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
	225	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
	226	PCIE_ATU_ENABLE \|
	227	PCIE_ATU_BAR_MODE_ENABLE \| (bar << 8));
	228
	229	/*
	230	* Make sure ATU enable takes effect before any subsequent config
	231	* and I/O accesses.
	232	*/
	233	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
	234	val = dw_pcie_readl_ib_unroll(pci, index,
	235	PCIE_ATU_UNR_REGION_CTRL2);
	236	if (val & PCIE_ATU_ENABLE)
	237	return 0;
	238
9024143e	239	mdelay(LINK_WAIT_IATU);
f8aed6ec	240	}
b4a8a51c	241	dev_err(pci->dev, "Inbound iATU is not being enabled\n");
f8aed6ec KVA	242
	243	return -EBUSY;
	244	}
	245
	246	int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
	247	u64 cpu_addr, enum dw_pcie_as_type as_type)
	248	{
	249	int type;
	250	u32 retries, val;
	251
	252	if (pci->iatu_unroll_enabled)
	253	return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
	254	cpu_addr, as_type);
	255
	256	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND \|
	257	index);
	258	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
	259	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
	260
	261	switch (as_type) {
	262	case DW_PCIE_AS_MEM:
	263	type = PCIE_ATU_TYPE_MEM;
	264	break;
	265	case DW_PCIE_AS_IO:
	266	type = PCIE_ATU_TYPE_IO;
	267	break;
	268	default:
	269	return -EINVAL;
	270	}
	271
	272	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
	273	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
	274	\| PCIE_ATU_BAR_MODE_ENABLE \| (bar << 8));
	275
	276	/*
	277	* Make sure ATU enable takes effect before any subsequent config
	278	* and I/O accesses.
	279	*/
	280	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
	281	val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
	282	if (val & PCIE_ATU_ENABLE)
	283	return 0;
	284
9024143e	285	mdelay(LINK_WAIT_IATU);
f8aed6ec	286	}
b4a8a51c	287	dev_err(pci->dev, "Inbound iATU is not being enabled\n");
f8aed6ec KVA	288
	289	return -EBUSY;
	290	}
	291
	292	void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
	293	enum dw_pcie_region_type type)
	294	{
	295	int region;
	296
	297	switch (type) {
	298	case DW_PCIE_REGION_INBOUND:
	299	region = PCIE_ATU_REGION_INBOUND;
	300	break;
	301	case DW_PCIE_REGION_OUTBOUND:
	302	region = PCIE_ATU_REGION_OUTBOUND;
	303	break;
	304	default:
	305	return;
	306	}
	307
	308	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region \| index);
	309	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
	310	}
	311
442ec4c0	312	int dw_pcie_wait_for_link(struct dw_pcie *pci)
886bc5ce JP	313	{
	314	int retries;
	315
b4a8a51c	316	/* Check if the link is up or not */
886bc5ce	317	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
442ec4c0	318	if (dw_pcie_link_up(pci)) {
b4a8a51c	319	dev_info(pci->dev, "Link up\n");
886bc5ce JP	320	return 0;
	321	}
	322	usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
	323	}
	324
b4a8a51c	325	dev_err(pci->dev, "Phy link never came up\n");
886bc5ce JP	326
	327	return -ETIMEDOUT;
	328	}
	329
442ec4c0	330	int dw_pcie_link_up(struct dw_pcie *pci)
4b1ced84	331	{
dac29e6c JP	332	u32 val;
dac29e6c JP	333
442ec4c0 KVA	334	if (pci->ops->link_up)
442ec4c0 KVA	335	return pci->ops->link_up(pci);
116a489d	336
442ec4c0	337	val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
01c07673 JZ	338	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
01c07673 JZ	339	(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
4b1ced84 JH	340	}
4b1ced84 JH	341
feb85d9b	342	void dw_pcie_setup(struct dw_pcie *pci)
340cba60	343	{
5f334db6	344	int ret;
340cba60	345	u32 val;
feb85d9b	346	u32 lanes;
5f334db6 KVA	347	struct device *dev = pci->dev;
	348	struct device_node *np = dev->of_node;
	349
	350	ret = of_property_read_u32(np, "num-lanes", &lanes);
	351	if (ret)
	352	lanes = 0;
340cba60	353
b4a8a51c	354	/* Set the number of lanes */
442ec4c0	355	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
340cba60	356	val &= ~PORT_LINK_MODE_MASK;
5f334db6	357	switch (lanes) {
4b1ced84 JH	358	case 1:
	359	val \|= PORT_LINK_MODE_1_LANES;
	360	break;
	361	case 2:
	362	val \|= PORT_LINK_MODE_2_LANES;
	363	break;
	364	case 4:
	365	val \|= PORT_LINK_MODE_4_LANES;
	366	break;
5b0f0738 ZW	367	case 8:
	368	val \|= PORT_LINK_MODE_8_LANES;
	369	break;
907fce09	370	default:
5f334db6	371	dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
907fce09	372	return;
4b1ced84	373	}
442ec4c0	374	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
340cba60	375
b4a8a51c	376	/* Set link width speed control register */
442ec4c0	377	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60	378	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
5f334db6	379	switch (lanes) {
4b1ced84 JH	380	case 1:
	381	val \|= PORT_LOGIC_LINK_WIDTH_1_LANES;
	382	break;
	383	case 2:
	384	val \|= PORT_LOGIC_LINK_WIDTH_2_LANES;
	385	break;
	386	case 4:
	387	val \|= PORT_LOGIC_LINK_WIDTH_4_LANES;
	388	break;
5b0f0738 ZW	389	case 8:
	390	val \|= PORT_LOGIC_LINK_WIDTH_8_LANES;
	391	break;
4b1ced84	392	}
442ec4c0	393	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
340cba60	394	}