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37dddf14 CP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017 Cadence | |
3 | // Cadence PCIe endpoint controller driver. | |
4 | // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> | |
5 | ||
6 | #include <linux/delay.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/of.h> | |
9 | #include <linux/pci-epc.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/pm_runtime.h> | |
12 | #include <linux/sizes.h> | |
13 | ||
14 | #include "pcie-cadence.h" | |
15 | ||
16 | #define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ | |
17 | #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 | |
18 | #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 | |
19 | ||
20 | /** | |
21 | * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver | |
22 | * @pcie: Cadence PCIe controller | |
23 | * @max_regions: maximum number of regions supported by hardware | |
24 | * @ob_region_map: bitmask of mapped outbound regions | |
25 | * @ob_addr: base addresses in the AXI bus where the outbound regions start | |
26 | * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ | |
27 | * dedicated outbound regions is mapped. | |
28 | * @irq_cpu_addr: base address in the CPU space where a write access triggers | |
29 | * the sending of a memory write (MSI) / normal message (legacy | |
30 | * IRQ) TLP through the PCIe bus. | |
31 | * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ | |
32 | * dedicated outbound region. | |
33 | * @irq_pci_fn: the latest PCI function that has updated the mapping of | |
34 | * the MSI/legacy IRQ dedicated outbound region. | |
35 | * @irq_pending: bitmask of asserted legacy IRQs. | |
36 | */ | |
37 | struct cdns_pcie_ep { | |
38 | struct cdns_pcie pcie; | |
39 | u32 max_regions; | |
40 | unsigned long ob_region_map; | |
41 | phys_addr_t *ob_addr; | |
42 | phys_addr_t irq_phys_addr; | |
43 | void __iomem *irq_cpu_addr; | |
44 | u64 irq_pci_addr; | |
45 | u8 irq_pci_fn; | |
46 | u8 irq_pending; | |
47 | }; | |
48 | ||
49 | static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, | |
50 | struct pci_epf_header *hdr) | |
51 | { | |
52 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
53 | struct cdns_pcie *pcie = &ep->pcie; | |
54 | ||
55 | cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); | |
56 | cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); | |
57 | cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); | |
58 | cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, | |
59 | hdr->subclass_code | hdr->baseclass_code << 8); | |
60 | cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, | |
61 | hdr->cache_line_size); | |
62 | cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); | |
63 | cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); | |
64 | ||
65 | /* | |
66 | * Vendor ID can only be modified from function 0, all other functions | |
67 | * use the same vendor ID as function 0. | |
68 | */ | |
69 | if (fn == 0) { | |
70 | /* Update the vendor IDs. */ | |
71 | u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | | |
72 | CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); | |
73 | ||
74 | cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); | |
75 | } | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
bc4a4897 NC |
80 | static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, |
81 | struct pci_epf_bar *epf_bar) | |
37dddf14 CP |
82 | { |
83 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
84 | struct cdns_pcie *pcie = &ep->pcie; | |
bc4a4897 NC |
85 | dma_addr_t bar_phys = epf_bar->phys_addr; |
86 | enum pci_barno bar = epf_bar->barno; | |
87 | int flags = epf_bar->flags; | |
37dddf14 CP |
88 | u32 addr0, addr1, reg, cfg, b, aperture, ctrl; |
89 | u64 sz; | |
90 | ||
91 | /* BAR size is 2^(aperture + 7) */ | |
bc4a4897 | 92 | sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); |
37dddf14 CP |
93 | /* |
94 | * roundup_pow_of_two() returns an unsigned long, which is not suited | |
95 | * for 64bit values. | |
96 | */ | |
97 | sz = 1ULL << fls64(sz - 1); | |
98 | aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ | |
99 | ||
100 | if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
101 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS; | |
102 | } else { | |
103 | bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
104 | bool is_64bits = sz > SZ_2G; | |
105 | ||
106 | if (is_64bits && (bar & 1)) | |
107 | return -EINVAL; | |
108 | ||
a2ea8ac4 NC |
109 | if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) |
110 | epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; | |
111 | ||
37dddf14 CP |
112 | if (is_64bits && is_prefetch) |
113 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; | |
114 | else if (is_prefetch) | |
115 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; | |
116 | else if (is_64bits) | |
117 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS; | |
118 | else | |
119 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS; | |
120 | } | |
121 | ||
122 | addr0 = lower_32_bits(bar_phys); | |
123 | addr1 = upper_32_bits(bar_phys); | |
124 | cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), | |
125 | addr0); | |
126 | cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), | |
127 | addr1); | |
128 | ||
129 | if (bar < BAR_4) { | |
130 | reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); | |
131 | b = bar; | |
132 | } else { | |
133 | reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); | |
134 | b = bar - BAR_4; | |
135 | } | |
136 | ||
137 | cfg = cdns_pcie_readl(pcie, reg); | |
138 | cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | | |
139 | CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); | |
140 | cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | | |
141 | CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); | |
142 | cdns_pcie_writel(pcie, reg, cfg); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, | |
77d08dbd | 148 | struct pci_epf_bar *epf_bar) |
37dddf14 CP |
149 | { |
150 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
151 | struct cdns_pcie *pcie = &ep->pcie; | |
77d08dbd | 152 | enum pci_barno bar = epf_bar->barno; |
37dddf14 CP |
153 | u32 reg, cfg, b, ctrl; |
154 | ||
155 | if (bar < BAR_4) { | |
156 | reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); | |
157 | b = bar; | |
158 | } else { | |
159 | reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); | |
160 | b = bar - BAR_4; | |
161 | } | |
162 | ||
163 | ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; | |
164 | cfg = cdns_pcie_readl(pcie, reg); | |
165 | cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | | |
166 | CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); | |
167 | cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); | |
168 | cdns_pcie_writel(pcie, reg, cfg); | |
169 | ||
170 | cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); | |
171 | cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); | |
172 | } | |
173 | ||
174 | static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, | |
175 | u64 pci_addr, size_t size) | |
176 | { | |
177 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
178 | struct cdns_pcie *pcie = &ep->pcie; | |
179 | u32 r; | |
180 | ||
181 | r = find_first_zero_bit(&ep->ob_region_map, | |
182 | sizeof(ep->ob_region_map) * BITS_PER_LONG); | |
183 | if (r >= ep->max_regions - 1) { | |
184 | dev_err(&epc->dev, "no free outbound region\n"); | |
185 | return -EINVAL; | |
186 | } | |
187 | ||
188 | cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size); | |
189 | ||
190 | set_bit(r, &ep->ob_region_map); | |
191 | ep->ob_addr[r] = addr; | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, | |
197 | phys_addr_t addr) | |
198 | { | |
199 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
200 | struct cdns_pcie *pcie = &ep->pcie; | |
201 | u32 r; | |
202 | ||
203 | for (r = 0; r < ep->max_regions - 1; r++) | |
204 | if (ep->ob_addr[r] == addr) | |
205 | break; | |
206 | ||
207 | if (r == ep->max_regions - 1) | |
208 | return; | |
209 | ||
210 | cdns_pcie_reset_outbound_region(pcie, r); | |
211 | ||
212 | ep->ob_addr[r] = 0; | |
213 | clear_bit(r, &ep->ob_region_map); | |
214 | } | |
215 | ||
216 | static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc) | |
217 | { | |
218 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
219 | struct cdns_pcie *pcie = &ep->pcie; | |
220 | u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; | |
221 | u16 flags; | |
222 | ||
223 | /* | |
224 | * Set the Multiple Message Capable bitfield into the Message Control | |
225 | * register. | |
226 | */ | |
227 | flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); | |
228 | flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); | |
229 | flags |= PCI_MSI_FLAGS_64BIT; | |
230 | flags &= ~PCI_MSI_FLAGS_MASKBIT; | |
231 | cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
236 | static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) | |
237 | { | |
238 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
239 | struct cdns_pcie *pcie = &ep->pcie; | |
240 | u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; | |
241 | u16 flags, mmc, mme; | |
242 | ||
243 | /* Validate that the MSI feature is actually enabled. */ | |
244 | flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); | |
245 | if (!(flags & PCI_MSI_FLAGS_ENABLE)) | |
246 | return -EINVAL; | |
247 | ||
248 | /* | |
249 | * Get the Multiple Message Enable bitfield from the Message Control | |
250 | * register. | |
251 | */ | |
252 | mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1; | |
253 | mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; | |
254 | ||
255 | return mme; | |
256 | } | |
257 | ||
258 | static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, | |
259 | u8 intx, bool is_asserted) | |
260 | { | |
261 | struct cdns_pcie *pcie = &ep->pcie; | |
262 | u32 r = ep->max_regions - 1; | |
263 | u32 offset; | |
264 | u16 status; | |
265 | u8 msg_code; | |
266 | ||
267 | intx &= 3; | |
268 | ||
269 | /* Set the outbound region if needed. */ | |
270 | if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || | |
271 | ep->irq_pci_fn != fn)) { | |
272 | /* Last region was reserved for IRQ writes. */ | |
273 | cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r, | |
274 | ep->irq_phys_addr); | |
275 | ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; | |
276 | ep->irq_pci_fn = fn; | |
277 | } | |
278 | ||
279 | if (is_asserted) { | |
280 | ep->irq_pending |= BIT(intx); | |
281 | msg_code = MSG_CODE_ASSERT_INTA + intx; | |
282 | } else { | |
283 | ep->irq_pending &= ~BIT(intx); | |
284 | msg_code = MSG_CODE_DEASSERT_INTA + intx; | |
285 | } | |
286 | ||
287 | status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); | |
288 | if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { | |
289 | status ^= PCI_STATUS_INTERRUPT; | |
290 | cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); | |
291 | } | |
292 | ||
293 | offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | | |
294 | CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | | |
295 | CDNS_PCIE_MSG_NO_DATA; | |
296 | writel(0, ep->irq_cpu_addr + offset); | |
297 | } | |
298 | ||
299 | static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx) | |
300 | { | |
301 | u16 cmd; | |
302 | ||
303 | cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); | |
304 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
305 | return -EINVAL; | |
306 | ||
307 | cdns_pcie_ep_assert_intx(ep, fn, intx, true); | |
308 | /* | |
309 | * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq() | |
310 | * from drivers/pci/dwc/pci-dra7xx.c | |
311 | */ | |
312 | mdelay(1); | |
313 | cdns_pcie_ep_assert_intx(ep, fn, intx, false); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, | |
318 | u8 interrupt_num) | |
319 | { | |
320 | struct cdns_pcie *pcie = &ep->pcie; | |
321 | u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; | |
322 | u16 flags, mme, data, data_mask; | |
323 | u8 msi_count; | |
324 | u64 pci_addr, pci_addr_mask = 0xff; | |
325 | ||
326 | /* Check whether the MSI feature has been enabled by the PCI host. */ | |
327 | flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); | |
328 | if (!(flags & PCI_MSI_FLAGS_ENABLE)) | |
329 | return -EINVAL; | |
330 | ||
331 | /* Get the number of enabled MSIs */ | |
332 | mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; | |
333 | msi_count = 1 << mme; | |
334 | if (!interrupt_num || interrupt_num > msi_count) | |
335 | return -EINVAL; | |
336 | ||
337 | /* Compute the data value to be written. */ | |
338 | data_mask = msi_count - 1; | |
339 | data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); | |
340 | data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); | |
341 | ||
342 | /* Get the PCI address where to write the data into. */ | |
343 | pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); | |
344 | pci_addr <<= 32; | |
345 | pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); | |
346 | pci_addr &= GENMASK_ULL(63, 2); | |
347 | ||
348 | /* Set the outbound region if needed. */ | |
349 | if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || | |
350 | ep->irq_pci_fn != fn)) { | |
351 | /* Last region was reserved for IRQ writes. */ | |
352 | cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1, | |
353 | false, | |
354 | ep->irq_phys_addr, | |
355 | pci_addr & ~pci_addr_mask, | |
356 | pci_addr_mask + 1); | |
357 | ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); | |
358 | ep->irq_pci_fn = fn; | |
359 | } | |
360 | writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, | |
366 | enum pci_epc_irq_type type, u8 interrupt_num) | |
367 | { | |
368 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
369 | ||
370 | switch (type) { | |
371 | case PCI_EPC_IRQ_LEGACY: | |
372 | return cdns_pcie_ep_send_legacy_irq(ep, fn, 0); | |
373 | ||
374 | case PCI_EPC_IRQ_MSI: | |
375 | return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num); | |
376 | ||
377 | default: | |
378 | break; | |
379 | } | |
380 | ||
381 | return -EINVAL; | |
382 | } | |
383 | ||
384 | static int cdns_pcie_ep_start(struct pci_epc *epc) | |
385 | { | |
386 | struct cdns_pcie_ep *ep = epc_get_drvdata(epc); | |
387 | struct cdns_pcie *pcie = &ep->pcie; | |
388 | struct pci_epf *epf; | |
389 | u32 cfg; | |
390 | ||
391 | /* | |
392 | * BIT(0) is hardwired to 1, hence function 0 is always enabled | |
393 | * and can't be disabled anyway. | |
394 | */ | |
395 | cfg = BIT(0); | |
396 | list_for_each_entry(epf, &epc->pci_epf, list) | |
397 | cfg |= BIT(epf->func_no); | |
398 | cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); | |
399 | ||
400 | /* | |
401 | * The PCIe links are automatically established by the controller | |
402 | * once for all at powerup: the software can neither start nor stop | |
403 | * those links later at runtime. | |
404 | * | |
405 | * Then we only have to notify the EP core that our links are already | |
406 | * established. However we don't call directly pci_epc_linkup() because | |
407 | * we've already locked the epc->lock. | |
408 | */ | |
409 | list_for_each_entry(epf, &epc->pci_epf, list) | |
410 | pci_epf_linkup(epf); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static const struct pci_epc_ops cdns_pcie_epc_ops = { | |
416 | .write_header = cdns_pcie_ep_write_header, | |
417 | .set_bar = cdns_pcie_ep_set_bar, | |
418 | .clear_bar = cdns_pcie_ep_clear_bar, | |
419 | .map_addr = cdns_pcie_ep_map_addr, | |
420 | .unmap_addr = cdns_pcie_ep_unmap_addr, | |
421 | .set_msi = cdns_pcie_ep_set_msi, | |
422 | .get_msi = cdns_pcie_ep_get_msi, | |
423 | .raise_irq = cdns_pcie_ep_raise_irq, | |
424 | .start = cdns_pcie_ep_start, | |
425 | }; | |
426 | ||
427 | static const struct of_device_id cdns_pcie_ep_of_match[] = { | |
428 | { .compatible = "cdns,cdns-pcie-ep" }, | |
429 | ||
430 | { }, | |
431 | }; | |
432 | ||
433 | static int cdns_pcie_ep_probe(struct platform_device *pdev) | |
434 | { | |
435 | struct device *dev = &pdev->dev; | |
436 | struct device_node *np = dev->of_node; | |
437 | struct cdns_pcie_ep *ep; | |
438 | struct cdns_pcie *pcie; | |
439 | struct pci_epc *epc; | |
440 | struct resource *res; | |
441 | int ret; | |
442 | ||
443 | ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); | |
444 | if (!ep) | |
445 | return -ENOMEM; | |
446 | ||
447 | pcie = &ep->pcie; | |
448 | pcie->is_rc = false; | |
449 | ||
450 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); | |
451 | pcie->reg_base = devm_ioremap_resource(dev, res); | |
452 | if (IS_ERR(pcie->reg_base)) { | |
453 | dev_err(dev, "missing \"reg\"\n"); | |
454 | return PTR_ERR(pcie->reg_base); | |
455 | } | |
456 | ||
457 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); | |
458 | if (!res) { | |
459 | dev_err(dev, "missing \"mem\"\n"); | |
460 | return -EINVAL; | |
461 | } | |
462 | pcie->mem_res = res; | |
463 | ||
464 | ret = of_property_read_u32(np, "cdns,max-outbound-regions", | |
465 | &ep->max_regions); | |
466 | if (ret < 0) { | |
467 | dev_err(dev, "missing \"cdns,max-outbound-regions\"\n"); | |
468 | return ret; | |
469 | } | |
a86854d0 KC |
470 | ep->ob_addr = devm_kcalloc(dev, |
471 | ep->max_regions, sizeof(*ep->ob_addr), | |
37dddf14 CP |
472 | GFP_KERNEL); |
473 | if (!ep->ob_addr) | |
474 | return -ENOMEM; | |
475 | ||
476 | pm_runtime_enable(dev); | |
477 | ret = pm_runtime_get_sync(dev); | |
478 | if (ret < 0) { | |
479 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
480 | goto err_get_sync; | |
481 | } | |
482 | ||
483 | /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */ | |
484 | cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); | |
485 | ||
486 | epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops); | |
487 | if (IS_ERR(epc)) { | |
488 | dev_err(dev, "failed to create epc device\n"); | |
489 | ret = PTR_ERR(epc); | |
490 | goto err_init; | |
491 | } | |
492 | ||
493 | epc_set_drvdata(epc, ep); | |
494 | ||
495 | if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) | |
496 | epc->max_functions = 1; | |
497 | ||
498 | ret = pci_epc_mem_init(epc, pcie->mem_res->start, | |
499 | resource_size(pcie->mem_res)); | |
500 | if (ret < 0) { | |
501 | dev_err(dev, "failed to initialize the memory space\n"); | |
502 | goto err_init; | |
503 | } | |
504 | ||
505 | ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, | |
506 | SZ_128K); | |
507 | if (!ep->irq_cpu_addr) { | |
508 | dev_err(dev, "failed to reserve memory space for MSI\n"); | |
509 | ret = -ENOMEM; | |
510 | goto free_epc_mem; | |
511 | } | |
512 | ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; | |
513 | ||
514 | return 0; | |
515 | ||
516 | free_epc_mem: | |
517 | pci_epc_mem_exit(epc); | |
518 | ||
519 | err_init: | |
520 | pm_runtime_put_sync(dev); | |
521 | ||
522 | err_get_sync: | |
523 | pm_runtime_disable(dev); | |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
528 | static void cdns_pcie_ep_shutdown(struct platform_device *pdev) | |
529 | { | |
530 | struct device *dev = &pdev->dev; | |
531 | int ret; | |
532 | ||
533 | ret = pm_runtime_put_sync(dev); | |
534 | if (ret < 0) | |
535 | dev_dbg(dev, "pm_runtime_put_sync failed\n"); | |
536 | ||
537 | pm_runtime_disable(dev); | |
538 | ||
539 | /* The PCIe controller can't be disabled. */ | |
540 | } | |
541 | ||
542 | static struct platform_driver cdns_pcie_ep_driver = { | |
543 | .driver = { | |
544 | .name = "cdns-pcie-ep", | |
545 | .of_match_table = cdns_pcie_ep_of_match, | |
546 | }, | |
547 | .probe = cdns_pcie_ep_probe, | |
548 | .shutdown = cdns_pcie_ep_shutdown, | |
549 | }; | |
550 | builtin_platform_driver(cdns_pcie_ep_driver); |