[linux-2.6-block.git] / drivers / pci / ats.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI Express I/O Virtualization (IOV) support
 *   Address Translation Service 1.0
 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
 *
 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
 * Copyright (C) 2011 Advanced Micro Devices,
 */

#include <linux/bitfield.h>
#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

void pci_ats_init(struct pci_dev *dev)
{
	int pos;

	if (pci_ats_disabled())
		return;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	if (!pos)
		return;

	dev->ats_cap = pos;
}

/**
 * pci_ats_supported - check if the device can use ATS
 * @dev: the PCI device
 *
 * Returns true if the device supports ATS and is allowed to use it, false
 * otherwise.
 */
bool pci_ats_supported(struct pci_dev *dev)
{
	if (!dev->ats_cap)
		return false;

	return (dev->untrusted == 0);
}
EXPORT_SYMBOL_GPL(pci_ats_supported);

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	u16 ctrl;
	struct pci_dev *pdev;

	if (!pci_ats_supported(dev))
		return -EINVAL;

	if (WARN_ON(dev->ats_enabled))
		return -EBUSY;

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	/*
	 * Note that enabling ATS on a VF fails unless it's already enabled
	 * with the same STU on the PF.
	 */
	ctrl = PCI_ATS_CTRL_ENABLE;
	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		if (pdev->ats_stu != ps)
			return -EINVAL;
	} else {
		dev->ats_stu = ps;
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	}
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 1;
	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);

/**
 * pci_disable_ats - disable the ATS capability
 * @dev: the PCI device
 */
void pci_disable_ats(struct pci_dev *dev)
{
	u16 ctrl;

	if (WARN_ON(!dev->ats_enabled))
		return;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
	ctrl &= ~PCI_ATS_CTRL_ENABLE;
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_ats);

void pci_restore_ats_state(struct pci_dev *dev)
{
	u16 ctrl;

	if (!dev->ats_enabled)
		return;

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
}

/**
 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
 * @dev: the PCI device
 *
 * Returns the queue depth on success, or negative on failure.
 *
 * The ATS spec uses 0 in the Invalidate Queue Depth field to
 * indicate that the function can accept 32 Invalidate Request.
 * But here we use the `real' values (i.e. 1~32) for the Queue
 * Depth; and 0 indicates the function shares the Queue with
 * other functions (doesn't exclusively own a Queue).
 */
int pci_ats_queue_depth(struct pci_dev *dev)
{
	u16 cap;

	if (!dev->ats_cap)
		return -EINVAL;

	if (dev->is_virtfn)
		return 0;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
}

/**
 * pci_ats_page_aligned - Return Page Aligned Request bit status.
 * @pdev: the PCI device
 *
 * Returns 1, if the Untranslated Addresses generated by the device
 * are always aligned or 0 otherwise.
 *
 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
 * is set, it indicates the Untranslated Addresses generated by the
 * device are always aligned to a 4096 byte boundary.
 */
int pci_ats_page_aligned(struct pci_dev *pdev)
{
	u16 cap;

	if (!pdev->ats_cap)
		return 0;

	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);

	if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
		return 1;

	return 0;
}

#ifdef CONFIG_PCI_PRI
void pci_pri_init(struct pci_dev *pdev)
{
	u16 status;

	pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pdev->pri_cap)
		return;

	pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
	if (status & PCI_PRI_STATUS_PASID)
		pdev->pasid_required = 1;
}

/**
 * pci_enable_pri - Enable PRI capability
 * @pdev: PCI device structure
 * @reqs: outstanding requests
 *
 * Returns 0 on success, negative value on error
 */
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
	u16 control, status;
	u32 max_requests;
	int pri = pdev->pri_cap;

	/*
	 * VFs must not implement the PRI Capability.  If their PF
	 * implements PRI, it is shared by the VFs, so if the PF PRI is
	 * enabled, it is also enabled for the VF.
	 */
	if (pdev->is_virtfn) {
		if (pci_physfn(pdev)->pri_enabled)
			return 0;
		return -EINVAL;
	}

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	if (!pri)
		return -EINVAL;

	pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
	if (!(status & PCI_PRI_STATUS_STOPPED))
		return -EBUSY;

	pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
	reqs = min(max_requests, reqs);
	pdev->pri_reqs_alloc = reqs;
	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);

	control = PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 1;

	return 0;
}

/**
 * pci_disable_pri - Disable PRI capability
 * @pdev: PCI device structure
 *
 * Only clears the enabled-bit, regardless of its former value
 */
void pci_disable_pri(struct pci_dev *pdev)
{
	u16 control;
	int pri = pdev->pri_cap;

	/* VFs share the PF PRI */
	if (pdev->is_virtfn)
		return;

	if (WARN_ON(!pdev->pri_enabled))
		return;

	if (!pri)
		return;

	pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
	control &= ~PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pri);

/**
 * pci_restore_pri_state - Restore PRI
 * @pdev: PCI device structure
 */
void pci_restore_pri_state(struct pci_dev *pdev)
{
	u16 control = PCI_PRI_CTRL_ENABLE;
	u32 reqs = pdev->pri_reqs_alloc;
	int pri = pdev->pri_cap;

	if (pdev->is_virtfn)
		return;

	if (!pdev->pri_enabled)
		return;

	if (!pri)
		return;

	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
}

/**
 * pci_reset_pri - Resets device's PRI state
 * @pdev: PCI device structure
 *
 * The PRI capability must be disabled before this function is called.
 * Returns 0 on success, negative value on error.
 */
int pci_reset_pri(struct pci_dev *pdev)
{
	u16 control;
	int pri = pdev->pri_cap;

	if (pdev->is_virtfn)
		return 0;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	if (!pri)
		return -EINVAL;

	control = PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);

	return 0;
}

/**
 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
 *				 status.
 * @pdev: PCI device structure
 *
 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
 */
int pci_prg_resp_pasid_required(struct pci_dev *pdev)
{
	if (pdev->is_virtfn)
		pdev = pci_physfn(pdev);

	return pdev->pasid_required;
}

/**
 * pci_pri_supported - Check if PRI is supported.
 * @pdev: PCI device structure
 *
 * Returns true if PRI capability is present, false otherwise.
 */
bool pci_pri_supported(struct pci_dev *pdev)
{
	/* VFs share the PF PRI */
	if (pci_physfn(pdev)->pri_cap)
		return true;
	return false;
}
EXPORT_SYMBOL_GPL(pci_pri_supported);
#endif /* CONFIG_PCI_PRI */

#ifdef CONFIG_PCI_PASID
void pci_pasid_init(struct pci_dev *pdev)
{
	pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
}

/**
 * pci_enable_pasid - Enable the PASID capability
 * @pdev: PCI device structure
 * @features: Features to enable
 *
 * Returns 0 on success, negative value on error. This function checks
 * whether the features are actually supported by the device and returns
 * an error if not.
 */
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
	u16 control, supported;
	int pasid = pdev->pasid_cap;

	/*
	 * VFs must not implement the PASID Capability, but if a PF
	 * supports PASID, its VFs share the PF PASID configuration.
	 */
	if (pdev->is_virtfn) {
		if (pci_physfn(pdev)->pasid_enabled)
			return 0;
		return -EINVAL;
	}

	if (WARN_ON(pdev->pasid_enabled))
		return -EBUSY;

	if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp)
		return -EINVAL;

	if (!pasid)
		return -EINVAL;

	if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF))
		return -EINVAL;

	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	/* User wants to enable anything unsupported? */
	if ((supported & features) != features)
		return -EINVAL;

	control = PCI_PASID_CTRL_ENABLE | features;
	pdev->pasid_features = features;

	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);

/**
 * pci_disable_pasid - Disable the PASID capability
 * @pdev: PCI device structure
 */
void pci_disable_pasid(struct pci_dev *pdev)
{
	u16 control = 0;
	int pasid = pdev->pasid_cap;

	/* VFs share the PF PASID configuration */
	if (pdev->is_virtfn)
		return;

	if (WARN_ON(!pdev->pasid_enabled))
		return;

	if (!pasid)
		return;

	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);

/**
 * pci_restore_pasid_state - Restore PASID capabilities
 * @pdev: PCI device structure
 */
void pci_restore_pasid_state(struct pci_dev *pdev)
{
	u16 control;
	int pasid = pdev->pasid_cap;

	if (pdev->is_virtfn)
		return;

	if (!pdev->pasid_enabled)
		return;

	if (!pasid)
		return;

	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
}

/**
 * pci_pasid_features - Check which PASID features are supported
 * @pdev: PCI device structure
 *
 * Returns a negative value when no PASI capability is present.
 * Otherwise is returns a bitmask with supported features. Current
 * features reported are:
 * PCI_PASID_CAP_EXEC - Execute permission supported
 * PCI_PASID_CAP_PRIV - Privileged mode supported
 */
int pci_pasid_features(struct pci_dev *pdev)
{
	u16 supported;
	int pasid;

	if (pdev->is_virtfn)
		pdev = pci_physfn(pdev);

	pasid = pdev->pasid_cap;
	if (!pasid)
		return -EINVAL;

	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);

/**
 * pci_max_pasids - Get maximum number of PASIDs supported by device
 * @pdev: PCI device structure
 *
 * Returns negative value when PASID capability is not present.
 * Otherwise it returns the number of supported PASIDs.
 */
int pci_max_pasids(struct pci_dev *pdev)
{
	u16 supported;
	int pasid;

	if (pdev->is_virtfn)
		pdev = pci_physfn(pdev);

	pasid = pdev->pasid_cap;
	if (!pasid)
		return -EINVAL;

	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);

	return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported));
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
db3c33c6	2	/*
df62ab5e	3	* PCI Express I/O Virtualization (IOV) support
db3c33c6	4	* Address Translation Service 1.0
c320b976	5	* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
086ac11f	6	* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
df62ab5e BH	7	*
	8	* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
	9	* Copyright (C) 2011 Advanced Micro Devices,
db3c33c6 JR	10	*/
db3c33c6 JR	11
e0701bd0	12	#include <linux/bitfield.h>
363c75db	13	#include <linux/export.h>
db3c33c6 JR	14	#include <linux/pci-ats.h>
db3c33c6 JR	15	#include <linux/pci.h>
8c451945	16	#include <linux/slab.h>
db3c33c6 JR	17
	18	#include "pci.h"
	19
afdd596c	20	void pci_ats_init(struct pci_dev *dev)
db3c33c6 JR	21	{
db3c33c6 JR	22	int pos;
db3c33c6	23
cef74409 GK	24	if (pci_ats_disabled())
	25	return;
	26
db3c33c6 JR	27	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
db3c33c6 JR	28	if (!pos)
edc90fee	29	return;
db3c33c6	30
d544d75a	31	dev->ats_cap = pos;
db3c33c6 JR	32	}
db3c33c6 JR	33
52137674 JPB	34	/**
	35	* pci_ats_supported - check if the device can use ATS
	36	* @dev: the PCI device
	37	*
	38	* Returns true if the device supports ATS and is allowed to use it, false
	39	* otherwise.
	40	*/
	41	bool pci_ats_supported(struct pci_dev *dev)
	42	{
	43	if (!dev->ats_cap)
	44	return false;
	45
	46	return (dev->untrusted == 0);
	47	}
	48	EXPORT_SYMBOL_GPL(pci_ats_supported);
	49
db3c33c6 JR	50	/**
	51	* pci_enable_ats - enable the ATS capability
	52	* @dev: the PCI device
	53	* @ps: the IOMMU page shift
	54	*
	55	* Returns 0 on success, or negative on failure.
	56	*/
	57	int pci_enable_ats(struct pci_dev *dev, int ps)
	58	{
db3c33c6	59	u16 ctrl;
c39127db	60	struct pci_dev *pdev;
db3c33c6	61
52137674	62	if (!pci_ats_supported(dev))
edc90fee BH	63	return -EINVAL;
edc90fee BH	64
f7ef1340	65	if (WARN_ON(dev->ats_enabled))
a021f301 BH	66	return -EBUSY;
a021f301 BH	67
db3c33c6 JR	68	if (ps < PCI_ATS_MIN_STU)
	69	return -EINVAL;
	70
edc90fee BH	71	/*
	72	* Note that enabling ATS on a VF fails unless it's already enabled
	73	* with the same STU on the PF.
	74	*/
	75	ctrl = PCI_ATS_CTRL_ENABLE;
	76	if (dev->is_virtfn) {
c39127db	77	pdev = pci_physfn(dev);
d544d75a	78	if (pdev->ats_stu != ps)
edc90fee	79	return -EINVAL;
edc90fee	80	} else {
d544d75a BH	81	dev->ats_stu = ps;
d544d75a BH	82	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
db3c33c6	83	}
d544d75a	84	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	85
d544d75a	86	dev->ats_enabled = 1;
db3c33c6 JR	87	return 0;
db3c33c6 JR	88	}
bb950bca	89	EXPORT_SYMBOL_GPL(pci_enable_ats);
db3c33c6 JR	90
	91	/**
	92	* pci_disable_ats - disable the ATS capability
	93	* @dev: the PCI device
	94	*/
	95	void pci_disable_ats(struct pci_dev *dev)
	96	{
	97	u16 ctrl;
	98
f7ef1340	99	if (WARN_ON(!dev->ats_enabled))
a021f301	100	return;
db3c33c6	101
d544d75a	102	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
db3c33c6	103	ctrl &= ~PCI_ATS_CTRL_ENABLE;
d544d75a	104	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	105
d544d75a	106	dev->ats_enabled = 0;
db3c33c6	107	}
bb950bca	108	EXPORT_SYMBOL_GPL(pci_disable_ats);
db3c33c6	109
1900ca13 HX	110	void pci_restore_ats_state(struct pci_dev *dev)
	111	{
	112	u16 ctrl;
	113
f7ef1340	114	if (!dev->ats_enabled)
1900ca13	115	return;
1900ca13 HX	116
	117	ctrl = PCI_ATS_CTRL_ENABLE;
	118	if (!dev->is_virtfn)
d544d75a BH	119	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
d544d75a BH	120	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
1900ca13	121	}
1900ca13	122
db3c33c6 JR	123	/**
	124	* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
	125	* @dev: the PCI device
	126	*
	127	* Returns the queue depth on success, or negative on failure.
	128	*
	129	* The ATS spec uses 0 in the Invalidate Queue Depth field to
	130	* indicate that the function can accept 32 Invalidate Request.
	131	* But here we use the `real' values (i.e. 1~32) for the Queue
	132	* Depth; and 0 indicates the function shares the Queue with
	133	* other functions (doesn't exclusively own a Queue).
	134	*/
	135	int pci_ats_queue_depth(struct pci_dev *dev)
	136	{
a71f938f BH	137	u16 cap;
a71f938f BH	138
3c765399 BH	139	if (!dev->ats_cap)
	140	return -EINVAL;
	141
db3c33c6 JR	142	if (dev->is_virtfn)
	143	return 0;
	144
a71f938f BH	145	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
a71f938f BH	146	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
db3c33c6	147	}
c320b976	148
8c938ddc KS	149	/**
	150	* pci_ats_page_aligned - Return Page Aligned Request bit status.
	151	* @pdev: the PCI device
	152	*
	153	* Returns 1, if the Untranslated Addresses generated by the device
	154	* are always aligned or 0 otherwise.
	155	*
	156	* Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
	157	* is set, it indicates the Untranslated Addresses generated by the
	158	* device are always aligned to a 4096 byte boundary.
	159	*/
	160	int pci_ats_page_aligned(struct pci_dev *pdev)
	161	{
	162	u16 cap;
	163
	164	if (!pdev->ats_cap)
	165	return 0;
	166
	167	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
	168
	169	if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
	170	return 1;
	171
	172	return 0;
	173	}
8c938ddc	174
c320b976	175	#ifdef CONFIG_PCI_PRI
c065190b KS	176	void pci_pri_init(struct pci_dev *pdev)
c065190b KS	177	{
e5adf79a BH	178	u16 status;
e5adf79a BH	179
c065190b	180	pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
e5adf79a BH	181
	182	if (!pdev->pri_cap)
	183	return;
	184
	185	pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
	186	if (status & PCI_PRI_STATUS_PASID)
	187	pdev->pasid_required = 1;
c065190b KS	188	}
c065190b KS	189
c320b976 JR	190	/**
c320b976 JR	191	* pci_enable_pri - Enable PRI capability
9b41d19a KK	192	* @pdev: PCI device structure
9b41d19a KK	193	* @reqs: outstanding requests
c320b976 JR	194	*
	195	* Returns 0 on success, negative value on error
	196	*/
	197	int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
	198	{
	199	u16 control, status;
	200	u32 max_requests;
c065190b	201	int pri = pdev->pri_cap;
c320b976	202
9bf49e36 KS	203	/*
	204	* VFs must not implement the PRI Capability. If their PF
	205	* implements PRI, it is shared by the VFs, so if the PF PRI is
	206	* enabled, it is also enabled for the VF.
	207	*/
	208	if (pdev->is_virtfn) {
	209	if (pci_physfn(pdev)->pri_enabled)
	210	return 0;
	211	return -EINVAL;
	212	}
	213
a4f4fa68 JPB	214	if (WARN_ON(pdev->pri_enabled))
	215	return -EBUSY;
	216
c065190b	217	if (!pri)
c320b976 JR	218	return -EINVAL;
c320b976 JR	219
c065190b	220	pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
4ebeb1ec	221	if (!(status & PCI_PRI_STATUS_STOPPED))
c320b976 JR	222	return -EBUSY;
c320b976 JR	223
c065190b	224	pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
c320b976	225	reqs = min(max_requests, reqs);
4ebeb1ec	226	pdev->pri_reqs_alloc = reqs;
c065190b	227	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
c320b976	228
4ebeb1ec	229	control = PCI_PRI_CTRL_ENABLE;
c065190b	230	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
c320b976	231
a4f4fa68 JPB	232	pdev->pri_enabled = 1;
a4f4fa68 JPB	233
c320b976 JR	234	return 0;
c320b976 JR	235	}
c320b976 JR	236
	237	/**
	238	* pci_disable_pri - Disable PRI capability
	239	* @pdev: PCI device structure
	240	*
	241	* Only clears the enabled-bit, regardless of its former value
	242	*/
	243	void pci_disable_pri(struct pci_dev *pdev)
	244	{
	245	u16 control;
c065190b	246	int pri = pdev->pri_cap;
c320b976	247
9bf49e36 KS	248	/* VFs share the PF PRI */
	249	if (pdev->is_virtfn)
	250	return;
	251
a4f4fa68 JPB	252	if (WARN_ON(!pdev->pri_enabled))
	253	return;
	254
c065190b	255	if (!pri)
c320b976 JR	256	return;
c320b976 JR	257
c065190b	258	pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
91f57d5e	259	control &= ~PCI_PRI_CTRL_ENABLE;
c065190b	260	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
a4f4fa68 JPB	261
a4f4fa68 JPB	262	pdev->pri_enabled = 0;
c320b976 JR	263	}
	264	EXPORT_SYMBOL_GPL(pci_disable_pri);
	265
4ebeb1ec CT	266	/**
	267	* pci_restore_pri_state - Restore PRI
	268	* @pdev: PCI device structure
	269	*/
	270	void pci_restore_pri_state(struct pci_dev *pdev)
	271	{
	272	u16 control = PCI_PRI_CTRL_ENABLE;
	273	u32 reqs = pdev->pri_reqs_alloc;
c065190b	274	int pri = pdev->pri_cap;
4ebeb1ec	275
9bf49e36 KS	276	if (pdev->is_virtfn)
	277	return;
	278
4ebeb1ec CT	279	if (!pdev->pri_enabled)
	280	return;
	281
c065190b	282	if (!pri)
4ebeb1ec CT	283	return;
4ebeb1ec CT	284
c065190b KS	285	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
c065190b KS	286	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
4ebeb1ec	287	}
4ebeb1ec	288
c320b976 JR	289	/**
	290	* pci_reset_pri - Resets device's PRI state
	291	* @pdev: PCI device structure
	292	*
	293	* The PRI capability must be disabled before this function is called.
	294	* Returns 0 on success, negative value on error.
	295	*/
	296	int pci_reset_pri(struct pci_dev *pdev)
	297	{
	298	u16 control;
c065190b	299	int pri = pdev->pri_cap;
c320b976	300
9bf49e36 KS	301	if (pdev->is_virtfn)
	302	return 0;
	303
a4f4fa68 JPB	304	if (WARN_ON(pdev->pri_enabled))
	305	return -EBUSY;
	306
c065190b	307	if (!pri)
c320b976 JR	308	return -EINVAL;
c320b976 JR	309
4ebeb1ec	310	control = PCI_PRI_CTRL_RESET;
c065190b	311	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
c320b976 JR	312
	313	return 0;
	314	}
8cbb8a93 BH	315
	316	/**
	317	* pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
	318	* status.
	319	* @pdev: PCI device structure
	320	*
	321	* Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
	322	*/
	323	int pci_prg_resp_pasid_required(struct pci_dev *pdev)
	324	{
9bf49e36 KS	325	if (pdev->is_virtfn)
	326	pdev = pci_physfn(pdev);
	327
e5adf79a	328	return pdev->pasid_required;
8cbb8a93	329	}
3f9a7a13 AR	330
	331	/**
	332	* pci_pri_supported - Check if PRI is supported.
	333	* @pdev: PCI device structure
	334	*
	335	* Returns true if PRI capability is present, false otherwise.
	336	*/
	337	bool pci_pri_supported(struct pci_dev *pdev)
	338	{
	339	/* VFs share the PF PRI */
	340	if (pci_physfn(pdev)->pri_cap)
	341	return true;
	342	return false;
	343	}
	344	EXPORT_SYMBOL_GPL(pci_pri_supported);
c320b976	345	#endif /* CONFIG_PCI_PRI */
086ac11f JR	346
086ac11f JR	347	#ifdef CONFIG_PCI_PASID
751035b8 KS	348	void pci_pasid_init(struct pci_dev *pdev)
	349	{
	350	pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	351	}
	352
086ac11f JR	353	/**
	354	* pci_enable_pasid - Enable the PASID capability
	355	* @pdev: PCI device structure
	356	* @features: Features to enable
	357	*
	358	* Returns 0 on success, negative value on error. This function checks
	359	* whether the features are actually supported by the device and returns
	360	* an error if not.
	361	*/
	362	int pci_enable_pasid(struct pci_dev *pdev, int features)
	363	{
	364	u16 control, supported;
751035b8	365	int pasid = pdev->pasid_cap;
086ac11f	366
2b0ae7cc KS	367	/*
	368	* VFs must not implement the PASID Capability, but if a PF
	369	* supports PASID, its VFs share the PF PASID configuration.
	370	*/
	371	if (pdev->is_virtfn) {
	372	if (pci_physfn(pdev)->pasid_enabled)
	373	return 0;
	374	return -EINVAL;
	375	}
	376
a4f4fa68 JPB	377	if (WARN_ON(pdev->pasid_enabled))
	378	return -EBUSY;
	379
8c09e896	380	if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp)
7ce3f912 SK	381	return -EINVAL;
7ce3f912 SK	382
751035b8	383	if (!pasid)
086ac11f JR	384	return -EINVAL;
086ac11f JR	385
201007ef LB	386	if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR \| PCI_ACS_UF))
	387	return -EINVAL;
	388
751035b8	389	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
91f57d5e	390	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	391
	392	/* User wants to enable anything unsupported? */
	393	if ((supported & features) != features)
	394	return -EINVAL;
	395
91f57d5e	396	control = PCI_PASID_CTRL_ENABLE \| features;
4ebeb1ec	397	pdev->pasid_features = features;
086ac11f	398
751035b8	399	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
086ac11f	400
a4f4fa68 JPB	401	pdev->pasid_enabled = 1;
a4f4fa68 JPB	402
086ac11f JR	403	return 0;
086ac11f JR	404	}
7682ce2b	405	EXPORT_SYMBOL_GPL(pci_enable_pasid);
086ac11f JR	406
	407	/**
	408	* pci_disable_pasid - Disable the PASID capability
	409	* @pdev: PCI device structure
086ac11f JR	410	*/
	411	void pci_disable_pasid(struct pci_dev *pdev)
	412	{
	413	u16 control = 0;
751035b8	414	int pasid = pdev->pasid_cap;
086ac11f	415
2b0ae7cc KS	416	/* VFs share the PF PASID configuration */
	417	if (pdev->is_virtfn)
	418	return;
	419
a4f4fa68 JPB	420	if (WARN_ON(!pdev->pasid_enabled))
	421	return;
	422
751035b8	423	if (!pasid)
086ac11f JR	424	return;
086ac11f JR	425
751035b8	426	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
a4f4fa68 JPB	427
a4f4fa68 JPB	428	pdev->pasid_enabled = 0;
086ac11f	429	}
7682ce2b	430	EXPORT_SYMBOL_GPL(pci_disable_pasid);
086ac11f	431
4ebeb1ec CT	432	/**
	433	* pci_restore_pasid_state - Restore PASID capabilities
	434	* @pdev: PCI device structure
	435	*/
	436	void pci_restore_pasid_state(struct pci_dev *pdev)
	437	{
	438	u16 control;
751035b8	439	int pasid = pdev->pasid_cap;
4ebeb1ec	440
2b0ae7cc KS	441	if (pdev->is_virtfn)
	442	return;
	443
4ebeb1ec CT	444	if (!pdev->pasid_enabled)
	445	return;
	446
751035b8	447	if (!pasid)
4ebeb1ec CT	448	return;
	449
	450	control = PCI_PASID_CTRL_ENABLE \| pdev->pasid_features;
751035b8	451	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
4ebeb1ec	452	}
4ebeb1ec	453
086ac11f JR	454	/**
	455	* pci_pasid_features - Check which PASID features are supported
	456	* @pdev: PCI device structure
	457	*
	458	* Returns a negative value when no PASI capability is present.
	459	* Otherwise is returns a bitmask with supported features. Current
	460	* features reported are:
91f57d5e	461	* PCI_PASID_CAP_EXEC - Execute permission supported
f7625980	462	* PCI_PASID_CAP_PRIV - Privileged mode supported
086ac11f JR	463	*/
	464	int pci_pasid_features(struct pci_dev *pdev)
	465	{
	466	u16 supported;
2e34673b	467	int pasid;
086ac11f	468
2b0ae7cc KS	469	if (pdev->is_virtfn)
	470	pdev = pci_physfn(pdev);
	471
2e34673b	472	pasid = pdev->pasid_cap;
751035b8	473	if (!pasid)
086ac11f JR	474	return -EINVAL;
086ac11f JR	475
751035b8	476	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
086ac11f	477
91f57d5e	478	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	479
	480	return supported;
	481	}
7682ce2b	482	EXPORT_SYMBOL_GPL(pci_pasid_features);
086ac11f	483
086ac11f	484	/**
43395d9e	485	* pci_max_pasids - Get maximum number of PASIDs supported by device
086ac11f JR	486	* @pdev: PCI device structure
	487	*
	488	* Returns negative value when PASID capability is not present.
f6b6aefe	489	* Otherwise it returns the number of supported PASIDs.
086ac11f JR	490	*/
	491	int pci_max_pasids(struct pci_dev *pdev)
	492	{
	493	u16 supported;
2e34673b	494	int pasid;
086ac11f	495
2b0ae7cc KS	496	if (pdev->is_virtfn)
	497	pdev = pci_physfn(pdev);
	498
2e34673b	499	pasid = pdev->pasid_cap;
751035b8	500	if (!pasid)
086ac11f JR	501	return -EINVAL;
086ac11f JR	502
751035b8	503	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
086ac11f	504
e0701bd0	505	return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported));
086ac11f	506	}
7682ce2b	507	EXPORT_SYMBOL_GPL(pci_max_pasids);
086ac11f	508	#endif /* CONFIG_PCI_PASID */