[linux-2.6-block.git] / drivers / pci / ats.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI Express I/O Virtualization (IOV) support
 *   Address Translation Service 1.0
 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
 *
 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
 * Copyright (C) 2011 Advanced Micro Devices,
 */

#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

void pci_ats_init(struct pci_dev *dev)
{
	int pos;

	if (pci_ats_disabled())
		return;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	if (!pos)
		return;

	dev->ats_cap = pos;
}

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	u16 ctrl;
	struct pci_dev *pdev;

	if (!dev->ats_cap)
		return -EINVAL;

	if (WARN_ON(dev->ats_enabled))
		return -EBUSY;

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	/*
	 * Note that enabling ATS on a VF fails unless it's already enabled
	 * with the same STU on the PF.
	 */
	ctrl = PCI_ATS_CTRL_ENABLE;
	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		if (pdev->ats_stu != ps)
			return -EINVAL;

		atomic_inc(&pdev->ats_ref_cnt);  /* count enabled VFs */
	} else {
		dev->ats_stu = ps;
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	}
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 1;
	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);

/**
 * pci_disable_ats - disable the ATS capability
 * @dev: the PCI device
 */
void pci_disable_ats(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 ctrl;

	if (WARN_ON(!dev->ats_enabled))
		return;

	if (atomic_read(&dev->ats_ref_cnt))
		return;		/* VFs still enabled */

	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		atomic_dec(&pdev->ats_ref_cnt);
	}

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
	ctrl &= ~PCI_ATS_CTRL_ENABLE;
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_ats);

void pci_restore_ats_state(struct pci_dev *dev)
{
	u16 ctrl;

	if (!dev->ats_enabled)
		return;

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
}
EXPORT_SYMBOL_GPL(pci_restore_ats_state);

/**
 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
 * @dev: the PCI device
 *
 * Returns the queue depth on success, or negative on failure.
 *
 * The ATS spec uses 0 in the Invalidate Queue Depth field to
 * indicate that the function can accept 32 Invalidate Request.
 * But here we use the `real' values (i.e. 1~32) for the Queue
 * Depth; and 0 indicates the function shares the Queue with
 * other functions (doesn't exclusively own a Queue).
 */
int pci_ats_queue_depth(struct pci_dev *dev)
{
	u16 cap;

	if (!dev->ats_cap)
		return -EINVAL;

	if (dev->is_virtfn)
		return 0;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
}
EXPORT_SYMBOL_GPL(pci_ats_queue_depth);

#ifdef CONFIG_PCI_PRI
/**
 * pci_enable_pri - Enable PRI capability
 * @ pdev: PCI device structure
 *
 * Returns 0 on success, negative value on error
 */
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
	u16 control, status;
	u32 max_requests;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	if (!(status & PCI_PRI_STATUS_STOPPED))
		return -EBUSY;

	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
	reqs = min(max_requests, reqs);
	pdev->pri_reqs_alloc = reqs;
	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);

	control = PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pri);

/**
 * pci_disable_pri - Disable PRI capability
 * @pdev: PCI device structure
 *
 * Only clears the enabled-bit, regardless of its former value
 */
void pci_disable_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(!pdev->pri_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	control &= ~PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pri);

/**
 * pci_restore_pri_state - Restore PRI
 * @pdev: PCI device structure
 */
void pci_restore_pri_state(struct pci_dev *pdev)
{
	u16 control = PCI_PRI_CTRL_ENABLE;
	u32 reqs = pdev->pri_reqs_alloc;
	int pos;

	if (!pdev->pri_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pri_state);

/**
 * pci_reset_pri - Resets device's PRI state
 * @pdev: PCI device structure
 *
 * The PRI capability must be disabled before this function is called.
 * Returns 0 on success, negative value on error.
 */
int pci_reset_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	control = PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	return 0;
}
EXPORT_SYMBOL_GPL(pci_reset_pri);
#endif /* CONFIG_PCI_PRI */

#ifdef CONFIG_PCI_PASID
/**
 * pci_enable_pasid - Enable the PASID capability
 * @pdev: PCI device structure
 * @features: Features to enable
 *
 * Returns 0 on success, negative value on error. This function checks
 * whether the features are actually supported by the device and returns
 * an error if not.
 */
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
	u16 control, supported;
	int pos;

	if (WARN_ON(pdev->pasid_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	/* User wants to enable anything unsupported? */
	if ((supported & features) != features)
		return -EINVAL;

	control = PCI_PASID_CTRL_ENABLE | features;
	pdev->pasid_features = features;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);

/**
 * pci_disable_pasid - Disable the PASID capability
 * @pdev: PCI device structure
 */
void pci_disable_pasid(struct pci_dev *pdev)
{
	u16 control = 0;
	int pos;

	if (WARN_ON(!pdev->pasid_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);

/**
 * pci_restore_pasid_state - Restore PASID capabilities
 * @pdev: PCI device structure
 */
void pci_restore_pasid_state(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (!pdev->pasid_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pasid_state);

/**
 * pci_pasid_features - Check which PASID features are supported
 * @pdev: PCI device structure
 *
 * Returns a negative value when no PASI capability is present.
 * Otherwise is returns a bitmask with supported features. Current
 * features reported are:
 * PCI_PASID_CAP_EXEC - Execute permission supported
 * PCI_PASID_CAP_PRIV - Privileged mode supported
 */
int pci_pasid_features(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);

#define PASID_NUMBER_SHIFT	8
#define PASID_NUMBER_MASK	(0x1f << PASID_NUMBER_SHIFT)
/**
 * pci_max_pasid - Get maximum number of PASIDs supported by device
 * @pdev: PCI device structure
 *
 * Returns negative value when PASID capability is not present.
 * Otherwise it returns the numer of supported PASIDs.
 */
int pci_max_pasids(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;

	return (1 << supported);
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
db3c33c6	2	/*
df62ab5e	3	* PCI Express I/O Virtualization (IOV) support
db3c33c6	4	* Address Translation Service 1.0
c320b976	5	* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
086ac11f	6	* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
df62ab5e BH	7	*
	8	* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
	9	* Copyright (C) 2011 Advanced Micro Devices,
db3c33c6 JR	10	*/
db3c33c6 JR	11
363c75db	12	#include <linux/export.h>
db3c33c6 JR	13	#include <linux/pci-ats.h>
db3c33c6 JR	14	#include <linux/pci.h>
8c451945	15	#include <linux/slab.h>
db3c33c6 JR	16
	17	#include "pci.h"
	18
afdd596c	19	void pci_ats_init(struct pci_dev *dev)
db3c33c6 JR	20	{
db3c33c6 JR	21	int pos;
db3c33c6	22
cef74409 GK	23	if (pci_ats_disabled())
	24	return;
	25
db3c33c6 JR	26	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
db3c33c6 JR	27	if (!pos)
edc90fee	28	return;
db3c33c6	29
d544d75a	30	dev->ats_cap = pos;
db3c33c6 JR	31	}
	32
	33	/**
	34	* pci_enable_ats - enable the ATS capability
	35	* @dev: the PCI device
	36	* @ps: the IOMMU page shift
	37	*
	38	* Returns 0 on success, or negative on failure.
	39	*/
	40	int pci_enable_ats(struct pci_dev *dev, int ps)
	41	{
db3c33c6	42	u16 ctrl;
c39127db	43	struct pci_dev *pdev;
db3c33c6	44
d544d75a	45	if (!dev->ats_cap)
edc90fee BH	46	return -EINVAL;
edc90fee BH	47
f7ef1340	48	if (WARN_ON(dev->ats_enabled))
a021f301 BH	49	return -EBUSY;
a021f301 BH	50
db3c33c6 JR	51	if (ps < PCI_ATS_MIN_STU)
	52	return -EINVAL;
	53
edc90fee BH	54	/*
	55	* Note that enabling ATS on a VF fails unless it's already enabled
	56	* with the same STU on the PF.
	57	*/
	58	ctrl = PCI_ATS_CTRL_ENABLE;
	59	if (dev->is_virtfn) {
c39127db	60	pdev = pci_physfn(dev);
d544d75a	61	if (pdev->ats_stu != ps)
edc90fee	62	return -EINVAL;
db3c33c6	63
d544d75a	64	atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
edc90fee	65	} else {
d544d75a BH	66	dev->ats_stu = ps;
d544d75a BH	67	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
db3c33c6	68	}
d544d75a	69	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	70
d544d75a	71	dev->ats_enabled = 1;
db3c33c6 JR	72	return 0;
db3c33c6 JR	73	}
d4c0636c	74	EXPORT_SYMBOL_GPL(pci_enable_ats);
db3c33c6 JR	75
	76	/**
	77	* pci_disable_ats - disable the ATS capability
	78	* @dev: the PCI device
	79	*/
	80	void pci_disable_ats(struct pci_dev *dev)
	81	{
c39127db	82	struct pci_dev *pdev;
db3c33c6 JR	83	u16 ctrl;
db3c33c6 JR	84
f7ef1340	85	if (WARN_ON(!dev->ats_enabled))
a021f301	86	return;
db3c33c6	87
d544d75a	88	if (atomic_read(&dev->ats_ref_cnt))
edc90fee BH	89	return; /* VFs still enabled */
	90
	91	if (dev->is_virtfn) {
c39127db	92	pdev = pci_physfn(dev);
d544d75a	93	atomic_dec(&pdev->ats_ref_cnt);
edc90fee BH	94	}
edc90fee BH	95
d544d75a	96	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
db3c33c6	97	ctrl &= ~PCI_ATS_CTRL_ENABLE;
d544d75a	98	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	99
d544d75a	100	dev->ats_enabled = 0;
db3c33c6	101	}
d4c0636c	102	EXPORT_SYMBOL_GPL(pci_disable_ats);
db3c33c6	103
1900ca13 HX	104	void pci_restore_ats_state(struct pci_dev *dev)
	105	{
	106	u16 ctrl;
	107
f7ef1340	108	if (!dev->ats_enabled)
1900ca13	109	return;
1900ca13 HX	110
	111	ctrl = PCI_ATS_CTRL_ENABLE;
	112	if (!dev->is_virtfn)
d544d75a BH	113	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
d544d75a BH	114	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
1900ca13 HX	115	}
	116	EXPORT_SYMBOL_GPL(pci_restore_ats_state);
	117
db3c33c6 JR	118	/**
	119	* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
	120	* @dev: the PCI device
	121	*
	122	* Returns the queue depth on success, or negative on failure.
	123	*
	124	* The ATS spec uses 0 in the Invalidate Queue Depth field to
	125	* indicate that the function can accept 32 Invalidate Request.
	126	* But here we use the `real' values (i.e. 1~32) for the Queue
	127	* Depth; and 0 indicates the function shares the Queue with
	128	* other functions (doesn't exclusively own a Queue).
	129	*/
	130	int pci_ats_queue_depth(struct pci_dev *dev)
	131	{
a71f938f BH	132	u16 cap;
a71f938f BH	133
3c765399 BH	134	if (!dev->ats_cap)
	135	return -EINVAL;
	136
db3c33c6 JR	137	if (dev->is_virtfn)
	138	return 0;
	139
a71f938f BH	140	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
a71f938f BH	141	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
db3c33c6	142	}
d4c0636c	143	EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
c320b976 JR	144
	145	#ifdef CONFIG_PCI_PRI
	146	/**
	147	* pci_enable_pri - Enable PRI capability
	148	* @ pdev: PCI device structure
	149	*
	150	* Returns 0 on success, negative value on error
	151	*/
	152	int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
	153	{
	154	u16 control, status;
	155	u32 max_requests;
	156	int pos;
	157
a4f4fa68 JPB	158	if (WARN_ON(pdev->pri_enabled))
	159	return -EBUSY;
	160
69166fbf	161	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	162	if (!pos)
	163	return -EINVAL;
	164
91f57d5e	165	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
4ebeb1ec	166	if (!(status & PCI_PRI_STATUS_STOPPED))
c320b976 JR	167	return -EBUSY;
c320b976 JR	168
91f57d5e	169	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
c320b976	170	reqs = min(max_requests, reqs);
4ebeb1ec	171	pdev->pri_reqs_alloc = reqs;
91f57d5e	172	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
c320b976	173
4ebeb1ec	174	control = PCI_PRI_CTRL_ENABLE;
91f57d5e	175	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976	176
a4f4fa68 JPB	177	pdev->pri_enabled = 1;
a4f4fa68 JPB	178
c320b976 JR	179	return 0;
	180	}
	181	EXPORT_SYMBOL_GPL(pci_enable_pri);
	182
	183	/**
	184	* pci_disable_pri - Disable PRI capability
	185	* @pdev: PCI device structure
	186	*
	187	* Only clears the enabled-bit, regardless of its former value
	188	*/
	189	void pci_disable_pri(struct pci_dev *pdev)
	190	{
	191	u16 control;
	192	int pos;
	193
a4f4fa68 JPB	194	if (WARN_ON(!pdev->pri_enabled))
	195	return;
	196
69166fbf	197	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	198	if (!pos)
	199	return;
	200
91f57d5e AW	201	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	202	control &= ~PCI_PRI_CTRL_ENABLE;
	203	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
a4f4fa68 JPB	204
a4f4fa68 JPB	205	pdev->pri_enabled = 0;
c320b976 JR	206	}
	207	EXPORT_SYMBOL_GPL(pci_disable_pri);
	208
4ebeb1ec CT	209	/**
	210	* pci_restore_pri_state - Restore PRI
	211	* @pdev: PCI device structure
	212	*/
	213	void pci_restore_pri_state(struct pci_dev *pdev)
	214	{
	215	u16 control = PCI_PRI_CTRL_ENABLE;
	216	u32 reqs = pdev->pri_reqs_alloc;
	217	int pos;
	218
	219	if (!pdev->pri_enabled)
	220	return;
	221
	222	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	223	if (!pos)
	224	return;
	225
	226	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	227	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	228	}
	229	EXPORT_SYMBOL_GPL(pci_restore_pri_state);
	230
c320b976 JR	231	/**
	232	* pci_reset_pri - Resets device's PRI state
	233	* @pdev: PCI device structure
	234	*
	235	* The PRI capability must be disabled before this function is called.
	236	* Returns 0 on success, negative value on error.
	237	*/
	238	int pci_reset_pri(struct pci_dev *pdev)
	239	{
	240	u16 control;
	241	int pos;
	242
a4f4fa68 JPB	243	if (WARN_ON(pdev->pri_enabled))
	244	return -EBUSY;
	245
69166fbf	246	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	247	if (!pos)
	248	return -EINVAL;
	249
4ebeb1ec	250	control = PCI_PRI_CTRL_RESET;
91f57d5e	251	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976 JR	252
	253	return 0;
	254	}
	255	EXPORT_SYMBOL_GPL(pci_reset_pri);
c320b976	256	#endif /* CONFIG_PCI_PRI */
086ac11f JR	257
	258	#ifdef CONFIG_PCI_PASID
	259	/**
	260	* pci_enable_pasid - Enable the PASID capability
	261	* @pdev: PCI device structure
	262	* @features: Features to enable
	263	*
	264	* Returns 0 on success, negative value on error. This function checks
	265	* whether the features are actually supported by the device and returns
	266	* an error if not.
	267	*/
	268	int pci_enable_pasid(struct pci_dev *pdev, int features)
	269	{
	270	u16 control, supported;
	271	int pos;
	272
a4f4fa68 JPB	273	if (WARN_ON(pdev->pasid_enabled))
	274	return -EBUSY;
	275
69166fbf	276	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	277	if (!pos)
	278	return -EINVAL;
	279
91f57d5e	280	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
91f57d5e	281	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	282
	283	/* User wants to enable anything unsupported? */
	284	if ((supported & features) != features)
	285	return -EINVAL;
	286
91f57d5e	287	control = PCI_PASID_CTRL_ENABLE \| features;
4ebeb1ec	288	pdev->pasid_features = features;
086ac11f	289
91f57d5e	290	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
086ac11f	291
a4f4fa68 JPB	292	pdev->pasid_enabled = 1;
a4f4fa68 JPB	293
086ac11f JR	294	return 0;
	295	}
	296	EXPORT_SYMBOL_GPL(pci_enable_pasid);
	297
	298	/**
	299	* pci_disable_pasid - Disable the PASID capability
	300	* @pdev: PCI device structure
086ac11f JR	301	*/
	302	void pci_disable_pasid(struct pci_dev *pdev)
	303	{
	304	u16 control = 0;
	305	int pos;
	306
a4f4fa68 JPB	307	if (WARN_ON(!pdev->pasid_enabled))
	308	return;
	309
69166fbf	310	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	311	if (!pos)
	312	return;
	313
91f57d5e	314	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
a4f4fa68 JPB	315
a4f4fa68 JPB	316	pdev->pasid_enabled = 0;
086ac11f JR	317	}
	318	EXPORT_SYMBOL_GPL(pci_disable_pasid);
	319
4ebeb1ec CT	320	/**
	321	* pci_restore_pasid_state - Restore PASID capabilities
	322	* @pdev: PCI device structure
	323	*/
	324	void pci_restore_pasid_state(struct pci_dev *pdev)
	325	{
	326	u16 control;
	327	int pos;
	328
	329	if (!pdev->pasid_enabled)
	330	return;
	331
	332	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	333	if (!pos)
	334	return;
	335
	336	control = PCI_PASID_CTRL_ENABLE \| pdev->pasid_features;
	337	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
	338	}
	339	EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
	340
086ac11f JR	341	/**
	342	* pci_pasid_features - Check which PASID features are supported
	343	* @pdev: PCI device structure
	344	*
	345	* Returns a negative value when no PASI capability is present.
	346	* Otherwise is returns a bitmask with supported features. Current
	347	* features reported are:
91f57d5e	348	* PCI_PASID_CAP_EXEC - Execute permission supported
f7625980	349	* PCI_PASID_CAP_PRIV - Privileged mode supported
086ac11f JR	350	*/
	351	int pci_pasid_features(struct pci_dev *pdev)
	352	{
	353	u16 supported;
	354	int pos;
	355
69166fbf	356	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	357	if (!pos)
	358	return -EINVAL;
	359
91f57d5e	360	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f	361
91f57d5e	362	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	363
	364	return supported;
	365	}
	366	EXPORT_SYMBOL_GPL(pci_pasid_features);
	367
	368	#define PASID_NUMBER_SHIFT 8
	369	#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
	370	/**
	371	* pci_max_pasid - Get maximum number of PASIDs supported by device
	372	* @pdev: PCI device structure
	373	*
	374	* Returns negative value when PASID capability is not present.
	375	* Otherwise it returns the numer of supported PASIDs.
	376	*/
	377	int pci_max_pasids(struct pci_dev *pdev)
	378	{
	379	u16 supported;
	380	int pos;
	381
69166fbf	382	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	383	if (!pos)
	384	return -EINVAL;
	385
91f57d5e	386	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f JR	387
	388	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
	389
	390	return (1 << supported);
	391	}
	392	EXPORT_SYMBOL_GPL(pci_max_pasids);
	393	#endif /* CONFIG_PCI_PASID */