[linux-block.git] / drivers / pci / access.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/wait.h>

#include "pci.h"

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */

DEFINE_RAW_SPINLOCK(pci_lock);

/*
 * Wrappers for all PCI configuration access functions.  They just check
 * alignment, do locking and call the low-level functions pointed to
 * by pci_dev->ops.
 */

#define PCI_byte_BAD 0
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)

#ifdef CONFIG_PCI_LOCKLESS_CONFIG
# define pci_lock_config(f)	do { (void)(f); } while (0)
# define pci_unlock_config(f)	do { (void)(f); } while (0)
#else
# define pci_lock_config(f)	raw_spin_lock_irqsave(&pci_lock, f)
# define pci_unlock_config(f)	raw_spin_unlock_irqrestore(&pci_lock, f)
#endif

#define PCI_OP_READ(size, type, len) \
int noinline pci_bus_read_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type *value)	\
{									\
	int res;							\
	unsigned long flags;						\
	u32 data = 0;							\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	pci_lock_config(flags);						\
	res = bus->ops->read(bus, devfn, pos, len, &data);		\
	*value = (type)data;						\
	pci_unlock_config(flags);					\
	return res;							\
}

#define PCI_OP_WRITE(size, type, len) \
int noinline pci_bus_write_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type value)	\
{									\
	int res;							\
	unsigned long flags;						\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	pci_lock_config(flags);						\
	res = bus->ops->write(bus, devfn, pos, len, value);		\
	pci_unlock_config(flags);					\
	return res;							\
}

PCI_OP_READ(byte, u8, 1)
PCI_OP_READ(word, u16, 2)
PCI_OP_READ(dword, u32, 4)
PCI_OP_WRITE(byte, u8, 1)
PCI_OP_WRITE(word, u16, 2)
PCI_OP_WRITE(dword, u32, 4)

EXPORT_SYMBOL(pci_bus_read_config_byte);
EXPORT_SYMBOL(pci_bus_read_config_word);
EXPORT_SYMBOL(pci_bus_read_config_dword);
EXPORT_SYMBOL(pci_bus_write_config_byte);
EXPORT_SYMBOL(pci_bus_write_config_word);
EXPORT_SYMBOL(pci_bus_write_config_dword);

int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
			    int where, int size, u32 *val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where);
	if (!addr) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (size == 1)
		*val = readb(addr);
	else if (size == 2)
		*val = readw(addr);
	else
		*val = readl(addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_read);

int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
			     int where, int size, u32 val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 1)
		writeb(val, addr);
	else if (size == 2)
		writew(val, addr);
	else
		writel(val, addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_write);

int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
			      int where, int size, u32 *val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	if (!addr) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	*val = readl(addr);

	if (size <= 2)
		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_read32);

int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
			       int where, int size, u32 val)
{
	void __iomem *addr;
	u32 mask, tmp;

	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 4) {
		writel(val, addr);
		return PCIBIOS_SUCCESSFUL;
	}

	/*
	 * In general, hardware that supports only 32-bit writes on PCI is
	 * not spec-compliant.  For example, software may perform a 16-bit
	 * write.  If the hardware only supports 32-bit accesses, we must
	 * do a 32-bit read, merge in the 16 bits we intend to write,
	 * followed by a 32-bit write.  If the 16 bits we *don't* intend to
	 * write happen to have any RW1C (write-one-to-clear) bits set, we
	 * just inadvertently cleared something we shouldn't have.
	 */
	dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
			     size, pci_domain_nr(bus), bus->number,
			     PCI_SLOT(devfn), PCI_FUNC(devfn), where);

	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
	tmp = readl(addr) & mask;
	tmp |= val << ((where & 0x3) * 8);
	writel(tmp, addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_write32);

/**
 * pci_bus_set_ops - Set raw operations of pci bus
 * @bus:	pci bus struct
 * @ops:	new raw operations
 *
 * Return previous raw operations
 */
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
{
	struct pci_ops *old_ops;
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);
	old_ops = bus->ops;
	bus->ops = ops;
	raw_spin_unlock_irqrestore(&pci_lock, flags);
	return old_ops;
}
EXPORT_SYMBOL(pci_bus_set_ops);

/*
 * The following routines are to prevent the user from accessing PCI config
 * space when it's unsafe to do so.  Some devices require this during BIST and
 * we're required to prevent it during D-state transitions.
 *
 * We have a bit per device to indicate it's blocked and a global wait queue
 * for callers to sleep on until devices are unblocked.
 */
static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);

static noinline void pci_wait_cfg(struct pci_dev *dev)
	__must_hold(&pci_lock)
{
	do {
		raw_spin_unlock_irq(&pci_lock);
		wait_event(pci_cfg_wait, !dev->block_cfg_access);
		raw_spin_lock_irq(&pci_lock);
	} while (dev->block_cfg_access);
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_READ_CONFIG(size, type)					\
int pci_user_read_config_##size						\
	(struct pci_dev *dev, int pos, type *val)			\
{									\
	int ret = PCIBIOS_SUCCESSFUL;					\
	u32 data = -1;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->read(dev->bus, dev->devfn,			\
					pos, sizeof(type), &data);	\
	raw_spin_unlock_irq(&pci_lock);				\
	*val = (type)data;						\
	return pcibios_err_to_errno(ret);				\
}									\
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_WRITE_CONFIG(size, type)				\
int pci_user_write_config_##size					\
	(struct pci_dev *dev, int pos, type val)			\
{									\
	int ret = PCIBIOS_SUCCESSFUL;					\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->write(dev->bus, dev->devfn,		\
					pos, sizeof(type), val);	\
	raw_spin_unlock_irq(&pci_lock);				\
	return pcibios_err_to_errno(ret);				\
}									\
EXPORT_SYMBOL_GPL(pci_user_write_config_##size);

PCI_USER_READ_CONFIG(byte, u8)
PCI_USER_READ_CONFIG(word, u16)
PCI_USER_READ_CONFIG(dword, u32)
PCI_USER_WRITE_CONFIG(byte, u8)
PCI_USER_WRITE_CONFIG(word, u16)
PCI_USER_WRITE_CONFIG(dword, u32)

/**
 * pci_cfg_access_lock - Lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * When access is locked, any userspace reads or writes to config
 * space and concurrent lock requests will sleep until access is
 * allowed via pci_cfg_access_unlock() again.
 */
void pci_cfg_access_lock(struct pci_dev *dev)
{
	might_sleep();

	raw_spin_lock_irq(&pci_lock);
	if (dev->block_cfg_access)
		pci_wait_cfg(dev);
	dev->block_cfg_access = 1;
	raw_spin_unlock_irq(&pci_lock);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_lock);

/**
 * pci_cfg_access_trylock - try to lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * Same as pci_cfg_access_lock, but will return 0 if access is
 * already locked, 1 otherwise. This function can be used from
 * atomic contexts.
 */
bool pci_cfg_access_trylock(struct pci_dev *dev)
{
	unsigned long flags;
	bool locked = true;

	raw_spin_lock_irqsave(&pci_lock, flags);
	if (dev->block_cfg_access)
		locked = false;
	else
		dev->block_cfg_access = 1;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	return locked;
}
EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);

/**
 * pci_cfg_access_unlock - Unlock PCI config reads/writes
 * @dev:	pci device struct
 *
 * This function allows PCI config accesses to resume.
 */
void pci_cfg_access_unlock(struct pci_dev *dev)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);

	/*
	 * This indicates a problem in the caller, but we don't need
	 * to kill them, unlike a double-block above.
	 */
	WARN_ON(!dev->block_cfg_access);

	dev->block_cfg_access = 0;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	wake_up_all(&pci_cfg_wait);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);

static inline int pcie_cap_version(const struct pci_dev *dev)
{
	return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
}

bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
	int type = pci_pcie_type(dev);

	return type == PCI_EXP_TYPE_ENDPOINT ||
	       type == PCI_EXP_TYPE_LEG_END ||
	       type == PCI_EXP_TYPE_ROOT_PORT ||
	       type == PCI_EXP_TYPE_UPSTREAM ||
	       type == PCI_EXP_TYPE_DOWNSTREAM ||
	       type == PCI_EXP_TYPE_PCI_BRIDGE ||
	       type == PCI_EXP_TYPE_PCIE_BRIDGE;
}

static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
	return pcie_downstream_port(dev) &&
	       pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
}

bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
	int type = pci_pcie_type(dev);

	return type == PCI_EXP_TYPE_ROOT_PORT ||
	       type == PCI_EXP_TYPE_RC_EC;
}

static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
	if (!pci_is_pcie(dev))
		return false;

	switch (pos) {
	case PCI_EXP_FLAGS:
		return true;
	case PCI_EXP_DEVCAP:
	case PCI_EXP_DEVCTL:
	case PCI_EXP_DEVSTA:
		return true;
	case PCI_EXP_LNKCAP:
	case PCI_EXP_LNKCTL:
	case PCI_EXP_LNKSTA:
		return pcie_cap_has_lnkctl(dev);
	case PCI_EXP_SLTCAP:
	case PCI_EXP_SLTCTL:
	case PCI_EXP_SLTSTA:
		return pcie_cap_has_sltctl(dev);
	case PCI_EXP_RTCTL:
	case PCI_EXP_RTCAP:
	case PCI_EXP_RTSTA:
		return pcie_cap_has_rtctl(dev);
	case PCI_EXP_DEVCAP2:
	case PCI_EXP_DEVCTL2:
	case PCI_EXP_LNKCAP2:
	case PCI_EXP_LNKCTL2:
	case PCI_EXP_LNKSTA2:
		return pcie_cap_version(dev) > 1;
	default:
		return false;
	}
}

/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
	int ret;

	*val = 0;
	if (pos & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (pcie_capability_reg_implemented(dev, pos)) {
		ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
		/*
		 * Reset *val to 0 if pci_read_config_word() fails, it may
		 * have been written as 0xFFFF if hardware error happens
		 * during pci_read_config_word().
		 */
		if (ret)
			*val = 0;
		return ret;
	}

	/*
	 * For Functions that do not implement the Slot Capabilities,
	 * Slot Status, and Slot Control registers, these spaces must
	 * be hardwired to 0b, with the exception of the Presence Detect
	 * State bit in the Slot Status register of Downstream Ports,
	 * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
	 */
	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
	    pos == PCI_EXP_SLTSTA)
		*val = PCI_EXP_SLTSTA_PDS;

	return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);

int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
	int ret;

	*val = 0;
	if (pos & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (pcie_capability_reg_implemented(dev, pos)) {
		ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
		/*
		 * Reset *val to 0 if pci_read_config_dword() fails, it may
		 * have been written as 0xFFFFFFFF if hardware error happens
		 * during pci_read_config_dword().
		 */
		if (ret)
			*val = 0;
		return ret;
	}

	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
	    pos == PCI_EXP_SLTSTA)
		*val = PCI_EXP_SLTSTA_PDS;

	return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);

int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
	if (pos & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!pcie_capability_reg_implemented(dev, pos))
		return 0;

	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);

int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
	if (pos & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!pcie_capability_reg_implemented(dev, pos))
		return 0;

	return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);

int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
				       u16 clear, u16 set)
{
	int ret;
	u16 val;

	ret = pcie_capability_read_word(dev, pos, &val);
	if (!ret) {
		val &= ~clear;
		val |= set;
		ret = pcie_capability_write_word(dev, pos, val);
	}

	return ret;
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);

int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
					u32 clear, u32 set)
{
	int ret;
	u32 val;

	ret = pcie_capability_read_dword(dev, pos, &val);
	if (!ret) {
		val &= ~clear;
		val |= set;
		ret = pcie_capability_write_dword(dev, pos, val);
	}

	return ret;
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);

int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_byte);

int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_word);

int pci_read_config_dword(const struct pci_dev *dev, int where,
					u32 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_dword);

int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_byte);

int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_word);

int pci_write_config_dword(const struct pci_dev *dev, int where,
					 u32 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_dword);
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	#include <linux/pci.h>
1da177e4 LT	3	#include <linux/module.h>
5a0e3ad6	4	#include <linux/slab.h>
1da177e4	5	#include <linux/ioport.h>
7ea7e98f	6	#include <linux/wait.h>
1da177e4	7
48b19148 AB	8	#include "pci.h"
48b19148 AB	9
1da177e4 LT	10	/*
	11	* This interrupt-safe spinlock protects all accesses to PCI
	12	* configuration space.
	13	*/
	14
a2e27787	15	DEFINE_RAW_SPINLOCK(pci_lock);
1da177e4 LT	16
1da177e4 LT	17	/*
df62ab5e BH	18	* Wrappers for all PCI configuration access functions. They just check
	19	* alignment, do locking and call the low-level functions pointed to
	20	* by pci_dev->ops.
1da177e4 LT	21	*/
	22
	23	#define PCI_byte_BAD 0
	24	#define PCI_word_BAD (pos & 1)
	25	#define PCI_dword_BAD (pos & 3)
	26
714fe383 TG	27	#ifdef CONFIG_PCI_LOCKLESS_CONFIG
	28	# define pci_lock_config(f) do { (void)(f); } while (0)
	29	# define pci_unlock_config(f) do { (void)(f); } while (0)
	30	#else
	31	# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
	32	# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
	33	#endif
	34
ff3ce480	35	#define PCI_OP_READ(size, type, len) \
5180fd91	36	int noinline pci_bus_read_config_##size \
1da177e4 LT	37	(struct pci_bus bus, unsigned int devfn, int pos, type value) \
	38	{ \
	39	int res; \
	40	unsigned long flags; \
	41	u32 data = 0; \
	42	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
714fe383	43	pci_lock_config(flags); \
1da177e4 LT	44	res = bus->ops->read(bus, devfn, pos, len, &data); \
1da177e4 LT	45	*value = (type)data; \
714fe383	46	pci_unlock_config(flags); \
1da177e4 LT	47	return res; \
	48	}
	49
ff3ce480	50	#define PCI_OP_WRITE(size, type, len) \
5180fd91	51	int noinline pci_bus_write_config_##size \
1da177e4 LT	52	(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
	53	{ \
	54	int res; \
	55	unsigned long flags; \
	56	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
714fe383	57	pci_lock_config(flags); \
1da177e4	58	res = bus->ops->write(bus, devfn, pos, len, value); \
714fe383	59	pci_unlock_config(flags); \
1da177e4 LT	60	return res; \
	61	}
	62
	63	PCI_OP_READ(byte, u8, 1)
	64	PCI_OP_READ(word, u16, 2)
	65	PCI_OP_READ(dword, u32, 4)
	66	PCI_OP_WRITE(byte, u8, 1)
	67	PCI_OP_WRITE(word, u16, 2)
	68	PCI_OP_WRITE(dword, u32, 4)
	69
	70	EXPORT_SYMBOL(pci_bus_read_config_byte);
	71	EXPORT_SYMBOL(pci_bus_read_config_word);
	72	EXPORT_SYMBOL(pci_bus_read_config_dword);
	73	EXPORT_SYMBOL(pci_bus_write_config_byte);
	74	EXPORT_SYMBOL(pci_bus_write_config_word);
	75	EXPORT_SYMBOL(pci_bus_write_config_dword);
e04b0ea2	76
1f94a94f RH	77	int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
	78	int where, int size, u32 *val)
	79	{
	80	void __iomem *addr;
	81
	82	addr = bus->ops->map_bus(bus, devfn, where);
	83	if (!addr) {
	84	*val = ~0;
	85	return PCIBIOS_DEVICE_NOT_FOUND;
	86	}
	87
	88	if (size == 1)
	89	*val = readb(addr);
	90	else if (size == 2)
	91	*val = readw(addr);
	92	else
	93	*val = readl(addr);
	94
	95	return PCIBIOS_SUCCESSFUL;
	96	}
	97	EXPORT_SYMBOL_GPL(pci_generic_config_read);
	98
	99	int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
	100	int where, int size, u32 val)
	101	{
	102	void __iomem *addr;
	103
	104	addr = bus->ops->map_bus(bus, devfn, where);
	105	if (!addr)
	106	return PCIBIOS_DEVICE_NOT_FOUND;
	107
	108	if (size == 1)
	109	writeb(val, addr);
	110	else if (size == 2)
	111	writew(val, addr);
	112	else
	113	writel(val, addr);
	114
	115	return PCIBIOS_SUCCESSFUL;
	116	}
	117	EXPORT_SYMBOL_GPL(pci_generic_config_write);
	118
	119	int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
	120	int where, int size, u32 *val)
	121	{
	122	void __iomem *addr;
	123
	124	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	125	if (!addr) {
	126	*val = ~0;
	127	return PCIBIOS_DEVICE_NOT_FOUND;
	128	}
	129
	130	*val = readl(addr);
	131
	132	if (size <= 2)
	133	val = (val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
	134
	135	return PCIBIOS_SUCCESSFUL;
	136	}
	137	EXPORT_SYMBOL_GPL(pci_generic_config_read32);
	138
	139	int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
	140	int where, int size, u32 val)
141	{
142	void __iomem *addr;
143	u32 mask, tmp;
144
145	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
146	if (!addr)
147	return PCIBIOS_DEVICE_NOT_FOUND;
148
149	if (size == 4) {
150	writel(val, addr);
151	return PCIBIOS_SUCCESSFUL;
1f94a94f RH	152	}
1f94a94f RH	153
fb265923 BH	154	/*
	155	* In general, hardware that supports only 32-bit writes on PCI is
	156	* not spec-compliant. For example, software may perform a 16-bit
	157	* write. If the hardware only supports 32-bit accesses, we must
	158	* do a 32-bit read, merge in the 16 bits we intend to write,
	159	* followed by a 32-bit write. If the 16 bits we don't intend to
	160	* write happen to have any RW1C (write-one-to-clear) bits set, we
	161	* just inadvertently cleared something we shouldn't have.
	162	*/
	163	dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
	164	size, pci_domain_nr(bus), bus->number,
	165	PCI_SLOT(devfn), PCI_FUNC(devfn), where);
	166
	167	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
1f94a94f RH	168	tmp = readl(addr) & mask;
	169	tmp \|= val << ((where & 0x3) * 8);
	170	writel(tmp, addr);
	171
	172	return PCIBIOS_SUCCESSFUL;
	173	}
	174	EXPORT_SYMBOL_GPL(pci_generic_config_write32);
	175
a72b46c3 HY	176	/**
	177	* pci_bus_set_ops - Set raw operations of pci bus
	178	* @bus: pci bus struct
	179	* @ops: new raw operations
	180	*
	181	* Return previous raw operations
	182	*/
	183	struct pci_ops pci_bus_set_ops(struct pci_bus bus, struct pci_ops *ops)
	184	{
	185	struct pci_ops *old_ops;
	186	unsigned long flags;
	187
511dd98c	188	raw_spin_lock_irqsave(&pci_lock, flags);
a72b46c3 HY	189	old_ops = bus->ops;
a72b46c3 HY	190	bus->ops = ops;
511dd98c	191	raw_spin_unlock_irqrestore(&pci_lock, flags);
a72b46c3 HY	192	return old_ops;
	193	}
	194	EXPORT_SYMBOL(pci_bus_set_ops);
287d19ce	195
7ea7e98f MW	196	/*
	197	* The following routines are to prevent the user from accessing PCI config
	198	* space when it's unsafe to do so. Some devices require this during BIST and
	199	* we're required to prevent it during D-state transitions.
	200	*
	201	* We have a bit per device to indicate it's blocked and a global wait queue
	202	* for callers to sleep on until devices are unblocked.
	203	*/
fb51ccbf	204	static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
e04b0ea2	205
fb51ccbf	206	static noinline void pci_wait_cfg(struct pci_dev *dev)
2a7e32d0	207	__must_hold(&pci_lock)
7ea7e98f	208	{
7ea7e98f	209	do {
511dd98c	210	raw_spin_unlock_irq(&pci_lock);
2a7e32d0	211	wait_event(pci_cfg_wait, !dev->block_cfg_access);
511dd98c	212	raw_spin_lock_irq(&pci_lock);
fb51ccbf	213	} while (dev->block_cfg_access);
e04b0ea2 BK	214	}
e04b0ea2 BK	215
34e32072	216	/* Returns 0 on success, negative values indicate error. */
ff3ce480	217	#define PCI_USER_READ_CONFIG(size, type) \
e04b0ea2 BK	218	int pci_user_read_config_##size \
	219	(struct pci_dev dev, int pos, type val) \
	220	{ \
d97ffe23	221	int ret = PCIBIOS_SUCCESSFUL; \
e04b0ea2	222	u32 data = -1; \
34e32072 GT	223	if (PCI_##size##_BAD) \
34e32072 GT	224	return -EINVAL; \
511dd98c	225	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	226	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	227	pci_wait_cfg(dev); \
7ea7e98f	228	ret = dev->bus->ops->read(dev->bus, dev->devfn, \
e04b0ea2	229	pos, sizeof(type), &data); \
511dd98c	230	raw_spin_unlock_irq(&pci_lock); \
e04b0ea2	231	*val = (type)data; \
d97ffe23	232	return pcibios_err_to_errno(ret); \
c63587d7 AW	233	} \
c63587d7 AW	234	EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
e04b0ea2	235
34e32072	236	/* Returns 0 on success, negative values indicate error. */
ff3ce480	237	#define PCI_USER_WRITE_CONFIG(size, type) \
e04b0ea2 BK	238	int pci_user_write_config_##size \
	239	(struct pci_dev *dev, int pos, type val) \
	240	{ \
d97ffe23	241	int ret = PCIBIOS_SUCCESSFUL; \
34e32072 GT	242	if (PCI_##size##_BAD) \
34e32072 GT	243	return -EINVAL; \
511dd98c	244	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	245	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	246	pci_wait_cfg(dev); \
7ea7e98f	247	ret = dev->bus->ops->write(dev->bus, dev->devfn, \
e04b0ea2	248	pos, sizeof(type), val); \
511dd98c	249	raw_spin_unlock_irq(&pci_lock); \
d97ffe23	250	return pcibios_err_to_errno(ret); \
c63587d7 AW	251	} \
c63587d7 AW	252	EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
e04b0ea2 BK	253
	254	PCI_USER_READ_CONFIG(byte, u8)
	255	PCI_USER_READ_CONFIG(word, u16)
	256	PCI_USER_READ_CONFIG(dword, u32)
	257	PCI_USER_WRITE_CONFIG(byte, u8)
	258	PCI_USER_WRITE_CONFIG(word, u16)
	259	PCI_USER_WRITE_CONFIG(dword, u32)
	260
	261	/**
fb51ccbf	262	* pci_cfg_access_lock - Lock PCI config reads/writes
e04b0ea2 BK	263	* @dev: pci device struct
e04b0ea2 BK	264	*
fb51ccbf JK	265	* When access is locked, any userspace reads or writes to config
fb51ccbf JK	266	* space and concurrent lock requests will sleep until access is
0b131b13	267	* allowed via pci_cfg_access_unlock() again.
7ea7e98f	268	*/
fb51ccbf JK	269	void pci_cfg_access_lock(struct pci_dev *dev)
	270	{
	271	might_sleep();
	272
	273	raw_spin_lock_irq(&pci_lock);
	274	if (dev->block_cfg_access)
	275	pci_wait_cfg(dev);
	276	dev->block_cfg_access = 1;
	277	raw_spin_unlock_irq(&pci_lock);
	278	}
	279	EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
	280
	281	/**
	282	* pci_cfg_access_trylock - try to lock PCI config reads/writes
	283	* @dev: pci device struct
	284	*
	285	* Same as pci_cfg_access_lock, but will return 0 if access is
	286	* already locked, 1 otherwise. This function can be used from
	287	* atomic contexts.
	288	*/
	289	bool pci_cfg_access_trylock(struct pci_dev *dev)
e04b0ea2 BK	290	{
e04b0ea2 BK	291	unsigned long flags;
fb51ccbf	292	bool locked = true;
e04b0ea2	293
511dd98c	294	raw_spin_lock_irqsave(&pci_lock, flags);
fb51ccbf JK	295	if (dev->block_cfg_access)
	296	locked = false;
	297	else
	298	dev->block_cfg_access = 1;
511dd98c	299	raw_spin_unlock_irqrestore(&pci_lock, flags);
7ea7e98f	300
fb51ccbf	301	return locked;
e04b0ea2	302	}
fb51ccbf	303	EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
e04b0ea2 BK	304
e04b0ea2 BK	305	/**
fb51ccbf	306	* pci_cfg_access_unlock - Unlock PCI config reads/writes
e04b0ea2 BK	307	* @dev: pci device struct
e04b0ea2 BK	308	*
fb51ccbf	309	* This function allows PCI config accesses to resume.
7ea7e98f	310	*/
fb51ccbf	311	void pci_cfg_access_unlock(struct pci_dev *dev)
e04b0ea2 BK	312	{
	313	unsigned long flags;
	314
511dd98c	315	raw_spin_lock_irqsave(&pci_lock, flags);
7ea7e98f	316
df62ab5e BH	317	/*
	318	* This indicates a problem in the caller, but we don't need
	319	* to kill them, unlike a double-block above.
	320	*/
fb51ccbf	321	WARN_ON(!dev->block_cfg_access);
7ea7e98f	322
fb51ccbf	323	dev->block_cfg_access = 0;
511dd98c	324	raw_spin_unlock_irqrestore(&pci_lock, flags);
cdcb33f9 BH	325
cdcb33f9 BH	326	wake_up_all(&pci_cfg_wait);
e04b0ea2	327	}
fb51ccbf	328	EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
8c0d3a02 JL	329
	330	static inline int pcie_cap_version(const struct pci_dev *dev)
	331	{
1c531d82	332	return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
8c0d3a02 JL	333	}
8c0d3a02 JL	334
7a1562d4	335	bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
8c0d3a02 JL	336	{
	337	int type = pci_pcie_type(dev);
	338
c8b303d0	339	return type == PCI_EXP_TYPE_ENDPOINT \|\|
d3694d4f BH	340	type == PCI_EXP_TYPE_LEG_END \|\|
	341	type == PCI_EXP_TYPE_ROOT_PORT \|\|
	342	type == PCI_EXP_TYPE_UPSTREAM \|\|
	343	type == PCI_EXP_TYPE_DOWNSTREAM \|\|
	344	type == PCI_EXP_TYPE_PCI_BRIDGE \|\|
	345	type == PCI_EXP_TYPE_PCIE_BRIDGE;
8c0d3a02 JL	346	}
	347
	348	static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
	349	{
ffb4d602	350	return pcie_downstream_port(dev) &&
6d3a1741	351	pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
8c0d3a02 JL	352	}
8c0d3a02 JL	353
af65d1ad	354	bool pcie_cap_has_rtctl(const struct pci_dev *dev)
8c0d3a02 JL	355	{
	356	int type = pci_pcie_type(dev);
	357
c8b303d0	358	return type == PCI_EXP_TYPE_ROOT_PORT \|\|
8c0d3a02 JL	359	type == PCI_EXP_TYPE_RC_EC;
	360	}
	361
	362	static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
	363	{
	364	if (!pci_is_pcie(dev))
	365	return false;
	366
	367	switch (pos) {
969daa34	368	case PCI_EXP_FLAGS:
8c0d3a02 JL	369	return true;
	370	case PCI_EXP_DEVCAP:
	371	case PCI_EXP_DEVCTL:
	372	case PCI_EXP_DEVSTA:
fed24515	373	return true;
8c0d3a02 JL	374	case PCI_EXP_LNKCAP:
	375	case PCI_EXP_LNKCTL:
	376	case PCI_EXP_LNKSTA:
	377	return pcie_cap_has_lnkctl(dev);
	378	case PCI_EXP_SLTCAP:
	379	case PCI_EXP_SLTCTL:
	380	case PCI_EXP_SLTSTA:
	381	return pcie_cap_has_sltctl(dev);
	382	case PCI_EXP_RTCTL:
	383	case PCI_EXP_RTCAP:
	384	case PCI_EXP_RTSTA:
	385	return pcie_cap_has_rtctl(dev);
	386	case PCI_EXP_DEVCAP2:
	387	case PCI_EXP_DEVCTL2:
	388	case PCI_EXP_LNKCAP2:
	389	case PCI_EXP_LNKCTL2:
	390	case PCI_EXP_LNKSTA2:
	391	return pcie_cap_version(dev) > 1;
	392	default:
	393	return false;
	394	}
	395	}
	396
	397	/*
	398	* Note that these accessor functions are only for the "PCI Express
	399	* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
	400	* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
	401	*/
	402	int pcie_capability_read_word(struct pci_dev dev, int pos, u16 val)
	403	{
	404	int ret;
	405
	406	*val = 0;
	407	if (pos & 1)
b9153581	408	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	409
	410	if (pcie_capability_reg_implemented(dev, pos)) {
	411	ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
	412	/*
	413	* Reset *val to 0 if pci_read_config_word() fails, it may
	414	* have been written as 0xFFFF if hardware error happens
	415	* during pci_read_config_word().
	416	*/
	417	if (ret)
	418	*val = 0;
	419	return ret;
	420	}
	421
	422	/*
	423	* For Functions that do not implement the Slot Capabilities,
	424	* Slot Status, and Slot Control registers, these spaces must
	425	* be hardwired to 0b, with the exception of the Presence Detect
	426	* State bit in the Slot Status register of Downstream Ports,
	427	* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
	428	*/
ffb4d602 BH	429	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
ffb4d602 BH	430	pos == PCI_EXP_SLTSTA)
8c0d3a02	431	*val = PCI_EXP_SLTSTA_PDS;
8c0d3a02 JL	432
	433	return 0;
	434	}
	435	EXPORT_SYMBOL(pcie_capability_read_word);
	436
	437	int pcie_capability_read_dword(struct pci_dev dev, int pos, u32 val)
	438	{
	439	int ret;
	440
	441	*val = 0;
	442	if (pos & 3)
b9153581	443	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	444
	445	if (pcie_capability_reg_implemented(dev, pos)) {
	446	ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
	447	/*
	448	* Reset *val to 0 if pci_read_config_dword() fails, it may
	449	* have been written as 0xFFFFFFFF if hardware error happens
	450	* during pci_read_config_dword().
	451	*/
	452	if (ret)
	453	*val = 0;
	454	return ret;
	455	}
	456
ffb4d602 BH	457	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
ffb4d602 BH	458	pos == PCI_EXP_SLTSTA)
8c0d3a02	459	*val = PCI_EXP_SLTSTA_PDS;
8c0d3a02 JL	460
	461	return 0;
	462	}
	463	EXPORT_SYMBOL(pcie_capability_read_dword);
	464
	465	int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
	466	{
	467	if (pos & 1)
b9153581	468	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	469
	470	if (!pcie_capability_reg_implemented(dev, pos))
	471	return 0;
	472
	473	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
	474	}
	475	EXPORT_SYMBOL(pcie_capability_write_word);
	476
	477	int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
	478	{
	479	if (pos & 3)
b9153581	480	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	481
	482	if (!pcie_capability_reg_implemented(dev, pos))
	483	return 0;
	484
	485	return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
	486	}
	487	EXPORT_SYMBOL(pcie_capability_write_dword);
	488
	489	int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
	490	u16 clear, u16 set)
	491	{
	492	int ret;
	493	u16 val;
	494
	495	ret = pcie_capability_read_word(dev, pos, &val);
	496	if (!ret) {
	497	val &= ~clear;
	498	val \|= set;
	499	ret = pcie_capability_write_word(dev, pos, val);
	500	}
	501
	502	return ret;
	503	}
	504	EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
	505
	506	int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
	507	u32 clear, u32 set)
	508	{
	509	int ret;
	510	u32 val;
	511
	512	ret = pcie_capability_read_dword(dev, pos, &val);
	513	if (!ret) {
	514	val &= ~clear;
	515	val \|= set;
	516	ret = pcie_capability_write_dword(dev, pos, val);
	517	}
	518
	519	return ret;
	520	}
	521	EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
d3881e50 KB	522
	523	int pci_read_config_byte(const struct pci_dev dev, int where, u8 val)
	524	{
4b103883 KB	525	if (pci_dev_is_disconnected(dev)) {
4b103883 KB	526	*val = ~0;
449e2f9e	527	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	528	}
d3881e50 KB	529	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
	530	}
	531	EXPORT_SYMBOL(pci_read_config_byte);
	532
	533	int pci_read_config_word(const struct pci_dev dev, int where, u16 val)
	534	{
4b103883 KB	535	if (pci_dev_is_disconnected(dev)) {
4b103883 KB	536	*val = ~0;
449e2f9e	537	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	538	}
d3881e50 KB	539	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
	540	}
	541	EXPORT_SYMBOL(pci_read_config_word);
	542
	543	int pci_read_config_dword(const struct pci_dev *dev, int where,
	544	u32 *val)
	545	{
4b103883 KB	546	if (pci_dev_is_disconnected(dev)) {
4b103883 KB	547	*val = ~0;
449e2f9e	548	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	549	}
d3881e50 KB	550	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
	551	}
	552	EXPORT_SYMBOL(pci_read_config_dword);
	553
	554	int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
	555	{
4b103883	556	if (pci_dev_is_disconnected(dev))
449e2f9e	557	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	558	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
	559	}
	560	EXPORT_SYMBOL(pci_write_config_byte);
	561
	562	int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
	563	{
4b103883	564	if (pci_dev_is_disconnected(dev))
449e2f9e	565	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	566	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
	567	}
	568	EXPORT_SYMBOL(pci_write_config_word);
	569
	570	int pci_write_config_dword(const struct pci_dev *dev, int where,
	571	u32 val)
	572	{
4b103883	573	if (pci_dev_is_disconnected(dev))
449e2f9e	574	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	575	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
	576	}
	577	EXPORT_SYMBOL(pci_write_config_dword);