Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | /* Low-level parallel-port routines for 8255-based PC-style hardware. |
3aeda9bc | 3 | * |
1da177e4 LT |
4 | * Authors: Phil Blundell <philb@gnu.org> |
5 | * Tim Waugh <tim@cyberelk.demon.co.uk> | |
6 | * Jose Renau <renau@acm.org> | |
bdca3f20 | 7 | * David Campbell |
1da177e4 LT |
8 | * Andrea Arcangeli |
9 | * | |
10 | * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. | |
11 | * | |
12 | * Cleaned up include files - Russell King <linux@arm.uk.linux.org> | |
13 | * DMA support - Bert De Jonghe <bert@sophis.be> | |
14 | * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 | |
3aeda9bc | 15 | * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. |
1da177e4 LT |
16 | * Various hacks, Fred Barnes, 04/2001 |
17 | * Updated probing logic - Adam Belay <ambx1@neo.rr.com> | |
18 | */ | |
19 | ||
20 | /* This driver should work with any hardware that is broadly compatible | |
21 | * with that in the IBM PC. This applies to the majority of integrated | |
22 | * I/O chipsets that are commonly available. The expected register | |
23 | * layout is: | |
24 | * | |
25 | * base+0 data | |
26 | * base+1 status | |
27 | * base+2 control | |
28 | * | |
29 | * In addition, there are some optional registers: | |
30 | * | |
31 | * base+3 EPP address | |
32 | * base+4 EPP data | |
33 | * base+0x400 ECP config A | |
34 | * base+0x401 ECP config B | |
35 | * base+0x402 ECP control | |
36 | * | |
37 | * All registers are 8 bits wide and read/write. If your hardware differs | |
38 | * only in register addresses (eg because your registers are on 32-bit | |
39 | * word boundaries) then you can alter the constants in parport_pc.h to | |
40 | * accommodate this. | |
41 | * | |
42 | * Note that the ECP registers may not start at offset 0x400 for PCI cards, | |
43 | * but rather will start at port->base_hi. | |
44 | */ | |
45 | ||
1da177e4 LT |
46 | #include <linux/module.h> |
47 | #include <linux/init.h> | |
174cd4b1 | 48 | #include <linux/sched/signal.h> |
1da177e4 LT |
49 | #include <linux/delay.h> |
50 | #include <linux/errno.h> | |
51 | #include <linux/interrupt.h> | |
52 | #include <linux/ioport.h> | |
53 | #include <linux/kernel.h> | |
54 | #include <linux/slab.h> | |
8382d2b9 | 55 | #include <linux/dma-mapping.h> |
1da177e4 LT |
56 | #include <linux/pci.h> |
57 | #include <linux/pnp.h> | |
a7d801af | 58 | #include <linux/platform_device.h> |
1da177e4 | 59 | #include <linux/sysctl.h> |
3aeda9bc AC |
60 | #include <linux/io.h> |
61 | #include <linux/uaccess.h> | |
1da177e4 | 62 | |
1da177e4 | 63 | #include <asm/dma.h> |
1da177e4 LT |
64 | |
65 | #include <linux/parport.h> | |
66 | #include <linux/parport_pc.h> | |
67 | #include <linux/via.h> | |
68 | #include <asm/parport.h> | |
69 | ||
70 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX | |
71 | ||
7fbacd52 AV |
72 | #ifdef CONFIG_ISA_DMA_API |
73 | #define HAS_DMA | |
74 | #endif | |
75 | ||
1da177e4 LT |
76 | /* ECR modes */ |
77 | #define ECR_SPP 00 | |
78 | #define ECR_PS2 01 | |
79 | #define ECR_PPF 02 | |
80 | #define ECR_ECP 03 | |
81 | #define ECR_EPP 04 | |
82 | #define ECR_VND 05 | |
83 | #define ECR_TST 06 | |
84 | #define ECR_CNF 07 | |
85 | #define ECR_MODE_MASK 0xe0 | |
3aeda9bc | 86 | #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v)) |
1da177e4 LT |
87 | |
88 | #undef DEBUG | |
89 | ||
90 | #ifdef DEBUG | |
91 | #define DPRINTK printk | |
92 | #else | |
93 | #define DPRINTK(stuff...) | |
94 | #endif | |
95 | ||
96 | ||
97 | #define NR_SUPERIOS 3 | |
98 | static struct superio_struct { /* For Super-IO chips autodetection */ | |
99 | int io; | |
100 | int irq; | |
101 | int dma; | |
96766a3c | 102 | } superios[NR_SUPERIOS] = { {0,},}; |
1da177e4 LT |
103 | |
104 | static int user_specified; | |
105 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
106 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
107 | static int verbose_probing; | |
108 | #endif | |
109 | static int pci_registered_parport; | |
110 | static int pnp_registered_parport; | |
111 | ||
112 | /* frob_control, but for ECR */ | |
3aeda9bc | 113 | static void frob_econtrol(struct parport *pb, unsigned char m, |
1da177e4 LT |
114 | unsigned char v) |
115 | { | |
116 | unsigned char ectr = 0; | |
117 | ||
118 | if (m != 0xff) | |
3aeda9bc | 119 | ectr = inb(ECONTROL(pb)); |
1da177e4 | 120 | |
3aeda9bc | 121 | DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", |
1da177e4 LT |
122 | m, v, ectr, (ectr & ~m) ^ v); |
123 | ||
3aeda9bc | 124 | outb((ectr & ~m) ^ v, ECONTROL(pb)); |
1da177e4 LT |
125 | } |
126 | ||
3aeda9bc | 127 | static inline void frob_set_mode(struct parport *p, int mode) |
1da177e4 | 128 | { |
3aeda9bc | 129 | frob_econtrol(p, ECR_MODE_MASK, mode << 5); |
1da177e4 LT |
130 | } |
131 | ||
132 | #ifdef CONFIG_PARPORT_PC_FIFO | |
3aeda9bc | 133 | /* Safely change the mode bits in the ECR |
1da177e4 LT |
134 | Returns: |
135 | 0 : Success | |
136 | -EBUSY: Could not drain FIFO in some finite amount of time, | |
137 | mode not changed! | |
138 | */ | |
139 | static int change_mode(struct parport *p, int m) | |
140 | { | |
141 | const struct parport_pc_private *priv = p->physport->private_data; | |
142 | unsigned char oecr; | |
143 | int mode; | |
144 | ||
3aeda9bc | 145 | DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m); |
1da177e4 LT |
146 | |
147 | if (!priv->ecr) { | |
3aeda9bc | 148 | printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); |
1da177e4 LT |
149 | return 0; |
150 | } | |
151 | ||
152 | /* Bits <7:5> contain the mode. */ | |
3aeda9bc | 153 | oecr = inb(ECONTROL(p)); |
1da177e4 | 154 | mode = (oecr >> 5) & 0x7; |
3aeda9bc AC |
155 | if (mode == m) |
156 | return 0; | |
1da177e4 LT |
157 | |
158 | if (mode >= 2 && !(priv->ctr & 0x20)) { | |
159 | /* This mode resets the FIFO, so we may | |
160 | * have to wait for it to drain first. */ | |
161 | unsigned long expire = jiffies + p->physport->cad->timeout; | |
162 | int counter; | |
163 | switch (mode) { | |
164 | case ECR_PPF: /* Parallel Port FIFO mode */ | |
165 | case ECR_ECP: /* ECP Parallel Port mode */ | |
166 | /* Busy wait for 200us */ | |
167 | for (counter = 0; counter < 40; counter++) { | |
3aeda9bc | 168 | if (inb(ECONTROL(p)) & 0x01) |
1da177e4 | 169 | break; |
3aeda9bc AC |
170 | if (signal_pending(current)) |
171 | break; | |
172 | udelay(5); | |
1da177e4 LT |
173 | } |
174 | ||
175 | /* Poll slowly. */ | |
3aeda9bc AC |
176 | while (!(inb(ECONTROL(p)) & 0x01)) { |
177 | if (time_after_eq(jiffies, expire)) | |
1da177e4 LT |
178 | /* The FIFO is stuck. */ |
179 | return -EBUSY; | |
3aeda9bc AC |
180 | schedule_timeout_interruptible( |
181 | msecs_to_jiffies(10)); | |
182 | if (signal_pending(current)) | |
1da177e4 LT |
183 | break; |
184 | } | |
185 | } | |
186 | } | |
187 | ||
188 | if (mode >= 2 && m >= 2) { | |
189 | /* We have to go through mode 001 */ | |
190 | oecr &= ~(7 << 5); | |
191 | oecr |= ECR_PS2 << 5; | |
3aeda9bc | 192 | ECR_WRITE(p, oecr); |
1da177e4 LT |
193 | } |
194 | ||
195 | /* Set the mode. */ | |
196 | oecr &= ~(7 << 5); | |
197 | oecr |= m << 5; | |
3aeda9bc | 198 | ECR_WRITE(p, oecr); |
1da177e4 LT |
199 | return 0; |
200 | } | |
1da177e4 LT |
201 | #endif /* FIFO support */ |
202 | ||
203 | /* | |
204 | * Clear TIMEOUT BIT in EPP MODE | |
205 | * | |
206 | * This is also used in SPP detection. | |
207 | */ | |
208 | static int clear_epp_timeout(struct parport *pb) | |
209 | { | |
210 | unsigned char r; | |
211 | ||
212 | if (!(parport_pc_read_status(pb) & 0x01)) | |
213 | return 1; | |
214 | ||
215 | /* To clear timeout some chips require double read */ | |
216 | parport_pc_read_status(pb); | |
217 | r = parport_pc_read_status(pb); | |
3aeda9bc AC |
218 | outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ |
219 | outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ | |
1da177e4 LT |
220 | r = parport_pc_read_status(pb); |
221 | ||
222 | return !(r & 0x01); | |
223 | } | |
224 | ||
225 | /* | |
226 | * Access functions. | |
227 | * | |
228 | * Most of these aren't static because they may be used by the | |
229 | * parport_xxx_yyy macros. extern __inline__ versions of several | |
230 | * of these are in parport_pc.h. | |
231 | */ | |
232 | ||
3aeda9bc AC |
233 | static void parport_pc_init_state(struct pardevice *dev, |
234 | struct parport_state *s) | |
1da177e4 LT |
235 | { |
236 | s->u.pc.ctr = 0xc; | |
237 | if (dev->irq_func && | |
238 | dev->port->irq != PARPORT_IRQ_NONE) | |
239 | /* Set ackIntEn */ | |
240 | s->u.pc.ctr |= 0x10; | |
241 | ||
242 | s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; | |
243 | * D.Gruszka VScom */ | |
244 | } | |
245 | ||
246 | static void parport_pc_save_state(struct parport *p, struct parport_state *s) | |
247 | { | |
248 | const struct parport_pc_private *priv = p->physport->private_data; | |
249 | s->u.pc.ctr = priv->ctr; | |
250 | if (priv->ecr) | |
3aeda9bc | 251 | s->u.pc.ecr = inb(ECONTROL(p)); |
1da177e4 LT |
252 | } |
253 | ||
3aeda9bc AC |
254 | static void parport_pc_restore_state(struct parport *p, |
255 | struct parport_state *s) | |
1da177e4 LT |
256 | { |
257 | struct parport_pc_private *priv = p->physport->private_data; | |
258 | register unsigned char c = s->u.pc.ctr & priv->ctr_writable; | |
3aeda9bc | 259 | outb(c, CONTROL(p)); |
1da177e4 LT |
260 | priv->ctr = c; |
261 | if (priv->ecr) | |
3aeda9bc | 262 | ECR_WRITE(p, s->u.pc.ecr); |
1da177e4 LT |
263 | } |
264 | ||
265 | #ifdef CONFIG_PARPORT_1284 | |
3aeda9bc AC |
266 | static size_t parport_pc_epp_read_data(struct parport *port, void *buf, |
267 | size_t length, int flags) | |
1da177e4 LT |
268 | { |
269 | size_t got = 0; | |
270 | ||
271 | if (flags & PARPORT_W91284PIC) { | |
272 | unsigned char status; | |
273 | size_t left = length; | |
274 | ||
275 | /* use knowledge about data lines..: | |
276 | * nFault is 0 if there is at least 1 byte in the Warp's FIFO | |
277 | * pError is 1 if there are 16 bytes in the Warp's FIFO | |
278 | */ | |
3aeda9bc | 279 | status = inb(STATUS(port)); |
1da177e4 | 280 | |
3aeda9bc AC |
281 | while (!(status & 0x08) && got < length) { |
282 | if (left >= 16 && (status & 0x20) && !(status & 0x08)) { | |
1da177e4 | 283 | /* can grab 16 bytes from warp fifo */ |
3aeda9bc AC |
284 | if (!((long)buf & 0x03)) |
285 | insl(EPPDATA(port), buf, 4); | |
286 | else | |
287 | insb(EPPDATA(port), buf, 16); | |
1da177e4 LT |
288 | buf += 16; |
289 | got += 16; | |
290 | left -= 16; | |
291 | } else { | |
292 | /* grab single byte from the warp fifo */ | |
3aeda9bc | 293 | *((char *)buf) = inb(EPPDATA(port)); |
1da177e4 LT |
294 | buf++; |
295 | got++; | |
296 | left--; | |
297 | } | |
3aeda9bc | 298 | status = inb(STATUS(port)); |
1da177e4 LT |
299 | if (status & 0x01) { |
300 | /* EPP timeout should never occur... */ | |
3aeda9bc AC |
301 | printk(KERN_DEBUG |
302 | "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name); | |
303 | clear_epp_timeout(port); | |
1da177e4 LT |
304 | } |
305 | } | |
306 | return got; | |
307 | } | |
308 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
309 | if (!(((long)buf | length) & 0x03)) |
310 | insl(EPPDATA(port), buf, (length >> 2)); | |
311 | else | |
312 | insb(EPPDATA(port), buf, length); | |
313 | if (inb(STATUS(port)) & 0x01) { | |
314 | clear_epp_timeout(port); | |
1da177e4 LT |
315 | return -EIO; |
316 | } | |
317 | return length; | |
318 | } | |
319 | for (; got < length; got++) { | |
3aeda9bc | 320 | *((char *)buf) = inb(EPPDATA(port)); |
1da177e4 | 321 | buf++; |
3aeda9bc | 322 | if (inb(STATUS(port)) & 0x01) { |
1da177e4 | 323 | /* EPP timeout */ |
3aeda9bc | 324 | clear_epp_timeout(port); |
1da177e4 LT |
325 | break; |
326 | } | |
327 | } | |
328 | ||
329 | return got; | |
330 | } | |
331 | ||
3aeda9bc AC |
332 | static size_t parport_pc_epp_write_data(struct parport *port, const void *buf, |
333 | size_t length, int flags) | |
1da177e4 LT |
334 | { |
335 | size_t written = 0; | |
336 | ||
337 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
338 | if (!(((long)buf | length) & 0x03)) |
339 | outsl(EPPDATA(port), buf, (length >> 2)); | |
340 | else | |
341 | outsb(EPPDATA(port), buf, length); | |
342 | if (inb(STATUS(port)) & 0x01) { | |
343 | clear_epp_timeout(port); | |
1da177e4 LT |
344 | return -EIO; |
345 | } | |
346 | return length; | |
347 | } | |
348 | for (; written < length; written++) { | |
3aeda9bc | 349 | outb(*((char *)buf), EPPDATA(port)); |
1da177e4 | 350 | buf++; |
3aeda9bc AC |
351 | if (inb(STATUS(port)) & 0x01) { |
352 | clear_epp_timeout(port); | |
1da177e4 LT |
353 | break; |
354 | } | |
355 | } | |
356 | ||
357 | return written; | |
358 | } | |
359 | ||
3aeda9bc | 360 | static size_t parport_pc_epp_read_addr(struct parport *port, void *buf, |
1da177e4 LT |
361 | size_t length, int flags) |
362 | { | |
363 | size_t got = 0; | |
364 | ||
365 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
366 | insb(EPPADDR(port), buf, length); |
367 | if (inb(STATUS(port)) & 0x01) { | |
368 | clear_epp_timeout(port); | |
1da177e4 LT |
369 | return -EIO; |
370 | } | |
371 | return length; | |
372 | } | |
373 | for (; got < length; got++) { | |
3aeda9bc | 374 | *((char *)buf) = inb(EPPADDR(port)); |
1da177e4 | 375 | buf++; |
3aeda9bc AC |
376 | if (inb(STATUS(port)) & 0x01) { |
377 | clear_epp_timeout(port); | |
1da177e4 LT |
378 | break; |
379 | } | |
380 | } | |
381 | ||
382 | return got; | |
383 | } | |
384 | ||
3aeda9bc | 385 | static size_t parport_pc_epp_write_addr(struct parport *port, |
1da177e4 LT |
386 | const void *buf, size_t length, |
387 | int flags) | |
388 | { | |
389 | size_t written = 0; | |
390 | ||
391 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
392 | outsb(EPPADDR(port), buf, length); |
393 | if (inb(STATUS(port)) & 0x01) { | |
394 | clear_epp_timeout(port); | |
1da177e4 LT |
395 | return -EIO; |
396 | } | |
397 | return length; | |
398 | } | |
399 | for (; written < length; written++) { | |
3aeda9bc | 400 | outb(*((char *)buf), EPPADDR(port)); |
1da177e4 | 401 | buf++; |
3aeda9bc AC |
402 | if (inb(STATUS(port)) & 0x01) { |
403 | clear_epp_timeout(port); | |
1da177e4 LT |
404 | break; |
405 | } | |
406 | } | |
407 | ||
408 | return written; | |
409 | } | |
410 | ||
3aeda9bc AC |
411 | static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf, |
412 | size_t length, int flags) | |
1da177e4 LT |
413 | { |
414 | size_t got; | |
415 | ||
3aeda9bc AC |
416 | frob_set_mode(port, ECR_EPP); |
417 | parport_pc_data_reverse(port); | |
418 | parport_pc_write_control(port, 0x4); | |
419 | got = parport_pc_epp_read_data(port, buf, length, flags); | |
420 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
421 | |
422 | return got; | |
423 | } | |
424 | ||
3aeda9bc AC |
425 | static size_t parport_pc_ecpepp_write_data(struct parport *port, |
426 | const void *buf, size_t length, | |
427 | int flags) | |
1da177e4 LT |
428 | { |
429 | size_t written; | |
430 | ||
3aeda9bc AC |
431 | frob_set_mode(port, ECR_EPP); |
432 | parport_pc_write_control(port, 0x4); | |
433 | parport_pc_data_forward(port); | |
434 | written = parport_pc_epp_write_data(port, buf, length, flags); | |
435 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
436 | |
437 | return written; | |
438 | } | |
439 | ||
3aeda9bc AC |
440 | static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf, |
441 | size_t length, int flags) | |
1da177e4 LT |
442 | { |
443 | size_t got; | |
444 | ||
3aeda9bc AC |
445 | frob_set_mode(port, ECR_EPP); |
446 | parport_pc_data_reverse(port); | |
447 | parport_pc_write_control(port, 0x4); | |
448 | got = parport_pc_epp_read_addr(port, buf, length, flags); | |
449 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
450 | |
451 | return got; | |
452 | } | |
453 | ||
3aeda9bc | 454 | static size_t parport_pc_ecpepp_write_addr(struct parport *port, |
1da177e4 LT |
455 | const void *buf, size_t length, |
456 | int flags) | |
457 | { | |
458 | size_t written; | |
459 | ||
3aeda9bc AC |
460 | frob_set_mode(port, ECR_EPP); |
461 | parport_pc_write_control(port, 0x4); | |
462 | parport_pc_data_forward(port); | |
463 | written = parport_pc_epp_write_addr(port, buf, length, flags); | |
464 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
465 | |
466 | return written; | |
467 | } | |
468 | #endif /* IEEE 1284 support */ | |
469 | ||
470 | #ifdef CONFIG_PARPORT_PC_FIFO | |
3aeda9bc | 471 | static size_t parport_pc_fifo_write_block_pio(struct parport *port, |
1da177e4 LT |
472 | const void *buf, size_t length) |
473 | { | |
474 | int ret = 0; | |
475 | const unsigned char *bufp = buf; | |
476 | size_t left = length; | |
477 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
3aeda9bc | 478 | const int fifo = FIFO(port); |
1da177e4 LT |
479 | int poll_for = 8; /* 80 usecs */ |
480 | const struct parport_pc_private *priv = port->physport->private_data; | |
481 | const int fifo_depth = priv->fifo_depth; | |
482 | ||
483 | port = port->physport; | |
484 | ||
485 | /* We don't want to be interrupted every character. */ | |
3aeda9bc | 486 | parport_pc_disable_irq(port); |
1da177e4 | 487 | /* set nErrIntrEn and serviceIntr */ |
3aeda9bc | 488 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); |
1da177e4 LT |
489 | |
490 | /* Forward mode. */ | |
3aeda9bc | 491 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
1da177e4 LT |
492 | |
493 | while (left) { | |
494 | unsigned char byte; | |
3aeda9bc | 495 | unsigned char ecrval = inb(ECONTROL(port)); |
1da177e4 LT |
496 | int i = 0; |
497 | ||
3aeda9bc | 498 | if (need_resched() && time_before(jiffies, expire)) |
1da177e4 | 499 | /* Can't yield the port. */ |
3aeda9bc | 500 | schedule(); |
1da177e4 LT |
501 | |
502 | /* Anyone else waiting for the port? */ | |
503 | if (port->waithead) { | |
3aeda9bc | 504 | printk(KERN_DEBUG "Somebody wants the port\n"); |
1da177e4 LT |
505 | break; |
506 | } | |
507 | ||
508 | if (ecrval & 0x02) { | |
509 | /* FIFO is full. Wait for interrupt. */ | |
510 | ||
511 | /* Clear serviceIntr */ | |
3aeda9bc AC |
512 | ECR_WRITE(port, ecrval & ~(1<<2)); |
513 | false_alarm: | |
514 | ret = parport_wait_event(port, HZ); | |
515 | if (ret < 0) | |
516 | break; | |
1da177e4 | 517 | ret = 0; |
3aeda9bc | 518 | if (!time_before(jiffies, expire)) { |
1da177e4 | 519 | /* Timed out. */ |
3aeda9bc | 520 | printk(KERN_DEBUG "FIFO write timed out\n"); |
1da177e4 LT |
521 | break; |
522 | } | |
3aeda9bc | 523 | ecrval = inb(ECONTROL(port)); |
1da177e4 LT |
524 | if (!(ecrval & (1<<2))) { |
525 | if (need_resched() && | |
3aeda9bc AC |
526 | time_before(jiffies, expire)) |
527 | schedule(); | |
1da177e4 LT |
528 | |
529 | goto false_alarm; | |
530 | } | |
531 | ||
532 | continue; | |
533 | } | |
534 | ||
535 | /* Can't fail now. */ | |
536 | expire = jiffies + port->cad->timeout; | |
537 | ||
3aeda9bc AC |
538 | poll: |
539 | if (signal_pending(current)) | |
1da177e4 LT |
540 | break; |
541 | ||
542 | if (ecrval & 0x01) { | |
543 | /* FIFO is empty. Blast it full. */ | |
544 | const int n = left < fifo_depth ? left : fifo_depth; | |
3aeda9bc | 545 | outsb(fifo, bufp, n); |
1da177e4 LT |
546 | bufp += n; |
547 | left -= n; | |
548 | ||
549 | /* Adjust the poll time. */ | |
3aeda9bc AC |
550 | if (i < (poll_for - 2)) |
551 | poll_for--; | |
1da177e4 LT |
552 | continue; |
553 | } else if (i++ < poll_for) { | |
3aeda9bc AC |
554 | udelay(10); |
555 | ecrval = inb(ECONTROL(port)); | |
1da177e4 LT |
556 | goto poll; |
557 | } | |
558 | ||
3aeda9bc | 559 | /* Half-full(call me an optimist) */ |
1da177e4 | 560 | byte = *bufp++; |
3aeda9bc | 561 | outb(byte, fifo); |
1da177e4 | 562 | left--; |
3aeda9bc AC |
563 | } |
564 | dump_parport_state("leave fifo_write_block_pio", port); | |
1da177e4 LT |
565 | return length - left; |
566 | } | |
567 | ||
7fbacd52 | 568 | #ifdef HAS_DMA |
3aeda9bc | 569 | static size_t parport_pc_fifo_write_block_dma(struct parport *port, |
1da177e4 LT |
570 | const void *buf, size_t length) |
571 | { | |
572 | int ret = 0; | |
573 | unsigned long dmaflag; | |
574 | size_t left = length; | |
575 | const struct parport_pc_private *priv = port->physport->private_data; | |
c15a3837 | 576 | struct device *dev = port->physport->dev; |
1da177e4 LT |
577 | dma_addr_t dma_addr, dma_handle; |
578 | size_t maxlen = 0x10000; /* max 64k per DMA transfer */ | |
579 | unsigned long start = (unsigned long) buf; | |
580 | unsigned long end = (unsigned long) buf + length - 1; | |
581 | ||
181bf1e8 | 582 | dump_parport_state("enter fifo_write_block_dma", port); |
1da177e4 LT |
583 | if (end < MAX_DMA_ADDRESS) { |
584 | /* If it would cross a 64k boundary, cap it at the end. */ | |
585 | if ((start ^ end) & ~0xffffUL) | |
586 | maxlen = 0x10000 - (start & 0xffff); | |
587 | ||
c15a3837 DB |
588 | dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, |
589 | DMA_TO_DEVICE); | |
3aeda9bc AC |
590 | } else { |
591 | /* above 16 MB we use a bounce buffer as ISA-DMA | |
592 | is not possible */ | |
1da177e4 LT |
593 | maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ |
594 | dma_addr = priv->dma_handle; | |
595 | dma_handle = 0; | |
596 | } | |
597 | ||
598 | port = port->physport; | |
599 | ||
600 | /* We don't want to be interrupted every character. */ | |
3aeda9bc | 601 | parport_pc_disable_irq(port); |
1da177e4 | 602 | /* set nErrIntrEn and serviceIntr */ |
3aeda9bc | 603 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); |
1da177e4 LT |
604 | |
605 | /* Forward mode. */ | |
3aeda9bc | 606 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
1da177e4 LT |
607 | |
608 | while (left) { | |
609 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
610 | ||
611 | size_t count = left; | |
612 | ||
613 | if (count > maxlen) | |
614 | count = maxlen; | |
615 | ||
616 | if (!dma_handle) /* bounce buffer ! */ | |
617 | memcpy(priv->dma_buf, buf, count); | |
618 | ||
619 | dmaflag = claim_dma_lock(); | |
620 | disable_dma(port->dma); | |
621 | clear_dma_ff(port->dma); | |
622 | set_dma_mode(port->dma, DMA_MODE_WRITE); | |
623 | set_dma_addr(port->dma, dma_addr); | |
624 | set_dma_count(port->dma, count); | |
625 | ||
626 | /* Set DMA mode */ | |
3aeda9bc | 627 | frob_econtrol(port, 1<<3, 1<<3); |
1da177e4 LT |
628 | |
629 | /* Clear serviceIntr */ | |
3aeda9bc | 630 | frob_econtrol(port, 1<<2, 0); |
1da177e4 LT |
631 | |
632 | enable_dma(port->dma); | |
633 | release_dma_lock(dmaflag); | |
634 | ||
635 | /* assume DMA will be successful */ | |
636 | left -= count; | |
637 | buf += count; | |
3aeda9bc AC |
638 | if (dma_handle) |
639 | dma_addr += count; | |
1da177e4 LT |
640 | |
641 | /* Wait for interrupt. */ | |
3aeda9bc AC |
642 | false_alarm: |
643 | ret = parport_wait_event(port, HZ); | |
644 | if (ret < 0) | |
645 | break; | |
1da177e4 | 646 | ret = 0; |
3aeda9bc | 647 | if (!time_before(jiffies, expire)) { |
1da177e4 | 648 | /* Timed out. */ |
3aeda9bc | 649 | printk(KERN_DEBUG "DMA write timed out\n"); |
1da177e4 LT |
650 | break; |
651 | } | |
652 | /* Is serviceIntr set? */ | |
3aeda9bc | 653 | if (!(inb(ECONTROL(port)) & (1<<2))) { |
1da177e4 LT |
654 | cond_resched(); |
655 | ||
656 | goto false_alarm; | |
657 | } | |
658 | ||
659 | dmaflag = claim_dma_lock(); | |
660 | disable_dma(port->dma); | |
661 | clear_dma_ff(port->dma); | |
662 | count = get_dma_residue(port->dma); | |
663 | release_dma_lock(dmaflag); | |
664 | ||
665 | cond_resched(); /* Can't yield the port. */ | |
666 | ||
667 | /* Anyone else waiting for the port? */ | |
668 | if (port->waithead) { | |
3aeda9bc | 669 | printk(KERN_DEBUG "Somebody wants the port\n"); |
1da177e4 LT |
670 | break; |
671 | } | |
672 | ||
673 | /* update for possible DMA residue ! */ | |
674 | buf -= count; | |
675 | left += count; | |
3aeda9bc AC |
676 | if (dma_handle) |
677 | dma_addr -= count; | |
1da177e4 LT |
678 | } |
679 | ||
680 | /* Maybe got here through break, so adjust for DMA residue! */ | |
681 | dmaflag = claim_dma_lock(); | |
682 | disable_dma(port->dma); | |
683 | clear_dma_ff(port->dma); | |
684 | left += get_dma_residue(port->dma); | |
685 | release_dma_lock(dmaflag); | |
686 | ||
687 | /* Turn off DMA mode */ | |
3aeda9bc | 688 | frob_econtrol(port, 1<<3, 0); |
c15a3837 | 689 | |
1da177e4 | 690 | if (dma_handle) |
c15a3837 | 691 | dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); |
1da177e4 | 692 | |
181bf1e8 | 693 | dump_parport_state("leave fifo_write_block_dma", port); |
1da177e4 LT |
694 | return length - left; |
695 | } | |
7fbacd52 AV |
696 | #endif |
697 | ||
698 | static inline size_t parport_pc_fifo_write_block(struct parport *port, | |
699 | const void *buf, size_t length) | |
700 | { | |
701 | #ifdef HAS_DMA | |
702 | if (port->dma != PARPORT_DMA_NONE) | |
3aeda9bc | 703 | return parport_pc_fifo_write_block_dma(port, buf, length); |
7fbacd52 | 704 | #endif |
3aeda9bc | 705 | return parport_pc_fifo_write_block_pio(port, buf, length); |
7fbacd52 | 706 | } |
1da177e4 LT |
707 | |
708 | /* Parallel Port FIFO mode (ECP chipsets) */ | |
3aeda9bc | 709 | static size_t parport_pc_compat_write_block_pio(struct parport *port, |
1da177e4 LT |
710 | const void *buf, size_t length, |
711 | int flags) | |
712 | { | |
713 | size_t written; | |
714 | int r; | |
715 | unsigned long expire; | |
716 | const struct parport_pc_private *priv = port->physport->private_data; | |
717 | ||
718 | /* Special case: a timeout of zero means we cannot call schedule(). | |
719 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
720 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
3aeda9bc | 721 | return parport_ieee1284_write_compat(port, buf, |
1da177e4 LT |
722 | length, flags); |
723 | ||
724 | /* Set up parallel port FIFO mode.*/ | |
3aeda9bc AC |
725 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
726 | parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); | |
727 | r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ | |
728 | if (r) | |
729 | printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", | |
730 | port->name); | |
1da177e4 LT |
731 | |
732 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
733 | ||
734 | /* Write the data to the FIFO. */ | |
7fbacd52 | 735 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
736 | |
737 | /* Finish up. */ | |
738 | /* For some hardware we don't want to touch the mode until | |
739 | * the FIFO is empty, so allow 4 seconds for each position | |
740 | * in the fifo. | |
741 | */ | |
3aeda9bc | 742 | expire = jiffies + (priv->fifo_depth * HZ * 4); |
1da177e4 LT |
743 | do { |
744 | /* Wait for the FIFO to empty */ | |
3aeda9bc AC |
745 | r = change_mode(port, ECR_PS2); |
746 | if (r != -EBUSY) | |
1da177e4 | 747 | break; |
3aeda9bc | 748 | } while (time_before(jiffies, expire)); |
1da177e4 LT |
749 | if (r == -EBUSY) { |
750 | ||
3aeda9bc | 751 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); |
1da177e4 LT |
752 | |
753 | /* Prevent further data transfer. */ | |
3aeda9bc | 754 | frob_set_mode(port, ECR_TST); |
1da177e4 LT |
755 | |
756 | /* Adjust for the contents of the FIFO. */ | |
757 | for (written -= priv->fifo_depth; ; written++) { | |
3aeda9bc | 758 | if (inb(ECONTROL(port)) & 0x2) { |
1da177e4 LT |
759 | /* Full up. */ |
760 | break; | |
761 | } | |
3aeda9bc | 762 | outb(0, FIFO(port)); |
1da177e4 LT |
763 | } |
764 | ||
765 | /* Reset the FIFO and return to PS2 mode. */ | |
3aeda9bc | 766 | frob_set_mode(port, ECR_PS2); |
1da177e4 LT |
767 | } |
768 | ||
3aeda9bc | 769 | r = parport_wait_peripheral(port, |
1da177e4 LT |
770 | PARPORT_STATUS_BUSY, |
771 | PARPORT_STATUS_BUSY); | |
772 | if (r) | |
3aeda9bc AC |
773 | printk(KERN_DEBUG |
774 | "%s: BUSY timeout (%d) in compat_write_block_pio\n", | |
1da177e4 LT |
775 | port->name, r); |
776 | ||
777 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
778 | ||
779 | return written; | |
780 | } | |
781 | ||
782 | /* ECP */ | |
783 | #ifdef CONFIG_PARPORT_1284 | |
3aeda9bc | 784 | static size_t parport_pc_ecp_write_block_pio(struct parport *port, |
1da177e4 LT |
785 | const void *buf, size_t length, |
786 | int flags) | |
787 | { | |
788 | size_t written; | |
789 | int r; | |
790 | unsigned long expire; | |
791 | const struct parport_pc_private *priv = port->physport->private_data; | |
792 | ||
793 | /* Special case: a timeout of zero means we cannot call schedule(). | |
794 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
795 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
3aeda9bc | 796 | return parport_ieee1284_ecp_write_data(port, buf, |
1da177e4 LT |
797 | length, flags); |
798 | ||
799 | /* Switch to forward mode if necessary. */ | |
800 | if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { | |
801 | /* Event 47: Set nInit high. */ | |
3aeda9bc | 802 | parport_frob_control(port, |
1da177e4 LT |
803 | PARPORT_CONTROL_INIT |
804 | | PARPORT_CONTROL_AUTOFD, | |
805 | PARPORT_CONTROL_INIT | |
806 | | PARPORT_CONTROL_AUTOFD); | |
807 | ||
808 | /* Event 49: PError goes high. */ | |
3aeda9bc | 809 | r = parport_wait_peripheral(port, |
1da177e4 LT |
810 | PARPORT_STATUS_PAPEROUT, |
811 | PARPORT_STATUS_PAPEROUT); | |
812 | if (r) { | |
3aeda9bc | 813 | printk(KERN_DEBUG "%s: PError timeout (%d) " |
1da177e4 LT |
814 | "in ecp_write_block_pio\n", port->name, r); |
815 | } | |
816 | } | |
817 | ||
818 | /* Set up ECP parallel port mode.*/ | |
3aeda9bc AC |
819 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
820 | parport_pc_frob_control(port, | |
1da177e4 LT |
821 | PARPORT_CONTROL_STROBE | |
822 | PARPORT_CONTROL_AUTOFD, | |
823 | 0); | |
3aeda9bc AC |
824 | r = change_mode(port, ECR_ECP); /* ECP FIFO */ |
825 | if (r) | |
826 | printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", | |
827 | port->name); | |
1da177e4 LT |
828 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; |
829 | ||
830 | /* Write the data to the FIFO. */ | |
7fbacd52 | 831 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
832 | |
833 | /* Finish up. */ | |
834 | /* For some hardware we don't want to touch the mode until | |
835 | * the FIFO is empty, so allow 4 seconds for each position | |
836 | * in the fifo. | |
837 | */ | |
838 | expire = jiffies + (priv->fifo_depth * (HZ * 4)); | |
839 | do { | |
840 | /* Wait for the FIFO to empty */ | |
3aeda9bc AC |
841 | r = change_mode(port, ECR_PS2); |
842 | if (r != -EBUSY) | |
1da177e4 | 843 | break; |
3aeda9bc | 844 | } while (time_before(jiffies, expire)); |
1da177e4 LT |
845 | if (r == -EBUSY) { |
846 | ||
3aeda9bc | 847 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); |
1da177e4 LT |
848 | |
849 | /* Prevent further data transfer. */ | |
3aeda9bc | 850 | frob_set_mode(port, ECR_TST); |
1da177e4 LT |
851 | |
852 | /* Adjust for the contents of the FIFO. */ | |
853 | for (written -= priv->fifo_depth; ; written++) { | |
3aeda9bc | 854 | if (inb(ECONTROL(port)) & 0x2) { |
1da177e4 LT |
855 | /* Full up. */ |
856 | break; | |
857 | } | |
3aeda9bc | 858 | outb(0, FIFO(port)); |
1da177e4 LT |
859 | } |
860 | ||
861 | /* Reset the FIFO and return to PS2 mode. */ | |
3aeda9bc | 862 | frob_set_mode(port, ECR_PS2); |
1da177e4 LT |
863 | |
864 | /* Host transfer recovery. */ | |
3aeda9bc AC |
865 | parport_pc_data_reverse(port); /* Must be in PS2 mode */ |
866 | udelay(5); | |
867 | parport_frob_control(port, PARPORT_CONTROL_INIT, 0); | |
868 | r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); | |
1da177e4 | 869 | if (r) |
3aeda9bc | 870 | printk(KERN_DEBUG "%s: PE,1 timeout (%d) " |
1da177e4 LT |
871 | "in ecp_write_block_pio\n", port->name, r); |
872 | ||
3aeda9bc | 873 | parport_frob_control(port, |
1da177e4 LT |
874 | PARPORT_CONTROL_INIT, |
875 | PARPORT_CONTROL_INIT); | |
3aeda9bc | 876 | r = parport_wait_peripheral(port, |
1da177e4 LT |
877 | PARPORT_STATUS_PAPEROUT, |
878 | PARPORT_STATUS_PAPEROUT); | |
3aeda9bc AC |
879 | if (r) |
880 | printk(KERN_DEBUG "%s: PE,2 timeout (%d) " | |
1da177e4 LT |
881 | "in ecp_write_block_pio\n", port->name, r); |
882 | } | |
883 | ||
3aeda9bc AC |
884 | r = parport_wait_peripheral(port, |
885 | PARPORT_STATUS_BUSY, | |
1da177e4 | 886 | PARPORT_STATUS_BUSY); |
3aeda9bc AC |
887 | if (r) |
888 | printk(KERN_DEBUG | |
1da177e4 LT |
889 | "%s: BUSY timeout (%d) in ecp_write_block_pio\n", |
890 | port->name, r); | |
891 | ||
892 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
893 | ||
894 | return written; | |
895 | } | |
1da177e4 LT |
896 | #endif /* IEEE 1284 support */ |
897 | #endif /* Allowed to use FIFO/DMA */ | |
898 | ||
899 | ||
900 | /* | |
901 | * ****************************************** | |
902 | * INITIALISATION AND MODULE STUFF BELOW HERE | |
903 | * ****************************************** | |
904 | */ | |
905 | ||
b8a14f33 | 906 | /* GCC is not inlining extern inline function later overwritten to non-inline, |
1da177e4 | 907 | so we use outlined_ variants here. */ |
3aeda9bc | 908 | static const struct parport_operations parport_pc_ops = { |
1da177e4 LT |
909 | .write_data = parport_pc_write_data, |
910 | .read_data = parport_pc_read_data, | |
911 | ||
912 | .write_control = parport_pc_write_control, | |
913 | .read_control = parport_pc_read_control, | |
914 | .frob_control = parport_pc_frob_control, | |
915 | ||
916 | .read_status = parport_pc_read_status, | |
917 | ||
918 | .enable_irq = parport_pc_enable_irq, | |
919 | .disable_irq = parport_pc_disable_irq, | |
920 | ||
921 | .data_forward = parport_pc_data_forward, | |
922 | .data_reverse = parport_pc_data_reverse, | |
923 | ||
924 | .init_state = parport_pc_init_state, | |
925 | .save_state = parport_pc_save_state, | |
926 | .restore_state = parport_pc_restore_state, | |
927 | ||
928 | .epp_write_data = parport_ieee1284_epp_write_data, | |
929 | .epp_read_data = parport_ieee1284_epp_read_data, | |
930 | .epp_write_addr = parport_ieee1284_epp_write_addr, | |
931 | .epp_read_addr = parport_ieee1284_epp_read_addr, | |
932 | ||
933 | .ecp_write_data = parport_ieee1284_ecp_write_data, | |
934 | .ecp_read_data = parport_ieee1284_ecp_read_data, | |
935 | .ecp_write_addr = parport_ieee1284_ecp_write_addr, | |
936 | ||
937 | .compat_write_data = parport_ieee1284_write_compat, | |
938 | .nibble_read_data = parport_ieee1284_read_nibble, | |
939 | .byte_read_data = parport_ieee1284_read_byte, | |
940 | ||
941 | .owner = THIS_MODULE, | |
942 | }; | |
943 | ||
944 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
181bf1e8 AC |
945 | |
946 | static struct superio_struct *find_free_superio(void) | |
947 | { | |
948 | int i; | |
949 | for (i = 0; i < NR_SUPERIOS; i++) | |
950 | if (superios[i].io == 0) | |
951 | return &superios[i]; | |
952 | return NULL; | |
953 | } | |
954 | ||
955 | ||
1da177e4 | 956 | /* Super-IO chipset detection, Winbond, SMSC */ |
312facaf | 957 | static void show_parconfig_smsc37c669(int io, int key) |
1da177e4 | 958 | { |
181bf1e8 AC |
959 | int cr1, cr4, cra, cr23, cr26, cr27; |
960 | struct superio_struct *s; | |
961 | ||
3aeda9bc | 962 | static const char *const modes[] = { |
a6767b7c MK |
963 | "SPP and Bidirectional (PS/2)", |
964 | "EPP and SPP", | |
965 | "ECP", | |
966 | "ECP and EPP" }; | |
1da177e4 | 967 | |
3aeda9bc AC |
968 | outb(key, io); |
969 | outb(key, io); | |
970 | outb(1, io); | |
971 | cr1 = inb(io + 1); | |
972 | outb(4, io); | |
973 | cr4 = inb(io + 1); | |
974 | outb(0x0a, io); | |
975 | cra = inb(io + 1); | |
976 | outb(0x23, io); | |
977 | cr23 = inb(io + 1); | |
978 | outb(0x26, io); | |
979 | cr26 = inb(io + 1); | |
980 | outb(0x27, io); | |
981 | cr27 = inb(io + 1); | |
982 | outb(0xaa, io); | |
1da177e4 LT |
983 | |
984 | if (verbose_probing) { | |
3aeda9bc AC |
985 | printk(KERN_INFO |
986 | "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " | |
1da177e4 | 987 | "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", |
3aeda9bc AC |
988 | cr1, cr4, cra, cr23, cr26, cr27); |
989 | ||
1da177e4 LT |
990 | /* The documentation calls DMA and IRQ-Lines by letters, so |
991 | the board maker can/will wire them | |
992 | appropriately/randomly... G=reserved H=IDE-irq, */ | |
3aeda9bc AC |
993 | printk(KERN_INFO |
994 | "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", | |
995 | cr23 * 4, | |
996 | (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', | |
997 | (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', | |
998 | cra & 0x0f); | |
1da177e4 | 999 | printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", |
3aeda9bc AC |
1000 | (cr23 * 4 >= 0x100) ? "yes" : "no", |
1001 | (cr1 & 4) ? "yes" : "no"); | |
1002 | printk(KERN_INFO | |
1003 | "SMSC LPT Config: Port mode=%s, EPP version =%s\n", | |
1004 | (cr1 & 0x08) ? "Standard mode only (SPP)" | |
1005 | : modes[cr4 & 0x03], | |
1006 | (cr4 & 0x40) ? "1.7" : "1.9"); | |
1da177e4 | 1007 | } |
73e0d48b | 1008 | |
1da177e4 LT |
1009 | /* Heuristics ! BIOS setup for this mainboard device limits |
1010 | the choices to standard settings, i.e. io-address and IRQ | |
1011 | are related, however DMA can be 1 or 3, assume DMA_A=DMA1, | |
1012 | DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ | |
73e0d48b | 1013 | if (cr23 * 4 >= 0x100) { /* if active */ |
181bf1e8 AC |
1014 | s = find_free_superio(); |
1015 | if (s == NULL) | |
1da177e4 | 1016 | printk(KERN_INFO "Super-IO: too many chips!\n"); |
181bf1e8 | 1017 | else { |
1da177e4 | 1018 | int d; |
3aeda9bc AC |
1019 | switch (cr23 * 4) { |
1020 | case 0x3bc: | |
181bf1e8 AC |
1021 | s->io = 0x3bc; |
1022 | s->irq = 7; | |
3aeda9bc AC |
1023 | break; |
1024 | case 0x378: | |
181bf1e8 AC |
1025 | s->io = 0x378; |
1026 | s->irq = 7; | |
3aeda9bc AC |
1027 | break; |
1028 | case 0x278: | |
181bf1e8 AC |
1029 | s->io = 0x278; |
1030 | s->irq = 5; | |
1da177e4 | 1031 | } |
3aeda9bc AC |
1032 | d = (cr26 & 0x0f); |
1033 | if (d == 1 || d == 3) | |
181bf1e8 | 1034 | s->dma = d; |
1da177e4 | 1035 | else |
181bf1e8 | 1036 | s->dma = PARPORT_DMA_NONE; |
1da177e4 | 1037 | } |
3aeda9bc | 1038 | } |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | ||
312facaf | 1042 | static void show_parconfig_winbond(int io, int key) |
1da177e4 | 1043 | { |
181bf1e8 AC |
1044 | int cr30, cr60, cr61, cr70, cr74, crf0; |
1045 | struct superio_struct *s; | |
a6767b7c | 1046 | static const char *const modes[] = { |
1da177e4 LT |
1047 | "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ |
1048 | "EPP-1.9 and SPP", | |
1049 | "ECP", | |
1050 | "ECP and EPP-1.9", | |
1051 | "Standard (SPP)", | |
1052 | "EPP-1.7 and SPP", /* 5 */ | |
1053 | "undefined!", | |
1054 | "ECP and EPP-1.7" }; | |
a6767b7c MK |
1055 | static char *const irqtypes[] = { |
1056 | "pulsed low, high-Z", | |
1057 | "follows nACK" }; | |
3aeda9bc | 1058 | |
1da177e4 | 1059 | /* The registers are called compatible-PnP because the |
3aeda9bc AC |
1060 | register layout is modelled after ISA-PnP, the access |
1061 | method is just another ... */ | |
1062 | outb(key, io); | |
1063 | outb(key, io); | |
1064 | outb(0x07, io); /* Register 7: Select Logical Device */ | |
1065 | outb(0x01, io + 1); /* LD1 is Parallel Port */ | |
1066 | outb(0x30, io); | |
1067 | cr30 = inb(io + 1); | |
1068 | outb(0x60, io); | |
1069 | cr60 = inb(io + 1); | |
1070 | outb(0x61, io); | |
1071 | cr61 = inb(io + 1); | |
1072 | outb(0x70, io); | |
1073 | cr70 = inb(io + 1); | |
1074 | outb(0x74, io); | |
1075 | cr74 = inb(io + 1); | |
1076 | outb(0xf0, io); | |
1077 | crf0 = inb(io + 1); | |
1078 | outb(0xaa, io); | |
1da177e4 LT |
1079 | |
1080 | if (verbose_probing) { | |
3aeda9bc AC |
1081 | printk(KERN_INFO |
1082 | "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", | |
1083 | cr30, cr60, cr61, cr70, cr74, crf0); | |
1084 | printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", | |
1085 | (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); | |
1da177e4 | 1086 | if ((cr74 & 0x07) > 3) |
6979b928 | 1087 | pr_cont("dma=none\n"); |
1da177e4 | 1088 | else |
6979b928 | 1089 | pr_cont("dma=%d\n", cr74 & 0x07); |
3aeda9bc AC |
1090 | printk(KERN_INFO |
1091 | "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", | |
1092 | irqtypes[crf0>>7], (crf0>>3)&0x0f); | |
1093 | printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", | |
1094 | modes[crf0 & 0x07]); | |
1da177e4 LT |
1095 | } |
1096 | ||
73e0d48b | 1097 | if (cr30 & 0x01) { /* the settings can be interrogated later ... */ |
181bf1e8 AC |
1098 | s = find_free_superio(); |
1099 | if (s == NULL) | |
1da177e4 | 1100 | printk(KERN_INFO "Super-IO: too many chips!\n"); |
181bf1e8 AC |
1101 | else { |
1102 | s->io = (cr60 << 8) | cr61; | |
1103 | s->irq = cr70 & 0x0f; | |
1104 | s->dma = (((cr74 & 0x07) > 3) ? | |
1da177e4 LT |
1105 | PARPORT_DMA_NONE : (cr74 & 0x07)); |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | ||
312facaf | 1110 | static void decode_winbond(int efer, int key, int devid, int devrev, int oldid) |
1da177e4 LT |
1111 | { |
1112 | const char *type = "unknown"; | |
3aeda9bc | 1113 | int id, progif = 2; |
1da177e4 LT |
1114 | |
1115 | if (devid == devrev) | |
1116 | /* simple heuristics, we happened to read some | |
3aeda9bc | 1117 | non-winbond register */ |
1da177e4 LT |
1118 | return; |
1119 | ||
3aeda9bc | 1120 | id = (devid << 8) | devrev; |
1da177e4 LT |
1121 | |
1122 | /* Values are from public data sheets pdf files, I can just | |
3aeda9bc AC |
1123 | confirm 83977TF is correct :-) */ |
1124 | if (id == 0x9771) | |
1125 | type = "83977F/AF"; | |
1126 | else if (id == 0x9773) | |
1127 | type = "83977TF / SMSC 97w33x/97w34x"; | |
1128 | else if (id == 0x9774) | |
1129 | type = "83977ATF"; | |
1130 | else if ((id & ~0x0f) == 0x5270) | |
1131 | type = "83977CTF / SMSC 97w36x"; | |
1132 | else if ((id & ~0x0f) == 0x52f0) | |
1133 | type = "83977EF / SMSC 97w35x"; | |
1134 | else if ((id & ~0x0f) == 0x5210) | |
1135 | type = "83627"; | |
1136 | else if ((id & ~0x0f) == 0x6010) | |
1137 | type = "83697HF"; | |
1138 | else if ((oldid & 0x0f) == 0x0a) { | |
1139 | type = "83877F"; | |
1140 | progif = 1; | |
1141 | } else if ((oldid & 0x0f) == 0x0b) { | |
1142 | type = "83877AF"; | |
1143 | progif = 1; | |
1144 | } else if ((oldid & 0x0f) == 0x0c) { | |
1145 | type = "83877TF"; | |
1146 | progif = 1; | |
1147 | } else if ((oldid & 0x0f) == 0x0d) { | |
1148 | type = "83877ATF"; | |
1149 | progif = 1; | |
1150 | } else | |
1151 | progif = 0; | |
1da177e4 LT |
1152 | |
1153 | if (verbose_probing) | |
1154 | printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " | |
3aeda9bc | 1155 | "devid=%02x devrev=%02x oldid=%02x type=%s\n", |
1da177e4 LT |
1156 | efer, key, devid, devrev, oldid, type); |
1157 | ||
1158 | if (progif == 2) | |
3aeda9bc | 1159 | show_parconfig_winbond(efer, key); |
1da177e4 LT |
1160 | } |
1161 | ||
312facaf | 1162 | static void decode_smsc(int efer, int key, int devid, int devrev) |
1da177e4 | 1163 | { |
3aeda9bc | 1164 | const char *type = "unknown"; |
1da177e4 | 1165 | void (*func)(int io, int key); |
3aeda9bc | 1166 | int id; |
1da177e4 | 1167 | |
3aeda9bc | 1168 | if (devid == devrev) |
1da177e4 | 1169 | /* simple heuristics, we happened to read some |
3aeda9bc | 1170 | non-smsc register */ |
1da177e4 LT |
1171 | return; |
1172 | ||
3aeda9bc AC |
1173 | func = NULL; |
1174 | id = (devid << 8) | devrev; | |
1da177e4 | 1175 | |
3aeda9bc AC |
1176 | if (id == 0x0302) { |
1177 | type = "37c669"; | |
1178 | func = show_parconfig_smsc37c669; | |
1179 | } else if (id == 0x6582) | |
1180 | type = "37c665IR"; | |
1181 | else if (devid == 0x65) | |
1182 | type = "37c665GT"; | |
1183 | else if (devid == 0x66) | |
1184 | type = "37c666GT"; | |
1da177e4 LT |
1185 | |
1186 | if (verbose_probing) | |
1187 | printk(KERN_INFO "SMSC chip at EFER=0x%x " | |
1188 | "key=0x%02x devid=%02x devrev=%02x type=%s\n", | |
1189 | efer, key, devid, devrev, type); | |
1190 | ||
1191 | if (func) | |
3aeda9bc | 1192 | func(efer, key); |
1da177e4 LT |
1193 | } |
1194 | ||
1195 | ||
312facaf | 1196 | static void winbond_check(int io, int key) |
1da177e4 | 1197 | { |
e2434dc1 | 1198 | int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid; |
1da177e4 | 1199 | |
145980a0 | 1200 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1201 | return; |
1202 | ||
e2434dc1 JR |
1203 | origval = inb(io); /* Save original value */ |
1204 | ||
1da177e4 | 1205 | /* First probe without key */ |
3aeda9bc AC |
1206 | outb(0x20, io); |
1207 | x_devid = inb(io + 1); | |
1208 | outb(0x21, io); | |
1209 | x_devrev = inb(io + 1); | |
1210 | outb(0x09, io); | |
1211 | x_oldid = inb(io + 1); | |
1212 | ||
1213 | outb(key, io); | |
1214 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
25985edc | 1215 | function enable register */ |
3aeda9bc AC |
1216 | outb(0x20, io); /* Write EFIR, extended function index register */ |
1217 | devid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1218 | outb(0x21, io); | |
1219 | devrev = inb(io + 1); | |
1220 | outb(0x09, io); | |
1221 | oldid = inb(io + 1); | |
1222 | outb(0xaa, io); /* Magic Seal */ | |
1da177e4 | 1223 | |
e2434dc1 JR |
1224 | outb(origval, io); /* in case we poked some entirely different hardware */ |
1225 | ||
1da177e4 LT |
1226 | if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) |
1227 | goto out; /* protection against false positives */ | |
1228 | ||
3aeda9bc | 1229 | decode_winbond(io, key, devid, devrev, oldid); |
1da177e4 LT |
1230 | out: |
1231 | release_region(io, 3); | |
1232 | } | |
1233 | ||
312facaf | 1234 | static void winbond_check2(int io, int key) |
1da177e4 | 1235 | { |
e2434dc1 | 1236 | int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid; |
1da177e4 | 1237 | |
145980a0 | 1238 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1239 | return; |
1240 | ||
e2434dc1 JR |
1241 | origval[0] = inb(io); /* Save original values */ |
1242 | origval[1] = inb(io + 1); | |
1243 | origval[2] = inb(io + 2); | |
1244 | ||
1da177e4 | 1245 | /* First probe without the key */ |
3aeda9bc AC |
1246 | outb(0x20, io + 2); |
1247 | x_devid = inb(io + 2); | |
1248 | outb(0x21, io + 1); | |
1249 | x_devrev = inb(io + 2); | |
1250 | outb(0x09, io + 1); | |
1251 | x_oldid = inb(io + 2); | |
1252 | ||
1253 | outb(key, io); /* Write Magic Byte to EFER, extended | |
25985edc | 1254 | function enable register */ |
3aeda9bc AC |
1255 | outb(0x20, io + 2); /* Write EFIR, extended function index register */ |
1256 | devid = inb(io + 2); /* Read EFDR, extended function data register */ | |
1257 | outb(0x21, io + 1); | |
1258 | devrev = inb(io + 2); | |
1259 | outb(0x09, io + 1); | |
1260 | oldid = inb(io + 2); | |
1261 | outb(0xaa, io); /* Magic Seal */ | |
1262 | ||
e2434dc1 JR |
1263 | outb(origval[0], io); /* in case we poked some entirely different hardware */ |
1264 | outb(origval[1], io + 1); | |
1265 | outb(origval[2], io + 2); | |
1266 | ||
3aeda9bc | 1267 | if (x_devid == devid && x_devrev == devrev && x_oldid == oldid) |
1da177e4 LT |
1268 | goto out; /* protection against false positives */ |
1269 | ||
3aeda9bc | 1270 | decode_winbond(io, key, devid, devrev, oldid); |
1da177e4 LT |
1271 | out: |
1272 | release_region(io, 3); | |
1273 | } | |
1274 | ||
312facaf | 1275 | static void smsc_check(int io, int key) |
1da177e4 | 1276 | { |
e2434dc1 | 1277 | int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev; |
1da177e4 | 1278 | |
145980a0 | 1279 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1280 | return; |
1281 | ||
e2434dc1 JR |
1282 | origval = inb(io); /* Save original value */ |
1283 | ||
1da177e4 | 1284 | /* First probe without the key */ |
3aeda9bc AC |
1285 | outb(0x0d, io); |
1286 | x_oldid = inb(io + 1); | |
1287 | outb(0x0e, io); | |
1288 | x_oldrev = inb(io + 1); | |
1289 | outb(0x20, io); | |
1290 | x_id = inb(io + 1); | |
1291 | outb(0x21, io); | |
1292 | x_rev = inb(io + 1); | |
1293 | ||
1294 | outb(key, io); | |
1295 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
25985edc | 1296 | function enable register */ |
3aeda9bc AC |
1297 | outb(0x0d, io); /* Write EFIR, extended function index register */ |
1298 | oldid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1299 | outb(0x0e, io); | |
1300 | oldrev = inb(io + 1); | |
1301 | outb(0x20, io); | |
1302 | id = inb(io + 1); | |
1303 | outb(0x21, io); | |
1304 | rev = inb(io + 1); | |
1305 | outb(0xaa, io); /* Magic Seal */ | |
1306 | ||
e2434dc1 JR |
1307 | outb(origval, io); /* in case we poked some entirely different hardware */ |
1308 | ||
3aeda9bc AC |
1309 | if (x_id == id && x_oldrev == oldrev && |
1310 | x_oldid == oldid && x_rev == rev) | |
1da177e4 LT |
1311 | goto out; /* protection against false positives */ |
1312 | ||
3aeda9bc | 1313 | decode_smsc(io, key, oldid, oldrev); |
1da177e4 LT |
1314 | out: |
1315 | release_region(io, 3); | |
1316 | } | |
1317 | ||
1318 | ||
312facaf | 1319 | static void detect_and_report_winbond(void) |
3aeda9bc | 1320 | { |
1da177e4 LT |
1321 | if (verbose_probing) |
1322 | printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); | |
3aeda9bc AC |
1323 | winbond_check(0x3f0, 0x87); |
1324 | winbond_check(0x370, 0x87); | |
1325 | winbond_check(0x2e , 0x87); | |
1326 | winbond_check(0x4e , 0x87); | |
1327 | winbond_check(0x3f0, 0x86); | |
1328 | winbond_check2(0x250, 0x88); | |
1329 | winbond_check2(0x250, 0x89); | |
1da177e4 LT |
1330 | } |
1331 | ||
312facaf | 1332 | static void detect_and_report_smsc(void) |
1da177e4 LT |
1333 | { |
1334 | if (verbose_probing) | |
1335 | printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); | |
3aeda9bc AC |
1336 | smsc_check(0x3f0, 0x55); |
1337 | smsc_check(0x370, 0x55); | |
1338 | smsc_check(0x3f0, 0x44); | |
1339 | smsc_check(0x370, 0x44); | |
1da177e4 | 1340 | } |
f63fd7e2 | 1341 | |
312facaf | 1342 | static void detect_and_report_it87(void) |
f63fd7e2 PC |
1343 | { |
1344 | u16 dev; | |
e2434dc1 | 1345 | u8 origval, r; |
f63fd7e2 PC |
1346 | if (verbose_probing) |
1347 | printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); | |
868d1721 | 1348 | if (!request_muxed_region(0x2e, 2, __func__)) |
f63fd7e2 | 1349 | return; |
e2434dc1 | 1350 | origval = inb(0x2e); /* Save original value */ |
f63fd7e2 PC |
1351 | outb(0x87, 0x2e); |
1352 | outb(0x01, 0x2e); | |
1353 | outb(0x55, 0x2e); | |
1354 | outb(0x55, 0x2e); | |
1355 | outb(0x20, 0x2e); | |
1356 | dev = inb(0x2f) << 8; | |
1357 | outb(0x21, 0x2e); | |
1358 | dev |= inb(0x2f); | |
1359 | if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || | |
1360 | dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { | |
1361 | printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); | |
1362 | outb(0x07, 0x2E); /* Parallel Port */ | |
1363 | outb(0x03, 0x2F); | |
1364 | outb(0xF0, 0x2E); /* BOOT 0x80 off */ | |
1365 | r = inb(0x2f); | |
1366 | outb(0xF0, 0x2E); | |
1367 | outb(r | 8, 0x2F); | |
1368 | outb(0x02, 0x2E); /* Lock */ | |
1369 | outb(0x02, 0x2F); | |
e2434dc1 JR |
1370 | } else { |
1371 | outb(origval, 0x2e); /* Oops, sorry to disturb */ | |
f63fd7e2 | 1372 | } |
e2434dc1 | 1373 | release_region(0x2e, 2); |
f63fd7e2 | 1374 | } |
1da177e4 LT |
1375 | #endif /* CONFIG_PARPORT_PC_SUPERIO */ |
1376 | ||
181bf1e8 | 1377 | static struct superio_struct *find_superio(struct parport *p) |
1da177e4 | 1378 | { |
181bf1e8 AC |
1379 | int i; |
1380 | for (i = 0; i < NR_SUPERIOS; i++) | |
21698fd5 | 1381 | if (superios[i].io == p->base) |
181bf1e8 AC |
1382 | return &superios[i]; |
1383 | return NULL; | |
1384 | } | |
73e0d48b | 1385 | |
181bf1e8 AC |
1386 | static int get_superio_dma(struct parport *p) |
1387 | { | |
1388 | struct superio_struct *s = find_superio(p); | |
1389 | if (s) | |
1390 | return s->dma; | |
1da177e4 LT |
1391 | return PARPORT_DMA_NONE; |
1392 | } | |
1393 | ||
3aeda9bc | 1394 | static int get_superio_irq(struct parport *p) |
1da177e4 | 1395 | { |
181bf1e8 AC |
1396 | struct superio_struct *s = find_superio(p); |
1397 | if (s) | |
1398 | return s->irq; | |
3aeda9bc | 1399 | return PARPORT_IRQ_NONE; |
1da177e4 | 1400 | } |
73e0d48b | 1401 | |
1da177e4 LT |
1402 | |
1403 | /* --- Mode detection ------------------------------------- */ | |
1404 | ||
1405 | /* | |
1406 | * Checks for port existence, all ports support SPP MODE | |
3aeda9bc | 1407 | * Returns: |
1da177e4 | 1408 | * 0 : No parallel port at this address |
3aeda9bc | 1409 | * PARPORT_MODE_PCSPP : SPP port detected |
1da177e4 LT |
1410 | * (if the user specified an ioport himself, |
1411 | * this shall always be the case!) | |
1412 | * | |
1413 | */ | |
96766a3c | 1414 | static int parport_SPP_supported(struct parport *pb) |
1da177e4 LT |
1415 | { |
1416 | unsigned char r, w; | |
1417 | ||
1418 | /* | |
3aeda9bc | 1419 | * first clear an eventually pending EPP timeout |
1da177e4 LT |
1420 | * I (sailer@ife.ee.ethz.ch) have an SMSC chipset |
1421 | * that does not even respond to SPP cycles if an EPP | |
1422 | * timeout is pending | |
1423 | */ | |
1424 | clear_epp_timeout(pb); | |
1425 | ||
1426 | /* Do a simple read-write test to make sure the port exists. */ | |
1427 | w = 0xc; | |
3aeda9bc | 1428 | outb(w, CONTROL(pb)); |
1da177e4 LT |
1429 | |
1430 | /* Is there a control register that we can read from? Some | |
1431 | * ports don't allow reads, so read_control just returns a | |
1432 | * software copy. Some ports _do_ allow reads, so bypass the | |
1433 | * software copy here. In addition, some bits aren't | |
1434 | * writable. */ | |
3aeda9bc | 1435 | r = inb(CONTROL(pb)); |
1da177e4 LT |
1436 | if ((r & 0xf) == w) { |
1437 | w = 0xe; | |
3aeda9bc AC |
1438 | outb(w, CONTROL(pb)); |
1439 | r = inb(CONTROL(pb)); | |
1440 | outb(0xc, CONTROL(pb)); | |
1da177e4 LT |
1441 | if ((r & 0xf) == w) |
1442 | return PARPORT_MODE_PCSPP; | |
1443 | } | |
1444 | ||
1445 | if (user_specified) | |
1446 | /* That didn't work, but the user thinks there's a | |
1447 | * port here. */ | |
3aeda9bc | 1448 | printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " |
1da177e4 LT |
1449 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); |
1450 | ||
1451 | /* Try the data register. The data lines aren't tri-stated at | |
1452 | * this stage, so we expect back what we wrote. */ | |
1453 | w = 0xaa; | |
3aeda9bc AC |
1454 | parport_pc_write_data(pb, w); |
1455 | r = parport_pc_read_data(pb); | |
1da177e4 LT |
1456 | if (r == w) { |
1457 | w = 0x55; | |
3aeda9bc AC |
1458 | parport_pc_write_data(pb, w); |
1459 | r = parport_pc_read_data(pb); | |
1da177e4 LT |
1460 | if (r == w) |
1461 | return PARPORT_MODE_PCSPP; | |
1462 | } | |
1463 | ||
1464 | if (user_specified) { | |
1465 | /* Didn't work, but the user is convinced this is the | |
1466 | * place. */ | |
3aeda9bc | 1467 | printk(KERN_INFO "parport 0x%lx (WARNING): DATA: " |
1da177e4 | 1468 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); |
3aeda9bc | 1469 | printk(KERN_INFO "parport 0x%lx: You gave this address, " |
1da177e4 LT |
1470 | "but there is probably no parallel port there!\n", |
1471 | pb->base); | |
1472 | } | |
1473 | ||
1474 | /* It's possible that we can't read the control register or | |
1475 | * the data register. In that case just believe the user. */ | |
1476 | if (user_specified) | |
1477 | return PARPORT_MODE_PCSPP; | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | /* Check for ECR | |
1483 | * | |
1484 | * Old style XT ports alias io ports every 0x400, hence accessing ECR | |
1485 | * on these cards actually accesses the CTR. | |
1486 | * | |
1487 | * Modern cards don't do this but reading from ECR will return 0xff | |
1488 | * regardless of what is written here if the card does NOT support | |
1489 | * ECP. | |
1490 | * | |
1491 | * We first check to see if ECR is the same as CTR. If not, the low | |
1492 | * two bits of ECR aren't writable, so we check by writing ECR and | |
1493 | * reading it back to see if it's what we expect. | |
1494 | */ | |
96766a3c | 1495 | static int parport_ECR_present(struct parport *pb) |
1da177e4 LT |
1496 | { |
1497 | struct parport_pc_private *priv = pb->private_data; | |
1498 | unsigned char r = 0xc; | |
1499 | ||
3aeda9bc AC |
1500 | outb(r, CONTROL(pb)); |
1501 | if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { | |
1502 | outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ | |
1da177e4 | 1503 | |
3aeda9bc AC |
1504 | r = inb(CONTROL(pb)); |
1505 | if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) | |
1da177e4 LT |
1506 | goto no_reg; /* Sure that no ECR register exists */ |
1507 | } | |
3aeda9bc AC |
1508 | |
1509 | if ((inb(ECONTROL(pb)) & 0x3) != 0x1) | |
1da177e4 LT |
1510 | goto no_reg; |
1511 | ||
3aeda9bc AC |
1512 | ECR_WRITE(pb, 0x34); |
1513 | if (inb(ECONTROL(pb)) != 0x35) | |
1da177e4 LT |
1514 | goto no_reg; |
1515 | ||
1516 | priv->ecr = 1; | |
3aeda9bc AC |
1517 | outb(0xc, CONTROL(pb)); |
1518 | ||
1da177e4 | 1519 | /* Go to mode 000 */ |
3aeda9bc | 1520 | frob_set_mode(pb, ECR_SPP); |
1da177e4 LT |
1521 | |
1522 | return 1; | |
1523 | ||
1524 | no_reg: | |
3aeda9bc AC |
1525 | outb(0xc, CONTROL(pb)); |
1526 | return 0; | |
1da177e4 LT |
1527 | } |
1528 | ||
1529 | #ifdef CONFIG_PARPORT_1284 | |
1530 | /* Detect PS/2 support. | |
1531 | * | |
1532 | * Bit 5 (0x20) sets the PS/2 data direction; setting this high | |
1533 | * allows us to read data from the data lines. In theory we would get back | |
1534 | * 0xff but any peripheral attached to the port may drag some or all of the | |
1535 | * lines down to zero. So if we get back anything that isn't the contents | |
3aeda9bc | 1536 | * of the data register we deem PS/2 support to be present. |
1da177e4 LT |
1537 | * |
1538 | * Some SPP ports have "half PS/2" ability - you can't turn off the line | |
1539 | * drivers, but an external peripheral with sufficiently beefy drivers of | |
1540 | * its own can overpower them and assert its own levels onto the bus, from | |
1541 | * where they can then be read back as normal. Ports with this property | |
1542 | * and the right type of device attached are likely to fail the SPP test, | |
1543 | * (as they will appear to have stuck bits) and so the fact that they might | |
3aeda9bc | 1544 | * be misdetected here is rather academic. |
1da177e4 LT |
1545 | */ |
1546 | ||
96766a3c | 1547 | static int parport_PS2_supported(struct parport *pb) |
1da177e4 LT |
1548 | { |
1549 | int ok = 0; | |
3aeda9bc | 1550 | |
1da177e4 LT |
1551 | clear_epp_timeout(pb); |
1552 | ||
1553 | /* try to tri-state the buffer */ | |
3aeda9bc AC |
1554 | parport_pc_data_reverse(pb); |
1555 | ||
1da177e4 | 1556 | parport_pc_write_data(pb, 0x55); |
3aeda9bc AC |
1557 | if (parport_pc_read_data(pb) != 0x55) |
1558 | ok++; | |
1da177e4 LT |
1559 | |
1560 | parport_pc_write_data(pb, 0xaa); | |
3aeda9bc AC |
1561 | if (parport_pc_read_data(pb) != 0xaa) |
1562 | ok++; | |
1da177e4 LT |
1563 | |
1564 | /* cancel input mode */ | |
3aeda9bc | 1565 | parport_pc_data_forward(pb); |
1da177e4 LT |
1566 | |
1567 | if (ok) { | |
1568 | pb->modes |= PARPORT_MODE_TRISTATE; | |
1569 | } else { | |
1570 | struct parport_pc_private *priv = pb->private_data; | |
1571 | priv->ctr_writable &= ~0x20; | |
1572 | } | |
1573 | ||
1574 | return ok; | |
1575 | } | |
1576 | ||
1577 | #ifdef CONFIG_PARPORT_PC_FIFO | |
55265b00 | 1578 | static int parport_ECP_supported(struct parport *pb) |
1da177e4 LT |
1579 | { |
1580 | int i; | |
1581 | int config, configb; | |
1582 | int pword; | |
1583 | struct parport_pc_private *priv = pb->private_data; | |
3aeda9bc AC |
1584 | /* Translate ECP intrLine to ISA irq value */ |
1585 | static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; | |
1da177e4 LT |
1586 | |
1587 | /* If there is no ECR, we have no hope of supporting ECP. */ | |
1588 | if (!priv->ecr) | |
1589 | return 0; | |
1590 | ||
1591 | /* Find out FIFO depth */ | |
3aeda9bc AC |
1592 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ |
1593 | ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */ | |
1594 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) | |
1595 | outb(0xaa, FIFO(pb)); | |
1da177e4 LT |
1596 | |
1597 | /* | |
1598 | * Using LGS chipset it uses ECR register, but | |
1599 | * it doesn't support ECP or FIFO MODE | |
1600 | */ | |
1601 | if (i == 1024) { | |
3aeda9bc | 1602 | ECR_WRITE(pb, ECR_SPP << 5); |
1da177e4 LT |
1603 | return 0; |
1604 | } | |
1605 | ||
1606 | priv->fifo_depth = i; | |
1607 | if (verbose_probing) | |
3aeda9bc | 1608 | printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); |
1da177e4 LT |
1609 | |
1610 | /* Find out writeIntrThreshold */ | |
3aeda9bc AC |
1611 | frob_econtrol(pb, 1<<2, 1<<2); |
1612 | frob_econtrol(pb, 1<<2, 0); | |
1da177e4 | 1613 | for (i = 1; i <= priv->fifo_depth; i++) { |
3aeda9bc AC |
1614 | inb(FIFO(pb)); |
1615 | udelay(50); | |
1616 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1da177e4 LT |
1617 | break; |
1618 | } | |
1619 | ||
1620 | if (i <= priv->fifo_depth) { | |
1621 | if (verbose_probing) | |
3aeda9bc | 1622 | printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", |
1da177e4 LT |
1623 | pb->base, i); |
1624 | } else | |
1625 | /* Number of bytes we know we can write if we get an | |
3aeda9bc | 1626 | interrupt. */ |
1da177e4 LT |
1627 | i = 0; |
1628 | ||
1629 | priv->writeIntrThreshold = i; | |
1630 | ||
1631 | /* Find out readIntrThreshold */ | |
3aeda9bc AC |
1632 | frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */ |
1633 | parport_pc_data_reverse(pb); /* Must be in PS2 mode */ | |
1634 | frob_set_mode(pb, ECR_TST); /* Test FIFO */ | |
1635 | frob_econtrol(pb, 1<<2, 1<<2); | |
1636 | frob_econtrol(pb, 1<<2, 0); | |
1da177e4 | 1637 | for (i = 1; i <= priv->fifo_depth; i++) { |
3aeda9bc AC |
1638 | outb(0xaa, FIFO(pb)); |
1639 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1da177e4 LT |
1640 | break; |
1641 | } | |
1642 | ||
1643 | if (i <= priv->fifo_depth) { | |
1644 | if (verbose_probing) | |
3aeda9bc | 1645 | printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n", |
1da177e4 LT |
1646 | pb->base, i); |
1647 | } else | |
1648 | /* Number of bytes we can read if we get an interrupt. */ | |
1649 | i = 0; | |
1650 | ||
1651 | priv->readIntrThreshold = i; | |
1652 | ||
3aeda9bc AC |
1653 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ |
1654 | ECR_WRITE(pb, 0xf4); /* Configuration mode */ | |
1655 | config = inb(CONFIGA(pb)); | |
1da177e4 LT |
1656 | pword = (config >> 4) & 0x7; |
1657 | switch (pword) { | |
1658 | case 0: | |
1659 | pword = 2; | |
3aeda9bc | 1660 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", |
1da177e4 LT |
1661 | pb->base); |
1662 | break; | |
1663 | case 2: | |
1664 | pword = 4; | |
3aeda9bc | 1665 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", |
1da177e4 LT |
1666 | pb->base); |
1667 | break; | |
1668 | default: | |
3aeda9bc | 1669 | printk(KERN_WARNING "0x%lx: Unknown implementation ID\n", |
1da177e4 | 1670 | pb->base); |
aa1f0fa3 | 1671 | /* Fall through - Assume 1 */ |
1da177e4 LT |
1672 | case 1: |
1673 | pword = 1; | |
1674 | } | |
1675 | priv->pword = pword; | |
1676 | ||
1677 | if (verbose_probing) { | |
3aeda9bc AC |
1678 | printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", |
1679 | pb->base, 8 * pword); | |
1680 | ||
1681 | printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, | |
1da177e4 LT |
1682 | config & 0x80 ? "Level" : "Pulses"); |
1683 | ||
3aeda9bc AC |
1684 | configb = inb(CONFIGB(pb)); |
1685 | printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", | |
1da177e4 | 1686 | pb->base, config, configb); |
3aeda9bc AC |
1687 | printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); |
1688 | if ((configb >> 3) & 0x07) | |
6979b928 | 1689 | pr_cont("%d", intrline[(configb >> 3) & 0x07]); |
1da177e4 | 1690 | else |
6979b928 MP |
1691 | pr_cont("<none or set by other means>"); |
1692 | pr_cont(" dma="); | |
3aeda9bc | 1693 | if ((configb & 0x03) == 0x00) |
6979b928 | 1694 | pr_cont("<none or set by other means>\n"); |
1da177e4 | 1695 | else |
6979b928 | 1696 | pr_cont("%d\n", configb & 0x07); |
1da177e4 LT |
1697 | } |
1698 | ||
1699 | /* Go back to mode 000 */ | |
3aeda9bc | 1700 | frob_set_mode(pb, ECR_SPP); |
1da177e4 LT |
1701 | |
1702 | return 1; | |
1703 | } | |
1704 | #endif | |
1705 | ||
0ae39cc9 MK |
1706 | #ifdef CONFIG_X86_32 |
1707 | static int intel_bug_present_check_epp(struct parport *pb) | |
17891c8a MK |
1708 | { |
1709 | const struct parport_pc_private *priv = pb->private_data; | |
1710 | int bug_present = 0; | |
1711 | ||
1712 | if (priv->ecr) { | |
1713 | /* store value of ECR */ | |
1714 | unsigned char ecr = inb(ECONTROL(pb)); | |
1715 | unsigned char i; | |
1716 | for (i = 0x00; i < 0x80; i += 0x20) { | |
1717 | ECR_WRITE(pb, i); | |
1718 | if (clear_epp_timeout(pb)) { | |
1719 | /* Phony EPP in ECP. */ | |
1720 | bug_present = 1; | |
1721 | break; | |
1722 | } | |
1723 | } | |
1724 | /* return ECR into the inital state */ | |
1725 | ECR_WRITE(pb, ecr); | |
1726 | } | |
1727 | ||
1728 | return bug_present; | |
1729 | } | |
0ae39cc9 MK |
1730 | static int intel_bug_present(struct parport *pb) |
1731 | { | |
1732 | /* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */ | |
1733 | if (pb->dev != NULL) { | |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | return intel_bug_present_check_epp(pb); | |
1738 | } | |
1739 | #else | |
1740 | static int intel_bug_present(struct parport *pb) | |
1741 | { | |
1742 | return 0; | |
1743 | } | |
1744 | #endif /* CONFIG_X86_32 */ | |
17891c8a | 1745 | |
96766a3c | 1746 | static int parport_ECPPS2_supported(struct parport *pb) |
1da177e4 LT |
1747 | { |
1748 | const struct parport_pc_private *priv = pb->private_data; | |
1749 | int result; | |
1750 | unsigned char oecr; | |
1751 | ||
1752 | if (!priv->ecr) | |
1753 | return 0; | |
1754 | ||
3aeda9bc AC |
1755 | oecr = inb(ECONTROL(pb)); |
1756 | ECR_WRITE(pb, ECR_PS2 << 5); | |
1da177e4 | 1757 | result = parport_PS2_supported(pb); |
3aeda9bc | 1758 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
1759 | return result; |
1760 | } | |
1761 | ||
1762 | /* EPP mode detection */ | |
1763 | ||
96766a3c | 1764 | static int parport_EPP_supported(struct parport *pb) |
1da177e4 | 1765 | { |
1da177e4 LT |
1766 | /* |
1767 | * Theory: | |
1768 | * Bit 0 of STR is the EPP timeout bit, this bit is 0 | |
1769 | * when EPP is possible and is set high when an EPP timeout | |
1770 | * occurs (EPP uses the HALT line to stop the CPU while it does | |
1771 | * the byte transfer, an EPP timeout occurs if the attached | |
1772 | * device fails to respond after 10 micro seconds). | |
1773 | * | |
1774 | * This bit is cleared by either reading it (National Semi) | |
1775 | * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? | |
1776 | * This bit is always high in non EPP modes. | |
1777 | */ | |
1778 | ||
1779 | /* If EPP timeout bit clear then EPP available */ | |
3aeda9bc | 1780 | if (!clear_epp_timeout(pb)) |
1da177e4 | 1781 | return 0; /* No way to clear timeout */ |
1da177e4 LT |
1782 | |
1783 | /* Check for Intel bug. */ | |
17891c8a MK |
1784 | if (intel_bug_present(pb)) |
1785 | return 0; | |
1da177e4 LT |
1786 | |
1787 | pb->modes |= PARPORT_MODE_EPP; | |
1788 | ||
1789 | /* Set up access functions to use EPP hardware. */ | |
1790 | pb->ops->epp_read_data = parport_pc_epp_read_data; | |
1791 | pb->ops->epp_write_data = parport_pc_epp_write_data; | |
1792 | pb->ops->epp_read_addr = parport_pc_epp_read_addr; | |
1793 | pb->ops->epp_write_addr = parport_pc_epp_write_addr; | |
1794 | ||
1795 | return 1; | |
1796 | } | |
1797 | ||
96766a3c | 1798 | static int parport_ECPEPP_supported(struct parport *pb) |
1da177e4 LT |
1799 | { |
1800 | struct parport_pc_private *priv = pb->private_data; | |
1801 | int result; | |
1802 | unsigned char oecr; | |
1803 | ||
3aeda9bc | 1804 | if (!priv->ecr) |
1da177e4 | 1805 | return 0; |
1da177e4 | 1806 | |
3aeda9bc | 1807 | oecr = inb(ECONTROL(pb)); |
1da177e4 | 1808 | /* Search for SMC style EPP+ECP mode */ |
3aeda9bc AC |
1809 | ECR_WRITE(pb, 0x80); |
1810 | outb(0x04, CONTROL(pb)); | |
1da177e4 LT |
1811 | result = parport_EPP_supported(pb); |
1812 | ||
3aeda9bc | 1813 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
1814 | |
1815 | if (result) { | |
1816 | /* Set up access functions to use ECP+EPP hardware. */ | |
1817 | pb->ops->epp_read_data = parport_pc_ecpepp_read_data; | |
1818 | pb->ops->epp_write_data = parport_pc_ecpepp_write_data; | |
1819 | pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; | |
1820 | pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; | |
1821 | } | |
1822 | ||
1823 | return result; | |
1824 | } | |
1825 | ||
1826 | #else /* No IEEE 1284 support */ | |
1827 | ||
1828 | /* Don't bother probing for modes we know we won't use. */ | |
312facaf | 1829 | static int parport_PS2_supported(struct parport *pb) { return 0; } |
1da177e4 | 1830 | #ifdef CONFIG_PARPORT_PC_FIFO |
3aeda9bc AC |
1831 | static int parport_ECP_supported(struct parport *pb) |
1832 | { | |
1833 | return 0; | |
1834 | } | |
1da177e4 | 1835 | #endif |
312facaf | 1836 | static int parport_EPP_supported(struct parport *pb) |
3aeda9bc AC |
1837 | { |
1838 | return 0; | |
1839 | } | |
1840 | ||
312facaf | 1841 | static int parport_ECPEPP_supported(struct parport *pb) |
3aeda9bc AC |
1842 | { |
1843 | return 0; | |
1844 | } | |
1845 | ||
312facaf | 1846 | static int parport_ECPPS2_supported(struct parport *pb) |
3aeda9bc AC |
1847 | { |
1848 | return 0; | |
1849 | } | |
1da177e4 LT |
1850 | |
1851 | #endif /* No IEEE 1284 support */ | |
1852 | ||
1853 | /* --- IRQ detection -------------------------------------- */ | |
1854 | ||
1855 | /* Only if supports ECP mode */ | |
4438982f | 1856 | static int programmable_irq_support(struct parport *pb) |
1da177e4 LT |
1857 | { |
1858 | int irq, intrLine; | |
3aeda9bc | 1859 | unsigned char oecr = inb(ECONTROL(pb)); |
1da177e4 LT |
1860 | static const int lookup[8] = { |
1861 | PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 | |
1862 | }; | |
1863 | ||
3aeda9bc | 1864 | ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */ |
1da177e4 | 1865 | |
3aeda9bc | 1866 | intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; |
1da177e4 LT |
1867 | irq = lookup[intrLine]; |
1868 | ||
3aeda9bc | 1869 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
1870 | return irq; |
1871 | } | |
1872 | ||
4438982f | 1873 | static int irq_probe_ECP(struct parport *pb) |
1da177e4 LT |
1874 | { |
1875 | int i; | |
1876 | unsigned long irqs; | |
1877 | ||
1878 | irqs = probe_irq_on(); | |
3aeda9bc AC |
1879 | |
1880 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ | |
1881 | ECR_WRITE(pb, (ECR_TST << 5) | 0x04); | |
1882 | ECR_WRITE(pb, ECR_TST << 5); | |
1da177e4 LT |
1883 | |
1884 | /* If Full FIFO sure that writeIntrThreshold is generated */ | |
3aeda9bc AC |
1885 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) |
1886 | outb(0xaa, FIFO(pb)); | |
1887 | ||
1da177e4 | 1888 | pb->irq = probe_irq_off(irqs); |
3aeda9bc | 1889 | ECR_WRITE(pb, ECR_SPP << 5); |
1da177e4 LT |
1890 | |
1891 | if (pb->irq <= 0) | |
1892 | pb->irq = PARPORT_IRQ_NONE; | |
1893 | ||
1894 | return pb->irq; | |
1895 | } | |
1896 | ||
1897 | /* | |
1898 | * This detection seems that only works in National Semiconductors | |
3aeda9bc | 1899 | * This doesn't work in SMC, LGS, and Winbond |
1da177e4 | 1900 | */ |
4438982f | 1901 | static int irq_probe_EPP(struct parport *pb) |
1da177e4 LT |
1902 | { |
1903 | #ifndef ADVANCED_DETECT | |
1904 | return PARPORT_IRQ_NONE; | |
1905 | #else | |
1906 | int irqs; | |
1907 | unsigned char oecr; | |
1908 | ||
1909 | if (pb->modes & PARPORT_MODE_PCECR) | |
3aeda9bc | 1910 | oecr = inb(ECONTROL(pb)); |
1da177e4 LT |
1911 | |
1912 | irqs = probe_irq_on(); | |
1913 | ||
1914 | if (pb->modes & PARPORT_MODE_PCECR) | |
3aeda9bc AC |
1915 | frob_econtrol(pb, 0x10, 0x10); |
1916 | ||
1da177e4 | 1917 | clear_epp_timeout(pb); |
3aeda9bc AC |
1918 | parport_pc_frob_control(pb, 0x20, 0x20); |
1919 | parport_pc_frob_control(pb, 0x10, 0x10); | |
1da177e4 LT |
1920 | clear_epp_timeout(pb); |
1921 | ||
1922 | /* Device isn't expecting an EPP read | |
1923 | * and generates an IRQ. | |
1924 | */ | |
1925 | parport_pc_read_epp(pb); | |
1926 | udelay(20); | |
1927 | ||
3aeda9bc | 1928 | pb->irq = probe_irq_off(irqs); |
1da177e4 | 1929 | if (pb->modes & PARPORT_MODE_PCECR) |
3aeda9bc | 1930 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
1931 | parport_pc_write_control(pb, 0xc); |
1932 | ||
1933 | if (pb->irq <= 0) | |
1934 | pb->irq = PARPORT_IRQ_NONE; | |
1935 | ||
1936 | return pb->irq; | |
1937 | #endif /* Advanced detection */ | |
1938 | } | |
1939 | ||
4438982f | 1940 | static int irq_probe_SPP(struct parport *pb) |
1da177e4 LT |
1941 | { |
1942 | /* Don't even try to do this. */ | |
1943 | return PARPORT_IRQ_NONE; | |
1944 | } | |
1945 | ||
1946 | /* We will attempt to share interrupt requests since other devices | |
1947 | * such as sound cards and network cards seem to like using the | |
1948 | * printer IRQs. | |
1949 | * | |
1950 | * When ECP is available we can autoprobe for IRQs. | |
1951 | * NOTE: If we can autoprobe it, we can register the IRQ. | |
1952 | */ | |
96766a3c | 1953 | static int parport_irq_probe(struct parport *pb) |
1da177e4 LT |
1954 | { |
1955 | struct parport_pc_private *priv = pb->private_data; | |
1956 | ||
1957 | if (priv->ecr) { | |
1958 | pb->irq = programmable_irq_support(pb); | |
1959 | ||
1960 | if (pb->irq == PARPORT_IRQ_NONE) | |
1961 | pb->irq = irq_probe_ECP(pb); | |
1962 | } | |
1963 | ||
1964 | if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && | |
1965 | (pb->modes & PARPORT_MODE_EPP)) | |
1966 | pb->irq = irq_probe_EPP(pb); | |
1967 | ||
1968 | clear_epp_timeout(pb); | |
1969 | ||
1970 | if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) | |
1971 | pb->irq = irq_probe_EPP(pb); | |
1972 | ||
1973 | clear_epp_timeout(pb); | |
1974 | ||
1975 | if (pb->irq == PARPORT_IRQ_NONE) | |
1976 | pb->irq = irq_probe_SPP(pb); | |
1977 | ||
1978 | if (pb->irq == PARPORT_IRQ_NONE) | |
1979 | pb->irq = get_superio_irq(pb); | |
1980 | ||
1981 | return pb->irq; | |
1982 | } | |
1983 | ||
1984 | /* --- DMA detection -------------------------------------- */ | |
1985 | ||
1986 | /* Only if chipset conforms to ECP ISA Interface Standard */ | |
3aeda9bc | 1987 | static int programmable_dma_support(struct parport *p) |
1da177e4 | 1988 | { |
3aeda9bc | 1989 | unsigned char oecr = inb(ECONTROL(p)); |
1da177e4 LT |
1990 | int dma; |
1991 | ||
3aeda9bc AC |
1992 | frob_set_mode(p, ECR_CNF); |
1993 | ||
1994 | dma = inb(CONFIGB(p)) & 0x07; | |
1da177e4 LT |
1995 | /* 000: Indicates jumpered 8-bit DMA if read-only. |
1996 | 100: Indicates jumpered 16-bit DMA if read-only. */ | |
1997 | if ((dma & 0x03) == 0) | |
1998 | dma = PARPORT_DMA_NONE; | |
1999 | ||
3aeda9bc | 2000 | ECR_WRITE(p, oecr); |
1da177e4 LT |
2001 | return dma; |
2002 | } | |
2003 | ||
3aeda9bc | 2004 | static int parport_dma_probe(struct parport *p) |
1da177e4 LT |
2005 | { |
2006 | const struct parport_pc_private *priv = p->private_data; | |
3aeda9bc AC |
2007 | if (priv->ecr) /* ask ECP chipset first */ |
2008 | p->dma = programmable_dma_support(p); | |
1da177e4 LT |
2009 | if (p->dma == PARPORT_DMA_NONE) { |
2010 | /* ask known Super-IO chips proper, although these | |
2011 | claim ECP compatible, some don't report their DMA | |
2012 | conforming to ECP standards */ | |
2013 | p->dma = get_superio_dma(p); | |
2014 | } | |
2015 | ||
2016 | return p->dma; | |
2017 | } | |
2018 | ||
2019 | /* --- Initialisation code -------------------------------- */ | |
2020 | ||
2021 | static LIST_HEAD(ports_list); | |
2022 | static DEFINE_SPINLOCK(ports_lock); | |
2023 | ||
51dcdfec AC |
2024 | struct parport *parport_pc_probe_port(unsigned long int base, |
2025 | unsigned long int base_hi, | |
2026 | int irq, int dma, | |
2027 | struct device *dev, | |
2028 | int irqflags) | |
1da177e4 LT |
2029 | { |
2030 | struct parport_pc_private *priv; | |
2031 | struct parport_operations *ops; | |
2032 | struct parport *p; | |
2033 | int probedirq = PARPORT_IRQ_NONE; | |
2034 | struct resource *base_res; | |
2035 | struct resource *ECR_res = NULL; | |
2036 | struct resource *EPP_res = NULL; | |
a7d801af | 2037 | struct platform_device *pdev = NULL; |
93b11b25 | 2038 | int ret; |
a7d801af JD |
2039 | |
2040 | if (!dev) { | |
2041 | /* We need a physical device to attach to, but none was | |
2042 | * provided. Create our own. */ | |
2043 | pdev = platform_device_register_simple("parport_pc", | |
2044 | base, NULL, 0); | |
2045 | if (IS_ERR(pdev)) | |
2046 | return NULL; | |
2047 | dev = &pdev->dev; | |
dfa7c4d8 | 2048 | |
93b11b25 RK |
2049 | ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24)); |
2050 | if (ret) { | |
2051 | dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n"); | |
2052 | dma = PARPORT_DMA_NONE; | |
2053 | } | |
a7d801af | 2054 | } |
1da177e4 | 2055 | |
51dcdfec | 2056 | ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); |
1da177e4 LT |
2057 | if (!ops) |
2058 | goto out1; | |
2059 | ||
51dcdfec | 2060 | priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL); |
1da177e4 LT |
2061 | if (!priv) |
2062 | goto out2; | |
2063 | ||
2064 | /* a misnomer, actually - it's allocate and reserve parport number */ | |
2065 | p = parport_register_port(base, irq, dma, ops); | |
2066 | if (!p) | |
2067 | goto out3; | |
2068 | ||
2069 | base_res = request_region(base, 3, p->name); | |
2070 | if (!base_res) | |
2071 | goto out4; | |
2072 | ||
3aeda9bc | 2073 | memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations)); |
1da177e4 LT |
2074 | priv->ctr = 0xc; |
2075 | priv->ctr_writable = ~0x10; | |
2076 | priv->ecr = 0; | |
2077 | priv->fifo_depth = 0; | |
2078 | priv->dma_buf = NULL; | |
2079 | priv->dma_handle = 0; | |
1da177e4 LT |
2080 | INIT_LIST_HEAD(&priv->list); |
2081 | priv->port = p; | |
c15a3837 DB |
2082 | |
2083 | p->dev = dev; | |
1da177e4 LT |
2084 | p->base_hi = base_hi; |
2085 | p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; | |
2086 | p->private_data = priv; | |
2087 | ||
2088 | if (base_hi) { | |
2089 | ECR_res = request_region(base_hi, 3, p->name); | |
2090 | if (ECR_res) | |
2091 | parport_ECR_present(p); | |
2092 | } | |
2093 | ||
2094 | if (base != 0x3bc) { | |
2095 | EPP_res = request_region(base+0x3, 5, p->name); | |
2096 | if (EPP_res) | |
2097 | if (!parport_EPP_supported(p)) | |
2098 | parport_ECPEPP_supported(p); | |
2099 | } | |
3aeda9bc | 2100 | if (!parport_SPP_supported(p)) |
1da177e4 LT |
2101 | /* No port. */ |
2102 | goto out5; | |
2103 | if (priv->ecr) | |
2104 | parport_ECPPS2_supported(p); | |
2105 | else | |
2106 | parport_PS2_supported(p); | |
2107 | ||
3aeda9bc | 2108 | p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; |
1da177e4 LT |
2109 | |
2110 | printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); | |
2111 | if (p->base_hi && priv->ecr) | |
2c03ead6 | 2112 | printk(KERN_CONT " (0x%lx)", p->base_hi); |
1da177e4 LT |
2113 | if (p->irq == PARPORT_IRQ_AUTO) { |
2114 | p->irq = PARPORT_IRQ_NONE; | |
2115 | parport_irq_probe(p); | |
2116 | } else if (p->irq == PARPORT_IRQ_PROBEONLY) { | |
2117 | p->irq = PARPORT_IRQ_NONE; | |
2118 | parport_irq_probe(p); | |
2119 | probedirq = p->irq; | |
2120 | p->irq = PARPORT_IRQ_NONE; | |
2121 | } | |
2122 | if (p->irq != PARPORT_IRQ_NONE) { | |
2c03ead6 | 2123 | printk(KERN_CONT ", irq %d", p->irq); |
1da177e4 LT |
2124 | priv->ctr_writable |= 0x10; |
2125 | ||
2126 | if (p->dma == PARPORT_DMA_AUTO) { | |
2127 | p->dma = PARPORT_DMA_NONE; | |
2128 | parport_dma_probe(p); | |
2129 | } | |
2130 | } | |
2131 | if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq | |
3aeda9bc | 2132 | is mandatory (see above) */ |
1da177e4 LT |
2133 | p->dma = PARPORT_DMA_NONE; |
2134 | ||
2135 | #ifdef CONFIG_PARPORT_PC_FIFO | |
2136 | if (parport_ECP_supported(p) && | |
2137 | p->dma != PARPORT_DMA_NOFIFO && | |
2138 | priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { | |
2139 | p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; | |
2140 | p->ops->compat_write_data = parport_pc_compat_write_block_pio; | |
2141 | #ifdef CONFIG_PARPORT_1284 | |
2142 | p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; | |
2143 | /* currently broken, but working on it.. (FB) */ | |
2144 | /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ | |
2145 | #endif /* IEEE 1284 support */ | |
2146 | if (p->dma != PARPORT_DMA_NONE) { | |
2c03ead6 | 2147 | printk(KERN_CONT ", dma %d", p->dma); |
1da177e4 | 2148 | p->modes |= PARPORT_MODE_DMA; |
3aeda9bc | 2149 | } else |
2c03ead6 | 2150 | printk(KERN_CONT ", using FIFO"); |
3aeda9bc | 2151 | } else |
1da177e4 LT |
2152 | /* We can't use the DMA channel after all. */ |
2153 | p->dma = PARPORT_DMA_NONE; | |
2154 | #endif /* Allowed to use FIFO/DMA */ | |
2155 | ||
2c03ead6 | 2156 | printk(KERN_CONT " ["); |
3aeda9bc AC |
2157 | |
2158 | #define printmode(x) \ | |
2159 | {\ | |
2160 | if (p->modes & PARPORT_MODE_##x) {\ | |
2c03ead6 | 2161 | printk(KERN_CONT "%s%s", f ? "," : "", #x);\ |
3aeda9bc AC |
2162 | f++;\ |
2163 | } \ | |
2164 | } | |
2165 | ||
1da177e4 LT |
2166 | { |
2167 | int f = 0; | |
2168 | printmode(PCSPP); | |
2169 | printmode(TRISTATE); | |
2170 | printmode(COMPAT) | |
2171 | printmode(EPP); | |
2172 | printmode(ECP); | |
2173 | printmode(DMA); | |
2174 | } | |
2175 | #undef printmode | |
2176 | #ifndef CONFIG_PARPORT_1284 | |
2c03ead6 | 2177 | printk(KERN_CONT "(,...)"); |
1da177e4 | 2178 | #endif /* CONFIG_PARPORT_1284 */ |
2c03ead6 | 2179 | printk(KERN_CONT "]\n"); |
3aeda9bc | 2180 | if (probedirq != PARPORT_IRQ_NONE) |
1da177e4 LT |
2181 | printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); |
2182 | ||
2183 | /* If No ECP release the ports grabbed above. */ | |
2184 | if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { | |
2185 | release_region(base_hi, 3); | |
2186 | ECR_res = NULL; | |
2187 | } | |
2188 | /* Likewise for EEP ports */ | |
2189 | if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { | |
2190 | release_region(base+3, 5); | |
2191 | EPP_res = NULL; | |
2192 | } | |
2193 | if (p->irq != PARPORT_IRQ_NONE) { | |
51dcdfec AC |
2194 | if (request_irq(p->irq, parport_irq_handler, |
2195 | irqflags, p->name, p)) { | |
3aeda9bc | 2196 | printk(KERN_WARNING "%s: irq %d in use, " |
1da177e4 LT |
2197 | "resorting to polled operation\n", |
2198 | p->name, p->irq); | |
2199 | p->irq = PARPORT_IRQ_NONE; | |
2200 | p->dma = PARPORT_DMA_NONE; | |
2201 | } | |
2202 | ||
2203 | #ifdef CONFIG_PARPORT_PC_FIFO | |
7fbacd52 | 2204 | #ifdef HAS_DMA |
1da177e4 | 2205 | if (p->dma != PARPORT_DMA_NONE) { |
3aeda9bc AC |
2206 | if (request_dma(p->dma, p->name)) { |
2207 | printk(KERN_WARNING "%s: dma %d in use, " | |
1da177e4 LT |
2208 | "resorting to PIO operation\n", |
2209 | p->name, p->dma); | |
2210 | p->dma = PARPORT_DMA_NONE; | |
2211 | } else { | |
2212 | priv->dma_buf = | |
c15a3837 | 2213 | dma_alloc_coherent(dev, |
1da177e4 | 2214 | PAGE_SIZE, |
c15a3837 DB |
2215 | &priv->dma_handle, |
2216 | GFP_KERNEL); | |
3aeda9bc AC |
2217 | if (!priv->dma_buf) { |
2218 | printk(KERN_WARNING "%s: " | |
1da177e4 LT |
2219 | "cannot get buffer for DMA, " |
2220 | "resorting to PIO operation\n", | |
2221 | p->name); | |
2222 | free_dma(p->dma); | |
2223 | p->dma = PARPORT_DMA_NONE; | |
2224 | } | |
2225 | } | |
2226 | } | |
7fbacd52 AV |
2227 | #endif |
2228 | #endif | |
1da177e4 LT |
2229 | } |
2230 | ||
2231 | /* Done probing. Now put the port into a sensible start-up state. */ | |
2232 | if (priv->ecr) | |
2233 | /* | |
2234 | * Put the ECP detected port in PS2 mode. | |
2235 | * Do this also for ports that have ECR but don't do ECP. | |
2236 | */ | |
3aeda9bc | 2237 | ECR_WRITE(p, 0x34); |
1da177e4 LT |
2238 | |
2239 | parport_pc_write_data(p, 0); | |
3aeda9bc | 2240 | parport_pc_data_forward(p); |
1da177e4 LT |
2241 | |
2242 | /* Now that we've told the sharing engine about the port, and | |
2243 | found out its characteristics, let the high-level drivers | |
2244 | know about it. */ | |
2245 | spin_lock(&ports_lock); | |
2246 | list_add(&priv->list, &ports_list); | |
2247 | spin_unlock(&ports_lock); | |
3aeda9bc | 2248 | parport_announce_port(p); |
1da177e4 LT |
2249 | |
2250 | return p; | |
2251 | ||
2252 | out5: | |
2253 | if (ECR_res) | |
2254 | release_region(base_hi, 3); | |
2255 | if (EPP_res) | |
2256 | release_region(base+0x3, 5); | |
2257 | release_region(base, 3); | |
2258 | out4: | |
6fa45a22 | 2259 | parport_del_port(p); |
1da177e4 | 2260 | out3: |
3aeda9bc | 2261 | kfree(priv); |
1da177e4 | 2262 | out2: |
3aeda9bc | 2263 | kfree(ops); |
1da177e4 | 2264 | out1: |
a7d801af JD |
2265 | if (pdev) |
2266 | platform_device_unregister(pdev); | |
1da177e4 LT |
2267 | return NULL; |
2268 | } | |
3aeda9bc | 2269 | EXPORT_SYMBOL(parport_pc_probe_port); |
1da177e4 | 2270 | |
3aeda9bc | 2271 | void parport_pc_unregister_port(struct parport *p) |
1da177e4 LT |
2272 | { |
2273 | struct parport_pc_private *priv = p->private_data; | |
2274 | struct parport_operations *ops = p->ops; | |
2275 | ||
2276 | parport_remove_port(p); | |
2277 | spin_lock(&ports_lock); | |
2278 | list_del_init(&priv->list); | |
2279 | spin_unlock(&ports_lock); | |
d1c4ac40 | 2280 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 LT |
2281 | if (p->dma != PARPORT_DMA_NONE) |
2282 | free_dma(p->dma); | |
d1c4ac40 | 2283 | #endif |
1da177e4 LT |
2284 | if (p->irq != PARPORT_IRQ_NONE) |
2285 | free_irq(p->irq, p); | |
2286 | release_region(p->base, 3); | |
2287 | if (p->size > 3) | |
2288 | release_region(p->base + 3, p->size - 3); | |
2289 | if (p->modes & PARPORT_MODE_ECP) | |
2290 | release_region(p->base_hi, 3); | |
d1c4ac40 | 2291 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 | 2292 | if (priv->dma_buf) |
c15a3837 | 2293 | dma_free_coherent(p->physport->dev, PAGE_SIZE, |
1da177e4 LT |
2294 | priv->dma_buf, |
2295 | priv->dma_handle); | |
7fbacd52 | 2296 | #endif |
3aeda9bc | 2297 | kfree(p->private_data); |
6fa45a22 | 2298 | parport_del_port(p); |
3aeda9bc | 2299 | kfree(ops); /* hope no-one cached it */ |
1da177e4 | 2300 | } |
3aeda9bc | 2301 | EXPORT_SYMBOL(parport_pc_unregister_port); |
1da177e4 LT |
2302 | |
2303 | #ifdef CONFIG_PCI | |
2304 | ||
2305 | /* ITE support maintained by Rich Liu <richliu@poorman.org> */ | |
312facaf GKH |
2306 | static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, |
2307 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2308 | { |
2309 | short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; | |
1da177e4 LT |
2310 | u32 ite8872set; |
2311 | u32 ite8872_lpt, ite8872_lpthi; | |
2312 | u8 ite8872_irq, type; | |
1da177e4 LT |
2313 | int irq; |
2314 | int i; | |
2315 | ||
3aeda9bc AC |
2316 | DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n"); |
2317 | ||
2318 | /* make sure which one chip */ | |
2319 | for (i = 0; i < 5; i++) { | |
0f6db217 | 2320 | if (request_region(inta_addr[i], 32, "it887x")) { |
1da177e4 | 2321 | int test; |
3aeda9bc | 2322 | pci_write_config_dword(pdev, 0x60, |
e7c310c3 | 2323 | 0xe5000000 | inta_addr[i]); |
3aeda9bc | 2324 | pci_write_config_dword(pdev, 0x78, |
1da177e4 | 2325 | 0x00000000 | inta_addr[i]); |
3aeda9bc AC |
2326 | test = inb(inta_addr[i]); |
2327 | if (test != 0xff) | |
2328 | break; | |
0f6db217 | 2329 | release_region(inta_addr[i], 32); |
1da177e4 LT |
2330 | } |
2331 | } | |
3aeda9bc AC |
2332 | if (i >= 5) { |
2333 | printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); | |
1da177e4 LT |
2334 | return 0; |
2335 | } | |
2336 | ||
3aeda9bc | 2337 | type = inb(inta_addr[i] + 0x18); |
1da177e4 LT |
2338 | type &= 0x0f; |
2339 | ||
2340 | switch (type) { | |
2341 | case 0x2: | |
3aeda9bc | 2342 | printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n"); |
1da177e4 LT |
2343 | ite8872set = 0x64200000; |
2344 | break; | |
2345 | case 0xa: | |
3aeda9bc | 2346 | printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n"); |
1da177e4 LT |
2347 | ite8872set = 0x64200000; |
2348 | break; | |
2349 | case 0xe: | |
3aeda9bc | 2350 | printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); |
1da177e4 LT |
2351 | ite8872set = 0x64e00000; |
2352 | break; | |
2353 | case 0x6: | |
3aeda9bc | 2354 | printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n"); |
9fdbdd06 | 2355 | release_region(inta_addr[i], 32); |
1da177e4 LT |
2356 | return 0; |
2357 | case 0x8: | |
6c8e4c92 | 2358 | printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n"); |
9fdbdd06 | 2359 | release_region(inta_addr[i], 32); |
1da177e4 LT |
2360 | return 0; |
2361 | default: | |
3aeda9bc AC |
2362 | printk(KERN_INFO "parport_pc: unknown ITE887x\n"); |
2363 | printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' " | |
1da177e4 | 2364 | "output to Rich.Liu@ite.com.tw\n"); |
9fdbdd06 | 2365 | release_region(inta_addr[i], 32); |
1da177e4 LT |
2366 | return 0; |
2367 | } | |
2368 | ||
3aeda9bc AC |
2369 | pci_read_config_byte(pdev, 0x3c, &ite8872_irq); |
2370 | pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); | |
1da177e4 | 2371 | ite8872_lpt &= 0x0000ff00; |
3aeda9bc | 2372 | pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); |
1da177e4 | 2373 | ite8872_lpthi &= 0x0000ff00; |
3aeda9bc AC |
2374 | pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); |
2375 | pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); | |
2376 | pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); | |
2377 | /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */ | |
2378 | /* SET Parallel IRQ */ | |
2379 | pci_write_config_dword(pdev, 0x9c, | |
1da177e4 LT |
2380 | ite8872set | (ite8872_irq * 0x11111)); |
2381 | ||
3aeda9bc AC |
2382 | DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); |
2383 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", | |
1da177e4 | 2384 | ite8872_lpt); |
3aeda9bc | 2385 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", |
1da177e4 LT |
2386 | ite8872_lpthi); |
2387 | ||
2388 | /* Let the user (or defaults) steer us away from interrupts */ | |
2389 | irq = ite8872_irq; | |
2390 | if (autoirq != PARPORT_IRQ_AUTO) | |
2391 | irq = PARPORT_IRQ_NONE; | |
2392 | ||
2393 | /* | |
2394 | * Release the resource so that parport_pc_probe_port can get it. | |
2395 | */ | |
0f6db217 | 2396 | release_region(inta_addr[i], 32); |
3aeda9bc | 2397 | if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, |
51dcdfec | 2398 | irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { |
3aeda9bc | 2399 | printk(KERN_INFO |
1da177e4 | 2400 | "parport_pc: ITE 8872 parallel port: io=0x%X", |
3aeda9bc | 2401 | ite8872_lpt); |
1da177e4 | 2402 | if (irq != PARPORT_IRQ_NONE) |
6979b928 MP |
2403 | pr_cont(", irq=%d", irq); |
2404 | pr_cont("\n"); | |
1da177e4 LT |
2405 | return 1; |
2406 | } | |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
2411 | /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> | |
2412 | based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ | |
312facaf | 2413 | static int parport_init_mode; |
1da177e4 LT |
2414 | |
2415 | /* Data for two known VIA chips */ | |
312facaf | 2416 | static struct parport_pc_via_data via_686a_data = { |
1da177e4 LT |
2417 | 0x51, |
2418 | 0x50, | |
2419 | 0x85, | |
2420 | 0x02, | |
2421 | 0xE2, | |
2422 | 0xF0, | |
2423 | 0xE6 | |
2424 | }; | |
312facaf | 2425 | static struct parport_pc_via_data via_8231_data = { |
1da177e4 LT |
2426 | 0x45, |
2427 | 0x44, | |
2428 | 0x50, | |
2429 | 0x04, | |
2430 | 0xF2, | |
2431 | 0xFA, | |
2432 | 0xF6 | |
2433 | }; | |
2434 | ||
312facaf GKH |
2435 | static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, |
2436 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2437 | { |
2438 | u8 tmp, tmp2, siofunc; | |
2439 | u8 ppcontrol = 0; | |
2440 | int dma, irq; | |
2441 | unsigned port1, port2; | |
2442 | unsigned have_epp = 0; | |
2443 | ||
2444 | printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); | |
2445 | ||
3aeda9bc | 2446 | switch (parport_init_mode) { |
1da177e4 | 2447 | case 1: |
3aeda9bc AC |
2448 | printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); |
2449 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2450 | break; | |
1da177e4 | 2451 | case 2: |
3aeda9bc AC |
2452 | printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); |
2453 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2454 | ppcontrol = VIA_PARPORT_BIDIR; | |
2455 | break; | |
1da177e4 | 2456 | case 3: |
3aeda9bc AC |
2457 | printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); |
2458 | siofunc = VIA_FUNCTION_PARPORT_EPP; | |
2459 | ppcontrol = VIA_PARPORT_BIDIR; | |
2460 | have_epp = 1; | |
2461 | break; | |
1da177e4 | 2462 | case 4: |
3aeda9bc AC |
2463 | printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); |
2464 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2465 | ppcontrol = VIA_PARPORT_BIDIR; | |
2466 | break; | |
1da177e4 | 2467 | case 5: |
3aeda9bc AC |
2468 | printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); |
2469 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2470 | ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; | |
2471 | have_epp = 1; | |
2472 | break; | |
2473 | default: | |
2474 | printk(KERN_DEBUG | |
2475 | "parport_pc: probing current configuration\n"); | |
2476 | siofunc = VIA_FUNCTION_PROBE; | |
2477 | break; | |
1da177e4 LT |
2478 | } |
2479 | /* | |
2480 | * unlock super i/o configuration | |
2481 | */ | |
2482 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2483 | tmp |= via->via_pci_superio_config_data; | |
2484 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2485 | ||
2486 | /* Bits 1-0: Parallel Port Mode / Enable */ | |
2487 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
3aeda9bc | 2488 | tmp = inb(VIA_CONFIG_DATA); |
1da177e4 LT |
2489 | /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ |
2490 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
3aeda9bc AC |
2491 | tmp2 = inb(VIA_CONFIG_DATA); |
2492 | if (siofunc == VIA_FUNCTION_PROBE) { | |
2493 | siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; | |
2494 | ppcontrol = tmp2; | |
2495 | } else { | |
2496 | tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; | |
2497 | tmp |= siofunc; | |
2498 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2499 | outb(tmp, VIA_CONFIG_DATA); | |
2500 | tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); | |
2501 | tmp2 |= ppcontrol; | |
2502 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2503 | outb(tmp2, VIA_CONFIG_DATA); | |
1da177e4 | 2504 | } |
3aeda9bc | 2505 | |
1da177e4 LT |
2506 | /* Parallel Port I/O Base Address, bits 9-2 */ |
2507 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2508 | port1 = inb(VIA_CONFIG_DATA) << 2; | |
3aeda9bc AC |
2509 | |
2510 | printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", | |
2511 | port1); | |
2512 | if (port1 == 0x3BC && have_epp) { | |
2513 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2514 | outb((0x378 >> 2), VIA_CONFIG_DATA); | |
2515 | printk(KERN_DEBUG | |
2516 | "parport_pc: Parallel port base changed to 0x378\n"); | |
2517 | port1 = 0x378; | |
1da177e4 LT |
2518 | } |
2519 | ||
2520 | /* | |
2521 | * lock super i/o configuration | |
2522 | */ | |
2523 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2524 | tmp &= ~via->via_pci_superio_config_data; | |
2525 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2526 | ||
2527 | if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { | |
2528 | printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); | |
2529 | return 0; | |
2530 | } | |
3aeda9bc | 2531 | |
1da177e4 LT |
2532 | /* Bits 7-4: PnP Routing for Parallel Port IRQ */ |
2533 | pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); | |
2534 | irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); | |
2535 | ||
3aeda9bc AC |
2536 | if (siofunc == VIA_FUNCTION_PARPORT_ECP) { |
2537 | /* Bits 3-2: PnP Routing for Parallel Port DMA */ | |
2538 | pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); | |
2539 | dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); | |
2540 | } else | |
2541 | /* if ECP not enabled, DMA is not enabled, assumed | |
2542 | bogus 'dma' value */ | |
2543 | dma = PARPORT_DMA_NONE; | |
1da177e4 LT |
2544 | |
2545 | /* Let the user (or defaults) steer us away from interrupts and DMA */ | |
2546 | if (autoirq == PARPORT_IRQ_NONE) { | |
3aeda9bc AC |
2547 | irq = PARPORT_IRQ_NONE; |
2548 | dma = PARPORT_DMA_NONE; | |
1da177e4 LT |
2549 | } |
2550 | if (autodma == PARPORT_DMA_NONE) | |
3aeda9bc | 2551 | dma = PARPORT_DMA_NONE; |
1da177e4 LT |
2552 | |
2553 | switch (port1) { | |
3aeda9bc AC |
2554 | case 0x3bc: |
2555 | port2 = 0x7bc; break; | |
2556 | case 0x378: | |
2557 | port2 = 0x778; break; | |
2558 | case 0x278: | |
2559 | port2 = 0x678; break; | |
1da177e4 | 2560 | default: |
3aeda9bc AC |
2561 | printk(KERN_INFO |
2562 | "parport_pc: Weird VIA parport base 0x%X, ignoring\n", | |
2563 | port1); | |
1da177e4 LT |
2564 | return 0; |
2565 | } | |
2566 | ||
2567 | /* filter bogus IRQs */ | |
2568 | switch (irq) { | |
2569 | case 0: | |
2570 | case 2: | |
2571 | case 8: | |
2572 | case 13: | |
2573 | irq = PARPORT_IRQ_NONE; | |
2574 | break; | |
2575 | ||
2576 | default: /* do nothing */ | |
2577 | break; | |
2578 | } | |
2579 | ||
2580 | /* finally, do the probe with values obtained */ | |
3aeda9bc AC |
2581 | if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { |
2582 | printk(KERN_INFO | |
1da177e4 LT |
2583 | "parport_pc: VIA parallel port: io=0x%X", port1); |
2584 | if (irq != PARPORT_IRQ_NONE) | |
6979b928 | 2585 | pr_cont(", irq=%d", irq); |
1da177e4 | 2586 | if (dma != PARPORT_DMA_NONE) |
6979b928 MP |
2587 | pr_cont(", dma=%d", dma); |
2588 | pr_cont("\n"); | |
1da177e4 LT |
2589 | return 1; |
2590 | } | |
3aeda9bc | 2591 | |
1da177e4 LT |
2592 | printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", |
2593 | port1, irq, dma); | |
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | ||
2598 | enum parport_pc_sio_types { | |
3aeda9bc AC |
2599 | sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ |
2600 | sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ | |
1da177e4 LT |
2601 | sio_ite_8872, |
2602 | last_sio | |
2603 | }; | |
2604 | ||
2605 | /* each element directly indexed from enum list, above */ | |
2606 | static struct parport_pc_superio { | |
a6767b7c MK |
2607 | int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, |
2608 | const struct parport_pc_via_data *via); | |
2609 | const struct parport_pc_via_data *via; | |
312facaf | 2610 | } parport_pc_superio_info[] = { |
1da177e4 LT |
2611 | { sio_via_probe, &via_686a_data, }, |
2612 | { sio_via_probe, &via_8231_data, }, | |
2613 | { sio_ite_8872_probe, NULL, }, | |
2614 | }; | |
2615 | ||
2616 | enum parport_pc_pci_cards { | |
2617 | siig_1p_10x = last_sio, | |
2618 | siig_2p_10x, | |
2619 | siig_1p_20x, | |
2620 | siig_2p_20x, | |
2621 | lava_parallel, | |
2622 | lava_parallel_dual_a, | |
2623 | lava_parallel_dual_b, | |
2624 | boca_ioppar, | |
2625 | plx_9050, | |
1da177e4 LT |
2626 | timedia_4006a, |
2627 | timedia_4014, | |
2628 | timedia_4008a, | |
2629 | timedia_4018, | |
2630 | timedia_9018a, | |
2631 | syba_2p_epp, | |
2632 | syba_1p_ecp, | |
2633 | titan_010l, | |
1da177e4 LT |
2634 | avlab_1p, |
2635 | avlab_2p, | |
c140e110 | 2636 | oxsemi_952, |
1da177e4 LT |
2637 | oxsemi_954, |
2638 | oxsemi_840, | |
7106b4e3 | 2639 | oxsemi_pcie_pport, |
1da177e4 LT |
2640 | aks_0100, |
2641 | mobility_pp, | |
2642 | netmos_9705, | |
2643 | netmos_9715, | |
2644 | netmos_9755, | |
2645 | netmos_9805, | |
2646 | netmos_9815, | |
c4285b47 | 2647 | netmos_9901, |
ac6ec5b1 | 2648 | netmos_9865, |
dc999159 | 2649 | quatech_sppxp100, |
823f7923 | 2650 | wch_ch382l, |
1da177e4 LT |
2651 | }; |
2652 | ||
2653 | ||
3aeda9bc | 2654 | /* each element directly indexed from enum list, above |
1da177e4 LT |
2655 | * (but offset by last_sio) */ |
2656 | static struct parport_pc_pci { | |
2657 | int numports; | |
2658 | struct { /* BAR (base address registers) numbers in the config | |
3aeda9bc | 2659 | space header */ |
1da177e4 | 2660 | int lo; |
3aeda9bc AC |
2661 | int hi; |
2662 | /* -1 if not there, >6 for offset-method (max BAR is 6) */ | |
1da177e4 LT |
2663 | } addr[4]; |
2664 | ||
2665 | /* If set, this is called immediately after pci_enable_device. | |
2666 | * If it returns non-zero, no probing will take place and the | |
2667 | * ports will not be used. */ | |
2668 | int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); | |
2669 | ||
2670 | /* If set, this is called after probing for ports. If 'failed' | |
2671 | * is non-zero we couldn't use any of the ports. */ | |
2672 | void (*postinit_hook) (struct pci_dev *pdev, int failed); | |
96766a3c | 2673 | } cards[] = { |
1da177e4 LT |
2674 | /* siig_1p_10x */ { 1, { { 2, 3 }, } }, |
2675 | /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2676 | /* siig_1p_20x */ { 1, { { 0, 1 }, } }, | |
2677 | /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2678 | /* lava_parallel */ { 1, { { 0, -1 }, } }, | |
2679 | /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, | |
2680 | /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, | |
2681 | /* boca_ioppar */ { 1, { { 0, -1 }, } }, | |
2682 | /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, | |
1da177e4 LT |
2683 | /* timedia_4006a */ { 1, { { 0, -1 }, } }, |
2684 | /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
2685 | /* timedia_4008a */ { 1, { { 0, 1 }, } }, | |
2686 | /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2687 | /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2688 | /* SYBA uses fixed offsets in | |
3aeda9bc | 2689 | a 1K io window */ |
1da177e4 LT |
2690 | /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, |
2691 | /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, | |
2692 | /* titan_010l */ { 1, { { 3, -1 }, } }, | |
1da177e4 LT |
2693 | /* avlab_1p */ { 1, { { 0, 1}, } }, |
2694 | /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, | |
2695 | /* The Oxford Semi cards are unusual: 954 doesn't support ECP, | |
2696 | * and 840 locks up if you write 1 to bit 2! */ | |
c140e110 | 2697 | /* oxsemi_952 */ { 1, { { 0, 1 }, } }, |
1da177e4 | 2698 | /* oxsemi_954 */ { 1, { { 0, -1 }, } }, |
adbd321a | 2699 | /* oxsemi_840 */ { 1, { { 0, 1 }, } }, |
7106b4e3 | 2700 | /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2701 | /* aks_0100 */ { 1, { { 0, -1 }, } }, |
2702 | /* mobility_pp */ { 1, { { 0, 1 }, } }, | |
3aeda9bc AC |
2703 | |
2704 | /* The netmos entries below are untested */ | |
2705 | /* netmos_9705 */ { 1, { { 0, -1 }, } }, | |
2706 | /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
2707 | /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
d6a48452 SAS |
2708 | /* netmos_9805 */ { 1, { { 0, 1 }, } }, |
2709 | /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
c4285b47 | 2710 | /* netmos_9901 */ { 1, { { 0, -1 }, } }, |
ac6ec5b1 | 2711 | /* netmos_9865 */ { 1, { { 0, -1 }, } }, |
dc999159 | 2712 | /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, |
823f7923 | 2713 | /* wch_ch382l */ { 1, { { 2, -1 }, } }, |
1da177e4 LT |
2714 | }; |
2715 | ||
a6767b7c | 2716 | static const struct pci_device_id parport_pc_pci_tbl[] = { |
1da177e4 LT |
2717 | /* Super-IO onboard chips */ |
2718 | { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, | |
2719 | { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, | |
2720 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | |
2721 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, | |
2722 | ||
2723 | /* PCI cards */ | |
2724 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, | |
2725 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, | |
2726 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, | |
2727 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, | |
2728 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, | |
2729 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, | |
2730 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, | |
2731 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, | |
2732 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, | |
2733 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, | |
2734 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, | |
2735 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, | |
2736 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, | |
2737 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, | |
2738 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, | |
2739 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, | |
2740 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3aeda9bc | 2741 | PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 }, |
1da177e4 | 2742 | /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ |
1da177e4 LT |
2743 | { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, |
2744 | { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, | |
2745 | { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, | |
2746 | { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, | |
2747 | { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, | |
1da177e4 LT |
2748 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, |
2749 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, | |
2750 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, | |
2751 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, | |
2752 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, | |
2753 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, | |
1da177e4 | 2754 | /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ |
3aeda9bc AC |
2755 | /* AFAVLAB_TK9902 */ |
2756 | { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, | |
1da177e4 | 2757 | { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, |
c140e110 RU |
2758 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, |
2759 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, | |
1da177e4 LT |
2760 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, |
2761 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, | |
2762 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, | |
2763 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, | |
7106b4e3 LH |
2764 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840, |
2765 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2766 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G, | |
2767 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2768 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0, | |
2769 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2770 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G, | |
2771 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2772 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1, | |
2773 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2774 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G, | |
2775 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2776 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U, | |
2777 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
2778 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU, | |
2779 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
1da177e4 LT |
2780 | { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, |
2781 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, | |
7106b4e3 | 2782 | { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, |
1da177e4 LT |
2783 | /* NetMos communication controllers */ |
2784 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, | |
2785 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, | |
2786 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, | |
2787 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, | |
2788 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, | |
2789 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, | |
2790 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, | |
2791 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, | |
2792 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, | |
2793 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, | |
c4285b47 MB |
2794 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, |
2795 | 0xA000, 0x2000, 0, 0, netmos_9901 }, | |
ac6ec5b1 IS |
2796 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
2797 | 0xA000, 0x1000, 0, 0, netmos_9865 }, | |
2798 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | |
2799 | 0xA000, 0x2000, 0, 0, netmos_9865 }, | |
dc999159 LM |
2800 | /* Quatech SPPXP-100 Parallel port PCI ExpressCard */ |
2801 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100, | |
2802 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, | |
823f7923 AG |
2803 | /* WCH CH382L PCI-E single parallel port card */ |
2804 | { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l }, | |
1da177e4 LT |
2805 | { 0, } /* terminate list */ |
2806 | }; | |
3aeda9bc | 2807 | MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl); |
1da177e4 LT |
2808 | |
2809 | struct pci_parport_data { | |
2810 | int num; | |
2811 | struct parport *ports[2]; | |
2812 | }; | |
2813 | ||
3aeda9bc | 2814 | static int parport_pc_pci_probe(struct pci_dev *dev, |
1da177e4 LT |
2815 | const struct pci_device_id *id) |
2816 | { | |
2817 | int err, count, n, i = id->driver_data; | |
2818 | struct pci_parport_data *data; | |
2819 | ||
2820 | if (i < last_sio) | |
2821 | /* This is an onboard Super-IO and has already been probed */ | |
2822 | return 0; | |
2823 | ||
2824 | /* This is a PCI card */ | |
2825 | i -= last_sio; | |
2826 | count = 0; | |
3aeda9bc AC |
2827 | err = pci_enable_device(dev); |
2828 | if (err) | |
1da177e4 LT |
2829 | return err; |
2830 | ||
2831 | data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); | |
2832 | if (!data) | |
2833 | return -ENOMEM; | |
2834 | ||
2835 | if (cards[i].preinit_hook && | |
3aeda9bc | 2836 | cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { |
1da177e4 LT |
2837 | kfree(data); |
2838 | return -ENODEV; | |
2839 | } | |
2840 | ||
2841 | for (n = 0; n < cards[i].numports; n++) { | |
2842 | int lo = cards[i].addr[n].lo; | |
2843 | int hi = cards[i].addr[n].hi; | |
51dcdfec | 2844 | int irq; |
1da177e4 | 2845 | unsigned long io_lo, io_hi; |
3aeda9bc | 2846 | io_lo = pci_resource_start(dev, lo); |
1da177e4 LT |
2847 | io_hi = 0; |
2848 | if ((hi >= 0) && (hi <= 6)) | |
3aeda9bc | 2849 | io_hi = pci_resource_start(dev, hi); |
1da177e4 LT |
2850 | else if (hi > 6) |
2851 | io_lo += hi; /* Reinterpret the meaning of | |
3aeda9bc AC |
2852 | "hi" as an offset (see SYBA |
2853 | def.) */ | |
1da177e4 | 2854 | /* TODO: test if sharing interrupts works */ |
51dcdfec AC |
2855 | irq = dev->irq; |
2856 | if (irq == IRQ_NONE) { | |
3aeda9bc | 2857 | printk(KERN_DEBUG |
51dcdfec | 2858 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", |
3f6e4859 | 2859 | id->vendor, id->device, io_lo, io_hi); |
51dcdfec AC |
2860 | irq = PARPORT_IRQ_NONE; |
2861 | } else { | |
3aeda9bc | 2862 | printk(KERN_DEBUG |
51dcdfec | 2863 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", |
3f6e4859 | 2864 | id->vendor, id->device, io_lo, io_hi, irq); |
51dcdfec | 2865 | } |
1da177e4 | 2866 | data->ports[count] = |
51dcdfec AC |
2867 | parport_pc_probe_port(io_lo, io_hi, irq, |
2868 | PARPORT_DMA_NONE, &dev->dev, | |
2869 | IRQF_SHARED); | |
1da177e4 LT |
2870 | if (data->ports[count]) |
2871 | count++; | |
2872 | } | |
2873 | ||
2874 | data->num = count; | |
2875 | ||
2876 | if (cards[i].postinit_hook) | |
3aeda9bc | 2877 | cards[i].postinit_hook(dev, count == 0); |
1da177e4 LT |
2878 | |
2879 | if (count) { | |
2880 | pci_set_drvdata(dev, data); | |
2881 | return 0; | |
2882 | } | |
2883 | ||
2884 | kfree(data); | |
2885 | ||
2886 | return -ENODEV; | |
2887 | } | |
2888 | ||
312facaf | 2889 | static void parport_pc_pci_remove(struct pci_dev *dev) |
1da177e4 LT |
2890 | { |
2891 | struct pci_parport_data *data = pci_get_drvdata(dev); | |
2892 | int i; | |
2893 | ||
1da177e4 LT |
2894 | if (data) { |
2895 | for (i = data->num - 1; i >= 0; i--) | |
2896 | parport_pc_unregister_port(data->ports[i]); | |
2897 | ||
2898 | kfree(data); | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | static struct pci_driver parport_pc_pci_driver = { | |
2903 | .name = "parport_pc", | |
2904 | .id_table = parport_pc_pci_tbl, | |
2905 | .probe = parport_pc_pci_probe, | |
312facaf | 2906 | .remove = parport_pc_pci_remove, |
1da177e4 LT |
2907 | }; |
2908 | ||
3aeda9bc | 2909 | static int __init parport_pc_init_superio(int autoirq, int autodma) |
1da177e4 LT |
2910 | { |
2911 | const struct pci_device_id *id; | |
2912 | struct pci_dev *pdev = NULL; | |
2913 | int ret = 0; | |
2914 | ||
c9d8073f | 2915 | for_each_pci_dev(pdev) { |
75865858 | 2916 | id = pci_match_id(parport_pc_pci_tbl, pdev); |
1da177e4 LT |
2917 | if (id == NULL || id->driver_data >= last_sio) |
2918 | continue; | |
2919 | ||
3aeda9bc AC |
2920 | if (parport_pc_superio_info[id->driver_data].probe( |
2921 | pdev, autoirq, autodma, | |
2922 | parport_pc_superio_info[id->driver_data].via)) { | |
1da177e4 LT |
2923 | ret++; |
2924 | } | |
2925 | } | |
2926 | ||
2927 | return ret; /* number of devices found */ | |
2928 | } | |
2929 | #else | |
2930 | static struct pci_driver parport_pc_pci_driver; | |
3aeda9bc AC |
2931 | static int __init parport_pc_init_superio(int autoirq, int autodma) |
2932 | { | |
2933 | return 0; | |
2934 | } | |
1da177e4 LT |
2935 | #endif /* CONFIG_PCI */ |
2936 | ||
f2b9a396 | 2937 | #ifdef CONFIG_PNP |
1da177e4 LT |
2938 | |
2939 | static const struct pnp_device_id parport_pc_pnp_tbl[] = { | |
2940 | /* Standard LPT Printer Port */ | |
2941 | {.id = "PNP0400", .driver_data = 0}, | |
2942 | /* ECP Printer Port */ | |
2943 | {.id = "PNP0401", .driver_data = 0}, | |
2944 | { } | |
2945 | }; | |
2946 | ||
3aeda9bc | 2947 | MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl); |
1da177e4 | 2948 | |
3aeda9bc AC |
2949 | static int parport_pc_pnp_probe(struct pnp_dev *dev, |
2950 | const struct pnp_device_id *id) | |
1da177e4 LT |
2951 | { |
2952 | struct parport *pdata; | |
2953 | unsigned long io_lo, io_hi; | |
2954 | int dma, irq; | |
2955 | ||
3aeda9bc AC |
2956 | if (pnp_port_valid(dev, 0) && |
2957 | !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2958 | io_lo = pnp_port_start(dev, 0); | |
1da177e4 LT |
2959 | } else |
2960 | return -EINVAL; | |
2961 | ||
3aeda9bc AC |
2962 | if (pnp_port_valid(dev, 1) && |
2963 | !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) { | |
2964 | io_hi = pnp_port_start(dev, 1); | |
1da177e4 LT |
2965 | } else |
2966 | io_hi = 0; | |
2967 | ||
3aeda9bc AC |
2968 | if (pnp_irq_valid(dev, 0) && |
2969 | !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2970 | irq = pnp_irq(dev, 0); | |
1da177e4 LT |
2971 | } else |
2972 | irq = PARPORT_IRQ_NONE; | |
2973 | ||
3aeda9bc AC |
2974 | if (pnp_dma_valid(dev, 0) && |
2975 | !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
2976 | dma = pnp_dma(dev, 0); | |
1da177e4 LT |
2977 | } else |
2978 | dma = PARPORT_DMA_NONE; | |
2979 | ||
c15a3837 | 2980 | dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); |
3aeda9bc AC |
2981 | pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); |
2982 | if (pdata == NULL) | |
1da177e4 LT |
2983 | return -ENODEV; |
2984 | ||
3aeda9bc | 2985 | pnp_set_drvdata(dev, pdata); |
1da177e4 LT |
2986 | return 0; |
2987 | } | |
2988 | ||
2989 | static void parport_pc_pnp_remove(struct pnp_dev *dev) | |
2990 | { | |
2991 | struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); | |
2992 | if (!pdata) | |
2993 | return; | |
2994 | ||
2995 | parport_pc_unregister_port(pdata); | |
2996 | } | |
2997 | ||
2998 | /* we only need the pnp layer to activate the device, at least for now */ | |
2999 | static struct pnp_driver parport_pc_pnp_driver = { | |
3000 | .name = "parport_pc", | |
3001 | .id_table = parport_pc_pnp_tbl, | |
3002 | .probe = parport_pc_pnp_probe, | |
3003 | .remove = parport_pc_pnp_remove, | |
3004 | }; | |
3005 | ||
f2b9a396 BH |
3006 | #else |
3007 | static struct pnp_driver parport_pc_pnp_driver; | |
3008 | #endif /* CONFIG_PNP */ | |
1da177e4 | 3009 | |
312facaf | 3010 | static int parport_pc_platform_probe(struct platform_device *pdev) |
a7d801af JD |
3011 | { |
3012 | /* Always succeed, the actual probing is done in | |
3013 | * parport_pc_probe_port(). */ | |
3014 | return 0; | |
3015 | } | |
3016 | ||
3017 | static struct platform_driver parport_pc_platform_driver = { | |
3018 | .driver = { | |
a7d801af JD |
3019 | .name = "parport_pc", |
3020 | }, | |
3021 | .probe = parport_pc_platform_probe, | |
3022 | }; | |
3023 | ||
1da177e4 | 3024 | /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ |
312facaf | 3025 | static int __attribute__((unused)) |
3aeda9bc | 3026 | parport_pc_find_isa_ports(int autoirq, int autodma) |
1da177e4 LT |
3027 | { |
3028 | int count = 0; | |
3029 | ||
51dcdfec | 3030 | if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) |
1da177e4 | 3031 | count++; |
51dcdfec | 3032 | if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) |
1da177e4 | 3033 | count++; |
51dcdfec | 3034 | if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) |
1da177e4 LT |
3035 | count++; |
3036 | ||
3037 | return count; | |
3038 | } | |
3039 | ||
3040 | /* This function is called by parport_pc_init if the user didn't | |
3041 | * specify any ports to probe. Its job is to find some ports. Order | |
3042 | * is important here -- we want ISA ports to be registered first, | |
3043 | * followed by PCI cards (for least surprise), but before that we want | |
3044 | * to do chipset-specific tests for some onboard ports that we know | |
3045 | * about. | |
3046 | * | |
3047 | * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY | |
3048 | * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO | |
3049 | */ | |
3aeda9bc | 3050 | static void __init parport_pc_find_ports(int autoirq, int autodma) |
1da177e4 | 3051 | { |
7597fee3 | 3052 | int count = 0, err; |
1da177e4 LT |
3053 | |
3054 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
f63fd7e2 PC |
3055 | detect_and_report_it87(); |
3056 | detect_and_report_winbond(); | |
3057 | detect_and_report_smsc(); | |
1da177e4 LT |
3058 | #endif |
3059 | ||
3060 | /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ | |
f63fd7e2 | 3061 | count += parport_pc_init_superio(autoirq, autodma); |
1da177e4 LT |
3062 | |
3063 | /* PnP ports, skip detection if SuperIO already found them */ | |
3064 | if (!count) { | |
f63fd7e2 | 3065 | err = pnp_register_driver(&parport_pc_pnp_driver); |
7597fee3 | 3066 | if (!err) |
1da177e4 | 3067 | pnp_registered_parport = 1; |
1da177e4 LT |
3068 | } |
3069 | ||
3070 | /* ISA ports and whatever (see asm/parport.h). */ | |
f63fd7e2 | 3071 | parport_pc_find_nonpci_ports(autoirq, autodma); |
1da177e4 | 3072 | |
f63fd7e2 | 3073 | err = pci_register_driver(&parport_pc_pci_driver); |
7597fee3 BH |
3074 | if (!err) |
3075 | pci_registered_parport = 1; | |
1da177e4 LT |
3076 | } |
3077 | ||
3078 | /* | |
3079 | * Piles of crap below pretend to be a parser for module and kernel | |
3080 | * parameters. Say "thank you" to whoever had come up with that | |
3081 | * syntax and keep in mind that code below is a cleaned up version. | |
3082 | */ | |
3083 | ||
3aeda9bc AC |
3084 | static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { |
3085 | [0 ... PARPORT_PC_MAX_PORTS] = 0 | |
3086 | }; | |
3087 | static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = { | |
3088 | [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO | |
3089 | }; | |
3090 | static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { | |
3091 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE | |
3092 | }; | |
3093 | static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { | |
3094 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY | |
3095 | }; | |
1da177e4 LT |
3096 | |
3097 | static int __init parport_parse_param(const char *s, int *val, | |
3098 | int automatic, int none, int nofifo) | |
3099 | { | |
3100 | if (!s) | |
3101 | return 0; | |
3102 | if (!strncmp(s, "auto", 4)) | |
3103 | *val = automatic; | |
3104 | else if (!strncmp(s, "none", 4)) | |
3105 | *val = none; | |
1f2c19f8 | 3106 | else if (nofifo && !strncmp(s, "nofifo", 6)) |
1da177e4 LT |
3107 | *val = nofifo; |
3108 | else { | |
3109 | char *ep; | |
3110 | unsigned long r = simple_strtoul(s, &ep, 0); | |
3111 | if (ep != s) | |
3112 | *val = r; | |
3113 | else { | |
3114 | printk(KERN_ERR "parport: bad specifier `%s'\n", s); | |
3115 | return -1; | |
3116 | } | |
3117 | } | |
3118 | return 0; | |
3119 | } | |
3120 | ||
3121 | static int __init parport_parse_irq(const char *irqstr, int *val) | |
3122 | { | |
3123 | return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, | |
3124 | PARPORT_IRQ_NONE, 0); | |
3125 | } | |
3126 | ||
3127 | static int __init parport_parse_dma(const char *dmastr, int *val) | |
3128 | { | |
3129 | return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, | |
3130 | PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); | |
3131 | } | |
3132 | ||
3133 | #ifdef CONFIG_PCI | |
3134 | static int __init parport_init_mode_setup(char *str) | |
3135 | { | |
3aeda9bc AC |
3136 | printk(KERN_DEBUG |
3137 | "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); | |
3138 | ||
3139 | if (!strcmp(str, "spp")) | |
3140 | parport_init_mode = 1; | |
3141 | if (!strcmp(str, "ps2")) | |
3142 | parport_init_mode = 2; | |
3143 | if (!strcmp(str, "epp")) | |
3144 | parport_init_mode = 3; | |
3145 | if (!strcmp(str, "ecp")) | |
3146 | parport_init_mode = 4; | |
3147 | if (!strcmp(str, "ecpepp")) | |
3148 | parport_init_mode = 5; | |
1da177e4 LT |
3149 | return 1; |
3150 | } | |
3151 | #endif | |
3152 | ||
3153 | #ifdef MODULE | |
45dac90f AM |
3154 | static char *irq[PARPORT_PC_MAX_PORTS]; |
3155 | static char *dma[PARPORT_PC_MAX_PORTS]; | |
1da177e4 LT |
3156 | |
3157 | MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); | |
c8fc074d | 3158 | module_param_hw_array(io, int, ioport, NULL, 0); |
1da177e4 | 3159 | MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); |
c8fc074d | 3160 | module_param_hw_array(io_hi, int, ioport, NULL, 0); |
1da177e4 | 3161 | MODULE_PARM_DESC(irq, "IRQ line"); |
c8fc074d | 3162 | module_param_hw_array(irq, charp, irq, NULL, 0); |
1da177e4 | 3163 | MODULE_PARM_DESC(dma, "DMA channel"); |
c8fc074d | 3164 | module_param_hw_array(dma, charp, dma, NULL, 0); |
1da177e4 LT |
3165 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ |
3166 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
3167 | MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); | |
3168 | module_param(verbose_probing, int, 0644); | |
3169 | #endif | |
3170 | #ifdef CONFIG_PCI | |
3171 | static char *init_mode; | |
3aeda9bc AC |
3172 | MODULE_PARM_DESC(init_mode, |
3173 | "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); | |
1da177e4 LT |
3174 | module_param(init_mode, charp, 0); |
3175 | #endif | |
3176 | ||
3177 | static int __init parse_parport_params(void) | |
3178 | { | |
3179 | unsigned int i; | |
3180 | int val; | |
3181 | ||
3182 | #ifdef CONFIG_PCI | |
3183 | if (init_mode) | |
3184 | parport_init_mode_setup(init_mode); | |
3185 | #endif | |
3186 | ||
3187 | for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { | |
3188 | if (parport_parse_irq(irq[i], &val)) | |
3189 | return 1; | |
3190 | irqval[i] = val; | |
3191 | if (parport_parse_dma(dma[i], &val)) | |
3192 | return 1; | |
3193 | dmaval[i] = val; | |
3194 | } | |
3195 | if (!io[0]) { | |
3196 | /* The user can make us use any IRQs or DMAs we find. */ | |
3197 | if (irq[0] && !parport_parse_irq(irq[0], &val)) | |
3198 | switch (val) { | |
3199 | case PARPORT_IRQ_NONE: | |
3200 | case PARPORT_IRQ_AUTO: | |
3201 | irqval[0] = val; | |
3202 | break; | |
3203 | default: | |
3aeda9bc | 3204 | printk(KERN_WARNING |
1da177e4 LT |
3205 | "parport_pc: irq specified " |
3206 | "without base address. Use 'io=' " | |
3207 | "to specify one\n"); | |
3208 | } | |
3209 | ||
3210 | if (dma[0] && !parport_parse_dma(dma[0], &val)) | |
3211 | switch (val) { | |
3212 | case PARPORT_DMA_NONE: | |
3213 | case PARPORT_DMA_AUTO: | |
3214 | dmaval[0] = val; | |
3215 | break; | |
3216 | default: | |
3aeda9bc | 3217 | printk(KERN_WARNING |
1da177e4 LT |
3218 | "parport_pc: dma specified " |
3219 | "without base address. Use 'io=' " | |
3220 | "to specify one\n"); | |
3221 | } | |
3222 | } | |
3223 | return 0; | |
3224 | } | |
3225 | ||
3226 | #else | |
3227 | ||
3aeda9bc | 3228 | static int parport_setup_ptr __initdata; |
1da177e4 LT |
3229 | |
3230 | /* | |
3231 | * Acceptable parameters: | |
3232 | * | |
3233 | * parport=0 | |
3234 | * parport=auto | |
3235 | * parport=0xBASE[,IRQ[,DMA]] | |
3236 | * | |
3237 | * IRQ/DMA may be numeric or 'auto' or 'none' | |
3238 | */ | |
3aeda9bc | 3239 | static int __init parport_setup(char *str) |
1da177e4 LT |
3240 | { |
3241 | char *endptr; | |
3242 | char *sep; | |
3243 | int val; | |
3244 | ||
3245 | if (!str || !*str || (*str == '0' && !*(str+1))) { | |
3246 | /* Disable parport if "parport=0" in cmdline */ | |
3247 | io[0] = PARPORT_DISABLE; | |
3248 | return 1; | |
3249 | } | |
3250 | ||
3aeda9bc | 3251 | if (!strncmp(str, "auto", 4)) { |
1da177e4 LT |
3252 | irqval[0] = PARPORT_IRQ_AUTO; |
3253 | dmaval[0] = PARPORT_DMA_AUTO; | |
3254 | return 1; | |
3255 | } | |
3256 | ||
3aeda9bc | 3257 | val = simple_strtoul(str, &endptr, 0); |
1da177e4 | 3258 | if (endptr == str) { |
3aeda9bc | 3259 | printk(KERN_WARNING "parport=%s not understood\n", str); |
1da177e4 LT |
3260 | return 1; |
3261 | } | |
3262 | ||
3263 | if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { | |
3264 | printk(KERN_ERR "parport=%s ignored, too many ports\n", str); | |
3265 | return 1; | |
3266 | } | |
3267 | ||
3268 | io[parport_setup_ptr] = val; | |
3269 | irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; | |
3270 | dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; | |
3271 | ||
3272 | sep = strchr(str, ','); | |
3273 | if (sep++) { | |
3274 | if (parport_parse_irq(sep, &val)) | |
3275 | return 1; | |
3276 | irqval[parport_setup_ptr] = val; | |
3277 | sep = strchr(sep, ','); | |
3278 | if (sep++) { | |
3279 | if (parport_parse_dma(sep, &val)) | |
3280 | return 1; | |
3281 | dmaval[parport_setup_ptr] = val; | |
3282 | } | |
3283 | } | |
3284 | parport_setup_ptr++; | |
3285 | return 1; | |
3286 | } | |
3287 | ||
3288 | static int __init parse_parport_params(void) | |
3289 | { | |
3290 | return io[0] == PARPORT_DISABLE; | |
3291 | } | |
3292 | ||
3aeda9bc | 3293 | __setup("parport=", parport_setup); |
1da177e4 LT |
3294 | |
3295 | /* | |
3296 | * Acceptable parameters: | |
3297 | * | |
3298 | * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] | |
3299 | */ | |
3300 | #ifdef CONFIG_PCI | |
3aeda9bc | 3301 | __setup("parport_init_mode=", parport_init_mode_setup); |
1da177e4 LT |
3302 | #endif |
3303 | #endif | |
3304 | ||
3305 | /* "Parser" ends here */ | |
3306 | ||
3307 | static int __init parport_pc_init(void) | |
3308 | { | |
a7d801af JD |
3309 | int err; |
3310 | ||
1da177e4 LT |
3311 | if (parse_parport_params()) |
3312 | return -EINVAL; | |
3313 | ||
a7d801af JD |
3314 | err = platform_driver_register(&parport_pc_platform_driver); |
3315 | if (err) | |
3316 | return err; | |
3317 | ||
1da177e4 LT |
3318 | if (io[0]) { |
3319 | int i; | |
3320 | /* Only probe the ports we were given. */ | |
3321 | user_specified = 1; | |
3322 | for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { | |
3323 | if (!io[i]) | |
3324 | break; | |
3aeda9bc AC |
3325 | if (io_hi[i] == PARPORT_IOHI_AUTO) |
3326 | io_hi[i] = 0x400 + io[i]; | |
7597fee3 | 3327 | parport_pc_probe_port(io[i], io_hi[i], |
3aeda9bc | 3328 | irqval[i], dmaval[i], NULL, 0); |
1da177e4 LT |
3329 | } |
3330 | } else | |
3aeda9bc | 3331 | parport_pc_find_ports(irqval[0], dmaval[0]); |
1da177e4 LT |
3332 | |
3333 | return 0; | |
3334 | } | |
3335 | ||
3336 | static void __exit parport_pc_exit(void) | |
3337 | { | |
3338 | if (pci_registered_parport) | |
3aeda9bc | 3339 | pci_unregister_driver(&parport_pc_pci_driver); |
1da177e4 | 3340 | if (pnp_registered_parport) |
3aeda9bc | 3341 | pnp_unregister_driver(&parport_pc_pnp_driver); |
a7d801af | 3342 | platform_driver_unregister(&parport_pc_platform_driver); |
1da177e4 | 3343 | |
1da177e4 LT |
3344 | while (!list_empty(&ports_list)) { |
3345 | struct parport_pc_private *priv; | |
3346 | struct parport *port; | |
91905b6f | 3347 | struct device *dev; |
1da177e4 LT |
3348 | priv = list_entry(ports_list.next, |
3349 | struct parport_pc_private, list); | |
3350 | port = priv->port; | |
91905b6f | 3351 | dev = port->dev; |
1da177e4 | 3352 | parport_pc_unregister_port(port); |
91905b6f JS |
3353 | if (dev && dev->bus == &platform_bus_type) |
3354 | platform_device_unregister(to_platform_device(dev)); | |
1da177e4 | 3355 | } |
1da177e4 LT |
3356 | } |
3357 | ||
3358 | MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); | |
3359 | MODULE_DESCRIPTION("PC-style parallel port driver"); | |
3360 | MODULE_LICENSE("GPL"); | |
3361 | module_init(parport_pc_init) | |
3362 | module_exit(parport_pc_exit) |