Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Low-level parallel-support for PC-style hardware integrated in the | |
4 | * LASI-Controller (on GSC-Bus) for HP-PARISC Workstations | |
5 | * | |
1da177e4 | 6 | * (C) 1999-2001 by Helge Deller <deller@gmx.de> |
1da177e4 LT |
7 | * |
8 | * based on parport_pc.c by | |
9 | * Grant Guenther <grant@torque.net> | |
10 | * Phil Blundell <philb@gnu.org> | |
11 | * Tim Waugh <tim@cyberelk.demon.co.uk> | |
12 | * Jose Renau <renau@acm.org> | |
bdca3f20 | 13 | * David Campbell |
1da177e4 LT |
14 | * Andrea Arcangeli |
15 | */ | |
16 | ||
17 | #undef DEBUG /* undef for production */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/errno.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/sysctl.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/dma.h> | |
7c0f6ba6 | 32 | #include <linux/uaccess.h> |
1da177e4 LT |
33 | #include <asm/superio.h> |
34 | ||
35 | #include <linux/parport.h> | |
36 | #include <asm/pdc.h> | |
37 | #include <asm/parisc-device.h> | |
38 | #include <asm/hardware.h> | |
39 | #include "parport_gsc.h" | |
40 | ||
41 | ||
42 | MODULE_AUTHOR("Helge Deller <deller@gmx.de>"); | |
43 | MODULE_DESCRIPTION("HP-PARISC PC-style parallel port driver"); | |
1da177e4 LT |
44 | MODULE_LICENSE("GPL"); |
45 | ||
46 | ||
47 | /* | |
48 | * Clear TIMEOUT BIT in EPP MODE | |
49 | * | |
50 | * This is also used in SPP detection. | |
51 | */ | |
52 | static int clear_epp_timeout(struct parport *pb) | |
53 | { | |
54 | unsigned char r; | |
55 | ||
56 | if (!(parport_gsc_read_status(pb) & 0x01)) | |
57 | return 1; | |
58 | ||
59 | /* To clear timeout some chips require double read */ | |
60 | parport_gsc_read_status(pb); | |
61 | r = parport_gsc_read_status(pb); | |
62 | parport_writeb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ | |
63 | parport_writeb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ | |
64 | r = parport_gsc_read_status(pb); | |
65 | ||
66 | return !(r & 0x01); | |
67 | } | |
68 | ||
69 | /* | |
70 | * Access functions. | |
71 | * | |
72 | * Most of these aren't static because they may be used by the | |
73 | * parport_xxx_yyy macros. extern __inline__ versions of several | |
74 | * of these are in parport_gsc.h. | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | void parport_gsc_init_state(struct pardevice *dev, struct parport_state *s) |
78 | { | |
79 | s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0); | |
80 | } | |
81 | ||
82 | void parport_gsc_save_state(struct parport *p, struct parport_state *s) | |
83 | { | |
84 | s->u.pc.ctr = parport_readb (CONTROL (p)); | |
85 | } | |
86 | ||
87 | void parport_gsc_restore_state(struct parport *p, struct parport_state *s) | |
88 | { | |
89 | parport_writeb (s->u.pc.ctr, CONTROL (p)); | |
90 | } | |
91 | ||
92 | struct parport_operations parport_gsc_ops = | |
93 | { | |
94 | .write_data = parport_gsc_write_data, | |
95 | .read_data = parport_gsc_read_data, | |
96 | ||
97 | .write_control = parport_gsc_write_control, | |
98 | .read_control = parport_gsc_read_control, | |
99 | .frob_control = parport_gsc_frob_control, | |
100 | ||
101 | .read_status = parport_gsc_read_status, | |
102 | ||
103 | .enable_irq = parport_gsc_enable_irq, | |
104 | .disable_irq = parport_gsc_disable_irq, | |
105 | ||
106 | .data_forward = parport_gsc_data_forward, | |
107 | .data_reverse = parport_gsc_data_reverse, | |
108 | ||
109 | .init_state = parport_gsc_init_state, | |
110 | .save_state = parport_gsc_save_state, | |
111 | .restore_state = parport_gsc_restore_state, | |
112 | ||
113 | .epp_write_data = parport_ieee1284_epp_write_data, | |
114 | .epp_read_data = parport_ieee1284_epp_read_data, | |
115 | .epp_write_addr = parport_ieee1284_epp_write_addr, | |
116 | .epp_read_addr = parport_ieee1284_epp_read_addr, | |
117 | ||
118 | .ecp_write_data = parport_ieee1284_ecp_write_data, | |
119 | .ecp_read_data = parport_ieee1284_ecp_read_data, | |
120 | .ecp_write_addr = parport_ieee1284_ecp_write_addr, | |
121 | ||
122 | .compat_write_data = parport_ieee1284_write_compat, | |
123 | .nibble_read_data = parport_ieee1284_read_nibble, | |
124 | .byte_read_data = parport_ieee1284_read_byte, | |
125 | ||
126 | .owner = THIS_MODULE, | |
127 | }; | |
128 | ||
129 | /* --- Mode detection ------------------------------------- */ | |
130 | ||
131 | /* | |
132 | * Checks for port existence, all ports support SPP MODE | |
133 | */ | |
312facaf | 134 | static int parport_SPP_supported(struct parport *pb) |
1da177e4 LT |
135 | { |
136 | unsigned char r, w; | |
137 | ||
138 | /* | |
139 | * first clear an eventually pending EPP timeout | |
140 | * I (sailer@ife.ee.ethz.ch) have an SMSC chipset | |
141 | * that does not even respond to SPP cycles if an EPP | |
142 | * timeout is pending | |
143 | */ | |
144 | clear_epp_timeout(pb); | |
145 | ||
146 | /* Do a simple read-write test to make sure the port exists. */ | |
147 | w = 0xc; | |
148 | parport_writeb (w, CONTROL (pb)); | |
149 | ||
150 | /* Is there a control register that we can read from? Some | |
151 | * ports don't allow reads, so read_control just returns a | |
152 | * software copy. Some ports _do_ allow reads, so bypass the | |
153 | * software copy here. In addition, some bits aren't | |
154 | * writable. */ | |
155 | r = parport_readb (CONTROL (pb)); | |
156 | if ((r & 0xf) == w) { | |
157 | w = 0xe; | |
158 | parport_writeb (w, CONTROL (pb)); | |
159 | r = parport_readb (CONTROL (pb)); | |
160 | parport_writeb (0xc, CONTROL (pb)); | |
161 | if ((r & 0xf) == w) | |
162 | return PARPORT_MODE_PCSPP; | |
163 | } | |
164 | ||
165 | /* Try the data register. The data lines aren't tri-stated at | |
166 | * this stage, so we expect back what we wrote. */ | |
167 | w = 0xaa; | |
168 | parport_gsc_write_data (pb, w); | |
169 | r = parport_gsc_read_data (pb); | |
170 | if (r == w) { | |
171 | w = 0x55; | |
172 | parport_gsc_write_data (pb, w); | |
173 | r = parport_gsc_read_data (pb); | |
174 | if (r == w) | |
175 | return PARPORT_MODE_PCSPP; | |
176 | } | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | /* Detect PS/2 support. | |
182 | * | |
183 | * Bit 5 (0x20) sets the PS/2 data direction; setting this high | |
184 | * allows us to read data from the data lines. In theory we would get back | |
185 | * 0xff but any peripheral attached to the port may drag some or all of the | |
186 | * lines down to zero. So if we get back anything that isn't the contents | |
187 | * of the data register we deem PS/2 support to be present. | |
188 | * | |
189 | * Some SPP ports have "half PS/2" ability - you can't turn off the line | |
190 | * drivers, but an external peripheral with sufficiently beefy drivers of | |
191 | * its own can overpower them and assert its own levels onto the bus, from | |
192 | * where they can then be read back as normal. Ports with this property | |
193 | * and the right type of device attached are likely to fail the SPP test, | |
194 | * (as they will appear to have stuck bits) and so the fact that they might | |
195 | * be misdetected here is rather academic. | |
196 | */ | |
197 | ||
312facaf | 198 | static int parport_PS2_supported(struct parport *pb) |
1da177e4 LT |
199 | { |
200 | int ok = 0; | |
201 | ||
202 | clear_epp_timeout(pb); | |
203 | ||
204 | /* try to tri-state the buffer */ | |
205 | parport_gsc_data_reverse (pb); | |
206 | ||
207 | parport_gsc_write_data(pb, 0x55); | |
208 | if (parport_gsc_read_data(pb) != 0x55) ok++; | |
209 | ||
210 | parport_gsc_write_data(pb, 0xaa); | |
211 | if (parport_gsc_read_data(pb) != 0xaa) ok++; | |
212 | ||
213 | /* cancel input mode */ | |
214 | parport_gsc_data_forward (pb); | |
215 | ||
216 | if (ok) { | |
217 | pb->modes |= PARPORT_MODE_TRISTATE; | |
218 | } else { | |
219 | struct parport_gsc_private *priv = pb->private_data; | |
220 | priv->ctr_writable &= ~0x20; | |
221 | } | |
222 | ||
223 | return ok; | |
224 | } | |
225 | ||
226 | ||
227 | /* --- Initialisation code -------------------------------- */ | |
228 | ||
312facaf GKH |
229 | struct parport *parport_gsc_probe_port(unsigned long base, |
230 | unsigned long base_hi, int irq, | |
4edb3869 | 231 | int dma, struct parisc_device *padev) |
1da177e4 LT |
232 | { |
233 | struct parport_gsc_private *priv; | |
234 | struct parport_operations *ops; | |
235 | struct parport tmp; | |
236 | struct parport *p = &tmp; | |
237 | ||
cb6fc18e | 238 | priv = kzalloc (sizeof (struct parport_gsc_private), GFP_KERNEL); |
1da177e4 | 239 | if (!priv) { |
aa3d6e7c | 240 | printk(KERN_DEBUG "parport (0x%lx): no memory!\n", base); |
1da177e4 LT |
241 | return NULL; |
242 | } | |
2451a848 SMP |
243 | ops = kmemdup(&parport_gsc_ops, sizeof(struct parport_operations), |
244 | GFP_KERNEL); | |
1da177e4 | 245 | if (!ops) { |
aa3d6e7c JP |
246 | printk(KERN_DEBUG "parport (0x%lx): no memory for ops!\n", |
247 | base); | |
1da177e4 LT |
248 | kfree (priv); |
249 | return NULL; | |
250 | } | |
1da177e4 LT |
251 | priv->ctr = 0xc; |
252 | priv->ctr_writable = 0xff; | |
c92826ef | 253 | priv->dma_buf = NULL; |
1da177e4 | 254 | priv->dma_handle = 0; |
1da177e4 LT |
255 | p->base = base; |
256 | p->base_hi = base_hi; | |
257 | p->irq = irq; | |
258 | p->dma = dma; | |
259 | p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; | |
260 | p->ops = ops; | |
261 | p->private_data = priv; | |
262 | p->physport = p; | |
263 | if (!parport_SPP_supported (p)) { | |
264 | /* No port. */ | |
265 | kfree (priv); | |
9986ffd9 | 266 | kfree(ops); |
1da177e4 LT |
267 | return NULL; |
268 | } | |
269 | parport_PS2_supported (p); | |
270 | ||
271 | if (!(p = parport_register_port(base, PARPORT_IRQ_NONE, | |
272 | PARPORT_DMA_NONE, ops))) { | |
273 | kfree (priv); | |
274 | kfree (ops); | |
275 | return NULL; | |
276 | } | |
277 | ||
4edb3869 | 278 | p->dev = &padev->dev; |
1da177e4 LT |
279 | p->base_hi = base_hi; |
280 | p->modes = tmp.modes; | |
281 | p->size = (p->modes & PARPORT_MODE_EPP)?8:3; | |
282 | p->private_data = priv; | |
283 | ||
decf26f6 | 284 | pr_info("%s: PC-style at 0x%lx", p->name, p->base); |
1da177e4 LT |
285 | p->irq = irq; |
286 | if (p->irq == PARPORT_IRQ_AUTO) { | |
287 | p->irq = PARPORT_IRQ_NONE; | |
288 | } | |
289 | if (p->irq != PARPORT_IRQ_NONE) { | |
83b5d1e3 | 290 | pr_cont(", irq %d", p->irq); |
1da177e4 LT |
291 | |
292 | if (p->dma == PARPORT_DMA_AUTO) { | |
293 | p->dma = PARPORT_DMA_NONE; | |
294 | } | |
295 | } | |
296 | if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq | |
297 | is mandatory (see above) */ | |
298 | p->dma = PARPORT_DMA_NONE; | |
299 | ||
83b5d1e3 | 300 | pr_cont(" ["); |
a6abfdff JP |
301 | #define printmode(x) \ |
302 | do { \ | |
303 | if (p->modes & PARPORT_MODE_##x) \ | |
304 | pr_cont("%s%s", f++ ? "," : "", #x); \ | |
305 | } while (0) | |
1da177e4 LT |
306 | { |
307 | int f = 0; | |
308 | printmode(PCSPP); | |
309 | printmode(TRISTATE); | |
a6abfdff | 310 | printmode(COMPAT); |
1da177e4 LT |
311 | printmode(EPP); |
312 | // printmode(ECP); | |
313 | // printmode(DMA); | |
314 | } | |
315 | #undef printmode | |
83b5d1e3 | 316 | pr_cont("]\n"); |
1da177e4 LT |
317 | |
318 | if (p->irq != PARPORT_IRQ_NONE) { | |
3f2e40df | 319 | if (request_irq (p->irq, parport_irq_handler, |
1da177e4 | 320 | 0, p->name, p)) { |
decf26f6 | 321 | pr_warn("%s: irq %d in use, resorting to polled operation\n", |
1da177e4 LT |
322 | p->name, p->irq); |
323 | p->irq = PARPORT_IRQ_NONE; | |
324 | p->dma = PARPORT_DMA_NONE; | |
325 | } | |
326 | } | |
327 | ||
328 | /* Done probing. Now put the port into a sensible start-up state. */ | |
329 | ||
330 | parport_gsc_write_data(p, 0); | |
331 | parport_gsc_data_forward (p); | |
332 | ||
333 | /* Now that we've told the sharing engine about the port, and | |
334 | found out its characteristics, let the high-level drivers | |
335 | know about it. */ | |
336 | parport_announce_port (p); | |
337 | ||
338 | return p; | |
339 | } | |
340 | ||
341 | ||
342 | #define PARPORT_GSC_OFFSET 0x800 | |
343 | ||
312facaf | 344 | static int parport_count; |
1da177e4 | 345 | |
f0973443 | 346 | static int __init parport_init_chip(struct parisc_device *dev) |
1da177e4 LT |
347 | { |
348 | struct parport *p; | |
349 | unsigned long port; | |
350 | ||
351 | if (!dev->irq) { | |
decf26f6 | 352 | pr_warn("IRQ not found for parallel device at 0x%llx\n", |
b5d598b4 | 353 | (unsigned long long)dev->hpa.start); |
1da177e4 LT |
354 | return -ENODEV; |
355 | } | |
356 | ||
53f01bba | 357 | port = dev->hpa.start + PARPORT_GSC_OFFSET; |
1da177e4 LT |
358 | |
359 | /* some older machines with ASP-chip don't support | |
360 | * the enhanced parport modes. | |
361 | */ | |
362 | if (boot_cpu_data.cpu_type > pcxt && !pdc_add_valid(port+4)) { | |
363 | ||
364 | /* Initialize bidirectional-mode (0x10) & data-tranfer-mode #1 (0x20) */ | |
aa3d6e7c | 365 | pr_info("%s: initialize bidirectional-mode\n", __func__); |
1da177e4 LT |
366 | parport_writeb ( (0x10 + 0x20), port + 4); |
367 | ||
368 | } else { | |
aa3d6e7c | 369 | pr_info("%s: enhanced parport-modes not supported\n", __func__); |
1da177e4 LT |
370 | } |
371 | ||
372 | p = parport_gsc_probe_port(port, 0, dev->irq, | |
4edb3869 | 373 | /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, dev); |
1da177e4 LT |
374 | if (p) |
375 | parport_count++; | |
61616115 | 376 | dev_set_drvdata(&dev->dev, p); |
1da177e4 LT |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
87875c10 | 381 | static void __exit parport_remove_chip(struct parisc_device *dev) |
1da177e4 | 382 | { |
61616115 | 383 | struct parport *p = dev_get_drvdata(&dev->dev); |
1da177e4 LT |
384 | if (p) { |
385 | struct parport_gsc_private *priv = p->private_data; | |
386 | struct parport_operations *ops = p->ops; | |
387 | parport_remove_port(p); | |
388 | if (p->dma != PARPORT_DMA_NONE) | |
389 | free_dma(p->dma); | |
390 | if (p->irq != PARPORT_IRQ_NONE) | |
391 | free_irq(p->irq, p); | |
392 | if (priv->dma_buf) | |
ab9c13a4 CJ |
393 | dma_free_coherent(&priv->dev->dev, PAGE_SIZE, |
394 | priv->dma_buf, priv->dma_handle); | |
1da177e4 LT |
395 | kfree (p->private_data); |
396 | parport_put_port(p); | |
397 | kfree (ops); /* hope no-one cached it */ | |
398 | } | |
1da177e4 LT |
399 | } |
400 | ||
f0973443 | 401 | static const struct parisc_device_id parport_tbl[] __initconst = { |
1da177e4 LT |
402 | { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x74 }, |
403 | { 0, } | |
404 | }; | |
405 | ||
406 | MODULE_DEVICE_TABLE(parisc, parport_tbl); | |
407 | ||
f0973443 | 408 | static struct parisc_driver parport_driver __refdata = { |
1da177e4 LT |
409 | .name = "Parallel", |
410 | .id_table = parport_tbl, | |
411 | .probe = parport_init_chip, | |
f0973443 | 412 | .remove = __exit_p(parport_remove_chip), |
1da177e4 LT |
413 | }; |
414 | ||
312facaf | 415 | int parport_gsc_init(void) |
1da177e4 LT |
416 | { |
417 | return register_parisc_driver(&parport_driver); | |
418 | } | |
419 | ||
312facaf | 420 | static void parport_gsc_exit(void) |
1da177e4 LT |
421 | { |
422 | unregister_parisc_driver(&parport_driver); | |
423 | } | |
424 | ||
425 | module_init(parport_gsc_init); | |
426 | module_exit(parport_gsc_exit); |