Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | ** System Bus Adapter (SBA) I/O MMU manager | |
4 | ** | |
5 | ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> | |
6 | ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> | |
7 | ** (c) Copyright 2000-2004 Hewlett-Packard Company | |
8 | ** | |
9 | ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) | |
10 | ** | |
1da177e4 LT |
11 | ** |
12 | ** | |
13 | ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ | |
14 | ** J5000/J7000/N-class/L-class machines and their successors. | |
15 | ** | |
16 | ** FIXME: add DMA hint support programming in both sba and lba modules. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/init.h> | |
24 | ||
25 | #include <linux/mm.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/pci.h> | |
0a0f0d8b | 28 | #include <linux/dma-map-ops.h> |
b61e8f48 | 29 | #include <linux/scatterlist.h> |
46663448 | 30 | #include <linux/iommu-helper.h> |
77bfc8bd LW |
31 | /* |
32 | * The semantics of 64 register access on 32bit systems can't be guaranteed | |
33 | * by the C standard, we hope the _lo_hi() macros defining readq and writeq | |
34 | * here will behave as expected. | |
35 | */ | |
36 | #include <linux/io-64-nonatomic-lo-hi.h> | |
1da177e4 LT |
37 | |
38 | #include <asm/byteorder.h> | |
39 | #include <asm/io.h> | |
40 | #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ | |
41 | ||
42 | #include <asm/hardware.h> /* for register_parisc_driver() stuff */ | |
43 | ||
44 | #include <linux/proc_fs.h> | |
7ec14e49 | 45 | #include <linux/seq_file.h> |
6caddf0a | 46 | #include <linux/module.h> |
7ec14e49 | 47 | |
1790cf91 | 48 | #include <asm/ropes.h> |
6f03495d | 49 | #include <asm/mckinley.h> /* for proc_mckinley_root */ |
1da177e4 | 50 | #include <asm/runway.h> /* for proc_runway_root */ |
4a8a0788 | 51 | #include <asm/page.h> /* for PAGE0 */ |
1da177e4 LT |
52 | #include <asm/pdc.h> /* for PDC_MODEL_* */ |
53 | #include <asm/pdcpat.h> /* for is_pdc_pat() */ | |
54 | #include <asm/parisc-device.h> | |
55 | ||
9b8eeab0 CH |
56 | #include "iommu.h" |
57 | ||
1da177e4 LT |
58 | #define MODULE_NAME "SBA" |
59 | ||
1da177e4 LT |
60 | /* |
61 | ** The number of debug flags is a clue - this code is fragile. | |
62 | ** Don't even think about messing with it unless you have | |
63 | ** plenty of 710's to sacrifice to the computer gods. :^) | |
64 | */ | |
65 | #undef DEBUG_SBA_INIT | |
66 | #undef DEBUG_SBA_RUN | |
67 | #undef DEBUG_SBA_RUN_SG | |
68 | #undef DEBUG_SBA_RESOURCE | |
69 | #undef ASSERT_PDIR_SANITY | |
70 | #undef DEBUG_LARGE_SG_ENTRIES | |
71 | #undef DEBUG_DMB_TRAP | |
72 | ||
73 | #ifdef DEBUG_SBA_INIT | |
74 | #define DBG_INIT(x...) printk(x) | |
75 | #else | |
76 | #define DBG_INIT(x...) | |
77 | #endif | |
78 | ||
79 | #ifdef DEBUG_SBA_RUN | |
80 | #define DBG_RUN(x...) printk(x) | |
81 | #else | |
82 | #define DBG_RUN(x...) | |
83 | #endif | |
84 | ||
85 | #ifdef DEBUG_SBA_RUN_SG | |
86 | #define DBG_RUN_SG(x...) printk(x) | |
87 | #else | |
88 | #define DBG_RUN_SG(x...) | |
89 | #endif | |
90 | ||
91 | ||
92 | #ifdef DEBUG_SBA_RESOURCE | |
93 | #define DBG_RES(x...) printk(x) | |
94 | #else | |
95 | #define DBG_RES(x...) | |
96 | #endif | |
97 | ||
1da177e4 LT |
98 | #define DEFAULT_DMA_HINT_REG 0 |
99 | ||
08a64368 KM |
100 | struct sba_device *sba_list; |
101 | EXPORT_SYMBOL_GPL(sba_list); | |
1da177e4 LT |
102 | |
103 | static unsigned long ioc_needs_fdc = 0; | |
104 | ||
105 | /* global count of IOMMUs in the system */ | |
106 | static unsigned int global_ioc_cnt = 0; | |
107 | ||
108 | /* PA8700 (Piranha 2.2) bug workaround */ | |
109 | static unsigned long piranha_bad_128k = 0; | |
110 | ||
111 | /* Looks nice and keeps the compiler happy */ | |
112 | #define SBA_DEV(d) ((struct sba_device *) (d)) | |
113 | ||
08a64368 KM |
114 | #ifdef CONFIG_AGP_PARISC |
115 | #define SBA_AGP_SUPPORT | |
116 | #endif /*CONFIG_AGP_PARISC*/ | |
117 | ||
64908ad9 | 118 | #ifdef SBA_AGP_SUPPORT |
08a64368 | 119 | static int sba_reserve_agpgart = 1; |
29a1e1d2 | 120 | module_param(sba_reserve_agpgart, int, 0444); |
08a64368 | 121 | MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); |
1da177e4 LT |
122 | #endif |
123 | ||
77e0ddf0 | 124 | static struct proc_dir_entry *proc_runway_root __ro_after_init; |
54725958 | 125 | struct proc_dir_entry *proc_mckinley_root __ro_after_init; |
1da177e4 LT |
126 | |
127 | /************************************ | |
128 | ** SBA register read and write support | |
129 | ** | |
130 | ** BE WARNED: register writes are posted. | |
131 | ** (ie follow writes which must reach HW with a read) | |
132 | ** | |
133 | ** Superdome (in particular, REO) allows only 64-bit CSR accesses. | |
134 | */ | |
40d78de1 GG |
135 | #define READ_REG32(addr) readl(addr) |
136 | #define READ_REG64(addr) readq(addr) | |
137 | #define WRITE_REG32(val, addr) writel((val), (addr)) | |
138 | #define WRITE_REG64(val, addr) writeq((val), (addr)) | |
1da177e4 | 139 | |
64908ad9 | 140 | #ifdef CONFIG_64BIT |
1da177e4 LT |
141 | #define READ_REG(addr) READ_REG64(addr) |
142 | #define WRITE_REG(value, addr) WRITE_REG64(value, addr) | |
143 | #else | |
144 | #define READ_REG(addr) READ_REG32(addr) | |
145 | #define WRITE_REG(value, addr) WRITE_REG32(value, addr) | |
146 | #endif | |
147 | ||
148 | #ifdef DEBUG_SBA_INIT | |
149 | ||
64908ad9 | 150 | /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ |
1da177e4 LT |
151 | |
152 | /** | |
153 | * sba_dump_ranges - debugging only - print ranges assigned to this IOA | |
154 | * @hpa: base address of the sba | |
155 | * | |
156 | * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO | |
157 | * IO Adapter (aka Bus Converter). | |
158 | */ | |
159 | static void | |
160 | sba_dump_ranges(void __iomem *hpa) | |
161 | { | |
162 | DBG_INIT("SBA at 0x%p\n", hpa); | |
163 | DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); | |
164 | DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); | |
165 | DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); | |
166 | DBG_INIT("\n"); | |
167 | DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); | |
168 | DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); | |
169 | DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); | |
170 | } | |
171 | ||
172 | /** | |
173 | * sba_dump_tlb - debugging only - print IOMMU operating parameters | |
174 | * @hpa: base address of the IOMMU | |
175 | * | |
176 | * Print the size/location of the IO MMU PDIR. | |
177 | */ | |
178 | static void sba_dump_tlb(void __iomem *hpa) | |
179 | { | |
180 | DBG_INIT("IO TLB at 0x%p\n", hpa); | |
181 | DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); | |
182 | DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); | |
183 | DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); | |
184 | DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); | |
185 | DBG_INIT("\n"); | |
186 | } | |
187 | #else | |
188 | #define sba_dump_ranges(x) | |
189 | #define sba_dump_tlb(x) | |
64908ad9 | 190 | #endif /* DEBUG_SBA_INIT */ |
1da177e4 LT |
191 | |
192 | ||
193 | #ifdef ASSERT_PDIR_SANITY | |
194 | ||
195 | /** | |
196 | * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry | |
197 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
198 | * @msg: text to print ont the output line. | |
199 | * @pide: pdir index. | |
200 | * | |
201 | * Print one entry of the IO MMU PDIR in human readable form. | |
202 | */ | |
203 | static void | |
204 | sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) | |
205 | { | |
206 | /* start printing from lowest pde in rval */ | |
207 | u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); | |
208 | unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); | |
209 | uint rcnt; | |
210 | ||
211 | printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", | |
212 | msg, | |
213 | rptr, pide & (BITS_PER_LONG - 1), *rptr); | |
214 | ||
215 | rcnt = 0; | |
216 | while (rcnt < BITS_PER_LONG) { | |
217 | printk(KERN_DEBUG "%s %2d %p %016Lx\n", | |
218 | (rcnt == (pide & (BITS_PER_LONG - 1))) | |
219 | ? " -->" : " ", | |
220 | rcnt, ptr, *ptr ); | |
221 | rcnt++; | |
222 | ptr++; | |
223 | } | |
224 | printk(KERN_DEBUG "%s", msg); | |
225 | } | |
226 | ||
227 | ||
228 | /** | |
229 | * sba_check_pdir - debugging only - consistency checker | |
230 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
231 | * @msg: text to print ont the output line. | |
232 | * | |
233 | * Verify the resource map and pdir state is consistent | |
234 | */ | |
235 | static int | |
236 | sba_check_pdir(struct ioc *ioc, char *msg) | |
237 | { | |
238 | u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); | |
239 | u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ | |
240 | u64 *pptr = ioc->pdir_base; /* pdir ptr */ | |
241 | uint pide = 0; | |
242 | ||
243 | while (rptr < rptr_end) { | |
244 | u32 rval = *rptr; | |
245 | int rcnt = 32; /* number of bits we might check */ | |
246 | ||
247 | while (rcnt) { | |
248 | /* Get last byte and highest bit from that */ | |
249 | u32 pde = ((u32) (((char *)pptr)[7])) << 24; | |
250 | if ((rval ^ pde) & 0x80000000) | |
251 | { | |
252 | /* | |
253 | ** BUMMER! -- res_map != pdir -- | |
254 | ** Dump rval and matching pdir entries | |
255 | */ | |
256 | sba_dump_pdir_entry(ioc, msg, pide); | |
257 | return(1); | |
258 | } | |
259 | rcnt--; | |
260 | rval <<= 1; /* try the next bit */ | |
261 | pptr++; | |
262 | pide++; | |
263 | } | |
264 | rptr++; /* look at next word of res_map */ | |
265 | } | |
266 | /* It'd be nice if we always got here :^) */ | |
267 | return 0; | |
268 | } | |
269 | ||
270 | ||
271 | /** | |
272 | * sba_dump_sg - debugging only - print Scatter-Gather list | |
273 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
274 | * @startsg: head of the SG list | |
275 | * @nents: number of entries in SG list | |
276 | * | |
277 | * print the SG list so we can verify it's correct by hand. | |
278 | */ | |
279 | static void | |
280 | sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) | |
281 | { | |
282 | while (nents-- > 0) { | |
283 | printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", | |
284 | nents, | |
285 | (unsigned long) sg_dma_address(startsg), | |
286 | sg_dma_len(startsg), | |
8bf8a1d1 | 287 | sg_virt(startsg), startsg->length); |
1da177e4 LT |
288 | startsg++; |
289 | } | |
290 | } | |
291 | ||
292 | #endif /* ASSERT_PDIR_SANITY */ | |
293 | ||
294 | ||
295 | ||
296 | ||
297 | /************************************************************** | |
298 | * | |
299 | * I/O Pdir Resource Management | |
300 | * | |
301 | * Bits set in the resource map are in use. | |
302 | * Each bit can represent a number of pages. | |
303 | * LSbs represent lower addresses (IOVA's). | |
304 | * | |
305 | ***************************************************************/ | |
306 | #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ | |
307 | ||
308 | /* Convert from IOVP to IOVA and vice versa. */ | |
309 | ||
310 | #ifdef ZX1_SUPPORT | |
311 | /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ | |
312 | #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) | |
313 | #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) | |
314 | #else | |
315 | /* only support Astro and ancestors. Saves a few cycles in key places */ | |
316 | #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) | |
317 | #define SBA_IOVP(ioc,iova) (iova) | |
318 | #endif | |
319 | ||
320 | #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) | |
321 | ||
322 | #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) | |
323 | #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) | |
324 | ||
56ee0cfd FT |
325 | static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, |
326 | unsigned int bitshiftcnt) | |
46663448 FT |
327 | { |
328 | return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) | |
329 | + bitshiftcnt; | |
330 | } | |
1da177e4 LT |
331 | |
332 | /** | |
333 | * sba_search_bitmap - find free space in IO PDIR resource bitmap | |
334 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
226b8ab8 | 335 | * @dev: device to query the bitmap for |
1da177e4 LT |
336 | * @bits_wanted: number of entries we need. |
337 | * | |
338 | * Find consecutive free bits in resource bitmap. | |
339 | * Each bit represents one entry in the IO Pdir. | |
340 | * Cool perf optimization: search for log2(size) bits at a time. | |
341 | */ | |
226b8ab8 | 342 | static unsigned long |
46663448 FT |
343 | sba_search_bitmap(struct ioc *ioc, struct device *dev, |
344 | unsigned long bits_wanted) | |
1da177e4 LT |
345 | { |
346 | unsigned long *res_ptr = ioc->res_hint; | |
347 | unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); | |
46663448 FT |
348 | unsigned long pide = ~0UL, tpide; |
349 | unsigned long boundary_size; | |
350 | unsigned long shift; | |
351 | int ret; | |
352 | ||
1e9d90db | 353 | boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT); |
46663448 FT |
354 | |
355 | #if defined(ZX1_SUPPORT) | |
356 | BUG_ON(ioc->ibase & ~IOVP_MASK); | |
357 | shift = ioc->ibase >> IOVP_SHIFT; | |
358 | #else | |
359 | shift = 0; | |
360 | #endif | |
1da177e4 LT |
361 | |
362 | if (bits_wanted > (BITS_PER_LONG/2)) { | |
363 | /* Search word at a time - no mask needed */ | |
364 | for(; res_ptr < res_end; ++res_ptr) { | |
46663448 FT |
365 | tpide = ptr_to_pide(ioc, res_ptr, 0); |
366 | ret = iommu_is_span_boundary(tpide, bits_wanted, | |
367 | shift, | |
368 | boundary_size); | |
369 | if ((*res_ptr == 0) && !ret) { | |
1da177e4 | 370 | *res_ptr = RESMAP_MASK(bits_wanted); |
46663448 | 371 | pide = tpide; |
1da177e4 LT |
372 | break; |
373 | } | |
374 | } | |
375 | /* point to the next word on next pass */ | |
376 | res_ptr++; | |
377 | ioc->res_bitshift = 0; | |
378 | } else { | |
379 | /* | |
380 | ** Search the resource bit map on well-aligned values. | |
381 | ** "o" is the alignment. | |
382 | ** We need the alignment to invalidate I/O TLB using | |
383 | ** SBA HW features in the unmap path. | |
384 | */ | |
385 | unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); | |
3cb1d958 | 386 | uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); |
1da177e4 LT |
387 | unsigned long mask; |
388 | ||
389 | if (bitshiftcnt >= BITS_PER_LONG) { | |
390 | bitshiftcnt = 0; | |
391 | res_ptr++; | |
392 | } | |
393 | mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; | |
394 | ||
a8043ecb | 395 | DBG_RES("%s() o %ld %p", __func__, o, res_ptr); |
1da177e4 LT |
396 | while(res_ptr < res_end) |
397 | { | |
398 | DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); | |
399 | WARN_ON(mask == 0); | |
46663448 FT |
400 | tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); |
401 | ret = iommu_is_span_boundary(tpide, bits_wanted, | |
402 | shift, | |
403 | boundary_size); | |
404 | if ((((*res_ptr) & mask) == 0) && !ret) { | |
1da177e4 | 405 | *res_ptr |= mask; /* mark resources busy! */ |
46663448 | 406 | pide = tpide; |
1da177e4 LT |
407 | break; |
408 | } | |
409 | mask >>= o; | |
410 | bitshiftcnt += o; | |
411 | if (mask == 0) { | |
412 | mask = RESMAP_MASK(bits_wanted); | |
413 | bitshiftcnt=0; | |
414 | res_ptr++; | |
415 | } | |
416 | } | |
417 | /* look in the same word on the next pass */ | |
418 | ioc->res_bitshift = bitshiftcnt + bits_wanted; | |
419 | } | |
420 | ||
421 | /* wrapped ? */ | |
422 | if (res_end <= res_ptr) { | |
423 | ioc->res_hint = (unsigned long *) ioc->res_map; | |
424 | ioc->res_bitshift = 0; | |
425 | } else { | |
426 | ioc->res_hint = res_ptr; | |
427 | } | |
428 | return (pide); | |
429 | } | |
430 | ||
431 | ||
432 | /** | |
433 | * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap | |
434 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
226b8ab8 | 435 | * @dev: device for which pages should be alloced |
1da177e4 LT |
436 | * @size: number of bytes to create a mapping for |
437 | * | |
438 | * Given a size, find consecutive unmarked and then mark those bits in the | |
439 | * resource bit map. | |
440 | */ | |
441 | static int | |
7c8cda62 | 442 | sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) |
1da177e4 LT |
443 | { |
444 | unsigned int pages_needed = size >> IOVP_SHIFT; | |
445 | #ifdef SBA_COLLECT_STATS | |
446 | unsigned long cr_start = mfctl(16); | |
447 | #endif | |
448 | unsigned long pide; | |
449 | ||
46663448 | 450 | pide = sba_search_bitmap(ioc, dev, pages_needed); |
1da177e4 | 451 | if (pide >= (ioc->res_size << 3)) { |
46663448 | 452 | pide = sba_search_bitmap(ioc, dev, pages_needed); |
1da177e4 LT |
453 | if (pide >= (ioc->res_size << 3)) |
454 | panic("%s: I/O MMU @ %p is out of mapping resources\n", | |
455 | __FILE__, ioc->ioc_hpa); | |
456 | } | |
457 | ||
458 | #ifdef ASSERT_PDIR_SANITY | |
459 | /* verify the first enable bit is clear */ | |
460 | if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { | |
461 | sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); | |
462 | } | |
463 | #endif | |
464 | ||
465 | DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", | |
a8043ecb | 466 | __func__, size, pages_needed, pide, |
1da177e4 LT |
467 | (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), |
468 | ioc->res_bitshift ); | |
469 | ||
470 | #ifdef SBA_COLLECT_STATS | |
471 | { | |
472 | unsigned long cr_end = mfctl(16); | |
473 | unsigned long tmp = cr_end - cr_start; | |
474 | /* check for roll over */ | |
475 | cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); | |
476 | } | |
477 | ioc->avg_search[ioc->avg_idx++] = cr_start; | |
478 | ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; | |
479 | ||
480 | ioc->used_pages += pages_needed; | |
481 | #endif | |
482 | ||
483 | return (pide); | |
484 | } | |
485 | ||
486 | ||
487 | /** | |
488 | * sba_free_range - unmark bits in IO PDIR resource bitmap | |
489 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
490 | * @iova: IO virtual address which was previously allocated. | |
491 | * @size: number of bytes to create a mapping for | |
492 | * | |
493 | * clear bits in the ioc's resource map | |
494 | */ | |
226b8ab8 | 495 | static void |
1da177e4 LT |
496 | sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) |
497 | { | |
498 | unsigned long iovp = SBA_IOVP(ioc, iova); | |
499 | unsigned int pide = PDIR_INDEX(iovp); | |
500 | unsigned int ridx = pide >> 3; /* convert bit to byte address */ | |
501 | unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); | |
502 | ||
503 | int bits_not_wanted = size >> IOVP_SHIFT; | |
504 | ||
505 | /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ | |
506 | unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); | |
507 | ||
508 | DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", | |
a8043ecb | 509 | __func__, (uint) iova, size, |
1da177e4 LT |
510 | bits_not_wanted, m, pide, res_ptr, *res_ptr); |
511 | ||
512 | #ifdef SBA_COLLECT_STATS | |
513 | ioc->used_pages -= bits_not_wanted; | |
514 | #endif | |
515 | ||
516 | *res_ptr &= ~m; | |
517 | } | |
518 | ||
519 | ||
520 | /************************************************************** | |
521 | * | |
522 | * "Dynamic DMA Mapping" support (aka "Coherent I/O") | |
523 | * | |
524 | ***************************************************************/ | |
525 | ||
64908ad9 | 526 | #ifdef SBA_HINT_SUPPORT |
1da177e4 LT |
527 | #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) |
528 | #endif | |
529 | ||
530 | typedef unsigned long space_t; | |
531 | #define KERNEL_SPACE 0 | |
532 | ||
533 | /** | |
534 | * sba_io_pdir_entry - fill in one IO PDIR entry | |
535 | * @pdir_ptr: pointer to IO PDIR entry | |
536 | * @sid: process Space ID - currently only support KERNEL_SPACE | |
537 | * @vba: Virtual CPU address of buffer to map | |
538 | * @hint: DMA hint set to use for this mapping | |
539 | * | |
540 | * SBA Mapping Routine | |
541 | * | |
542 | * Given a virtual address (vba, arg2) and space id, (sid, arg1) | |
543 | * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by | |
544 | * pdir_ptr (arg0). | |
545 | * Using the bass-ackwards HP bit numbering, Each IO Pdir entry | |
546 | * for Astro/Ike looks like: | |
547 | * | |
548 | * | |
549 | * 0 19 51 55 63 | |
550 | * +-+---------------------+----------------------------------+----+--------+ | |
551 | * |V| U | PPN[43:12] | U | VI | | |
552 | * +-+---------------------+----------------------------------+----+--------+ | |
553 | * | |
554 | * Pluto is basically identical, supports fewer physical address bits: | |
555 | * | |
556 | * 0 23 51 55 63 | |
557 | * +-+------------------------+-------------------------------+----+--------+ | |
558 | * |V| U | PPN[39:12] | U | VI | | |
559 | * +-+------------------------+-------------------------------+----+--------+ | |
560 | * | |
561 | * V == Valid Bit (Most Significant Bit is bit 0) | |
562 | * U == Unused | |
563 | * PPN == Physical Page Number | |
564 | * VI == Virtual Index (aka Coherent Index) | |
565 | * | |
566 | * LPA instruction output is put into PPN field. | |
567 | * LCI (Load Coherence Index) instruction provides the "VI" bits. | |
568 | * | |
569 | * We pre-swap the bytes since PCX-W is Big Endian and the | |
570 | * IOMMU uses little endian for the pdir. | |
571 | */ | |
572 | ||
226b8ab8 | 573 | static void |
1da177e4 LT |
574 | sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, |
575 | unsigned long hint) | |
576 | { | |
577 | u64 pa; /* physical address */ | |
578 | register unsigned ci; /* coherent index */ | |
579 | ||
116d7533 | 580 | pa = lpa(vba); |
1da177e4 LT |
581 | pa &= IOVP_MASK; |
582 | ||
63923d2c | 583 | asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba)); |
6a45716a | 584 | pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */ |
1da177e4 | 585 | |
983daeec | 586 | pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ |
1da177e4 LT |
587 | *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ |
588 | ||
589 | /* | |
590 | * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set | |
591 | * (bit #61, big endian), we have to flush and sync every time | |
592 | * IO-PDIR is changed in Ike/Astro. | |
593 | */ | |
3847dab7 | 594 | asm_io_fdc(pdir_ptr); |
1da177e4 LT |
595 | } |
596 | ||
597 | ||
598 | /** | |
599 | * sba_mark_invalid - invalidate one or more IO PDIR entries | |
600 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
601 | * @iova: IO Virtual Address mapped earlier | |
602 | * @byte_cnt: number of bytes this mapping covers. | |
603 | * | |
604 | * Marking the IO PDIR entry(ies) as Invalid and invalidate | |
605 | * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) | |
606 | * is to purge stale entries in the IO TLB when unmapping entries. | |
607 | * | |
608 | * The PCOM register supports purging of multiple pages, with a minium | |
609 | * of 1 page and a maximum of 2GB. Hardware requires the address be | |
610 | * aligned to the size of the range being purged. The size of the range | |
611 | * must be a power of 2. The "Cool perf optimization" in the | |
612 | * allocation routine helps keep that true. | |
613 | */ | |
226b8ab8 | 614 | static void |
1da177e4 LT |
615 | sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) |
616 | { | |
617 | u32 iovp = (u32) SBA_IOVP(ioc,iova); | |
64908ad9 | 618 | u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; |
1da177e4 LT |
619 | |
620 | #ifdef ASSERT_PDIR_SANITY | |
64908ad9 GG |
621 | /* Assert first pdir entry is set. |
622 | ** | |
623 | ** Even though this is a big-endian machine, the entries | |
624 | ** in the iopdir are little endian. That's why we look at | |
625 | ** the byte at +7 instead of at +0. | |
626 | */ | |
627 | if (0x80 != (((u8 *) pdir_ptr)[7])) { | |
1da177e4 LT |
628 | sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); |
629 | } | |
630 | #endif | |
631 | ||
64908ad9 | 632 | if (byte_cnt > IOVP_SIZE) |
1da177e4 | 633 | { |
64908ad9 GG |
634 | #if 0 |
635 | unsigned long entries_per_cacheline = ioc_needs_fdc ? | |
636 | L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) | |
637 | - (unsigned long) pdir_ptr; | |
638 | : 262144; | |
639 | #endif | |
1da177e4 | 640 | |
64908ad9 GG |
641 | /* set "size" field for PCOM */ |
642 | iovp |= get_order(byte_cnt) + PAGE_SHIFT; | |
1da177e4 | 643 | |
1da177e4 LT |
644 | do { |
645 | /* clear I/O Pdir entry "valid" bit first */ | |
64908ad9 | 646 | ((u8 *) pdir_ptr)[7] = 0; |
3847dab7 | 647 | asm_io_fdc(pdir_ptr); |
64908ad9 | 648 | if (ioc_needs_fdc) { |
64908ad9 GG |
649 | #if 0 |
650 | entries_per_cacheline = L1_CACHE_SHIFT - 3; | |
651 | #endif | |
652 | } | |
653 | pdir_ptr++; | |
1da177e4 | 654 | byte_cnt -= IOVP_SIZE; |
64908ad9 GG |
655 | } while (byte_cnt > IOVP_SIZE); |
656 | } else | |
657 | iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ | |
658 | ||
659 | /* | |
660 | ** clear I/O PDIR entry "valid" bit. | |
661 | ** We have to R/M/W the cacheline regardless how much of the | |
662 | ** pdir entry that we clobber. | |
663 | ** The rest of the entry would be useful for debugging if we | |
664 | ** could dump core on HPMC. | |
665 | */ | |
666 | ((u8 *) pdir_ptr)[7] = 0; | |
3847dab7 | 667 | asm_io_fdc(pdir_ptr); |
1da177e4 LT |
668 | |
669 | WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); | |
670 | } | |
671 | ||
672 | /** | |
673 | * sba_dma_supported - PCI driver can query DMA support | |
674 | * @dev: instance of PCI owned by the driver that's asking | |
675 | * @mask: number of address bits this PCI device can handle | |
676 | * | |
985098a0 | 677 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
678 | */ |
679 | static int sba_dma_supported( struct device *dev, u64 mask) | |
680 | { | |
681 | struct ioc *ioc; | |
64908ad9 | 682 | |
1da177e4 LT |
683 | if (dev == NULL) { |
684 | printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); | |
685 | BUG(); | |
686 | return(0); | |
687 | } | |
688 | ||
64908ad9 | 689 | ioc = GET_IOC(dev); |
33f9e024 TB |
690 | if (!ioc) |
691 | return 0; | |
1da177e4 | 692 | |
64908ad9 GG |
693 | /* |
694 | * check if mask is >= than the current max IO Virt Address | |
695 | * The max IO Virt address will *always* < 30 bits. | |
696 | */ | |
697 | return((int)(mask >= (ioc->ibase - 1 + | |
698 | (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); | |
1da177e4 LT |
699 | } |
700 | ||
701 | ||
702 | /** | |
703 | * sba_map_single - map one buffer and return IOVA for DMA | |
704 | * @dev: instance of PCI owned by the driver that's asking. | |
705 | * @addr: driver buffer to map. | |
706 | * @size: number of bytes to map in driver buffer. | |
707 | * @direction: R/W or both. | |
708 | * | |
985098a0 | 709 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
710 | */ |
711 | static dma_addr_t | |
712 | sba_map_single(struct device *dev, void *addr, size_t size, | |
713 | enum dma_data_direction direction) | |
714 | { | |
715 | struct ioc *ioc; | |
716 | unsigned long flags; | |
717 | dma_addr_t iovp; | |
718 | dma_addr_t offset; | |
719 | u64 *pdir_start; | |
720 | int pide; | |
721 | ||
722 | ioc = GET_IOC(dev); | |
33f9e024 | 723 | if (!ioc) |
fb1b53f1 | 724 | return DMA_MAPPING_ERROR; |
1da177e4 LT |
725 | |
726 | /* save offset bits */ | |
727 | offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; | |
728 | ||
729 | /* round up to nearest IOVP_SIZE */ | |
730 | size = (size + offset + ~IOVP_MASK) & IOVP_MASK; | |
731 | ||
732 | spin_lock_irqsave(&ioc->res_lock, flags); | |
733 | #ifdef ASSERT_PDIR_SANITY | |
734 | sba_check_pdir(ioc,"Check before sba_map_single()"); | |
735 | #endif | |
736 | ||
737 | #ifdef SBA_COLLECT_STATS | |
738 | ioc->msingle_calls++; | |
739 | ioc->msingle_pages += size >> IOVP_SHIFT; | |
740 | #endif | |
7c8cda62 | 741 | pide = sba_alloc_range(ioc, dev, size); |
1da177e4 LT |
742 | iovp = (dma_addr_t) pide << IOVP_SHIFT; |
743 | ||
744 | DBG_RUN("%s() 0x%p -> 0x%lx\n", | |
a8043ecb | 745 | __func__, addr, (long) iovp | offset); |
1da177e4 LT |
746 | |
747 | pdir_start = &(ioc->pdir_base[pide]); | |
748 | ||
749 | while (size > 0) { | |
750 | sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); | |
751 | ||
752 | DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", | |
753 | pdir_start, | |
754 | (u8) (((u8 *) pdir_start)[7]), | |
755 | (u8) (((u8 *) pdir_start)[6]), | |
756 | (u8) (((u8 *) pdir_start)[5]), | |
757 | (u8) (((u8 *) pdir_start)[4]), | |
758 | (u8) (((u8 *) pdir_start)[3]), | |
759 | (u8) (((u8 *) pdir_start)[2]), | |
760 | (u8) (((u8 *) pdir_start)[1]), | |
761 | (u8) (((u8 *) pdir_start)[0]) | |
762 | ); | |
763 | ||
764 | addr += IOVP_SIZE; | |
765 | size -= IOVP_SIZE; | |
766 | pdir_start++; | |
767 | } | |
64908ad9 GG |
768 | |
769 | /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ | |
3847dab7 | 770 | asm_io_sync(); |
64908ad9 | 771 | |
1da177e4 LT |
772 | #ifdef ASSERT_PDIR_SANITY |
773 | sba_check_pdir(ioc,"Check after sba_map_single()"); | |
774 | #endif | |
775 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
64908ad9 GG |
776 | |
777 | /* form complete address */ | |
1da177e4 LT |
778 | return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); |
779 | } | |
780 | ||
781 | ||
79387179 CH |
782 | static dma_addr_t |
783 | sba_map_page(struct device *dev, struct page *page, unsigned long offset, | |
784 | size_t size, enum dma_data_direction direction, | |
00085f1e | 785 | unsigned long attrs) |
79387179 CH |
786 | { |
787 | return sba_map_single(dev, page_address(page) + offset, size, | |
788 | direction); | |
789 | } | |
790 | ||
791 | ||
1da177e4 | 792 | /** |
79387179 | 793 | * sba_unmap_page - unmap one IOVA and free resources |
1da177e4 LT |
794 | * @dev: instance of PCI owned by the driver that's asking. |
795 | * @iova: IOVA of driver buffer previously mapped. | |
796 | * @size: number of bytes mapped in driver buffer. | |
797 | * @direction: R/W or both. | |
226b8ab8 | 798 | * @attrs: attributes |
1da177e4 | 799 | * |
985098a0 | 800 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
801 | */ |
802 | static void | |
79387179 | 803 | sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size, |
00085f1e | 804 | enum dma_data_direction direction, unsigned long attrs) |
1da177e4 LT |
805 | { |
806 | struct ioc *ioc; | |
807 | #if DELAYED_RESOURCE_CNT > 0 | |
808 | struct sba_dma_pair *d; | |
809 | #endif | |
810 | unsigned long flags; | |
811 | dma_addr_t offset; | |
812 | ||
a8043ecb | 813 | DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); |
1da177e4 LT |
814 | |
815 | ioc = GET_IOC(dev); | |
33f9e024 TB |
816 | if (!ioc) { |
817 | WARN_ON(!ioc); | |
818 | return; | |
819 | } | |
1da177e4 LT |
820 | offset = iova & ~IOVP_MASK; |
821 | iova ^= offset; /* clear offset bits */ | |
822 | size += offset; | |
3cb1d958 | 823 | size = ALIGN(size, IOVP_SIZE); |
1da177e4 LT |
824 | |
825 | spin_lock_irqsave(&ioc->res_lock, flags); | |
826 | ||
827 | #ifdef SBA_COLLECT_STATS | |
828 | ioc->usingle_calls++; | |
829 | ioc->usingle_pages += size >> IOVP_SHIFT; | |
830 | #endif | |
831 | ||
832 | sba_mark_invalid(ioc, iova, size); | |
833 | ||
834 | #if DELAYED_RESOURCE_CNT > 0 | |
835 | /* Delaying when we re-use a IO Pdir entry reduces the number | |
836 | * of MMIO reads needed to flush writes to the PCOM register. | |
837 | */ | |
838 | d = &(ioc->saved[ioc->saved_cnt]); | |
839 | d->iova = iova; | |
840 | d->size = size; | |
841 | if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { | |
842 | int cnt = ioc->saved_cnt; | |
843 | while (cnt--) { | |
844 | sba_free_range(ioc, d->iova, d->size); | |
845 | d--; | |
846 | } | |
847 | ioc->saved_cnt = 0; | |
64908ad9 | 848 | |
1da177e4 LT |
849 | READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ |
850 | } | |
851 | #else /* DELAYED_RESOURCE_CNT == 0 */ | |
852 | sba_free_range(ioc, iova, size); | |
64908ad9 GG |
853 | |
854 | /* If fdc's were issued, force fdc's to be visible now */ | |
3847dab7 | 855 | asm_io_sync(); |
64908ad9 | 856 | |
1da177e4 LT |
857 | READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ |
858 | #endif /* DELAYED_RESOURCE_CNT == 0 */ | |
64908ad9 | 859 | |
1da177e4 LT |
860 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
861 | ||
862 | /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. | |
863 | ** For Astro based systems this isn't a big deal WRT performance. | |
864 | ** As long as 2.4 kernels copyin/copyout data from/to userspace, | |
865 | ** we don't need the syncdma. The issue here is I/O MMU cachelines | |
866 | ** are *not* coherent in all cases. May be hwrev dependent. | |
867 | ** Need to investigate more. | |
868 | asm volatile("syncdma"); | |
869 | */ | |
870 | } | |
871 | ||
872 | ||
873 | /** | |
79387179 | 874 | * sba_alloc - allocate/map shared mem for DMA |
1da177e4 LT |
875 | * @hwdev: instance of PCI owned by the driver that's asking. |
876 | * @size: number of bytes mapped in driver buffer. | |
877 | * @dma_handle: IOVA of new buffer. | |
226b8ab8 HD |
878 | * @gfp: allocation flags |
879 | * @attrs: attributes | |
1da177e4 | 880 | * |
985098a0 | 881 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 | 882 | */ |
79387179 | 883 | static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, |
00085f1e | 884 | gfp_t gfp, unsigned long attrs) |
1da177e4 LT |
885 | { |
886 | void *ret; | |
887 | ||
888 | if (!hwdev) { | |
889 | /* only support PCI */ | |
890 | *dma_handle = 0; | |
c2c4798e | 891 | return NULL; |
1da177e4 LT |
892 | } |
893 | ||
894 | ret = (void *) __get_free_pages(gfp, get_order(size)); | |
895 | ||
896 | if (ret) { | |
897 | memset(ret, 0, size); | |
898 | *dma_handle = sba_map_single(hwdev, ret, size, 0); | |
899 | } | |
900 | ||
901 | return ret; | |
902 | } | |
903 | ||
904 | ||
905 | /** | |
79387179 | 906 | * sba_free - free/unmap shared mem for DMA |
1da177e4 LT |
907 | * @hwdev: instance of PCI owned by the driver that's asking. |
908 | * @size: number of bytes mapped in driver buffer. | |
909 | * @vaddr: virtual address IOVA of "consistent" buffer. | |
226b8ab8 HD |
910 | * @dma_handle: IO virtual address of "consistent" buffer. |
911 | * @attrs: attributes | |
1da177e4 | 912 | * |
985098a0 | 913 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
914 | */ |
915 | static void | |
79387179 | 916 | sba_free(struct device *hwdev, size_t size, void *vaddr, |
00085f1e | 917 | dma_addr_t dma_handle, unsigned long attrs) |
1da177e4 | 918 | { |
00085f1e | 919 | sba_unmap_page(hwdev, dma_handle, size, 0, 0); |
1da177e4 LT |
920 | free_pages((unsigned long) vaddr, get_order(size)); |
921 | } | |
922 | ||
923 | ||
924 | /* | |
925 | ** Since 0 is a valid pdir_base index value, can't use that | |
926 | ** to determine if a value is valid or not. Use a flag to indicate | |
927 | ** the SG list entry contains a valid pdir index. | |
928 | */ | |
929 | #define PIDE_FLAG 0x80000000UL | |
930 | ||
931 | #ifdef SBA_COLLECT_STATS | |
932 | #define IOMMU_MAP_STATS | |
933 | #endif | |
934 | #include "iommu-helpers.h" | |
935 | ||
936 | #ifdef DEBUG_LARGE_SG_ENTRIES | |
937 | int dump_run_sg = 0; | |
938 | #endif | |
939 | ||
940 | ||
941 | /** | |
942 | * sba_map_sg - map Scatter/Gather list | |
943 | * @dev: instance of PCI owned by the driver that's asking. | |
944 | * @sglist: array of buffer/length pairs | |
945 | * @nents: number of entries in list | |
946 | * @direction: R/W or both. | |
226b8ab8 | 947 | * @attrs: attributes |
1da177e4 | 948 | * |
985098a0 | 949 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
950 | */ |
951 | static int | |
952 | sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, | |
00085f1e | 953 | enum dma_data_direction direction, unsigned long attrs) |
1da177e4 LT |
954 | { |
955 | struct ioc *ioc; | |
226b8ab8 | 956 | int filled = 0; |
1da177e4 LT |
957 | unsigned long flags; |
958 | ||
a8043ecb | 959 | DBG_RUN_SG("%s() START %d entries\n", __func__, nents); |
1da177e4 LT |
960 | |
961 | ioc = GET_IOC(dev); | |
33f9e024 | 962 | if (!ioc) |
9a22f2f3 | 963 | return -EINVAL; |
1da177e4 LT |
964 | |
965 | /* Fast path single entry scatterlists. */ | |
966 | if (nents == 1) { | |
8bf8a1d1 | 967 | sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist), |
1da177e4 LT |
968 | sglist->length, direction); |
969 | sg_dma_len(sglist) = sglist->length; | |
970 | return 1; | |
971 | } | |
972 | ||
973 | spin_lock_irqsave(&ioc->res_lock, flags); | |
974 | ||
975 | #ifdef ASSERT_PDIR_SANITY | |
976 | if (sba_check_pdir(ioc,"Check before sba_map_sg()")) | |
977 | { | |
978 | sba_dump_sg(ioc, sglist, nents); | |
979 | panic("Check before sba_map_sg()"); | |
980 | } | |
981 | #endif | |
982 | ||
983 | #ifdef SBA_COLLECT_STATS | |
984 | ioc->msg_calls++; | |
985 | #endif | |
986 | ||
987 | /* | |
988 | ** First coalesce the chunks and allocate I/O pdir space | |
989 | ** | |
990 | ** If this is one DMA stream, we can properly map using the | |
991 | ** correct virtual address associated with each DMA page. | |
992 | ** w/o this association, we wouldn't have coherent DMA! | |
993 | ** Access to the virtual address is what forces a two pass algorithm. | |
994 | */ | |
226b8ab8 | 995 | iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); |
1da177e4 LT |
996 | |
997 | /* | |
998 | ** Program the I/O Pdir | |
999 | ** | |
1000 | ** map the virtual addresses to the I/O Pdir | |
1001 | ** o dma_address will contain the pdir index | |
1002 | ** o dma_len will contain the number of bytes to map | |
1003 | ** o address contains the virtual address. | |
1004 | */ | |
1005 | filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); | |
1006 | ||
64908ad9 | 1007 | /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ |
3847dab7 | 1008 | asm_io_sync(); |
64908ad9 | 1009 | |
1da177e4 LT |
1010 | #ifdef ASSERT_PDIR_SANITY |
1011 | if (sba_check_pdir(ioc,"Check after sba_map_sg()")) | |
1012 | { | |
1013 | sba_dump_sg(ioc, sglist, nents); | |
1014 | panic("Check after sba_map_sg()\n"); | |
1015 | } | |
1016 | #endif | |
1017 | ||
1018 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1019 | ||
a8043ecb | 1020 | DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); |
1da177e4 LT |
1021 | |
1022 | return filled; | |
1023 | } | |
1024 | ||
1025 | ||
1026 | /** | |
1027 | * sba_unmap_sg - unmap Scatter/Gather list | |
1028 | * @dev: instance of PCI owned by the driver that's asking. | |
1029 | * @sglist: array of buffer/length pairs | |
1030 | * @nents: number of entries in list | |
1031 | * @direction: R/W or both. | |
226b8ab8 | 1032 | * @attrs: attributes |
1da177e4 | 1033 | * |
985098a0 | 1034 | * See Documentation/core-api/dma-api-howto.rst |
1da177e4 LT |
1035 | */ |
1036 | static void | |
1037 | sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, | |
00085f1e | 1038 | enum dma_data_direction direction, unsigned long attrs) |
1da177e4 LT |
1039 | { |
1040 | struct ioc *ioc; | |
1041 | #ifdef ASSERT_PDIR_SANITY | |
1042 | unsigned long flags; | |
1043 | #endif | |
1044 | ||
1045 | DBG_RUN_SG("%s() START %d entries, %p,%x\n", | |
8bf8a1d1 | 1046 | __func__, nents, sg_virt(sglist), sglist->length); |
1da177e4 LT |
1047 | |
1048 | ioc = GET_IOC(dev); | |
33f9e024 TB |
1049 | if (!ioc) { |
1050 | WARN_ON(!ioc); | |
1051 | return; | |
1052 | } | |
1da177e4 LT |
1053 | |
1054 | #ifdef SBA_COLLECT_STATS | |
1055 | ioc->usg_calls++; | |
1056 | #endif | |
1057 | ||
1058 | #ifdef ASSERT_PDIR_SANITY | |
1059 | spin_lock_irqsave(&ioc->res_lock, flags); | |
1060 | sba_check_pdir(ioc,"Check before sba_unmap_sg()"); | |
1061 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1062 | #endif | |
1063 | ||
b7d6f44a | 1064 | while (nents && sg_dma_len(sglist)) { |
1da177e4 | 1065 | |
79387179 | 1066 | sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist), |
00085f1e | 1067 | direction, 0); |
1da177e4 LT |
1068 | #ifdef SBA_COLLECT_STATS |
1069 | ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; | |
1070 | ioc->usingle_calls--; /* kluge since call is unmap_sg() */ | |
1071 | #endif | |
1072 | ++sglist; | |
b7d6f44a | 1073 | nents--; |
1da177e4 LT |
1074 | } |
1075 | ||
a8043ecb | 1076 | DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); |
1da177e4 LT |
1077 | |
1078 | #ifdef ASSERT_PDIR_SANITY | |
1079 | spin_lock_irqsave(&ioc->res_lock, flags); | |
1080 | sba_check_pdir(ioc,"Check after sba_unmap_sg()"); | |
1081 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1082 | #endif | |
1083 | ||
1084 | } | |
1085 | ||
5299709d | 1086 | static const struct dma_map_ops sba_ops = { |
1da177e4 | 1087 | .dma_supported = sba_dma_supported, |
79387179 CH |
1088 | .alloc = sba_alloc, |
1089 | .free = sba_free, | |
1090 | .map_page = sba_map_page, | |
1091 | .unmap_page = sba_unmap_page, | |
1da177e4 LT |
1092 | .map_sg = sba_map_sg, |
1093 | .unmap_sg = sba_unmap_sg, | |
f9f3232a | 1094 | .get_sgtable = dma_common_get_sgtable, |
efa70f2f CH |
1095 | .alloc_pages = dma_common_alloc_pages, |
1096 | .free_pages = dma_common_free_pages, | |
1da177e4 LT |
1097 | }; |
1098 | ||
1099 | ||
1100 | /************************************************************************** | |
1101 | ** | |
1102 | ** SBA PAT PDC support | |
1103 | ** | |
1104 | ** o call pdc_pat_cell_module() | |
1105 | ** o store ranges in PCI "resource" structures | |
1106 | ** | |
1107 | **************************************************************************/ | |
1108 | ||
1109 | static void | |
1110 | sba_get_pat_resources(struct sba_device *sba_dev) | |
1111 | { | |
1112 | #if 0 | |
1113 | /* | |
1114 | ** TODO/REVISIT/FIXME: support for directed ranges requires calls to | |
1115 | ** PAT PDC to program the SBA/LBA directed range registers...this | |
1116 | ** burden may fall on the LBA code since it directly supports the | |
1117 | ** PCI subsystem. It's not clear yet. - ggg | |
1118 | */ | |
1119 | PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); | |
1120 | FIXME : ??? | |
1121 | PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); | |
1122 | Tells where the dvi bits are located in the address. | |
1123 | PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); | |
1124 | FIXME : ??? | |
1125 | #endif | |
1126 | } | |
1127 | ||
1128 | ||
1129 | /************************************************************** | |
1130 | * | |
1131 | * Initialization and claim | |
1132 | * | |
1133 | ***************************************************************/ | |
1134 | #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ | |
1135 | #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ | |
1136 | static void * | |
1137 | sba_alloc_pdir(unsigned int pdir_size) | |
1138 | { | |
1139 | unsigned long pdir_base; | |
1140 | unsigned long pdir_order = get_order(pdir_size); | |
1141 | ||
1142 | pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); | |
64908ad9 GG |
1143 | if (NULL == (void *) pdir_base) { |
1144 | panic("%s() could not allocate I/O Page Table\n", | |
a8043ecb | 1145 | __func__); |
64908ad9 | 1146 | } |
1da177e4 LT |
1147 | |
1148 | /* If this is not PA8700 (PCX-W2) | |
1149 | ** OR newer than ver 2.2 | |
1150 | ** OR in a system that doesn't need VINDEX bits from SBA, | |
1151 | ** | |
1152 | ** then we aren't exposed to the HW bug. | |
1153 | */ | |
1154 | if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 | |
1155 | || (boot_cpu_data.pdc.versions > 0x202) | |
1156 | || (boot_cpu_data.pdc.capabilities & 0x08L) ) | |
1157 | return (void *) pdir_base; | |
1158 | ||
1159 | /* | |
1160 | * PA8700 (PCX-W2, aka piranha) silent data corruption fix | |
1161 | * | |
1162 | * An interaction between PA8700 CPU (Ver 2.2 or older) and | |
1163 | * Ike/Astro can cause silent data corruption. This is only | |
1164 | * a problem if the I/O PDIR is located in memory such that | |
1165 | * (little-endian) bits 17 and 18 are on and bit 20 is off. | |
1166 | * | |
1167 | * Since the max IO Pdir size is 2MB, by cleverly allocating the | |
1168 | * right physical address, we can either avoid (IOPDIR <= 1MB) | |
1169 | * or minimize (2MB IO Pdir) the problem if we restrict the | |
1170 | * IO Pdir to a maximum size of 2MB-128K (1902K). | |
1171 | * | |
1172 | * Because we always allocate 2^N sized IO pdirs, either of the | |
1173 | * "bad" regions will be the last 128K if at all. That's easy | |
1174 | * to test for. | |
1175 | * | |
1176 | */ | |
1177 | if (pdir_order <= (19-12)) { | |
1178 | if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { | |
1179 | /* allocate a new one on 512k alignment */ | |
1180 | unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); | |
1181 | /* release original */ | |
1182 | free_pages(pdir_base, pdir_order); | |
1183 | ||
1184 | pdir_base = new_pdir; | |
1185 | ||
1186 | /* release excess */ | |
1187 | while (pdir_order < (19-12)) { | |
1188 | new_pdir += pdir_size; | |
1189 | free_pages(new_pdir, pdir_order); | |
1190 | pdir_order +=1; | |
1191 | pdir_size <<=1; | |
1192 | } | |
1193 | } | |
1194 | } else { | |
1195 | /* | |
1196 | ** 1MB or 2MB Pdir | |
1197 | ** Needs to be aligned on an "odd" 1MB boundary. | |
1198 | */ | |
1199 | unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ | |
1200 | ||
1201 | /* release original */ | |
1202 | free_pages( pdir_base, pdir_order); | |
1203 | ||
1204 | /* release first 1MB */ | |
1205 | free_pages(new_pdir, 20-12); | |
1206 | ||
1207 | pdir_base = new_pdir + 1024*1024; | |
1208 | ||
1209 | if (pdir_order > (20-12)) { | |
1210 | /* | |
1211 | ** 2MB Pdir. | |
1212 | ** | |
1213 | ** Flag tells init_bitmap() to mark bad 128k as used | |
1214 | ** and to reduce the size by 128k. | |
1215 | */ | |
1216 | piranha_bad_128k = 1; | |
1217 | ||
1218 | new_pdir += 3*1024*1024; | |
1219 | /* release last 1MB */ | |
1220 | free_pages(new_pdir, 20-12); | |
1221 | ||
1222 | /* release unusable 128KB */ | |
1223 | free_pages(new_pdir - 128*1024 , 17-12); | |
1224 | ||
1225 | pdir_size -= 128*1024; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | memset((void *) pdir_base, 0, pdir_size); | |
1230 | return (void *) pdir_base; | |
1231 | } | |
1232 | ||
bfe4f4f8 JB |
1233 | struct ibase_data_struct { |
1234 | struct ioc *ioc; | |
1235 | int ioc_num; | |
1236 | }; | |
1237 | ||
1238 | static int setup_ibase_imask_callback(struct device *dev, void *data) | |
56583747 | 1239 | { |
bfe4f4f8 JB |
1240 | struct parisc_device *lba = to_parisc_device(dev); |
1241 | struct ibase_data_struct *ibd = data; | |
1242 | int rope_num = (lba->hpa.start >> 13) & 0xf; | |
1243 | if (rope_num >> 3 == ibd->ioc_num) | |
1244 | lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); | |
1245 | return 0; | |
56583747 MW |
1246 | } |
1247 | ||
1da177e4 | 1248 | /* setup Mercury or Elroy IBASE/IMASK registers. */ |
56583747 MW |
1249 | static void |
1250 | setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |
1da177e4 | 1251 | { |
bfe4f4f8 JB |
1252 | struct ibase_data_struct ibase_data = { |
1253 | .ioc = ioc, | |
1254 | .ioc_num = ioc_num, | |
1255 | }; | |
1256 | ||
1257 | device_for_each_child(&sba->dev, &ibase_data, | |
1258 | setup_ibase_imask_callback); | |
1da177e4 LT |
1259 | } |
1260 | ||
bfe4f4f8 JB |
1261 | #ifdef SBA_AGP_SUPPORT |
1262 | static int | |
1263 | sba_ioc_find_quicksilver(struct device *dev, void *data) | |
1264 | { | |
1265 | int *agp_found = data; | |
1266 | struct parisc_device *lba = to_parisc_device(dev); | |
1267 | ||
1268 | if (IS_QUICKSILVER(lba)) | |
1269 | *agp_found = 1; | |
1270 | return 0; | |
1271 | } | |
1272 | #endif | |
1273 | ||
1da177e4 LT |
1274 | static void |
1275 | sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |
1276 | { | |
1277 | u32 iova_space_mask; | |
1278 | u32 iova_space_size; | |
1279 | int iov_order, tcnfg; | |
64908ad9 | 1280 | #ifdef SBA_AGP_SUPPORT |
1da177e4 LT |
1281 | int agp_found = 0; |
1282 | #endif | |
1283 | /* | |
1284 | ** Firmware programs the base and size of a "safe IOVA space" | |
1285 | ** (one that doesn't overlap memory or LMMIO space) in the | |
1286 | ** IBASE and IMASK registers. | |
1287 | */ | |
5b24993c | 1288 | ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL; |
1da177e4 LT |
1289 | iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; |
1290 | ||
1291 | if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { | |
1292 | printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); | |
1293 | iova_space_size /= 2; | |
1294 | } | |
1295 | ||
1296 | /* | |
1297 | ** iov_order is always based on a 1GB IOVA space since we want to | |
1298 | ** turn on the other half for AGP GART. | |
1299 | */ | |
1300 | iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); | |
1301 | ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); | |
1302 | ||
40d78de1 | 1303 | DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", |
a8043ecb | 1304 | __func__, ioc->ioc_hpa, iova_space_size >> 20, |
1da177e4 LT |
1305 | iov_order + PAGE_SHIFT); |
1306 | ||
1307 | ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, | |
1308 | get_order(ioc->pdir_size)); | |
1309 | if (!ioc->pdir_base) | |
1310 | panic("Couldn't allocate I/O Page Table\n"); | |
1311 | ||
1312 | memset(ioc->pdir_base, 0, ioc->pdir_size); | |
1313 | ||
1314 | DBG_INIT("%s() pdir %p size %x\n", | |
a8043ecb | 1315 | __func__, ioc->pdir_base, ioc->pdir_size); |
1da177e4 | 1316 | |
64908ad9 | 1317 | #ifdef SBA_HINT_SUPPORT |
1da177e4 LT |
1318 | ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; |
1319 | ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); | |
1320 | ||
1321 | DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", | |
1322 | ioc->hint_shift_pdir, ioc->hint_mask_pdir); | |
1323 | #endif | |
1324 | ||
1325 | WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); | |
1326 | WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); | |
1327 | ||
1328 | /* build IMASK for IOC and Elroy */ | |
1329 | iova_space_mask = 0xffffffff; | |
1330 | iova_space_mask <<= (iov_order + PAGE_SHIFT); | |
1331 | ioc->imask = iova_space_mask; | |
1332 | #ifdef ZX1_SUPPORT | |
1333 | ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); | |
1334 | #endif | |
1335 | sba_dump_tlb(ioc->ioc_hpa); | |
1336 | ||
1337 | setup_ibase_imask(sba, ioc, ioc_num); | |
1338 | ||
1339 | WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); | |
1340 | ||
64908ad9 | 1341 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1342 | /* |
1343 | ** Setting the upper bits makes checking for bypass addresses | |
1344 | ** a little faster later on. | |
1345 | */ | |
1346 | ioc->imask |= 0xFFFFFFFF00000000UL; | |
1347 | #endif | |
1348 | ||
1349 | /* Set I/O PDIR Page size to system page size */ | |
1350 | switch (PAGE_SHIFT) { | |
1351 | case 12: tcnfg = 0; break; /* 4K */ | |
1352 | case 13: tcnfg = 1; break; /* 8K */ | |
1353 | case 14: tcnfg = 2; break; /* 16K */ | |
1354 | case 16: tcnfg = 3; break; /* 64K */ | |
1355 | default: | |
1356 | panic(__FILE__ "Unsupported system page size %d", | |
1357 | 1 << PAGE_SHIFT); | |
1358 | break; | |
1359 | } | |
1360 | WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); | |
1361 | ||
1362 | /* | |
1363 | ** Program the IOC's ibase and enable IOVA translation | |
1364 | ** Bit zero == enable bit. | |
1365 | */ | |
1366 | WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); | |
1367 | ||
1368 | /* | |
1369 | ** Clear I/O TLB of any possible entries. | |
1370 | ** (Yes. This is a bit paranoid...but so what) | |
1371 | */ | |
1372 | WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); | |
1373 | ||
64908ad9 | 1374 | #ifdef SBA_AGP_SUPPORT |
08a64368 | 1375 | |
1da177e4 LT |
1376 | /* |
1377 | ** If an AGP device is present, only use half of the IOV space | |
1378 | ** for PCI DMA. Unfortunately we can't know ahead of time | |
1379 | ** whether GART support will actually be used, for now we | |
1380 | ** can just key on any AGP device found in the system. | |
1381 | ** We program the next pdir index after we stop w/ a key for | |
1382 | ** the GART code to handshake on. | |
1383 | */ | |
bfe4f4f8 | 1384 | device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); |
1da177e4 | 1385 | |
08a64368 KM |
1386 | if (agp_found && sba_reserve_agpgart) { |
1387 | printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", | |
a8043ecb | 1388 | __func__, (iova_space_size/2) >> 20); |
1da177e4 | 1389 | ioc->pdir_size /= 2; |
08a64368 | 1390 | ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; |
1da177e4 | 1391 | } |
08a64368 | 1392 | #endif /*SBA_AGP_SUPPORT*/ |
1da177e4 LT |
1393 | } |
1394 | ||
1395 | static void | |
1396 | sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |
1397 | { | |
1398 | u32 iova_space_size, iova_space_mask; | |
6a45716a | 1399 | unsigned int pdir_size, iov_order, tcnfg; |
1da177e4 LT |
1400 | |
1401 | /* | |
1402 | ** Determine IOVA Space size from memory size. | |
1403 | ** | |
1404 | ** Ideally, PCI drivers would register the maximum number | |
1405 | ** of DMA they can have outstanding for each device they | |
1406 | ** own. Next best thing would be to guess how much DMA | |
1407 | ** can be outstanding based on PCI Class/sub-class. Both | |
1408 | ** methods still require some "extra" to support PCI | |
1409 | ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). | |
1410 | ** | |
1411 | ** While we have 32-bits "IOVA" space, top two 2 bits are used | |
1412 | ** for DMA hints - ergo only 30 bits max. | |
1413 | */ | |
1414 | ||
ca79b0c2 | 1415 | iova_space_size = (u32) (totalram_pages()/global_ioc_cnt); |
1da177e4 LT |
1416 | |
1417 | /* limit IOVA space size to 1MB-1GB */ | |
1418 | if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { | |
1419 | iova_space_size = 1 << (20 - PAGE_SHIFT); | |
1420 | } | |
1da177e4 LT |
1421 | else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { |
1422 | iova_space_size = 1 << (30 - PAGE_SHIFT); | |
1423 | } | |
1da177e4 LT |
1424 | |
1425 | /* | |
1426 | ** iova space must be log2() in size. | |
1427 | ** thus, pdir/res_map will also be log2(). | |
1428 | ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) | |
1429 | */ | |
1430 | iov_order = get_order(iova_space_size << PAGE_SHIFT); | |
1431 | ||
1432 | /* iova_space_size is now bytes, not pages */ | |
1433 | iova_space_size = 1 << (iov_order + PAGE_SHIFT); | |
1434 | ||
1435 | ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); | |
1436 | ||
1437 | DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", | |
a8043ecb | 1438 | __func__, |
1da177e4 | 1439 | ioc->ioc_hpa, |
ca79b0c2 | 1440 | (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), |
1da177e4 LT |
1441 | iova_space_size>>20, |
1442 | iov_order + PAGE_SHIFT); | |
1443 | ||
1444 | ioc->pdir_base = sba_alloc_pdir(pdir_size); | |
1445 | ||
1446 | DBG_INIT("%s() pdir %p size %x\n", | |
a8043ecb | 1447 | __func__, ioc->pdir_base, pdir_size); |
1da177e4 | 1448 | |
64908ad9 | 1449 | #ifdef SBA_HINT_SUPPORT |
1da177e4 LT |
1450 | /* FIXME : DMA HINTs not used */ |
1451 | ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; | |
1452 | ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); | |
1453 | ||
1454 | DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", | |
1455 | ioc->hint_shift_pdir, ioc->hint_mask_pdir); | |
1456 | #endif | |
1457 | ||
1458 | WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); | |
1459 | ||
1460 | /* build IMASK for IOC and Elroy */ | |
1461 | iova_space_mask = 0xffffffff; | |
1462 | iova_space_mask <<= (iov_order + PAGE_SHIFT); | |
1463 | ||
1464 | /* | |
1465 | ** On C3000 w/512MB mem, HP-UX 10.20 reports: | |
1466 | ** ibase=0, imask=0xFE000000, size=0x2000000. | |
1467 | */ | |
1468 | ioc->ibase = 0; | |
1469 | ioc->imask = iova_space_mask; /* save it */ | |
1470 | #ifdef ZX1_SUPPORT | |
1471 | ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); | |
1472 | #endif | |
1473 | ||
1474 | DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", | |
a8043ecb | 1475 | __func__, ioc->ibase, ioc->imask); |
1da177e4 LT |
1476 | |
1477 | /* | |
1478 | ** FIXME: Hint registers are programmed with default hint | |
1479 | ** values during boot, so hints should be sane even if we | |
1480 | ** can't reprogram them the way drivers want. | |
1481 | */ | |
1482 | ||
1483 | setup_ibase_imask(sba, ioc, ioc_num); | |
1484 | ||
1485 | /* | |
1486 | ** Program the IOC's ibase and enable IOVA translation | |
1487 | */ | |
1488 | WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); | |
1489 | WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); | |
1490 | ||
6a45716a HD |
1491 | /* Set I/O PDIR Page size to system page size */ |
1492 | switch (PAGE_SHIFT) { | |
1493 | case 12: tcnfg = 0; break; /* 4K */ | |
1494 | case 13: tcnfg = 1; break; /* 8K */ | |
1495 | case 14: tcnfg = 2; break; /* 16K */ | |
1496 | case 16: tcnfg = 3; break; /* 64K */ | |
1497 | default: | |
1498 | panic(__FILE__ "Unsupported system page size %d", | |
1499 | 1 << PAGE_SHIFT); | |
1500 | break; | |
1501 | } | |
1502 | /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */ | |
1503 | WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG); | |
1da177e4 LT |
1504 | |
1505 | /* | |
1506 | ** Clear I/O TLB of any possible entries. | |
1507 | ** (Yes. This is a bit paranoid...but so what) | |
1508 | */ | |
1509 | WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); | |
1510 | ||
1511 | ioc->ibase = 0; /* used by SBA_IOVA and related macros */ | |
1512 | ||
a8043ecb | 1513 | DBG_INIT("%s() DONE\n", __func__); |
1da177e4 LT |
1514 | } |
1515 | ||
1516 | ||
1517 | ||
1518 | /************************************************************************** | |
1519 | ** | |
1520 | ** SBA initialization code (HW and SW) | |
1521 | ** | |
1522 | ** o identify SBA chip itself | |
1523 | ** o initialize SBA chip modes (HardFail) | |
1524 | ** o initialize SBA chip modes (HardFail) | |
1525 | ** o FIXME: initialize DMA hints for reasonable defaults | |
1526 | ** | |
1527 | **************************************************************************/ | |
1528 | ||
5076c158 | 1529 | static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) |
1da177e4 | 1530 | { |
4bdc0d67 | 1531 | return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); |
1da177e4 LT |
1532 | } |
1533 | ||
1534 | static void sba_hw_init(struct sba_device *sba_dev) | |
1535 | { | |
1536 | int i; | |
1537 | int num_ioc; | |
1538 | u64 ioc_ctl; | |
1539 | ||
1540 | if (!is_pdc_pat()) { | |
1541 | /* Shutdown the USB controller on Astro-based workstations. | |
1542 | ** Once we reprogram the IOMMU, the next DMA performed by | |
1543 | ** USB will HPMC the box. USB is only enabled if a | |
1544 | ** keyboard is present and found. | |
1545 | ** | |
1546 | ** With serial console, j6k v5.0 firmware says: | |
1547 | ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 | |
1548 | ** | |
1549 | ** FIXME: Using GFX+USB console at power up but direct | |
1550 | ** linux to serial console is still broken. | |
1551 | ** USB could generate DMA so we must reset USB. | |
1552 | ** The proper sequence would be: | |
1553 | ** o block console output | |
1554 | ** o reset USB device | |
1555 | ** o reprogram serial port | |
1556 | ** o unblock console output | |
1557 | */ | |
1558 | if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { | |
1559 | pdc_io_reset_devices(); | |
1560 | } | |
1561 | ||
1562 | } | |
1563 | ||
1564 | ||
1565 | #if 0 | |
1566 | printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, | |
1567 | PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); | |
1568 | ||
1569 | /* | |
1570 | ** Need to deal with DMA from LAN. | |
1571 | ** Maybe use page zero boot device as a handle to talk | |
1572 | ** to PDC about which device to shutdown. | |
1573 | ** | |
1574 | ** Netbooting, j6k v5.0 firmware says: | |
1575 | ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 | |
1576 | ** ARGH! invalid class. | |
1577 | */ | |
1578 | if ((PAGE0->mem_boot.cl_class != CL_RANDOM) | |
1579 | && (PAGE0->mem_boot.cl_class != CL_SEQU)) { | |
1580 | pdc_io_reset(); | |
1581 | } | |
1582 | #endif | |
1583 | ||
1b240f41 | 1584 | if (!IS_PLUTO(sba_dev->dev)) { |
1da177e4 LT |
1585 | ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); |
1586 | DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", | |
a8043ecb | 1587 | __func__, sba_dev->sba_hpa, ioc_ctl); |
1da177e4 LT |
1588 | ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); |
1589 | ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; | |
1590 | /* j6700 v1.6 firmware sets 0x294f */ | |
1591 | /* A500 firmware sets 0x4d */ | |
1592 | ||
1593 | WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); | |
1594 | ||
1595 | #ifdef DEBUG_SBA_INIT | |
1596 | ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); | |
1597 | DBG_INIT(" 0x%Lx\n", ioc_ctl); | |
1598 | #endif | |
1599 | } /* if !PLUTO */ | |
1600 | ||
1b240f41 | 1601 | if (IS_ASTRO(sba_dev->dev)) { |
1da177e4 | 1602 | int err; |
1da177e4 LT |
1603 | sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); |
1604 | num_ioc = 1; | |
1605 | ||
1606 | sba_dev->chip_resv.name = "Astro Intr Ack"; | |
1607 | sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; | |
1608 | sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; | |
1609 | err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); | |
b7494554 | 1610 | BUG_ON(err < 0); |
1da177e4 | 1611 | |
1b240f41 | 1612 | } else if (IS_PLUTO(sba_dev->dev)) { |
1da177e4 LT |
1613 | int err; |
1614 | ||
1da177e4 LT |
1615 | sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); |
1616 | num_ioc = 1; | |
1617 | ||
1618 | sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; | |
1619 | sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; | |
1620 | sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); | |
1621 | err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); | |
1622 | WARN_ON(err < 0); | |
1623 | ||
1624 | sba_dev->iommu_resv.name = "IOVA Space"; | |
1625 | sba_dev->iommu_resv.start = 0x40000000UL; | |
1626 | sba_dev->iommu_resv.end = 0x50000000UL - 1; | |
1627 | err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); | |
1628 | WARN_ON(err < 0); | |
1629 | } else { | |
7886089e | 1630 | /* IKE, REO */ |
1da177e4 LT |
1631 | sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); |
1632 | sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); | |
1633 | num_ioc = 2; | |
1634 | ||
1635 | /* TODO - LOOKUP Ike/Stretch chipset mem map */ | |
1636 | } | |
7886089e | 1637 | /* XXX: What about Reo Grande? */ |
1da177e4 LT |
1638 | |
1639 | sba_dev->num_ioc = num_ioc; | |
1640 | for (i = 0; i < num_ioc; i++) { | |
40d78de1 | 1641 | void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; |
b312c33e GG |
1642 | unsigned int j; |
1643 | ||
1644 | for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { | |
1645 | ||
1646 | /* | |
1647 | * Clear ROPE(N)_CONFIG AO bit. | |
1648 | * Disables "NT Ordering" (~= !"Relaxed Ordering") | |
1649 | * Overrides bit 1 in DMA Hint Sets. | |
1650 | * Improves netperf UDP_STREAM by ~10% for bcm5701. | |
1651 | */ | |
1b240f41 | 1652 | if (IS_PLUTO(sba_dev->dev)) { |
40d78de1 GG |
1653 | void __iomem *rope_cfg; |
1654 | unsigned long cfg_val; | |
b312c33e GG |
1655 | |
1656 | rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; | |
1657 | cfg_val = READ_REG(rope_cfg); | |
1658 | cfg_val &= ~IOC_ROPE_AO; | |
1659 | WRITE_REG(cfg_val, rope_cfg); | |
1660 | } | |
1661 | ||
1662 | /* | |
1663 | ** Make sure the box crashes on rope errors. | |
1664 | */ | |
1665 | WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); | |
1666 | } | |
1667 | ||
1668 | /* flush out the last writes */ | |
1da177e4 LT |
1669 | READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); |
1670 | ||
1671 | DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", | |
1672 | i, | |
1673 | READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), | |
1674 | READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) | |
1675 | ); | |
1676 | DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", | |
1677 | READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), | |
1678 | READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) | |
1679 | ); | |
1680 | ||
1b240f41 | 1681 | if (IS_PLUTO(sba_dev->dev)) { |
1da177e4 LT |
1682 | sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); |
1683 | } else { | |
1684 | sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); | |
1685 | } | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | static void | |
1690 | sba_common_init(struct sba_device *sba_dev) | |
1691 | { | |
1692 | int i; | |
1693 | ||
1694 | /* add this one to the head of the list (order doesn't matter) | |
1695 | ** This will be useful for debugging - especially if we get coredumps | |
1696 | */ | |
1697 | sba_dev->next = sba_list; | |
1698 | sba_list = sba_dev; | |
1699 | ||
1700 | for(i=0; i< sba_dev->num_ioc; i++) { | |
1701 | int res_size; | |
1702 | #ifdef DEBUG_DMB_TRAP | |
1703 | extern void iterate_pages(unsigned long , unsigned long , | |
1704 | void (*)(pte_t * , unsigned long), | |
1705 | unsigned long ); | |
1706 | void set_data_memory_break(pte_t * , unsigned long); | |
1707 | #endif | |
1708 | /* resource map size dictated by pdir_size */ | |
1709 | res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ | |
1710 | ||
1711 | /* Second part of PIRANHA BUG */ | |
1712 | if (piranha_bad_128k) { | |
1713 | res_size -= (128*1024)/sizeof(u64); | |
1714 | } | |
1715 | ||
1716 | res_size >>= 3; /* convert bit count to byte count */ | |
1717 | DBG_INIT("%s() res_size 0x%x\n", | |
a8043ecb | 1718 | __func__, res_size); |
1da177e4 LT |
1719 | |
1720 | sba_dev->ioc[i].res_size = res_size; | |
1721 | sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); | |
1722 | ||
1723 | #ifdef DEBUG_DMB_TRAP | |
1724 | iterate_pages( sba_dev->ioc[i].res_map, res_size, | |
1725 | set_data_memory_break, 0); | |
1726 | #endif | |
1727 | ||
1728 | if (NULL == sba_dev->ioc[i].res_map) | |
1729 | { | |
1730 | panic("%s:%s() could not allocate resource map\n", | |
a8043ecb | 1731 | __FILE__, __func__ ); |
1da177e4 LT |
1732 | } |
1733 | ||
1734 | memset(sba_dev->ioc[i].res_map, 0, res_size); | |
1735 | /* next available IOVP - circular search */ | |
1736 | sba_dev->ioc[i].res_hint = (unsigned long *) | |
1737 | &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); | |
1738 | ||
1739 | #ifdef ASSERT_PDIR_SANITY | |
1740 | /* Mark first bit busy - ie no IOVA 0 */ | |
1741 | sba_dev->ioc[i].res_map[0] = 0x80; | |
1742 | sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; | |
1743 | #endif | |
1744 | ||
1745 | /* Third (and last) part of PIRANHA BUG */ | |
1746 | if (piranha_bad_128k) { | |
1747 | /* region from +1408K to +1536 is un-usable. */ | |
1748 | ||
1749 | int idx_start = (1408*1024/sizeof(u64)) >> 3; | |
1750 | int idx_end = (1536*1024/sizeof(u64)) >> 3; | |
1751 | long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); | |
1752 | long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); | |
1753 | ||
1754 | /* mark that part of the io pdir busy */ | |
1755 | while (p_start < p_end) | |
1756 | *p_start++ = -1; | |
1757 | ||
1758 | } | |
1759 | ||
1760 | #ifdef DEBUG_DMB_TRAP | |
1761 | iterate_pages( sba_dev->ioc[i].res_map, res_size, | |
1762 | set_data_memory_break, 0); | |
1763 | iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, | |
1764 | set_data_memory_break, 0); | |
1765 | #endif | |
1766 | ||
1767 | DBG_INIT("%s() %d res_map %x %p\n", | |
a8043ecb | 1768 | __func__, i, res_size, sba_dev->ioc[i].res_map); |
1da177e4 LT |
1769 | } |
1770 | ||
1771 | spin_lock_init(&sba_dev->sba_lock); | |
1772 | ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; | |
1773 | ||
1774 | #ifdef DEBUG_SBA_INIT | |
1775 | /* | |
1776 | * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set | |
1777 | * (bit #61, big endian), we have to flush and sync every time | |
1778 | * IO-PDIR is changed in Ike/Astro. | |
1779 | */ | |
692086e0 | 1780 | if (ioc_needs_fdc) { |
1da177e4 LT |
1781 | printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); |
1782 | } else { | |
1783 | printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); | |
1784 | } | |
1785 | #endif | |
1786 | } | |
1787 | ||
1788 | #ifdef CONFIG_PROC_FS | |
7ec14e49 | 1789 | static int sba_proc_info(struct seq_file *m, void *p) |
1da177e4 LT |
1790 | { |
1791 | struct sba_device *sba_dev = sba_list; | |
1792 | struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ | |
1793 | int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ | |
1da177e4 LT |
1794 | #ifdef SBA_COLLECT_STATS |
1795 | unsigned long avg = 0, min, max; | |
1796 | #endif | |
e693d73c JP |
1797 | int i; |
1798 | ||
1799 | seq_printf(m, "%s rev %d.%d\n", | |
1800 | sba_dev->name, | |
1801 | (sba_dev->hw_rev & 0x7) + 1, | |
1802 | (sba_dev->hw_rev & 0x18) >> 3); | |
1803 | seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", | |
1804 | (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ | |
1805 | total_pages); | |
1806 | ||
1807 | seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", | |
1808 | ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ | |
1809 | ||
1810 | seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", | |
1811 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), | |
1812 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), | |
1813 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)); | |
1da177e4 LT |
1814 | |
1815 | for (i=0; i<4; i++) | |
e693d73c JP |
1816 | seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", |
1817 | i, | |
1818 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), | |
1819 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), | |
1820 | READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)); | |
1da177e4 LT |
1821 | |
1822 | #ifdef SBA_COLLECT_STATS | |
e693d73c JP |
1823 | seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", |
1824 | total_pages - ioc->used_pages, ioc->used_pages, | |
1825 | (int)(ioc->used_pages * 100 / total_pages)); | |
1da177e4 LT |
1826 | |
1827 | min = max = ioc->avg_search[0]; | |
1828 | for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { | |
1829 | avg += ioc->avg_search[i]; | |
1830 | if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; | |
1831 | if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; | |
1832 | } | |
1833 | avg /= SBA_SEARCH_SAMPLE; | |
e693d73c JP |
1834 | seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", |
1835 | min, avg, max); | |
1da177e4 | 1836 | |
e693d73c JP |
1837 | seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", |
1838 | ioc->msingle_calls, ioc->msingle_pages, | |
1839 | (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); | |
1da177e4 LT |
1840 | |
1841 | /* KLUGE - unmap_sg calls unmap_single for each mapped page */ | |
1842 | min = ioc->usingle_calls; | |
1843 | max = ioc->usingle_pages - ioc->usg_pages; | |
e693d73c JP |
1844 | seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", |
1845 | min, max, (int)((max * 1000)/min)); | |
1da177e4 | 1846 | |
e693d73c JP |
1847 | seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", |
1848 | ioc->msg_calls, ioc->msg_pages, | |
1849 | (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); | |
1da177e4 | 1850 | |
e693d73c JP |
1851 | seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", |
1852 | ioc->usg_calls, ioc->usg_pages, | |
1853 | (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); | |
1da177e4 LT |
1854 | #endif |
1855 | ||
7ec14e49 | 1856 | return 0; |
1da177e4 LT |
1857 | } |
1858 | ||
7ec14e49 KM |
1859 | static int |
1860 | sba_proc_bitmap_info(struct seq_file *m, void *p) | |
1da177e4 LT |
1861 | { |
1862 | struct sba_device *sba_dev = sba_list; | |
7ec14e49 | 1863 | struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ |
1da177e4 | 1864 | |
b342a65d AS |
1865 | seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, |
1866 | ioc->res_size, false); | |
e693d73c | 1867 | seq_putc(m, '\n'); |
1da177e4 | 1868 | |
7ec14e49 | 1869 | return 0; |
1da177e4 | 1870 | } |
1da177e4 LT |
1871 | #endif /* CONFIG_PROC_FS */ |
1872 | ||
cfe4fbfb | 1873 | static const struct parisc_device_id sba_tbl[] __initconst = { |
1da177e4 LT |
1874 | { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, |
1875 | { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, | |
1876 | { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, | |
1877 | { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, | |
1878 | { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, | |
1879 | { 0, } | |
1880 | }; | |
1881 | ||
df8e5bc6 | 1882 | static int sba_driver_callback(struct parisc_device *); |
1da177e4 | 1883 | |
cfe4fbfb | 1884 | static struct parisc_driver sba_driver __refdata = { |
1da177e4 LT |
1885 | .name = MODULE_NAME, |
1886 | .id_table = sba_tbl, | |
1887 | .probe = sba_driver_callback, | |
1888 | }; | |
1889 | ||
1890 | /* | |
1891 | ** Determine if sba should claim this chip (return 0) or not (return 1). | |
1892 | ** If so, initialize the chip and tell other partners in crime they | |
1893 | ** have work to do. | |
1894 | */ | |
cfe4fbfb | 1895 | static int __init sba_driver_callback(struct parisc_device *dev) |
1da177e4 LT |
1896 | { |
1897 | struct sba_device *sba_dev; | |
1898 | u32 func_class; | |
1899 | int i; | |
1900 | char *version; | |
4bdc0d67 | 1901 | void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE); |
0fd68946 DL |
1902 | #ifdef CONFIG_PROC_FS |
1903 | struct proc_dir_entry *root; | |
1904 | #endif | |
1da177e4 LT |
1905 | |
1906 | sba_dump_ranges(sba_addr); | |
1907 | ||
1908 | /* Read HW Rev First */ | |
1909 | func_class = READ_REG(sba_addr + SBA_FCLASS); | |
1910 | ||
1b240f41 | 1911 | if (IS_ASTRO(dev)) { |
1da177e4 LT |
1912 | unsigned long fclass; |
1913 | static char astro_rev[]="Astro ?.?"; | |
1914 | ||
1915 | /* Astro is broken...Read HW Rev First */ | |
1916 | fclass = READ_REG(sba_addr); | |
1917 | ||
1918 | astro_rev[6] = '1' + (char) (fclass & 0x7); | |
1919 | astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); | |
1920 | version = astro_rev; | |
1921 | ||
1b240f41 | 1922 | } else if (IS_IKE(dev)) { |
1da177e4 LT |
1923 | static char ike_rev[] = "Ike rev ?"; |
1924 | ike_rev[8] = '0' + (char) (func_class & 0xff); | |
1925 | version = ike_rev; | |
1b240f41 | 1926 | } else if (IS_PLUTO(dev)) { |
1da177e4 LT |
1927 | static char pluto_rev[]="Pluto ?.?"; |
1928 | pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); | |
1929 | pluto_rev[8] = '0' + (char) (func_class & 0x0f); | |
1930 | version = pluto_rev; | |
1931 | } else { | |
1932 | static char reo_rev[] = "REO rev ?"; | |
1933 | reo_rev[8] = '0' + (char) (func_class & 0xff); | |
1934 | version = reo_rev; | |
1935 | } | |
1936 | ||
1937 | if (!global_ioc_cnt) { | |
1938 | global_ioc_cnt = count_parisc_driver(&sba_driver); | |
1939 | ||
1940 | /* Astro and Pluto have one IOC per SBA */ | |
1b240f41 | 1941 | if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) |
1da177e4 LT |
1942 | global_ioc_cnt *= 2; |
1943 | } | |
1944 | ||
e9a03990 KM |
1945 | printk(KERN_INFO "%s found %s at 0x%llx\n", |
1946 | MODULE_NAME, version, (unsigned long long)dev->hpa.start); | |
1da177e4 | 1947 | |
cb6fc18e | 1948 | sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); |
1da177e4 LT |
1949 | if (!sba_dev) { |
1950 | printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); | |
1951 | return -ENOMEM; | |
1952 | } | |
1953 | ||
1954 | parisc_set_drvdata(dev, sba_dev); | |
1da177e4 LT |
1955 | |
1956 | for(i=0; i<MAX_IOC; i++) | |
1957 | spin_lock_init(&(sba_dev->ioc[i].res_lock)); | |
1958 | ||
1959 | sba_dev->dev = dev; | |
1960 | sba_dev->hw_rev = func_class; | |
1da177e4 LT |
1961 | sba_dev->name = dev->name; |
1962 | sba_dev->sba_hpa = sba_addr; | |
1963 | ||
1964 | sba_get_pat_resources(sba_dev); | |
1965 | sba_hw_init(sba_dev); | |
1966 | sba_common_init(sba_dev); | |
1967 | ||
1968 | hppa_dma_ops = &sba_ops; | |
1969 | ||
1970 | #ifdef CONFIG_PROC_FS | |
7ec14e49 KM |
1971 | switch (dev->id.hversion) { |
1972 | case PLUTO_MCKINLEY_PORT: | |
54725958 HD |
1973 | if (!proc_mckinley_root) |
1974 | proc_mckinley_root = proc_mkdir("bus/mckinley", NULL); | |
7ec14e49 KM |
1975 | root = proc_mckinley_root; |
1976 | break; | |
1977 | case ASTRO_RUNWAY_PORT: | |
1978 | case IKE_MERCED_PORT: | |
1979 | default: | |
54725958 HD |
1980 | if (!proc_runway_root) |
1981 | proc_runway_root = proc_mkdir("bus/runway", NULL); | |
7ec14e49 KM |
1982 | root = proc_runway_root; |
1983 | break; | |
1da177e4 | 1984 | } |
7ec14e49 | 1985 | |
3f3942ac CH |
1986 | proc_create_single("sba_iommu", 0, root, sba_proc_info); |
1987 | proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info); | |
1da177e4 | 1988 | #endif |
1da177e4 LT |
1989 | return 0; |
1990 | } | |
1991 | ||
1992 | /* | |
1993 | ** One time initialization to let the world know the SBA was found. | |
1994 | ** This is the only routine which is NOT static. | |
1995 | ** Must be called exactly once before pci_init(). | |
1996 | */ | |
53861a91 | 1997 | static int __init sba_init(void) |
1da177e4 | 1998 | { |
53861a91 | 1999 | return register_parisc_driver(&sba_driver); |
1da177e4 | 2000 | } |
53861a91 | 2001 | arch_initcall(sba_init); |
1da177e4 LT |
2002 | |
2003 | ||
2004 | /** | |
2005 | * sba_get_iommu - Assign the iommu pointer for the pci bus controller. | |
226b8ab8 | 2006 | * @pci_hba: The parisc device. |
1da177e4 LT |
2007 | * |
2008 | * Returns the appropriate IOMMU data for the given parisc PCI controller. | |
2009 | * This is cached and used later for PCI DMA Mapping. | |
2010 | */ | |
2011 | void * sba_get_iommu(struct parisc_device *pci_hba) | |
2012 | { | |
2013 | struct parisc_device *sba_dev = parisc_parent(pci_hba); | |
d18dbfa7 | 2014 | struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); |
1da177e4 LT |
2015 | char t = sba_dev->id.hw_type; |
2016 | int iocnum = (pci_hba->hw_path >> 3); /* rope # */ | |
2017 | ||
2018 | WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); | |
2019 | ||
2020 | return &(sba->ioc[iocnum]); | |
2021 | } | |
2022 | ||
2023 | ||
2024 | /** | |
2025 | * sba_directed_lmmio - return first directed LMMIO range routed to rope | |
226b8ab8 | 2026 | * @pci_hba: The parisc device. |
1da177e4 LT |
2027 | * @r: resource PCI host controller wants start/end fields assigned. |
2028 | * | |
2029 | * For the given parisc PCI controller, determine if any direct ranges | |
2030 | * are routed down the corresponding rope. | |
2031 | */ | |
2032 | void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) | |
2033 | { | |
2034 | struct parisc_device *sba_dev = parisc_parent(pci_hba); | |
d18dbfa7 | 2035 | struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); |
1da177e4 LT |
2036 | char t = sba_dev->id.hw_type; |
2037 | int i; | |
2038 | int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ | |
2039 | ||
b7494554 | 2040 | BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); |
1da177e4 LT |
2041 | |
2042 | r->start = r->end = 0; | |
2043 | ||
2044 | /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ | |
2045 | for (i=0; i<4; i++) { | |
2046 | int base, size; | |
2047 | void __iomem *reg = sba->sba_hpa + i*0x18; | |
2048 | ||
2049 | base = READ_REG32(reg + LMMIO_DIRECT0_BASE); | |
2050 | if ((base & 1) == 0) | |
2051 | continue; /* not enabled */ | |
2052 | ||
2053 | size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); | |
2054 | ||
2055 | if ((size & (ROPES_PER_IOC-1)) != rope) | |
2056 | continue; /* directed down different rope */ | |
2057 | ||
2058 | r->start = (base & ~1UL) | PCI_F_EXTEND; | |
2059 | size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); | |
2060 | r->end = r->start + size; | |
ca0844e3 | 2061 | r->flags = IORESOURCE_MEM; |
1da177e4 LT |
2062 | } |
2063 | } | |
2064 | ||
2065 | ||
2066 | /** | |
2067 | * sba_distributed_lmmio - return portion of distributed LMMIO range | |
226b8ab8 | 2068 | * @pci_hba: The parisc device. |
1da177e4 LT |
2069 | * @r: resource PCI host controller wants start/end fields assigned. |
2070 | * | |
2071 | * For the given parisc PCI controller, return portion of distributed LMMIO | |
2072 | * range. The distributed LMMIO is always present and it's just a question | |
2073 | * of the base address and size of the range. | |
2074 | */ | |
2075 | void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) | |
2076 | { | |
2077 | struct parisc_device *sba_dev = parisc_parent(pci_hba); | |
d18dbfa7 | 2078 | struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); |
1da177e4 LT |
2079 | char t = sba_dev->id.hw_type; |
2080 | int base, size; | |
2081 | int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ | |
2082 | ||
b7494554 | 2083 | BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); |
1da177e4 LT |
2084 | |
2085 | r->start = r->end = 0; | |
2086 | ||
2087 | base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); | |
2088 | if ((base & 1) == 0) { | |
2089 | BUG(); /* Gah! Distr Range wasn't enabled! */ | |
2090 | return; | |
2091 | } | |
2092 | ||
2093 | r->start = (base & ~1UL) | PCI_F_EXTEND; | |
2094 | ||
2095 | size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; | |
2096 | r->start += rope * (size + 1); /* adjust base for this rope */ | |
2097 | r->end = r->start + size; | |
ca0844e3 | 2098 | r->flags = IORESOURCE_MEM; |
1da177e4 | 2099 | } |