Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | ** ccio-dma.c: | |
3 | ** DMA management routines for first generation cache-coherent machines. | |
4 | ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. | |
5 | ** | |
6 | ** (c) Copyright 2000 Grant Grundler | |
7 | ** (c) Copyright 2000 Ryan Bradetich | |
8 | ** (c) Copyright 2000 Hewlett-Packard Company | |
9 | ** | |
10 | ** This program is free software; you can redistribute it and/or modify | |
11 | ** it under the terms of the GNU General Public License as published by | |
12 | ** the Free Software Foundation; either version 2 of the License, or | |
13 | ** (at your option) any later version. | |
14 | ** | |
15 | ** | |
16 | ** "Real Mode" operation refers to U2/Uturn chip operation. | |
17 | ** U2/Uturn were designed to perform coherency checks w/o using | |
18 | ** the I/O MMU - basically what x86 does. | |
19 | ** | |
20 | ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: | |
21 | ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc | |
22 | ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c | |
23 | ** | |
24 | ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. | |
25 | ** | |
26 | ** Drawbacks of using Real Mode are: | |
27 | ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). | |
28 | ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. | |
29 | ** o Ability to do scatter/gather in HW is lost. | |
30 | ** o Doesn't work under PCX-U/U+ machines since they didn't follow | |
31 | ** the coherency design originally worked out. Only PCX-W does. | |
32 | */ | |
33 | ||
1da177e4 | 34 | #include <linux/types.h> |
3cb1d958 | 35 | #include <linux/kernel.h> |
1da177e4 LT |
36 | #include <linux/init.h> |
37 | #include <linux/mm.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/string.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/reboot.h> | |
f823bcae KM |
43 | #include <linux/proc_fs.h> |
44 | #include <linux/seq_file.h> | |
b61e8f48 | 45 | #include <linux/scatterlist.h> |
46663448 | 46 | #include <linux/iommu-helper.h> |
1da177e4 LT |
47 | |
48 | #include <asm/byteorder.h> | |
49 | #include <asm/cache.h> /* for L1_CACHE_BYTES */ | |
50 | #include <asm/uaccess.h> | |
51 | #include <asm/page.h> | |
52 | #include <asm/dma.h> | |
53 | #include <asm/io.h> | |
54 | #include <asm/hardware.h> /* for register_module() */ | |
55 | #include <asm/parisc-device.h> | |
56 | ||
57 | /* | |
58 | ** Choose "ccio" since that's what HP-UX calls it. | |
59 | ** Make it easier for folks to migrate from one to the other :^) | |
60 | */ | |
61 | #define MODULE_NAME "ccio" | |
62 | ||
63 | #undef DEBUG_CCIO_RES | |
64 | #undef DEBUG_CCIO_RUN | |
65 | #undef DEBUG_CCIO_INIT | |
66 | #undef DEBUG_CCIO_RUN_SG | |
67 | ||
68 | #ifdef CONFIG_PROC_FS | |
69 | /* | |
70 | * CCIO_SEARCH_TIME can help measure how fast the bitmap search is. | |
71 | * impacts performance though - ditch it if you don't use it. | |
72 | */ | |
73 | #define CCIO_SEARCH_TIME | |
74 | #undef CCIO_MAP_STATS | |
75 | #else | |
76 | #undef CCIO_SEARCH_TIME | |
77 | #undef CCIO_MAP_STATS | |
78 | #endif | |
79 | ||
80 | #include <linux/proc_fs.h> | |
81 | #include <asm/runway.h> /* for proc_runway_root */ | |
82 | ||
83 | #ifdef DEBUG_CCIO_INIT | |
84 | #define DBG_INIT(x...) printk(x) | |
85 | #else | |
86 | #define DBG_INIT(x...) | |
87 | #endif | |
88 | ||
89 | #ifdef DEBUG_CCIO_RUN | |
90 | #define DBG_RUN(x...) printk(x) | |
91 | #else | |
92 | #define DBG_RUN(x...) | |
93 | #endif | |
94 | ||
95 | #ifdef DEBUG_CCIO_RES | |
96 | #define DBG_RES(x...) printk(x) | |
97 | #else | |
98 | #define DBG_RES(x...) | |
99 | #endif | |
100 | ||
101 | #ifdef DEBUG_CCIO_RUN_SG | |
102 | #define DBG_RUN_SG(x...) printk(x) | |
103 | #else | |
104 | #define DBG_RUN_SG(x...) | |
105 | #endif | |
106 | ||
86a61ee9 GG |
107 | #define CCIO_INLINE inline |
108 | #define WRITE_U32(value, addr) __raw_writel(value, addr) | |
109 | #define READ_U32(addr) __raw_readl(addr) | |
1da177e4 LT |
110 | |
111 | #define U2_IOA_RUNWAY 0x580 | |
112 | #define U2_BC_GSC 0x501 | |
113 | #define UTURN_IOA_RUNWAY 0x581 | |
114 | #define UTURN_BC_GSC 0x502 | |
115 | ||
116 | #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ | |
117 | #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ | |
118 | #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ | |
119 | ||
120 | struct ioa_registers { | |
121 | /* Runway Supervisory Set */ | |
86a61ee9 GG |
122 | int32_t unused1[12]; |
123 | uint32_t io_command; /* Offset 12 */ | |
124 | uint32_t io_status; /* Offset 13 */ | |
125 | uint32_t io_control; /* Offset 14 */ | |
126 | int32_t unused2[1]; | |
1da177e4 LT |
127 | |
128 | /* Runway Auxiliary Register Set */ | |
86a61ee9 GG |
129 | uint32_t io_err_resp; /* Offset 0 */ |
130 | uint32_t io_err_info; /* Offset 1 */ | |
131 | uint32_t io_err_req; /* Offset 2 */ | |
132 | uint32_t io_err_resp_hi; /* Offset 3 */ | |
133 | uint32_t io_tlb_entry_m; /* Offset 4 */ | |
134 | uint32_t io_tlb_entry_l; /* Offset 5 */ | |
135 | uint32_t unused3[1]; | |
136 | uint32_t io_pdir_base; /* Offset 7 */ | |
137 | uint32_t io_io_low_hv; /* Offset 8 */ | |
138 | uint32_t io_io_high_hv; /* Offset 9 */ | |
139 | uint32_t unused4[1]; | |
140 | uint32_t io_chain_id_mask; /* Offset 11 */ | |
141 | uint32_t unused5[2]; | |
142 | uint32_t io_io_low; /* Offset 14 */ | |
143 | uint32_t io_io_high; /* Offset 15 */ | |
1da177e4 LT |
144 | }; |
145 | ||
146 | /* | |
147 | ** IOA Registers | |
148 | ** ------------- | |
149 | ** | |
150 | ** Runway IO_CONTROL Register (+0x38) | |
151 | ** | |
152 | ** The Runway IO_CONTROL register controls the forwarding of transactions. | |
153 | ** | |
154 | ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | | |
155 | ** | HV | TLB | reserved | HV | mode | reserved | | |
156 | ** | |
157 | ** o mode field indicates the address translation of transactions | |
158 | ** forwarded from Runway to GSC+: | |
159 | ** Mode Name Value Definition | |
160 | ** Off (default) 0 Opaque to matching addresses. | |
161 | ** Include 1 Transparent for matching addresses. | |
162 | ** Peek 3 Map matching addresses. | |
163 | ** | |
164 | ** + "Off" mode: Runway transactions which match the I/O range | |
165 | ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. | |
166 | ** + "Include" mode: all addresses within the I/O range specified | |
167 | ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently | |
168 | ** forwarded. This is the I/O Adapter's normal operating mode. | |
169 | ** + "Peek" mode: used during system configuration to initialize the | |
170 | ** GSC+ bus. Runway Write_Shorts in the address range specified by | |
171 | ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter | |
172 | ** *AND* the GSC+ address is remapped to the Broadcast Physical | |
173 | ** Address space by setting the 14 high order address bits of the | |
174 | ** 32 bit GSC+ address to ones. | |
175 | ** | |
176 | ** o TLB field affects transactions which are forwarded from GSC+ to Runway. | |
177 | ** "Real" mode is the poweron default. | |
178 | ** | |
179 | ** TLB Mode Value Description | |
180 | ** Real 0 No TLB translation. Address is directly mapped and the | |
181 | ** virtual address is composed of selected physical bits. | |
182 | ** Error 1 Software fills the TLB manually. | |
183 | ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). | |
184 | ** | |
185 | ** | |
186 | ** IO_IO_LOW_HV +0x60 (HV dependent) | |
187 | ** IO_IO_HIGH_HV +0x64 (HV dependent) | |
188 | ** IO_IO_LOW +0x78 (Architected register) | |
189 | ** IO_IO_HIGH +0x7c (Architected register) | |
190 | ** | |
191 | ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the | |
192 | ** I/O Adapter address space, respectively. | |
193 | ** | |
194 | ** 0 ... 7 | 8 ... 15 | 16 ... 31 | | |
195 | ** 11111111 | 11111111 | address | | |
196 | ** | |
197 | ** Each LOW/HIGH pair describes a disjoint address space region. | |
198 | ** (2 per GSC+ port). Each incoming Runway transaction address is compared | |
199 | ** with both sets of LOW/HIGH registers. If the address is in the range | |
200 | ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction | |
201 | ** for forwarded to the respective GSC+ bus. | |
202 | ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying | |
203 | ** an address space region. | |
204 | ** | |
205 | ** In order for a Runway address to reside within GSC+ extended address space: | |
206 | ** Runway Address [0:7] must identically compare to 8'b11111111 | |
207 | ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] | |
208 | ** Runway Address [12:23] must be greater than or equal to | |
209 | ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. | |
210 | ** Runway Address [24:39] is not used in the comparison. | |
211 | ** | |
212 | ** When the Runway transaction is forwarded to GSC+, the GSC+ address is | |
213 | ** as follows: | |
214 | ** GSC+ Address[0:3] 4'b1111 | |
215 | ** GSC+ Address[4:29] Runway Address[12:37] | |
216 | ** GSC+ Address[30:31] 2'b00 | |
217 | ** | |
218 | ** All 4 Low/High registers must be initialized (by PDC) once the lower bus | |
219 | ** is interrogated and address space is defined. The operating system will | |
220 | ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following | |
221 | ** the PDC initialization. However, the hardware version dependent IO_IO_LOW | |
222 | ** and IO_IO_HIGH registers should not be subsequently altered by the OS. | |
223 | ** | |
224 | ** Writes to both sets of registers will take effect immediately, bypassing | |
225 | ** the queues, which ensures that subsequent Runway transactions are checked | |
226 | ** against the updated bounds values. However reads are queued, introducing | |
227 | ** the possibility of a read being bypassed by a subsequent write to the same | |
228 | ** register. This sequence can be avoided by having software wait for read | |
229 | ** returns before issuing subsequent writes. | |
230 | */ | |
231 | ||
232 | struct ioc { | |
86a61ee9 | 233 | struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ |
1da177e4 LT |
234 | u8 *res_map; /* resource map, bit == pdir entry */ |
235 | u64 *pdir_base; /* physical base address */ | |
236 | u32 pdir_size; /* bytes, function of IOV Space size */ | |
237 | u32 res_hint; /* next available IOVP - | |
238 | circular search */ | |
239 | u32 res_size; /* size of resource map in bytes */ | |
240 | spinlock_t res_lock; | |
241 | ||
242 | #ifdef CCIO_SEARCH_TIME | |
243 | #define CCIO_SEARCH_SAMPLE 0x100 | |
244 | unsigned long avg_search[CCIO_SEARCH_SAMPLE]; | |
245 | unsigned long avg_idx; /* current index into avg_search */ | |
246 | #endif | |
247 | #ifdef CCIO_MAP_STATS | |
248 | unsigned long used_pages; | |
249 | unsigned long msingle_calls; | |
250 | unsigned long msingle_pages; | |
251 | unsigned long msg_calls; | |
252 | unsigned long msg_pages; | |
253 | unsigned long usingle_calls; | |
254 | unsigned long usingle_pages; | |
255 | unsigned long usg_calls; | |
256 | unsigned long usg_pages; | |
257 | #endif | |
258 | unsigned short cujo20_bug; | |
259 | ||
260 | /* STUFF We don't need in performance path */ | |
261 | u32 chainid_shift; /* specify bit location of chain_id */ | |
262 | struct ioc *next; /* Linked list of discovered iocs */ | |
263 | const char *name; /* device name from firmware */ | |
264 | unsigned int hw_path; /* the hardware path this ioc is associatd with */ | |
265 | struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ | |
266 | struct resource mmio_region[2]; /* The "routed" MMIO regions */ | |
267 | }; | |
268 | ||
269 | static struct ioc *ioc_list; | |
270 | static int ioc_count; | |
271 | ||
272 | /************************************************************** | |
273 | * | |
274 | * I/O Pdir Resource Management | |
275 | * | |
276 | * Bits set in the resource map are in use. | |
277 | * Each bit can represent a number of pages. | |
278 | * LSbs represent lower addresses (IOVA's). | |
279 | * | |
280 | * This was was copied from sba_iommu.c. Don't try to unify | |
281 | * the two resource managers unless a way to have different | |
282 | * allocation policies is also adjusted. We'd like to avoid | |
283 | * I/O TLB thrashing by having resource allocation policy | |
284 | * match the I/O TLB replacement policy. | |
285 | * | |
286 | ***************************************************************/ | |
287 | #define IOVP_SIZE PAGE_SIZE | |
288 | #define IOVP_SHIFT PAGE_SHIFT | |
289 | #define IOVP_MASK PAGE_MASK | |
290 | ||
291 | /* Convert from IOVP to IOVA and vice versa. */ | |
292 | #define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) | |
293 | #define CCIO_IOVP(iova) ((iova) & IOVP_MASK) | |
294 | ||
295 | #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) | |
296 | #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) | |
297 | #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) | |
1da177e4 LT |
298 | |
299 | /* | |
300 | ** Don't worry about the 150% average search length on a miss. | |
301 | ** If the search wraps around, and passes the res_hint, it will | |
302 | ** cause the kernel to panic anyhow. | |
303 | */ | |
304 | #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ | |
305 | for(; res_ptr < res_end; ++res_ptr) { \ | |
46663448 FT |
306 | int ret;\ |
307 | unsigned int idx;\ | |
308 | idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ | |
309 | ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\ | |
310 | if ((0 == (*res_ptr & mask)) && !ret) { \ | |
311 | *res_ptr |= mask; \ | |
312 | res_idx = idx;\ | |
313 | ioc->res_hint = res_idx + (size >> 3); \ | |
314 | goto resource_found; \ | |
315 | } \ | |
316 | } | |
1da177e4 LT |
317 | |
318 | #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ | |
319 | u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ | |
320 | u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ | |
321 | CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ | |
322 | res_ptr = (u##size *)&(ioc)->res_map[0]; \ | |
323 | CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); | |
324 | ||
325 | /* | |
326 | ** Find available bit in this ioa's resource map. | |
327 | ** Use a "circular" search: | |
328 | ** o Most IOVA's are "temporary" - avg search time should be small. | |
329 | ** o keep a history of what happened for debugging | |
330 | ** o KISS. | |
331 | ** | |
332 | ** Perf optimizations: | |
333 | ** o search for log2(size) bits at a time. | |
334 | ** o search for available resource bits using byte/word/whatever. | |
335 | ** o use different search for "large" (eg > 4 pages) or "very large" | |
336 | ** (eg > 16 pages) mappings. | |
337 | */ | |
338 | ||
339 | /** | |
340 | * ccio_alloc_range - Allocate pages in the ioc's resource map. | |
341 | * @ioc: The I/O Controller. | |
342 | * @pages_needed: The requested number of pages to be mapped into the | |
343 | * I/O Pdir... | |
344 | * | |
345 | * This function searches the resource map of the ioc to locate a range | |
346 | * of available pages for the requested size. | |
347 | */ | |
348 | static int | |
7c8cda62 | 349 | ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size) |
1da177e4 LT |
350 | { |
351 | unsigned int pages_needed = size >> IOVP_SHIFT; | |
352 | unsigned int res_idx; | |
46663448 | 353 | unsigned long boundary_size; |
1da177e4 LT |
354 | #ifdef CCIO_SEARCH_TIME |
355 | unsigned long cr_start = mfctl(16); | |
356 | #endif | |
357 | ||
358 | BUG_ON(pages_needed == 0); | |
359 | BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); | |
360 | ||
361 | DBG_RES("%s() size: %d pages_needed %d\n", | |
362 | __FUNCTION__, size, pages_needed); | |
363 | ||
364 | /* | |
365 | ** "seek and ye shall find"...praying never hurts either... | |
366 | ** ggg sacrifices another 710 to the computer gods. | |
367 | */ | |
368 | ||
4a0d3f3a FT |
369 | boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, |
370 | 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; | |
46663448 | 371 | |
1da177e4 LT |
372 | if (pages_needed <= 8) { |
373 | /* | |
374 | * LAN traffic will not thrash the TLB IFF the same NIC | |
4f63ba17 | 375 | * uses 8 adjacent pages to map separate payload data. |
1da177e4 LT |
376 | * ie the same byte in the resource bit map. |
377 | */ | |
378 | #if 0 | |
379 | /* FIXME: bit search should shift it's way through | |
380 | * an unsigned long - not byte at a time. As it is now, | |
381 | * we effectively allocate this byte to this mapping. | |
382 | */ | |
383 | unsigned long mask = ~(~0UL >> pages_needed); | |
384 | CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8); | |
385 | #else | |
386 | CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); | |
387 | #endif | |
388 | } else if (pages_needed <= 16) { | |
389 | CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); | |
390 | } else if (pages_needed <= 32) { | |
391 | CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); | |
392 | #ifdef __LP64__ | |
393 | } else if (pages_needed <= 64) { | |
394 | CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); | |
395 | #endif | |
396 | } else { | |
397 | panic("%s: %s() Too many pages to map. pages_needed: %u\n", | |
398 | __FILE__, __FUNCTION__, pages_needed); | |
399 | } | |
400 | ||
401 | panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, | |
402 | __FUNCTION__); | |
403 | ||
404 | resource_found: | |
405 | ||
406 | DBG_RES("%s() res_idx %d res_hint: %d\n", | |
407 | __FUNCTION__, res_idx, ioc->res_hint); | |
408 | ||
409 | #ifdef CCIO_SEARCH_TIME | |
410 | { | |
411 | unsigned long cr_end = mfctl(16); | |
412 | unsigned long tmp = cr_end - cr_start; | |
413 | /* check for roll over */ | |
414 | cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); | |
415 | } | |
416 | ioc->avg_search[ioc->avg_idx++] = cr_start; | |
417 | ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; | |
418 | #endif | |
419 | #ifdef CCIO_MAP_STATS | |
420 | ioc->used_pages += pages_needed; | |
421 | #endif | |
422 | /* | |
423 | ** return the bit address. | |
424 | */ | |
425 | return res_idx << 3; | |
426 | } | |
427 | ||
428 | #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ | |
429 | u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ | |
430 | BUG_ON((*res_ptr & mask) != mask); \ | |
431 | *res_ptr &= ~(mask); | |
432 | ||
433 | /** | |
434 | * ccio_free_range - Free pages from the ioc's resource map. | |
435 | * @ioc: The I/O Controller. | |
436 | * @iova: The I/O Virtual Address. | |
437 | * @pages_mapped: The requested number of pages to be freed from the | |
438 | * I/O Pdir. | |
439 | * | |
440 | * This function frees the resouces allocated for the iova. | |
441 | */ | |
442 | static void | |
443 | ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) | |
444 | { | |
445 | unsigned long iovp = CCIO_IOVP(iova); | |
446 | unsigned int res_idx = PDIR_INDEX(iovp) >> 3; | |
447 | ||
448 | BUG_ON(pages_mapped == 0); | |
449 | BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); | |
450 | BUG_ON(pages_mapped > BITS_PER_LONG); | |
451 | ||
452 | DBG_RES("%s(): res_idx: %d pages_mapped %d\n", | |
453 | __FUNCTION__, res_idx, pages_mapped); | |
454 | ||
455 | #ifdef CCIO_MAP_STATS | |
456 | ioc->used_pages -= pages_mapped; | |
457 | #endif | |
458 | ||
459 | if(pages_mapped <= 8) { | |
460 | #if 0 | |
461 | /* see matching comments in alloc_range */ | |
462 | unsigned long mask = ~(~0UL >> pages_mapped); | |
463 | CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8); | |
464 | #else | |
465 | CCIO_FREE_MAPPINGS(ioc, res_idx, 0xff, 8); | |
466 | #endif | |
467 | } else if(pages_mapped <= 16) { | |
468 | CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffff, 16); | |
469 | } else if(pages_mapped <= 32) { | |
470 | CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); | |
471 | #ifdef __LP64__ | |
472 | } else if(pages_mapped <= 64) { | |
473 | CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); | |
474 | #endif | |
475 | } else { | |
476 | panic("%s:%s() Too many pages to unmap.\n", __FILE__, | |
477 | __FUNCTION__); | |
478 | } | |
479 | } | |
480 | ||
481 | /**************************************************************** | |
482 | ** | |
483 | ** CCIO dma_ops support routines | |
484 | ** | |
485 | *****************************************************************/ | |
486 | ||
487 | typedef unsigned long space_t; | |
488 | #define KERNEL_SPACE 0 | |
489 | ||
490 | /* | |
491 | ** DMA "Page Type" and Hints | |
492 | ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be | |
493 | ** set for subcacheline DMA transfers since we don't want to damage the | |
494 | ** other part of a cacheline. | |
495 | ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent(). | |
496 | ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming" | |
497 | ** data can avoid this if the mapping covers full cache lines. | |
498 | ** o STOP_MOST is needed for atomicity across cachelines. | |
0779bf2d | 499 | ** Apparently only "some EISA devices" need this. |
1da177e4 LT |
500 | ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs |
501 | ** to use this hint iff the EISA devices needs this feature. | |
502 | ** According to the U2 ERS, STOP_MOST enabled pages hurt performance. | |
503 | ** o PREFETCH should *not* be set for cases like Multiple PCI devices | |
504 | ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC | |
505 | ** device can be fetched and multiply DMA streams will thrash the | |
506 | ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules | |
507 | ** and Invalidation of Prefetch Entries". | |
508 | ** | |
509 | ** FIXME: the default hints need to be per GSC device - not global. | |
510 | ** | |
511 | ** HP-UX dorks: linux device driver programming model is totally different | |
512 | ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers | |
513 | ** do special things to work on non-coherent platforms...linux has to | |
514 | ** be much more careful with this. | |
515 | */ | |
516 | #define IOPDIR_VALID 0x01UL | |
517 | #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ | |
518 | #ifdef CONFIG_EISA | |
519 | #define HINT_STOP_MOST 0x04UL /* LSL support */ | |
520 | #else | |
521 | #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ | |
522 | #endif | |
523 | #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ | |
524 | #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ | |
525 | ||
526 | ||
527 | /* | |
528 | ** Use direction (ie PCI_DMA_TODEVICE) to pick hint. | |
529 | ** ccio_alloc_consistent() depends on this to get SAFE_DMA | |
530 | ** when it passes in BIDIRECTIONAL flag. | |
531 | */ | |
532 | static u32 hint_lookup[] = { | |
533 | [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, | |
534 | [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, | |
535 | [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, | |
536 | }; | |
537 | ||
538 | /** | |
539 | * ccio_io_pdir_entry - Initialize an I/O Pdir. | |
540 | * @pdir_ptr: A pointer into I/O Pdir. | |
541 | * @sid: The Space Identifier. | |
542 | * @vba: The virtual address. | |
543 | * @hints: The DMA Hint. | |
544 | * | |
545 | * Given a virtual address (vba, arg2) and space id, (sid, arg1), | |
546 | * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir | |
547 | * entry consists of 8 bytes as shown below (MSB == bit 0): | |
548 | * | |
549 | * | |
550 | * WORD 0: | |
551 | * +------+----------------+-----------------------------------------------+ | |
552 | * | Phys | Virtual Index | Phys | | |
553 | * | 0:3 | 0:11 | 4:19 | | |
554 | * |4 bits| 12 bits | 16 bits | | |
555 | * +------+----------------+-----------------------------------------------+ | |
556 | * WORD 1: | |
557 | * +-----------------------+-----------------------------------------------+ | |
558 | * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | | |
559 | * | 20:39 | | Enable |Enable | |Enable|DMA | | | |
560 | * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | | |
561 | * +-----------------------+-----------------------------------------------+ | |
562 | * | |
563 | * The virtual index field is filled with the results of the LCI | |
564 | * (Load Coherence Index) instruction. The 8 bits used for the virtual | |
565 | * index are bits 12:19 of the value returned by LCI. | |
566 | */ | |
567 | void CCIO_INLINE | |
568 | ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, | |
569 | unsigned long hints) | |
570 | { | |
571 | register unsigned long pa; | |
572 | register unsigned long ci; /* coherent index */ | |
573 | ||
574 | /* We currently only support kernel addresses */ | |
575 | BUG_ON(sid != KERNEL_SPACE); | |
576 | ||
577 | mtsp(sid,1); | |
578 | ||
579 | /* | |
580 | ** WORD 1 - low order word | |
581 | ** "hints" parm includes the VALID bit! | |
582 | ** "dep" clobbers the physical address offset bits as well. | |
583 | */ | |
584 | pa = virt_to_phys(vba); | |
585 | asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); | |
586 | ((u32 *)pdir_ptr)[1] = (u32) pa; | |
587 | ||
588 | /* | |
589 | ** WORD 0 - high order word | |
590 | */ | |
591 | ||
592 | #ifdef __LP64__ | |
593 | /* | |
594 | ** get bits 12:15 of physical address | |
595 | ** shift bits 16:31 of physical address | |
596 | ** and deposit them | |
597 | */ | |
598 | asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); | |
599 | asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); | |
600 | asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); | |
601 | #else | |
602 | pa = 0; | |
603 | #endif | |
604 | /* | |
605 | ** get CPU coherency index bits | |
606 | ** Grab virtual index [0:11] | |
607 | ** Deposit virt_idx bits into I/O PDIR word | |
608 | */ | |
86a61ee9 | 609 | asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); |
1da177e4 LT |
610 | asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); |
611 | asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); | |
612 | ||
613 | ((u32 *)pdir_ptr)[0] = (u32) pa; | |
614 | ||
615 | ||
616 | /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) | |
617 | ** PCX-U/U+ do. (eg C200/C240) | |
618 | ** PCX-T'? Don't know. (eg C110 or similar K-class) | |
619 | ** | |
620 | ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". | |
621 | ** Hopefully we can patch (NOP) these out at boot time somehow. | |
622 | ** | |
623 | ** "Since PCX-U employs an offset hash that is incompatible with | |
624 | ** the real mode coherence index generation of U2, the PDIR entry | |
625 | ** must be flushed to memory to retain coherence." | |
626 | */ | |
86a61ee9 | 627 | asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); |
1da177e4 LT |
628 | asm volatile("sync"); |
629 | } | |
630 | ||
631 | /** | |
632 | * ccio_clear_io_tlb - Remove stale entries from the I/O TLB. | |
633 | * @ioc: The I/O Controller. | |
634 | * @iovp: The I/O Virtual Page. | |
635 | * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. | |
636 | * | |
637 | * Purge invalid I/O PDIR entries from the I/O TLB. | |
638 | * | |
639 | * FIXME: Can we change the byte_cnt to pages_mapped? | |
640 | */ | |
641 | static CCIO_INLINE void | |
642 | ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) | |
643 | { | |
644 | u32 chain_size = 1 << ioc->chainid_shift; | |
645 | ||
646 | iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ | |
647 | byte_cnt += chain_size; | |
648 | ||
649 | while(byte_cnt > chain_size) { | |
86a61ee9 | 650 | WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); |
1da177e4 LT |
651 | iovp += chain_size; |
652 | byte_cnt -= chain_size; | |
653 | } | |
654 | } | |
655 | ||
656 | /** | |
657 | * ccio_mark_invalid - Mark the I/O Pdir entries invalid. | |
658 | * @ioc: The I/O Controller. | |
659 | * @iova: The I/O Virtual Address. | |
660 | * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. | |
661 | * | |
662 | * Mark the I/O Pdir entries invalid and blow away the corresponding I/O | |
663 | * TLB entries. | |
664 | * | |
665 | * FIXME: at some threshhold it might be "cheaper" to just blow | |
666 | * away the entire I/O TLB instead of individual entries. | |
667 | * | |
668 | * FIXME: Uturn has 256 TLB entries. We don't need to purge every | |
669 | * PDIR entry - just once for each possible TLB entry. | |
670 | * (We do need to maker I/O PDIR entries invalid regardless). | |
671 | * | |
672 | * FIXME: Can we change byte_cnt to pages_mapped? | |
673 | */ | |
674 | static CCIO_INLINE void | |
675 | ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) | |
676 | { | |
677 | u32 iovp = (u32)CCIO_IOVP(iova); | |
678 | size_t saved_byte_cnt; | |
679 | ||
680 | /* round up to nearest page size */ | |
3cb1d958 | 681 | saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); |
1da177e4 LT |
682 | |
683 | while(byte_cnt > 0) { | |
684 | /* invalidate one page at a time */ | |
685 | unsigned int idx = PDIR_INDEX(iovp); | |
686 | char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); | |
687 | ||
688 | BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); | |
689 | pdir_ptr[7] = 0; /* clear only VALID bit */ | |
690 | /* | |
691 | ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) | |
692 | ** PCX-U/U+ do. (eg C200/C240) | |
693 | ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". | |
694 | ** | |
695 | ** Hopefully someone figures out how to patch (NOP) the | |
696 | ** FDC/SYNC out at boot time. | |
697 | */ | |
86a61ee9 | 698 | asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7])); |
1da177e4 LT |
699 | |
700 | iovp += IOVP_SIZE; | |
701 | byte_cnt -= IOVP_SIZE; | |
702 | } | |
703 | ||
704 | asm volatile("sync"); | |
705 | ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); | |
706 | } | |
707 | ||
708 | /**************************************************************** | |
709 | ** | |
710 | ** CCIO dma_ops | |
711 | ** | |
712 | *****************************************************************/ | |
713 | ||
714 | /** | |
715 | * ccio_dma_supported - Verify the IOMMU supports the DMA address range. | |
716 | * @dev: The PCI device. | |
717 | * @mask: A bit mask describing the DMA address range of the device. | |
718 | * | |
719 | * This function implements the pci_dma_supported function. | |
720 | */ | |
721 | static int | |
722 | ccio_dma_supported(struct device *dev, u64 mask) | |
723 | { | |
724 | if(dev == NULL) { | |
725 | printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); | |
726 | BUG(); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | /* only support 32-bit devices (ie PCI/GSC) */ | |
731 | return (int)(mask == 0xffffffffUL); | |
732 | } | |
733 | ||
734 | /** | |
735 | * ccio_map_single - Map an address range into the IOMMU. | |
736 | * @dev: The PCI device. | |
737 | * @addr: The start address of the DMA region. | |
738 | * @size: The length of the DMA region. | |
739 | * @direction: The direction of the DMA transaction (to/from device). | |
740 | * | |
741 | * This function implements the pci_map_single function. | |
742 | */ | |
743 | static dma_addr_t | |
744 | ccio_map_single(struct device *dev, void *addr, size_t size, | |
745 | enum dma_data_direction direction) | |
746 | { | |
747 | int idx; | |
748 | struct ioc *ioc; | |
749 | unsigned long flags; | |
750 | dma_addr_t iovp; | |
751 | dma_addr_t offset; | |
752 | u64 *pdir_start; | |
753 | unsigned long hint = hint_lookup[(int)direction]; | |
754 | ||
755 | BUG_ON(!dev); | |
756 | ioc = GET_IOC(dev); | |
757 | ||
758 | BUG_ON(size <= 0); | |
759 | ||
760 | /* save offset bits */ | |
761 | offset = ((unsigned long) addr) & ~IOVP_MASK; | |
762 | ||
763 | /* round up to nearest IOVP_SIZE */ | |
3cb1d958 | 764 | size = ALIGN(size + offset, IOVP_SIZE); |
1da177e4 LT |
765 | spin_lock_irqsave(&ioc->res_lock, flags); |
766 | ||
767 | #ifdef CCIO_MAP_STATS | |
768 | ioc->msingle_calls++; | |
769 | ioc->msingle_pages += size >> IOVP_SHIFT; | |
770 | #endif | |
771 | ||
7c8cda62 | 772 | idx = ccio_alloc_range(ioc, dev, size); |
1da177e4 LT |
773 | iovp = (dma_addr_t)MKIOVP(idx); |
774 | ||
775 | pdir_start = &(ioc->pdir_base[idx]); | |
776 | ||
777 | DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", | |
778 | __FUNCTION__, addr, (long)iovp | offset, size); | |
779 | ||
780 | /* If not cacheline aligned, force SAFE_DMA on the whole mess */ | |
781 | if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) | |
782 | hint |= HINT_SAFE_DMA; | |
783 | ||
784 | while(size > 0) { | |
785 | ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); | |
786 | ||
787 | DBG_RUN(" pdir %p %08x%08x\n", | |
788 | pdir_start, | |
789 | (u32) (((u32 *) pdir_start)[0]), | |
790 | (u32) (((u32 *) pdir_start)[1])); | |
791 | ++pdir_start; | |
792 | addr += IOVP_SIZE; | |
793 | size -= IOVP_SIZE; | |
794 | } | |
795 | ||
796 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
797 | ||
798 | /* form complete address */ | |
799 | return CCIO_IOVA(iovp, offset); | |
800 | } | |
801 | ||
802 | /** | |
803 | * ccio_unmap_single - Unmap an address range from the IOMMU. | |
804 | * @dev: The PCI device. | |
805 | * @addr: The start address of the DMA region. | |
806 | * @size: The length of the DMA region. | |
807 | * @direction: The direction of the DMA transaction (to/from device). | |
808 | * | |
809 | * This function implements the pci_unmap_single function. | |
810 | */ | |
811 | static void | |
812 | ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size, | |
813 | enum dma_data_direction direction) | |
814 | { | |
815 | struct ioc *ioc; | |
816 | unsigned long flags; | |
817 | dma_addr_t offset = iova & ~IOVP_MASK; | |
818 | ||
819 | BUG_ON(!dev); | |
820 | ioc = GET_IOC(dev); | |
821 | ||
822 | DBG_RUN("%s() iovp 0x%lx/%x\n", | |
823 | __FUNCTION__, (long)iova, size); | |
824 | ||
825 | iova ^= offset; /* clear offset bits */ | |
826 | size += offset; | |
3cb1d958 | 827 | size = ALIGN(size, IOVP_SIZE); |
1da177e4 LT |
828 | |
829 | spin_lock_irqsave(&ioc->res_lock, flags); | |
830 | ||
831 | #ifdef CCIO_MAP_STATS | |
832 | ioc->usingle_calls++; | |
833 | ioc->usingle_pages += size >> IOVP_SHIFT; | |
834 | #endif | |
835 | ||
836 | ccio_mark_invalid(ioc, iova, size); | |
837 | ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); | |
838 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
839 | } | |
840 | ||
841 | /** | |
842 | * ccio_alloc_consistent - Allocate a consistent DMA mapping. | |
843 | * @dev: The PCI device. | |
844 | * @size: The length of the DMA region. | |
845 | * @dma_handle: The DMA address handed back to the device (not the cpu). | |
846 | * | |
847 | * This function implements the pci_alloc_consistent function. | |
848 | */ | |
849 | static void * | |
5c1fb41f | 850 | ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) |
1da177e4 LT |
851 | { |
852 | void *ret; | |
853 | #if 0 | |
854 | /* GRANT Need to establish hierarchy for non-PCI devs as well | |
855 | ** and then provide matching gsc_map_xxx() functions for them as well. | |
856 | */ | |
857 | if(!hwdev) { | |
858 | /* only support PCI */ | |
859 | *dma_handle = 0; | |
860 | return 0; | |
861 | } | |
862 | #endif | |
863 | ret = (void *) __get_free_pages(flag, get_order(size)); | |
864 | ||
865 | if (ret) { | |
866 | memset(ret, 0, size); | |
867 | *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); | |
868 | } | |
869 | ||
870 | return ret; | |
871 | } | |
872 | ||
873 | /** | |
874 | * ccio_free_consistent - Free a consistent DMA mapping. | |
875 | * @dev: The PCI device. | |
876 | * @size: The length of the DMA region. | |
877 | * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. | |
878 | * @dma_handle: The device address returned from the ccio_alloc_consistent. | |
879 | * | |
880 | * This function implements the pci_free_consistent function. | |
881 | */ | |
882 | static void | |
883 | ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr, | |
884 | dma_addr_t dma_handle) | |
885 | { | |
886 | ccio_unmap_single(dev, dma_handle, size, 0); | |
887 | free_pages((unsigned long)cpu_addr, get_order(size)); | |
888 | } | |
889 | ||
890 | /* | |
891 | ** Since 0 is a valid pdir_base index value, can't use that | |
892 | ** to determine if a value is valid or not. Use a flag to indicate | |
893 | ** the SG list entry contains a valid pdir index. | |
894 | */ | |
895 | #define PIDE_FLAG 0x80000000UL | |
896 | ||
897 | #ifdef CCIO_MAP_STATS | |
898 | #define IOMMU_MAP_STATS | |
899 | #endif | |
900 | #include "iommu-helpers.h" | |
901 | ||
902 | /** | |
903 | * ccio_map_sg - Map the scatter/gather list into the IOMMU. | |
904 | * @dev: The PCI device. | |
905 | * @sglist: The scatter/gather list to be mapped in the IOMMU. | |
906 | * @nents: The number of entries in the scatter/gather list. | |
907 | * @direction: The direction of the DMA transaction (to/from device). | |
908 | * | |
909 | * This function implements the pci_map_sg function. | |
910 | */ | |
911 | static int | |
912 | ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, | |
913 | enum dma_data_direction direction) | |
914 | { | |
915 | struct ioc *ioc; | |
916 | int coalesced, filled = 0; | |
917 | unsigned long flags; | |
918 | unsigned long hint = hint_lookup[(int)direction]; | |
919 | unsigned long prev_len = 0, current_len = 0; | |
920 | int i; | |
921 | ||
922 | BUG_ON(!dev); | |
923 | ioc = GET_IOC(dev); | |
924 | ||
925 | DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); | |
926 | ||
927 | /* Fast path single entry scatterlists. */ | |
928 | if (nents == 1) { | |
929 | sg_dma_address(sglist) = ccio_map_single(dev, | |
930 | (void *)sg_virt_addr(sglist), sglist->length, | |
931 | direction); | |
932 | sg_dma_len(sglist) = sglist->length; | |
933 | return 1; | |
934 | } | |
935 | ||
936 | for(i = 0; i < nents; i++) | |
937 | prev_len += sglist[i].length; | |
938 | ||
939 | spin_lock_irqsave(&ioc->res_lock, flags); | |
940 | ||
941 | #ifdef CCIO_MAP_STATS | |
942 | ioc->msg_calls++; | |
943 | #endif | |
944 | ||
945 | /* | |
946 | ** First coalesce the chunks and allocate I/O pdir space | |
947 | ** | |
948 | ** If this is one DMA stream, we can properly map using the | |
949 | ** correct virtual address associated with each DMA page. | |
950 | ** w/o this association, we wouldn't have coherent DMA! | |
951 | ** Access to the virtual address is what forces a two pass algorithm. | |
952 | */ | |
d1b51632 | 953 | coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range); |
1da177e4 LT |
954 | |
955 | /* | |
956 | ** Program the I/O Pdir | |
957 | ** | |
958 | ** map the virtual addresses to the I/O Pdir | |
959 | ** o dma_address will contain the pdir index | |
960 | ** o dma_len will contain the number of bytes to map | |
961 | ** o page/offset contain the virtual address. | |
962 | */ | |
963 | filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); | |
964 | ||
965 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
966 | ||
967 | BUG_ON(coalesced != filled); | |
968 | ||
969 | DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); | |
970 | ||
971 | for (i = 0; i < filled; i++) | |
972 | current_len += sg_dma_len(sglist + i); | |
973 | ||
974 | BUG_ON(current_len != prev_len); | |
975 | ||
976 | return filled; | |
977 | } | |
978 | ||
979 | /** | |
980 | * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. | |
981 | * @dev: The PCI device. | |
982 | * @sglist: The scatter/gather list to be unmapped from the IOMMU. | |
983 | * @nents: The number of entries in the scatter/gather list. | |
984 | * @direction: The direction of the DMA transaction (to/from device). | |
985 | * | |
986 | * This function implements the pci_unmap_sg function. | |
987 | */ | |
988 | static void | |
989 | ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, | |
990 | enum dma_data_direction direction) | |
991 | { | |
992 | struct ioc *ioc; | |
993 | ||
994 | BUG_ON(!dev); | |
995 | ioc = GET_IOC(dev); | |
996 | ||
997 | DBG_RUN_SG("%s() START %d entries, %08lx,%x\n", | |
998 | __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); | |
999 | ||
1000 | #ifdef CCIO_MAP_STATS | |
1001 | ioc->usg_calls++; | |
1002 | #endif | |
1003 | ||
1004 | while(sg_dma_len(sglist) && nents--) { | |
1005 | ||
1006 | #ifdef CCIO_MAP_STATS | |
1007 | ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; | |
1008 | #endif | |
1009 | ccio_unmap_single(dev, sg_dma_address(sglist), | |
1010 | sg_dma_len(sglist), direction); | |
1011 | ++sglist; | |
1012 | } | |
1013 | ||
1014 | DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents); | |
1015 | } | |
1016 | ||
1017 | static struct hppa_dma_ops ccio_ops = { | |
1018 | .dma_supported = ccio_dma_supported, | |
1019 | .alloc_consistent = ccio_alloc_consistent, | |
1020 | .alloc_noncoherent = ccio_alloc_consistent, | |
1021 | .free_consistent = ccio_free_consistent, | |
1022 | .map_single = ccio_map_single, | |
1023 | .unmap_single = ccio_unmap_single, | |
1024 | .map_sg = ccio_map_sg, | |
1025 | .unmap_sg = ccio_unmap_sg, | |
1026 | .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */ | |
1027 | .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */ | |
1028 | .dma_sync_sg_for_cpu = NULL, /* ditto */ | |
1029 | .dma_sync_sg_for_device = NULL, /* ditto */ | |
1030 | }; | |
1031 | ||
1032 | #ifdef CONFIG_PROC_FS | |
f823bcae | 1033 | static int ccio_proc_info(struct seq_file *m, void *p) |
1da177e4 | 1034 | { |
f823bcae | 1035 | int len = 0; |
1da177e4 LT |
1036 | struct ioc *ioc = ioc_list; |
1037 | ||
1038 | while (ioc != NULL) { | |
1039 | unsigned int total_pages = ioc->res_size << 3; | |
1040 | unsigned long avg = 0, min, max; | |
f823bcae | 1041 | int j; |
1da177e4 | 1042 | |
f823bcae | 1043 | len += seq_printf(m, "%s\n", ioc->name); |
1da177e4 | 1044 | |
f823bcae KM |
1045 | len += seq_printf(m, "Cujo 2.0 bug : %s\n", |
1046 | (ioc->cujo20_bug ? "yes" : "no")); | |
1da177e4 | 1047 | |
f823bcae KM |
1048 | len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", |
1049 | total_pages * 8, total_pages); | |
1050 | ||
1da177e4 | 1051 | #ifdef CCIO_MAP_STATS |
f823bcae KM |
1052 | len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", |
1053 | total_pages - ioc->used_pages, ioc->used_pages, | |
1054 | (int)(ioc->used_pages * 100 / total_pages)); | |
1da177e4 | 1055 | #endif |
f823bcae KM |
1056 | |
1057 | len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", | |
1058 | ioc->res_size, total_pages); | |
1059 | ||
1da177e4 LT |
1060 | #ifdef CCIO_SEARCH_TIME |
1061 | min = max = ioc->avg_search[0]; | |
1062 | for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { | |
1063 | avg += ioc->avg_search[j]; | |
1064 | if(ioc->avg_search[j] > max) | |
1065 | max = ioc->avg_search[j]; | |
1066 | if(ioc->avg_search[j] < min) | |
1067 | min = ioc->avg_search[j]; | |
1068 | } | |
1069 | avg /= CCIO_SEARCH_SAMPLE; | |
f823bcae KM |
1070 | len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", |
1071 | min, avg, max); | |
1da177e4 LT |
1072 | #endif |
1073 | #ifdef CCIO_MAP_STATS | |
f823bcae KM |
1074 | len += seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", |
1075 | ioc->msingle_calls, ioc->msingle_pages, | |
1076 | (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); | |
1da177e4 LT |
1077 | |
1078 | /* KLUGE - unmap_sg calls unmap_single for each mapped page */ | |
1079 | min = ioc->usingle_calls - ioc->usg_calls; | |
1080 | max = ioc->usingle_pages - ioc->usg_pages; | |
f823bcae KM |
1081 | len += seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", |
1082 | min, max, (int)((max * 1000)/min)); | |
1da177e4 | 1083 | |
f823bcae KM |
1084 | len += seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", |
1085 | ioc->msg_calls, ioc->msg_pages, | |
1086 | (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); | |
1087 | ||
1088 | len += seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", | |
1089 | ioc->usg_calls, ioc->usg_pages, | |
1090 | (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); | |
1da177e4 | 1091 | #endif /* CCIO_MAP_STATS */ |
f823bcae | 1092 | |
1da177e4 LT |
1093 | ioc = ioc->next; |
1094 | } | |
1095 | ||
f823bcae KM |
1096 | return 0; |
1097 | } | |
1098 | ||
1099 | static int ccio_proc_info_open(struct inode *inode, struct file *file) | |
1100 | { | |
1101 | return single_open(file, &ccio_proc_info, NULL); | |
1da177e4 LT |
1102 | } |
1103 | ||
d54b1fdb | 1104 | static const struct file_operations ccio_proc_info_fops = { |
f823bcae KM |
1105 | .owner = THIS_MODULE, |
1106 | .open = ccio_proc_info_open, | |
1107 | .read = seq_read, | |
1108 | .llseek = seq_lseek, | |
1109 | .release = single_release, | |
1110 | }; | |
1111 | ||
1112 | static int ccio_proc_bitmap_info(struct seq_file *m, void *p) | |
1da177e4 | 1113 | { |
f823bcae | 1114 | int len = 0; |
1da177e4 LT |
1115 | struct ioc *ioc = ioc_list; |
1116 | ||
1da177e4 LT |
1117 | while (ioc != NULL) { |
1118 | u32 *res_ptr = (u32 *)ioc->res_map; | |
1119 | int j; | |
1120 | ||
1121 | for (j = 0; j < (ioc->res_size / sizeof(u32)); j++) { | |
1122 | if ((j & 7) == 0) | |
f823bcae KM |
1123 | len += seq_puts(m, "\n "); |
1124 | len += seq_printf(m, "%08x", *res_ptr); | |
1da177e4 LT |
1125 | res_ptr++; |
1126 | } | |
f823bcae | 1127 | len += seq_puts(m, "\n\n"); |
1da177e4 LT |
1128 | ioc = ioc->next; |
1129 | break; /* XXX - remove me */ | |
1130 | } | |
1131 | ||
f823bcae | 1132 | return 0; |
1da177e4 | 1133 | } |
f823bcae KM |
1134 | |
1135 | static int ccio_proc_bitmap_open(struct inode *inode, struct file *file) | |
1136 | { | |
1137 | return single_open(file, &ccio_proc_bitmap_info, NULL); | |
1138 | } | |
1139 | ||
d54b1fdb | 1140 | static const struct file_operations ccio_proc_bitmap_fops = { |
f823bcae KM |
1141 | .owner = THIS_MODULE, |
1142 | .open = ccio_proc_bitmap_open, | |
1143 | .read = seq_read, | |
1144 | .llseek = seq_lseek, | |
1145 | .release = single_release, | |
1146 | }; | |
1da177e4 LT |
1147 | #endif |
1148 | ||
1149 | /** | |
1150 | * ccio_find_ioc - Find the ioc in the ioc_list | |
1151 | * @hw_path: The hardware path of the ioc. | |
1152 | * | |
1153 | * This function searches the ioc_list for an ioc that matches | |
1154 | * the provide hardware path. | |
1155 | */ | |
1156 | static struct ioc * ccio_find_ioc(int hw_path) | |
1157 | { | |
1158 | int i; | |
1159 | struct ioc *ioc; | |
1160 | ||
1161 | ioc = ioc_list; | |
1162 | for (i = 0; i < ioc_count; i++) { | |
1163 | if (ioc->hw_path == hw_path) | |
1164 | return ioc; | |
1165 | ||
1166 | ioc = ioc->next; | |
1167 | } | |
1168 | ||
1169 | return NULL; | |
1170 | } | |
1171 | ||
1172 | /** | |
1173 | * ccio_get_iommu - Find the iommu which controls this device | |
1174 | * @dev: The parisc device. | |
1175 | * | |
1176 | * This function searches through the registered IOMMU's and returns | |
1177 | * the appropriate IOMMU for the device based on its hardware path. | |
1178 | */ | |
1179 | void * ccio_get_iommu(const struct parisc_device *dev) | |
1180 | { | |
1181 | dev = find_pa_parent_type(dev, HPHW_IOA); | |
1182 | if (!dev) | |
1183 | return NULL; | |
1184 | ||
1185 | return ccio_find_ioc(dev->hw_path); | |
1186 | } | |
1187 | ||
1188 | #define CUJO_20_STEP 0x10000000 /* inc upper nibble */ | |
1189 | ||
1190 | /* Cujo 2.0 has a bug which will silently corrupt data being transferred | |
1191 | * to/from certain pages. To avoid this happening, we mark these pages | |
1192 | * as `used', and ensure that nothing will try to allocate from them. | |
1193 | */ | |
1194 | void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) | |
1195 | { | |
1196 | unsigned int idx; | |
1197 | struct parisc_device *dev = parisc_parent(cujo); | |
1198 | struct ioc *ioc = ccio_get_iommu(dev); | |
1199 | u8 *res_ptr; | |
1200 | ||
1201 | ioc->cujo20_bug = 1; | |
1202 | res_ptr = ioc->res_map; | |
1203 | idx = PDIR_INDEX(iovp) >> 3; | |
1204 | ||
1205 | while (idx < ioc->res_size) { | |
1206 | res_ptr[idx] |= 0xff; | |
1207 | idx += PDIR_INDEX(CUJO_20_STEP) >> 3; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | #if 0 | |
1212 | /* GRANT - is this needed for U2 or not? */ | |
1213 | ||
1214 | /* | |
1215 | ** Get the size of the I/O TLB for this I/O MMU. | |
1216 | ** | |
1217 | ** If spa_shift is non-zero (ie probably U2), | |
1218 | ** then calculate the I/O TLB size using spa_shift. | |
1219 | ** | |
1220 | ** Otherwise we are supposed to get the IODC entry point ENTRY TLB | |
1221 | ** and execute it. However, both U2 and Uturn firmware supplies spa_shift. | |
1222 | ** I think only Java (K/D/R-class too?) systems don't do this. | |
1223 | */ | |
1224 | static int | |
1225 | ccio_get_iotlb_size(struct parisc_device *dev) | |
1226 | { | |
1227 | if (dev->spa_shift == 0) { | |
1228 | panic("%s() : Can't determine I/O TLB size.\n", __FUNCTION__); | |
1229 | } | |
1230 | return (1 << dev->spa_shift); | |
1231 | } | |
1232 | #else | |
1233 | ||
1234 | /* Uturn supports 256 TLB entries */ | |
1235 | #define CCIO_CHAINID_SHIFT 8 | |
1236 | #define CCIO_CHAINID_MASK 0xff | |
1237 | #endif /* 0 */ | |
1238 | ||
1239 | /* We *can't* support JAVA (T600). Venture there at your own risk. */ | |
25971f68 | 1240 | static const struct parisc_device_id ccio_tbl[] = { |
1da177e4 LT |
1241 | { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ |
1242 | { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ | |
1243 | { 0, } | |
1244 | }; | |
1245 | ||
1246 | static int ccio_probe(struct parisc_device *dev); | |
1247 | ||
1248 | static struct parisc_driver ccio_driver = { | |
bdad1f83 | 1249 | .name = "ccio", |
1da177e4 LT |
1250 | .id_table = ccio_tbl, |
1251 | .probe = ccio_probe, | |
1252 | }; | |
1253 | ||
1254 | /** | |
1255 | * ccio_ioc_init - Initalize the I/O Controller | |
1256 | * @ioc: The I/O Controller. | |
1257 | * | |
1258 | * Initalize the I/O Controller which includes setting up the | |
1259 | * I/O Page Directory, the resource map, and initalizing the | |
1260 | * U2/Uturn chip into virtual mode. | |
1261 | */ | |
1262 | static void | |
1263 | ccio_ioc_init(struct ioc *ioc) | |
1264 | { | |
1265 | int i; | |
1266 | unsigned int iov_order; | |
1267 | u32 iova_space_size; | |
1268 | ||
1269 | /* | |
1270 | ** Determine IOVA Space size from memory size. | |
1271 | ** | |
1272 | ** Ideally, PCI drivers would register the maximum number | |
1273 | ** of DMA they can have outstanding for each device they | |
1274 | ** own. Next best thing would be to guess how much DMA | |
1275 | ** can be outstanding based on PCI Class/sub-class. Both | |
1276 | ** methods still require some "extra" to support PCI | |
1277 | ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). | |
1278 | */ | |
1279 | ||
1280 | iova_space_size = (u32) (num_physpages / count_parisc_driver(&ccio_driver)); | |
1281 | ||
1282 | /* limit IOVA space size to 1MB-1GB */ | |
1283 | ||
1284 | if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { | |
1285 | iova_space_size = 1 << (20 - PAGE_SHIFT); | |
1286 | #ifdef __LP64__ | |
1287 | } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { | |
1288 | iova_space_size = 1 << (30 - PAGE_SHIFT); | |
1289 | #endif | |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | ** iova space must be log2() in size. | |
1294 | ** thus, pdir/res_map will also be log2(). | |
1295 | */ | |
1296 | ||
1297 | /* We could use larger page sizes in order to *decrease* the number | |
1298 | ** of mappings needed. (ie 8k pages means 1/2 the mappings). | |
1299 | ** | |
1300 | ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either | |
1301 | ** since the pages must also be physically contiguous - typically | |
1302 | ** this is the case under linux." | |
1303 | */ | |
1304 | ||
1305 | iov_order = get_order(iova_space_size << PAGE_SHIFT); | |
1306 | ||
1307 | /* iova_space_size is now bytes, not pages */ | |
1308 | iova_space_size = 1 << (iov_order + PAGE_SHIFT); | |
1309 | ||
1310 | ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); | |
1311 | ||
86a61ee9 | 1312 | BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ |
1da177e4 LT |
1313 | |
1314 | /* Verify it's a power of two */ | |
1315 | BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); | |
1316 | ||
86a61ee9 GG |
1317 | DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", |
1318 | __FUNCTION__, ioc->ioc_regs, | |
1da177e4 LT |
1319 | (unsigned long) num_physpages >> (20 - PAGE_SHIFT), |
1320 | iova_space_size>>20, | |
1321 | iov_order + PAGE_SHIFT); | |
1322 | ||
1323 | ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, | |
1324 | get_order(ioc->pdir_size)); | |
1325 | if(NULL == ioc->pdir_base) { | |
86a61ee9 | 1326 | panic("%s() could not allocate I/O Page Table\n", __FUNCTION__); |
1da177e4 LT |
1327 | } |
1328 | memset(ioc->pdir_base, 0, ioc->pdir_size); | |
1329 | ||
1330 | BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); | |
86a61ee9 | 1331 | DBG_INIT(" base %p\n", ioc->pdir_base); |
1da177e4 LT |
1332 | |
1333 | /* resource map size dictated by pdir_size */ | |
1334 | ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; | |
1335 | DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size); | |
1336 | ||
1337 | ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, | |
1338 | get_order(ioc->res_size)); | |
1339 | if(NULL == ioc->res_map) { | |
86a61ee9 | 1340 | panic("%s() could not allocate resource map\n", __FUNCTION__); |
1da177e4 LT |
1341 | } |
1342 | memset(ioc->res_map, 0, ioc->res_size); | |
1343 | ||
1344 | /* Initialize the res_hint to 16 */ | |
1345 | ioc->res_hint = 16; | |
1346 | ||
1347 | /* Initialize the spinlock */ | |
1348 | spin_lock_init(&ioc->res_lock); | |
1349 | ||
1350 | /* | |
1351 | ** Chainid is the upper most bits of an IOVP used to determine | |
1352 | ** which TLB entry an IOVP will use. | |
1353 | */ | |
1354 | ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; | |
1355 | DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); | |
1356 | ||
1357 | /* | |
1358 | ** Initialize IOA hardware | |
1359 | */ | |
1360 | WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, | |
86a61ee9 | 1361 | &ioc->ioc_regs->io_chain_id_mask); |
1da177e4 LT |
1362 | |
1363 | WRITE_U32(virt_to_phys(ioc->pdir_base), | |
86a61ee9 | 1364 | &ioc->ioc_regs->io_pdir_base); |
1da177e4 LT |
1365 | |
1366 | /* | |
1367 | ** Go to "Virtual Mode" | |
1368 | */ | |
86a61ee9 | 1369 | WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); |
1da177e4 LT |
1370 | |
1371 | /* | |
1372 | ** Initialize all I/O TLB entries to 0 (Valid bit off). | |
1373 | */ | |
86a61ee9 GG |
1374 | WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); |
1375 | WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); | |
1da177e4 LT |
1376 | |
1377 | for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { | |
1378 | WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), | |
86a61ee9 | 1379 | &ioc->ioc_regs->io_command); |
1da177e4 LT |
1380 | } |
1381 | } | |
1382 | ||
25971f68 | 1383 | static void __init |
86a61ee9 | 1384 | ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) |
1da177e4 LT |
1385 | { |
1386 | int result; | |
1387 | ||
1388 | res->parent = NULL; | |
1389 | res->flags = IORESOURCE_MEM; | |
86a61ee9 GG |
1390 | /* |
1391 | * bracing ((signed) ...) are required for 64bit kernel because | |
1392 | * we only want to sign extend the lower 16 bits of the register. | |
1393 | * The upper 16-bits of range registers are hardcoded to 0xffff. | |
1394 | */ | |
1395 | res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); | |
1396 | res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); | |
1da177e4 | 1397 | res->name = name; |
86a61ee9 GG |
1398 | /* |
1399 | * Check if this MMIO range is disable | |
1400 | */ | |
1da177e4 LT |
1401 | if (res->end + 1 == res->start) |
1402 | return; | |
86a61ee9 GG |
1403 | |
1404 | /* On some platforms (e.g. K-Class), we have already registered | |
1405 | * resources for devices reported by firmware. Some are children | |
1406 | * of ccio. | |
1407 | * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). | |
1408 | */ | |
1409 | result = insert_resource(&iomem_resource, res); | |
1da177e4 | 1410 | if (result < 0) { |
86a61ee9 GG |
1411 | printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", |
1412 | __FUNCTION__, res->start, res->end); | |
1da177e4 LT |
1413 | } |
1414 | } | |
1415 | ||
1416 | static void __init ccio_init_resources(struct ioc *ioc) | |
1417 | { | |
1418 | struct resource *res = ioc->mmio_region; | |
1419 | char *name = kmalloc(14, GFP_KERNEL); | |
1420 | ||
cb6fc18e | 1421 | snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); |
1da177e4 | 1422 | |
86a61ee9 GG |
1423 | ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); |
1424 | ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); | |
1da177e4 LT |
1425 | } |
1426 | ||
1427 | static int new_ioc_area(struct resource *res, unsigned long size, | |
1428 | unsigned long min, unsigned long max, unsigned long align) | |
1429 | { | |
1430 | if (max <= min) | |
1431 | return -EBUSY; | |
1432 | ||
1433 | res->start = (max - size + 1) &~ (align - 1); | |
1434 | res->end = res->start + size; | |
86a61ee9 GG |
1435 | |
1436 | /* We might be trying to expand the MMIO range to include | |
1437 | * a child device that has already registered it's MMIO space. | |
1438 | * Use "insert" instead of request_resource(). | |
1439 | */ | |
1440 | if (!insert_resource(&iomem_resource, res)) | |
1da177e4 LT |
1441 | return 0; |
1442 | ||
1443 | return new_ioc_area(res, size, min, max - size, align); | |
1444 | } | |
1445 | ||
1446 | static int expand_ioc_area(struct resource *res, unsigned long size, | |
1447 | unsigned long min, unsigned long max, unsigned long align) | |
1448 | { | |
1449 | unsigned long start, len; | |
1450 | ||
1451 | if (!res->parent) | |
1452 | return new_ioc_area(res, size, min, max, align); | |
1453 | ||
1454 | start = (res->start - size) &~ (align - 1); | |
1455 | len = res->end - start + 1; | |
1456 | if (start >= min) { | |
1457 | if (!adjust_resource(res, start, len)) | |
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | start = res->start; | |
1462 | len = ((size + res->end + align) &~ (align - 1)) - start; | |
1463 | if (start + len <= max) { | |
1464 | if (!adjust_resource(res, start, len)) | |
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | return -EBUSY; | |
1469 | } | |
1470 | ||
1471 | /* | |
1472 | * Dino calls this function. Beware that we may get called on systems | |
1473 | * which have no IOC (725, B180, C160L, etc) but do have a Dino. | |
1474 | * So it's legal to find no parent IOC. | |
1475 | * | |
1476 | * Some other issues: one of the resources in the ioc may be unassigned. | |
1477 | */ | |
1478 | int ccio_allocate_resource(const struct parisc_device *dev, | |
1479 | struct resource *res, unsigned long size, | |
1480 | unsigned long min, unsigned long max, unsigned long align) | |
1481 | { | |
1482 | struct resource *parent = &iomem_resource; | |
1483 | struct ioc *ioc = ccio_get_iommu(dev); | |
1484 | if (!ioc) | |
1485 | goto out; | |
1486 | ||
1487 | parent = ioc->mmio_region; | |
1488 | if (parent->parent && | |
1489 | !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) | |
1490 | return 0; | |
1491 | ||
1492 | if ((parent + 1)->parent && | |
1493 | !allocate_resource(parent + 1, res, size, min, max, align, | |
1494 | NULL, NULL)) | |
1495 | return 0; | |
1496 | ||
1497 | if (!expand_ioc_area(parent, size, min, max, align)) { | |
1498 | __raw_writel(((parent->start)>>16) | 0xffff0000, | |
86a61ee9 | 1499 | &ioc->ioc_regs->io_io_low); |
1da177e4 | 1500 | __raw_writel(((parent->end)>>16) | 0xffff0000, |
86a61ee9 | 1501 | &ioc->ioc_regs->io_io_high); |
1da177e4 LT |
1502 | } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { |
1503 | parent++; | |
1504 | __raw_writel(((parent->start)>>16) | 0xffff0000, | |
86a61ee9 | 1505 | &ioc->ioc_regs->io_io_low_hv); |
1da177e4 | 1506 | __raw_writel(((parent->end)>>16) | 0xffff0000, |
86a61ee9 | 1507 | &ioc->ioc_regs->io_io_high_hv); |
1da177e4 LT |
1508 | } else { |
1509 | return -EBUSY; | |
1510 | } | |
1511 | ||
1512 | out: | |
1513 | return allocate_resource(parent, res, size, min, max, align, NULL,NULL); | |
1514 | } | |
1515 | ||
1516 | int ccio_request_resource(const struct parisc_device *dev, | |
1517 | struct resource *res) | |
1518 | { | |
1519 | struct resource *parent; | |
1520 | struct ioc *ioc = ccio_get_iommu(dev); | |
1521 | ||
1522 | if (!ioc) { | |
1523 | parent = &iomem_resource; | |
1524 | } else if ((ioc->mmio_region->start <= res->start) && | |
1525 | (res->end <= ioc->mmio_region->end)) { | |
1526 | parent = ioc->mmio_region; | |
1527 | } else if (((ioc->mmio_region + 1)->start <= res->start) && | |
1528 | (res->end <= (ioc->mmio_region + 1)->end)) { | |
1529 | parent = ioc->mmio_region + 1; | |
1530 | } else { | |
1531 | return -EBUSY; | |
1532 | } | |
1533 | ||
86a61ee9 GG |
1534 | /* "transparent" bus bridges need to register MMIO resources |
1535 | * firmware assigned them. e.g. children of hppb.c (e.g. K-class) | |
1536 | * registered their resources in the PDC "bus walk" (See | |
1537 | * arch/parisc/kernel/inventory.c). | |
1538 | */ | |
1539 | return insert_resource(parent, res); | |
1da177e4 LT |
1540 | } |
1541 | ||
1542 | /** | |
1543 | * ccio_probe - Determine if ccio should claim this device. | |
1544 | * @dev: The device which has been found | |
1545 | * | |
1546 | * Determine if ccio should claim this chip (return 0) or not (return 1). | |
1547 | * If so, initialize the chip and tell other partners in crime they | |
1548 | * have work to do. | |
1549 | */ | |
25971f68 | 1550 | static int __init ccio_probe(struct parisc_device *dev) |
1da177e4 LT |
1551 | { |
1552 | int i; | |
1553 | struct ioc *ioc, **ioc_p = &ioc_list; | |
f823bcae | 1554 | struct proc_dir_entry *info_entry, *bitmap_entry; |
1da177e4 | 1555 | |
cb6fc18e | 1556 | ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); |
1da177e4 LT |
1557 | if (ioc == NULL) { |
1558 | printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); | |
1559 | return 1; | |
1560 | } | |
1da177e4 LT |
1561 | |
1562 | ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; | |
1563 | ||
53f01bba | 1564 | printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, dev->hpa.start); |
1da177e4 LT |
1565 | |
1566 | for (i = 0; i < ioc_count; i++) { | |
1567 | ioc_p = &(*ioc_p)->next; | |
1568 | } | |
1569 | *ioc_p = ioc; | |
1570 | ||
1571 | ioc->hw_path = dev->hw_path; | |
5076c158 | 1572 | ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); |
1da177e4 LT |
1573 | ccio_ioc_init(ioc); |
1574 | ccio_init_resources(ioc); | |
1575 | hppa_dma_ops = &ccio_ops; | |
cb6fc18e | 1576 | dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); |
1da177e4 LT |
1577 | |
1578 | /* if this fails, no I/O cards will work, so may as well bug */ | |
1579 | BUG_ON(dev->dev.platform_data == NULL); | |
1580 | HBA_DATA(dev->dev.platform_data)->iommu = ioc; | |
1581 | ||
1da177e4 | 1582 | if (ioc_count == 0) { |
f823bcae KM |
1583 | info_entry = create_proc_entry(MODULE_NAME, 0, proc_runway_root); |
1584 | if (info_entry) | |
1585 | info_entry->proc_fops = &ccio_proc_info_fops; | |
1586 | ||
1587 | bitmap_entry = create_proc_entry(MODULE_NAME"-bitmap", 0, proc_runway_root); | |
1588 | if (bitmap_entry) | |
1589 | bitmap_entry->proc_fops = &ccio_proc_bitmap_fops; | |
1da177e4 LT |
1590 | } |
1591 | ||
1592 | ioc_count++; | |
1593 | ||
1594 | parisc_vmerge_boundary = IOVP_SIZE; | |
1595 | parisc_vmerge_max_size = BITS_PER_LONG * IOVP_SIZE; | |
1596 | parisc_has_iommu(); | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | /** | |
4f63ba17 | 1601 | * ccio_init - ccio initialization procedure. |
1da177e4 LT |
1602 | * |
1603 | * Register this driver. | |
1604 | */ | |
1605 | void __init ccio_init(void) | |
1606 | { | |
1607 | register_parisc_driver(&ccio_driver); | |
1608 | } | |
1609 |