Commit | Line | Data |
---|---|---|
af6074fc | 1 | // SPDX-License-Identifier: GPL-2.0 |
606ad42a RH |
2 | #define pr_fmt(fmt) "OF: " fmt |
3 | ||
5019f0b1 | 4 | #include <linux/device.h> |
fcfaab30 | 5 | #include <linux/fwnode.h> |
6b884a8d GL |
6 | #include <linux/io.h> |
7 | #include <linux/ioport.h> | |
65af618d | 8 | #include <linux/logic_pio.h> |
dbbdee94 | 9 | #include <linux/module.h> |
6b884a8d | 10 | #include <linux/of_address.h> |
000f6d58 | 11 | #include <linux/overflow.h> |
c5076cfe | 12 | #include <linux/pci.h> |
dbbdee94 | 13 | #include <linux/pci_regs.h> |
41f8bba7 LD |
14 | #include <linux/sizes.h> |
15 | #include <linux/slab.h> | |
dbbdee94 | 16 | #include <linux/string.h> |
e0d07278 | 17 | #include <linux/dma-direct.h> /* for bus_dma_region */ |
6b884a8d | 18 | |
e6649328 TW |
19 | #include <kunit/visibility.h> |
20 | ||
17345145 ZH |
21 | /* Uncomment me to enable of_dump_addr() debugging output */ |
22 | // #define DEBUG | |
dbbdee94 | 23 | |
17345145 | 24 | #include "of_private.h" |
dbbdee94 GL |
25 | |
26 | /* Callbacks for bus specific translators */ | |
27 | struct of_bus { | |
28 | const char *name; | |
29 | const char *addresses; | |
30 | int (*match)(struct device_node *parent); | |
31 | void (*count_cells)(struct device_node *child, | |
32 | int *addrc, int *sizec); | |
47b1e689 | 33 | u64 (*map)(__be32 *addr, const __be32 *range, |
73ae3088 | 34 | int na, int ns, int pna, int fna); |
47b1e689 | 35 | int (*translate)(__be32 *addr, u64 offset, int na); |
88696db0 | 36 | int flag_cells; |
0131d897 | 37 | unsigned int (*get_flags)(const __be32 *addr); |
dbbdee94 GL |
38 | }; |
39 | ||
40 | /* | |
41 | * Default translator (generic bus) | |
42 | */ | |
43 | ||
44 | static void of_bus_default_count_cells(struct device_node *dev, | |
45 | int *addrc, int *sizec) | |
46 | { | |
47 | if (addrc) | |
48 | *addrc = of_n_addr_cells(dev); | |
49 | if (sizec) | |
50 | *sizec = of_n_size_cells(dev); | |
51 | } | |
52 | ||
47b1e689 | 53 | static u64 of_bus_default_map(__be32 *addr, const __be32 *range, |
73ae3088 | 54 | int na, int ns, int pna, int fna) |
dbbdee94 GL |
55 | { |
56 | u64 cp, s, da; | |
57 | ||
73ae3088 | 58 | cp = of_read_number(range + fna, na - fna); |
dbbdee94 | 59 | s = of_read_number(range + na + pna, ns); |
73ae3088 | 60 | da = of_read_number(addr + fna, na - fna); |
dbbdee94 | 61 | |
0e407a9a | 62 | pr_debug("default map, cp=%llx, s=%llx, da=%llx\n", cp, s, da); |
dbbdee94 GL |
63 | |
64 | if (da < cp || da >= (cp + s)) | |
65 | return OF_BAD_ADDR; | |
66 | return da - cp; | |
67 | } | |
68 | ||
47b1e689 | 69 | static int of_bus_default_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
70 | { |
71 | u64 a = of_read_number(addr, na); | |
72 | memset(addr, 0, na * 4); | |
73 | a += offset; | |
74 | if (na > 1) | |
154063a9 GL |
75 | addr[na - 2] = cpu_to_be32(a >> 32); |
76 | addr[na - 1] = cpu_to_be32(a & 0xffffffffu); | |
dbbdee94 GL |
77 | |
78 | return 0; | |
79 | } | |
80 | ||
3d5089c4 RH |
81 | static unsigned int of_bus_default_flags_get_flags(const __be32 *addr) |
82 | { | |
83 | return of_read_number(addr, 1); | |
84 | } | |
85 | ||
0131d897 | 86 | static unsigned int of_bus_default_get_flags(const __be32 *addr) |
dbbdee94 GL |
87 | { |
88 | return IORESOURCE_MEM; | |
89 | } | |
90 | ||
42604f8e | 91 | static u64 of_bus_default_flags_map(__be32 *addr, const __be32 *range, int na, |
73ae3088 | 92 | int ns, int pna, int fna) |
42604f8e | 93 | { |
42604f8e HC |
94 | /* Check that flags match */ |
95 | if (*addr != *range) | |
96 | return OF_BAD_ADDR; | |
97 | ||
73ae3088 | 98 | return of_bus_default_map(addr, range, na, ns, pna, fna); |
42604f8e HC |
99 | } |
100 | ||
101 | static int of_bus_default_flags_translate(__be32 *addr, u64 offset, int na) | |
102 | { | |
103 | /* Keep "flags" part (high cell) in translated address */ | |
104 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
105 | } | |
3d5089c4 | 106 | |
0fc0ead3 | 107 | #ifdef CONFIG_PCI |
67ccd2b9 RH |
108 | static unsigned int of_bus_pci_get_flags(const __be32 *addr) |
109 | { | |
110 | unsigned int flags = 0; | |
111 | u32 w = be32_to_cpup(addr); | |
112 | ||
113 | if (!IS_ENABLED(CONFIG_PCI)) | |
114 | return 0; | |
115 | ||
116 | switch((w >> 24) & 0x03) { | |
117 | case 0x01: | |
118 | flags |= IORESOURCE_IO; | |
119 | break; | |
120 | case 0x02: /* 32 bits */ | |
67ccd2b9 RH |
121 | flags |= IORESOURCE_MEM; |
122 | break; | |
9d57e61b LB |
123 | |
124 | case 0x03: /* 64 bits */ | |
125 | flags |= IORESOURCE_MEM | IORESOURCE_MEM_64; | |
126 | break; | |
67ccd2b9 RH |
127 | } |
128 | if (w & 0x40000000) | |
129 | flags |= IORESOURCE_PREFETCH; | |
130 | return flags; | |
131 | } | |
132 | ||
dbbdee94 GL |
133 | /* |
134 | * PCI bus specific translator | |
135 | */ | |
136 | ||
ec8c2329 | 137 | static bool of_node_is_pcie(const struct device_node *np) |
d1ac0002 MZ |
138 | { |
139 | bool is_pcie = of_node_name_eq(np, "pcie"); | |
140 | ||
141 | if (is_pcie) | |
142 | pr_warn_once("%pOF: Missing device_type\n", np); | |
143 | ||
144 | return is_pcie; | |
145 | } | |
146 | ||
dbbdee94 GL |
147 | static int of_bus_pci_match(struct device_node *np) |
148 | { | |
6dd18e46 | 149 | /* |
14e2abb7 | 150 | * "pciex" is PCI Express |
6dd18e46 BH |
151 | * "vci" is for the /chaos bridge on 1st-gen PCI powermacs |
152 | * "ht" is hypertransport | |
d1ac0002 MZ |
153 | * |
154 | * If none of the device_type match, and that the node name is | |
155 | * "pcie", accept the device as PCI (with a warning). | |
6dd18e46 | 156 | */ |
e8b1dee2 | 157 | return of_node_is_type(np, "pci") || of_node_is_type(np, "pciex") || |
d1ac0002 MZ |
158 | of_node_is_type(np, "vci") || of_node_is_type(np, "ht") || |
159 | of_node_is_pcie(np); | |
dbbdee94 GL |
160 | } |
161 | ||
162 | static void of_bus_pci_count_cells(struct device_node *np, | |
163 | int *addrc, int *sizec) | |
164 | { | |
165 | if (addrc) | |
166 | *addrc = 3; | |
167 | if (sizec) | |
168 | *sizec = 2; | |
169 | } | |
170 | ||
47b1e689 | 171 | static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, |
73ae3088 | 172 | int pna, int fna) |
dbbdee94 | 173 | { |
dbbdee94 GL |
174 | unsigned int af, rf; |
175 | ||
176 | af = of_bus_pci_get_flags(addr); | |
177 | rf = of_bus_pci_get_flags(range); | |
178 | ||
179 | /* Check address type match */ | |
180 | if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO)) | |
181 | return OF_BAD_ADDR; | |
182 | ||
73ae3088 | 183 | return of_bus_default_map(addr, range, na, ns, pna, fna); |
dbbdee94 GL |
184 | } |
185 | ||
c3c0dc75 | 186 | #endif /* CONFIG_PCI */ |
dbbdee94 | 187 | |
e6649328 | 188 | VISIBLE_IF_KUNIT int __of_address_resource_bounds(struct resource *r, u64 start, u64 size) |
1a52a094 | 189 | { |
1a52a094 TW |
190 | if (overflows_type(start, r->start)) |
191 | return -EOVERFLOW; | |
1a52a094 TW |
192 | |
193 | r->start = start; | |
15e2f65f TW |
194 | |
195 | if (!size) | |
196 | r->end = wrapping_sub(typeof(r->end), r->start, 1); | |
197 | else if (size && check_add_overflow(r->start, size - 1, &r->end)) | |
198 | return -EOVERFLOW; | |
1a52a094 TW |
199 | |
200 | return 0; | |
201 | } | |
e6649328 | 202 | EXPORT_SYMBOL_IF_KUNIT(__of_address_resource_bounds); |
1a52a094 | 203 | |
0b0b0893 LD |
204 | /* |
205 | * of_pci_range_to_resource - Create a resource from an of_pci_range | |
206 | * @range: the PCI range that describes the resource | |
207 | * @np: device node where the range belongs to | |
208 | * @res: pointer to a valid resource that will be updated to | |
209 | * reflect the values contained in the range. | |
210 | * | |
65b6b046 | 211 | * Returns -EINVAL if the range cannot be converted to resource. |
0b0b0893 LD |
212 | * |
213 | * Note that if the range is an IO range, the resource will be converted | |
214 | * using pci_address_to_pio() which can fail if it is called too early or | |
215 | * if the range cannot be matched to any host bridge IO space (our case here). | |
216 | * To guard against that we try to register the IO range first. | |
217 | * If that fails we know that pci_address_to_pio() will do too. | |
218 | */ | |
ec8c2329 RHA |
219 | int of_pci_range_to_resource(const struct of_pci_range *range, |
220 | const struct device_node *np, struct resource *res) | |
83bbde1c | 221 | { |
1a52a094 | 222 | u64 start; |
0b0b0893 | 223 | int err; |
83bbde1c | 224 | res->flags = range->flags; |
83bbde1c LD |
225 | res->parent = res->child = res->sibling = NULL; |
226 | res->name = np->full_name; | |
0b0b0893 LD |
227 | |
228 | if (res->flags & IORESOURCE_IO) { | |
229 | unsigned long port; | |
fcfaab30 GP |
230 | err = pci_register_io_range(&np->fwnode, range->cpu_addr, |
231 | range->size); | |
0b0b0893 LD |
232 | if (err) |
233 | goto invalid_range; | |
234 | port = pci_address_to_pio(range->cpu_addr); | |
235 | if (port == (unsigned long)-1) { | |
236 | err = -EINVAL; | |
237 | goto invalid_range; | |
238 | } | |
1a52a094 | 239 | start = port; |
0b0b0893 | 240 | } else { |
1a52a094 | 241 | start = range->cpu_addr; |
0b0b0893 | 242 | } |
1a52a094 | 243 | return __of_address_resource_bounds(res, start, range->size); |
0b0b0893 LD |
244 | |
245 | invalid_range: | |
246 | res->start = (resource_size_t)OF_BAD_ADDR; | |
247 | res->end = (resource_size_t)OF_BAD_ADDR; | |
248 | return err; | |
83bbde1c | 249 | } |
bf6681ea | 250 | EXPORT_SYMBOL(of_pci_range_to_resource); |
dbbdee94 | 251 | |
c75a7949 RH |
252 | /* |
253 | * of_range_to_resource - Create a resource from a ranges entry | |
254 | * @np: device node where the range belongs to | |
255 | * @index: the 'ranges' index to convert to a resource | |
256 | * @res: pointer to a valid resource that will be updated to | |
257 | * reflect the values contained in the range. | |
258 | * | |
1a52a094 TW |
259 | * Returns -ENOENT if the entry is not found or -EOVERFLOW if the range |
260 | * cannot be converted to resource. | |
c75a7949 RH |
261 | */ |
262 | int of_range_to_resource(struct device_node *np, int index, struct resource *res) | |
263 | { | |
264 | int ret, i = 0; | |
265 | struct of_range_parser parser; | |
266 | struct of_range range; | |
267 | ||
268 | ret = of_range_parser_init(&parser, np); | |
269 | if (ret) | |
270 | return ret; | |
271 | ||
272 | for_each_of_range(&parser, &range) | |
273 | if (i++ == index) | |
274 | return of_pci_range_to_resource(&range, np, res); | |
275 | ||
276 | return -ENOENT; | |
277 | } | |
278 | EXPORT_SYMBOL(of_range_to_resource); | |
279 | ||
dbbdee94 GL |
280 | /* |
281 | * ISA bus specific translator | |
282 | */ | |
283 | ||
284 | static int of_bus_isa_match(struct device_node *np) | |
285 | { | |
b3e46d1a | 286 | return of_node_name_eq(np, "isa"); |
dbbdee94 GL |
287 | } |
288 | ||
289 | static void of_bus_isa_count_cells(struct device_node *child, | |
290 | int *addrc, int *sizec) | |
291 | { | |
292 | if (addrc) | |
293 | *addrc = 2; | |
294 | if (sizec) | |
295 | *sizec = 1; | |
296 | } | |
297 | ||
47b1e689 | 298 | static u64 of_bus_isa_map(__be32 *addr, const __be32 *range, int na, int ns, |
73ae3088 | 299 | int pna, int fna) |
dbbdee94 | 300 | { |
dbbdee94 | 301 | /* Check address type match */ |
0131d897 | 302 | if ((addr[0] ^ range[0]) & cpu_to_be32(1)) |
dbbdee94 GL |
303 | return OF_BAD_ADDR; |
304 | ||
73ae3088 | 305 | return of_bus_default_map(addr, range, na, ns, pna, fna); |
dbbdee94 GL |
306 | } |
307 | ||
0131d897 | 308 | static unsigned int of_bus_isa_get_flags(const __be32 *addr) |
dbbdee94 GL |
309 | { |
310 | unsigned int flags = 0; | |
0131d897 | 311 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
312 | |
313 | if (w & 1) | |
314 | flags |= IORESOURCE_IO; | |
315 | else | |
316 | flags |= IORESOURCE_MEM; | |
317 | return flags; | |
318 | } | |
319 | ||
3d5089c4 RH |
320 | static int of_bus_default_flags_match(struct device_node *np) |
321 | { | |
64ee3cf0 RHA |
322 | /* |
323 | * Check for presence first since of_bus_n_addr_cells() will warn when | |
324 | * walking parent nodes. | |
325 | */ | |
326 | return of_property_present(np, "#address-cells") && (of_bus_n_addr_cells(np) == 3); | |
3d5089c4 RH |
327 | } |
328 | ||
6e5773d5 RHA |
329 | static int of_bus_default_match(struct device_node *np) |
330 | { | |
331 | /* | |
332 | * Check for presence first since of_bus_n_addr_cells() will warn when | |
333 | * walking parent nodes. | |
334 | */ | |
335 | return of_property_present(np, "#address-cells"); | |
336 | } | |
337 | ||
dbbdee94 GL |
338 | /* |
339 | * Array of bus specific translators | |
340 | */ | |
341 | ||
d79616b0 | 342 | static const struct of_bus of_busses[] = { |
4670d610 | 343 | #ifdef CONFIG_PCI |
dbbdee94 GL |
344 | /* PCI */ |
345 | { | |
346 | .name = "pci", | |
347 | .addresses = "assigned-addresses", | |
348 | .match = of_bus_pci_match, | |
349 | .count_cells = of_bus_pci_count_cells, | |
350 | .map = of_bus_pci_map, | |
3eb030c6 | 351 | .translate = of_bus_default_flags_translate, |
88696db0 | 352 | .flag_cells = 1, |
dbbdee94 GL |
353 | .get_flags = of_bus_pci_get_flags, |
354 | }, | |
4670d610 | 355 | #endif /* CONFIG_PCI */ |
dbbdee94 GL |
356 | /* ISA */ |
357 | { | |
358 | .name = "isa", | |
359 | .addresses = "reg", | |
360 | .match = of_bus_isa_match, | |
361 | .count_cells = of_bus_isa_count_cells, | |
362 | .map = of_bus_isa_map, | |
3eb030c6 | 363 | .translate = of_bus_default_flags_translate, |
88696db0 | 364 | .flag_cells = 1, |
dbbdee94 GL |
365 | .get_flags = of_bus_isa_get_flags, |
366 | }, | |
3d5089c4 RH |
367 | /* Default with flags cell */ |
368 | { | |
369 | .name = "default-flags", | |
370 | .addresses = "reg", | |
371 | .match = of_bus_default_flags_match, | |
372 | .count_cells = of_bus_default_count_cells, | |
42604f8e HC |
373 | .map = of_bus_default_flags_map, |
374 | .translate = of_bus_default_flags_translate, | |
88696db0 | 375 | .flag_cells = 1, |
3d5089c4 RH |
376 | .get_flags = of_bus_default_flags_get_flags, |
377 | }, | |
dbbdee94 GL |
378 | /* Default */ |
379 | { | |
380 | .name = "default", | |
381 | .addresses = "reg", | |
6e5773d5 | 382 | .match = of_bus_default_match, |
dbbdee94 GL |
383 | .count_cells = of_bus_default_count_cells, |
384 | .map = of_bus_default_map, | |
385 | .translate = of_bus_default_translate, | |
386 | .get_flags = of_bus_default_get_flags, | |
387 | }, | |
388 | }; | |
389 | ||
d79616b0 | 390 | static const struct of_bus *of_match_bus(struct device_node *np) |
dbbdee94 GL |
391 | { |
392 | int i; | |
393 | ||
394 | for (i = 0; i < ARRAY_SIZE(of_busses); i++) | |
395 | if (!of_busses[i].match || of_busses[i].match(np)) | |
396 | return &of_busses[i]; | |
dbbdee94 GL |
397 | return NULL; |
398 | } | |
399 | ||
ec8c2329 | 400 | static int of_empty_ranges_quirk(const struct device_node *np) |
746c9e9f BH |
401 | { |
402 | if (IS_ENABLED(CONFIG_PPC)) { | |
41d94893 | 403 | /* To save cycles, we cache the result for global "Mac" setting */ |
746c9e9f BH |
404 | static int quirk_state = -1; |
405 | ||
41d94893 BH |
406 | /* PA-SEMI sdc DT bug */ |
407 | if (of_device_is_compatible(np, "1682m-sdc")) | |
408 | return true; | |
409 | ||
410 | /* Make quirk cached */ | |
746c9e9f BH |
411 | if (quirk_state < 0) |
412 | quirk_state = | |
413 | of_machine_is_compatible("Power Macintosh") || | |
414 | of_machine_is_compatible("MacRISC"); | |
415 | return quirk_state; | |
416 | } | |
417 | return false; | |
418 | } | |
419 | ||
d79616b0 RHA |
420 | static int of_translate_one(const struct device_node *parent, const struct of_bus *bus, |
421 | const struct of_bus *pbus, __be32 *addr, | |
dbbdee94 GL |
422 | int na, int ns, int pna, const char *rprop) |
423 | { | |
0131d897 | 424 | const __be32 *ranges; |
dbbdee94 GL |
425 | unsigned int rlen; |
426 | int rone; | |
427 | u64 offset = OF_BAD_ADDR; | |
428 | ||
ba85edbe MY |
429 | /* |
430 | * Normally, an absence of a "ranges" property means we are | |
dbbdee94 | 431 | * crossing a non-translatable boundary, and thus the addresses |
ba85edbe | 432 | * below the current cannot be converted to CPU physical ones. |
dbbdee94 GL |
433 | * Unfortunately, while this is very clear in the spec, it's not |
434 | * what Apple understood, and they do have things like /uni-n or | |
435 | * /ht nodes with no "ranges" property and a lot of perfectly | |
436 | * useable mapped devices below them. Thus we treat the absence of | |
437 | * "ranges" as equivalent to an empty "ranges" property which means | |
438 | * a 1:1 translation at that level. It's up to the caller not to try | |
439 | * to translate addresses that aren't supposed to be translated in | |
440 | * the first place. --BenH. | |
3930f294 GL |
441 | * |
442 | * As far as we know, this damage only exists on Apple machines, so | |
443 | * This code is only enabled on powerpc. --gcl | |
81db12ee RH |
444 | * |
445 | * This quirk also applies for 'dma-ranges' which frequently exist in | |
446 | * child nodes without 'dma-ranges' in the parent nodes. --RobH | |
dbbdee94 GL |
447 | */ |
448 | ranges = of_get_property(parent, rprop, &rlen); | |
81db12ee RH |
449 | if (ranges == NULL && !of_empty_ranges_quirk(parent) && |
450 | strcmp(rprop, "dma-ranges")) { | |
606ad42a | 451 | pr_debug("no ranges; cannot translate\n"); |
3930f294 GL |
452 | return 1; |
453 | } | |
dbbdee94 GL |
454 | if (ranges == NULL || rlen == 0) { |
455 | offset = of_read_number(addr, na); | |
7f05e20b AP |
456 | /* set address to zero, pass flags through */ |
457 | memset(addr + pbus->flag_cells, 0, (pna - pbus->flag_cells) * 4); | |
606ad42a | 458 | pr_debug("empty ranges; 1:1 translation\n"); |
dbbdee94 GL |
459 | goto finish; |
460 | } | |
461 | ||
606ad42a | 462 | pr_debug("walking ranges...\n"); |
dbbdee94 GL |
463 | |
464 | /* Now walk through the ranges */ | |
465 | rlen /= 4; | |
466 | rone = na + pna + ns; | |
467 | for (; rlen >= rone; rlen -= rone, ranges += rone) { | |
73ae3088 | 468 | offset = bus->map(addr, ranges, na, ns, pna, bus->flag_cells); |
dbbdee94 GL |
469 | if (offset != OF_BAD_ADDR) |
470 | break; | |
471 | } | |
472 | if (offset == OF_BAD_ADDR) { | |
606ad42a | 473 | pr_debug("not found !\n"); |
dbbdee94 GL |
474 | return 1; |
475 | } | |
476 | memcpy(addr, ranges + na, 4 * pna); | |
477 | ||
478 | finish: | |
606ad42a | 479 | of_dump_addr("parent translation for:", addr, pna); |
0e407a9a | 480 | pr_debug("with offset: %llx\n", offset); |
dbbdee94 GL |
481 | |
482 | /* Translate it into parent bus space */ | |
483 | return pbus->translate(addr, offset, pna); | |
484 | } | |
485 | ||
486 | /* | |
487 | * Translate an address from the device-tree into a CPU physical address, | |
488 | * this walks up the tree and applies the various bus mappings on the | |
489 | * way. | |
490 | * | |
491 | * Note: We consider that crossing any level with #size-cells == 0 to mean | |
492 | * that translation is impossible (that is we are not dealing with a value | |
493 | * that can be mapped to a cpu physical address). This is not really specified | |
494 | * that way, but this is traditionally the way IBM at least do things | |
65af618d ZY |
495 | * |
496 | * Whenever the translation fails, the *host pointer will be set to the | |
497 | * device that had registered logical PIO mapping, and the return code is | |
498 | * relative to that node. | |
dbbdee94 | 499 | */ |
a5737b21 | 500 | static u64 __of_translate_address(struct device_node *node, |
95835a8d | 501 | struct device_node *(*get_parent)(const struct device_node *), |
65af618d ZY |
502 | const __be32 *in_addr, const char *rprop, |
503 | struct device_node **host) | |
dbbdee94 | 504 | { |
a5737b21 RH |
505 | struct device_node *dev __free(device_node) = of_node_get(node); |
506 | struct device_node *parent __free(device_node) = get_parent(dev); | |
d79616b0 | 507 | const struct of_bus *bus, *pbus; |
47b1e689 | 508 | __be32 addr[OF_MAX_ADDR_CELLS]; |
dbbdee94 | 509 | int na, ns, pna, pns; |
dbbdee94 | 510 | |
0d638a07 | 511 | pr_debug("** translation for device %pOF **\n", dev); |
dbbdee94 | 512 | |
65af618d | 513 | *host = NULL; |
a5737b21 | 514 | |
dbbdee94 | 515 | if (parent == NULL) |
a5737b21 | 516 | return OF_BAD_ADDR; |
dbbdee94 | 517 | bus = of_match_bus(parent); |
6e5773d5 RHA |
518 | if (!bus) |
519 | return OF_BAD_ADDR; | |
dbbdee94 | 520 | |
59f5ca48 | 521 | /* Count address cells & copy address locally */ |
dbbdee94 GL |
522 | bus->count_cells(dev, &na, &ns); |
523 | if (!OF_CHECK_COUNTS(na, ns)) { | |
0d638a07 | 524 | pr_debug("Bad cell count for %pOF\n", dev); |
a5737b21 | 525 | return OF_BAD_ADDR; |
dbbdee94 GL |
526 | } |
527 | memcpy(addr, in_addr, na * 4); | |
528 | ||
0d638a07 RH |
529 | pr_debug("bus is %s (na=%d, ns=%d) on %pOF\n", |
530 | bus->name, na, ns, parent); | |
606ad42a | 531 | of_dump_addr("translating address:", addr, na); |
dbbdee94 GL |
532 | |
533 | /* Translate */ | |
534 | for (;;) { | |
65af618d ZY |
535 | struct logic_pio_hwaddr *iorange; |
536 | ||
dbbdee94 GL |
537 | /* Switch to parent bus */ |
538 | of_node_put(dev); | |
539 | dev = parent; | |
95835a8d | 540 | parent = get_parent(dev); |
dbbdee94 GL |
541 | |
542 | /* If root, we have finished */ | |
543 | if (parent == NULL) { | |
606ad42a | 544 | pr_debug("reached root node\n"); |
a5737b21 | 545 | return of_read_number(addr, na); |
dbbdee94 GL |
546 | } |
547 | ||
65af618d ZY |
548 | /* |
549 | * For indirectIO device which has no ranges property, get | |
550 | * the address from reg directly. | |
551 | */ | |
552 | iorange = find_io_range_by_fwnode(&dev->fwnode); | |
553 | if (iorange && (iorange->flags != LOGIC_PIO_CPU_MMIO)) { | |
a5737b21 | 554 | u64 result = of_read_number(addr + 1, na - 1); |
65af618d ZY |
555 | pr_debug("indirectIO matched(%pOF) 0x%llx\n", |
556 | dev, result); | |
a5737b21 RH |
557 | *host = no_free_ptr(dev); |
558 | return result; | |
65af618d ZY |
559 | } |
560 | ||
dbbdee94 GL |
561 | /* Get new parent bus and counts */ |
562 | pbus = of_match_bus(parent); | |
6e5773d5 RHA |
563 | if (!pbus) |
564 | return OF_BAD_ADDR; | |
dbbdee94 GL |
565 | pbus->count_cells(dev, &pna, &pns); |
566 | if (!OF_CHECK_COUNTS(pna, pns)) { | |
0d638a07 | 567 | pr_err("Bad cell count for %pOF\n", dev); |
a5737b21 | 568 | return OF_BAD_ADDR; |
dbbdee94 GL |
569 | } |
570 | ||
0d638a07 RH |
571 | pr_debug("parent bus is %s (na=%d, ns=%d) on %pOF\n", |
572 | pbus->name, pna, pns, parent); | |
dbbdee94 GL |
573 | |
574 | /* Apply bus translation */ | |
575 | if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) | |
a5737b21 | 576 | return OF_BAD_ADDR; |
dbbdee94 GL |
577 | |
578 | /* Complete the move up one level */ | |
579 | na = pna; | |
580 | ns = pns; | |
581 | bus = pbus; | |
582 | ||
606ad42a | 583 | of_dump_addr("one level translation:", addr, na); |
dbbdee94 | 584 | } |
dbbdee94 | 585 | |
a5737b21 | 586 | unreachable(); |
dbbdee94 GL |
587 | } |
588 | ||
0131d897 | 589 | u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 590 | { |
65af618d ZY |
591 | struct device_node *host; |
592 | u64 ret; | |
593 | ||
95835a8d MR |
594 | ret = __of_translate_address(dev, of_get_parent, |
595 | in_addr, "ranges", &host); | |
65af618d ZY |
596 | if (host) { |
597 | of_node_put(host); | |
598 | return OF_BAD_ADDR; | |
599 | } | |
600 | ||
601 | return ret; | |
dbbdee94 GL |
602 | } |
603 | EXPORT_SYMBOL(of_translate_address); | |
604 | ||
f1ad5338 RM |
605 | #ifdef CONFIG_HAS_DMA |
606 | struct device_node *__of_get_dma_parent(const struct device_node *np) | |
f83a6e5d MR |
607 | { |
608 | struct of_phandle_args args; | |
609 | int ret, index; | |
610 | ||
611 | index = of_property_match_string(np, "interconnect-names", "dma-mem"); | |
612 | if (index < 0) | |
613 | return of_get_parent(np); | |
614 | ||
615 | ret = of_parse_phandle_with_args(np, "interconnects", | |
616 | "#interconnect-cells", | |
617 | index, &args); | |
618 | if (ret < 0) | |
619 | return of_get_parent(np); | |
620 | ||
5d009e02 | 621 | return args.np; |
f83a6e5d | 622 | } |
f1ad5338 | 623 | #endif |
f83a6e5d | 624 | |
862ab557 RM |
625 | static struct device_node *of_get_next_dma_parent(struct device_node *np) |
626 | { | |
627 | struct device_node *parent; | |
628 | ||
629 | parent = __of_get_dma_parent(np); | |
630 | of_node_put(np); | |
631 | ||
632 | return parent; | |
633 | } | |
634 | ||
0131d897 | 635 | u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 636 | { |
65af618d ZY |
637 | struct device_node *host; |
638 | u64 ret; | |
639 | ||
f83a6e5d | 640 | ret = __of_translate_address(dev, __of_get_dma_parent, |
95835a8d | 641 | in_addr, "dma-ranges", &host); |
65af618d ZY |
642 | |
643 | if (host) { | |
644 | of_node_put(host); | |
645 | return OF_BAD_ADDR; | |
646 | } | |
647 | ||
648 | return ret; | |
dbbdee94 GL |
649 | } |
650 | EXPORT_SYMBOL(of_translate_dma_address); | |
651 | ||
e251c213 TR |
652 | /** |
653 | * of_translate_dma_region - Translate device tree address and size tuple | |
654 | * @dev: device tree node for which to translate | |
655 | * @prop: pointer into array of cells | |
656 | * @start: return value for the start of the DMA range | |
657 | * @length: return value for the length of the DMA range | |
658 | * | |
659 | * Returns a pointer to the cell immediately following the translated DMA region. | |
660 | */ | |
661 | const __be32 *of_translate_dma_region(struct device_node *dev, const __be32 *prop, | |
662 | phys_addr_t *start, size_t *length) | |
663 | { | |
a5737b21 | 664 | struct device_node *parent __free(device_node) = __of_get_dma_parent(dev); |
e251c213 TR |
665 | u64 address, size; |
666 | int na, ns; | |
667 | ||
e251c213 TR |
668 | if (!parent) |
669 | return NULL; | |
670 | ||
671 | na = of_bus_n_addr_cells(parent); | |
672 | ns = of_bus_n_size_cells(parent); | |
673 | ||
e251c213 TR |
674 | address = of_translate_dma_address(dev, prop); |
675 | if (address == OF_BAD_ADDR) | |
676 | return NULL; | |
677 | ||
678 | size = of_read_number(prop + na, ns); | |
679 | ||
680 | if (start) | |
681 | *start = address; | |
682 | ||
683 | if (length) | |
684 | *length = size; | |
685 | ||
686 | return prop + na + ns; | |
687 | } | |
688 | EXPORT_SYMBOL(of_translate_dma_region); | |
689 | ||
050a2c62 RH |
690 | const __be32 *__of_get_address(struct device_node *dev, int index, int bar_no, |
691 | u64 *size, unsigned int *flags) | |
dbbdee94 | 692 | { |
0131d897 | 693 | const __be32 *prop; |
dbbdee94 | 694 | unsigned int psize; |
a5737b21 | 695 | struct device_node *parent __free(device_node) = of_get_parent(dev); |
d79616b0 | 696 | const struct of_bus *bus; |
dbbdee94 GL |
697 | int onesize, i, na, ns; |
698 | ||
dbbdee94 GL |
699 | if (parent == NULL) |
700 | return NULL; | |
a5737b21 RH |
701 | |
702 | /* match the parent's bus type */ | |
dbbdee94 | 703 | bus = of_match_bus(parent); |
6e5773d5 | 704 | if (!bus || (strcmp(bus->name, "pci") && (bar_no >= 0))) |
050a2c62 | 705 | return NULL; |
a5737b21 | 706 | |
dbbdee94 GL |
707 | /* Get "reg" or "assigned-addresses" property */ |
708 | prop = of_get_property(dev, bus->addresses, &psize); | |
709 | if (prop == NULL) | |
710 | return NULL; | |
711 | psize /= 4; | |
712 | ||
64ee3cf0 RHA |
713 | bus->count_cells(dev, &na, &ns); |
714 | if (!OF_CHECK_ADDR_COUNT(na)) | |
715 | return NULL; | |
716 | ||
dbbdee94 | 717 | onesize = na + ns; |
050a2c62 RH |
718 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) { |
719 | u32 val = be32_to_cpu(prop[0]); | |
720 | /* PCI bus matches on BAR number instead of index */ | |
721 | if (((bar_no >= 0) && ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0))) || | |
722 | ((index >= 0) && (i == index))) { | |
dbbdee94 GL |
723 | if (size) |
724 | *size = of_read_number(prop + na, ns); | |
725 | if (flags) | |
726 | *flags = bus->get_flags(prop); | |
727 | return prop; | |
728 | } | |
050a2c62 | 729 | } |
dbbdee94 GL |
730 | return NULL; |
731 | } | |
050a2c62 | 732 | EXPORT_SYMBOL(__of_get_address); |
dbbdee94 | 733 | |
ff61bacd RH |
734 | /** |
735 | * of_property_read_reg - Retrieve the specified "reg" entry index without translating | |
736 | * @np: device tree node for which to retrieve "reg" from | |
737 | * @idx: "reg" entry index to read | |
738 | * @addr: return value for the untranslated address | |
739 | * @size: return value for the entry size | |
740 | * | |
741 | * Returns -EINVAL if "reg" is not found. Returns 0 on success with addr and | |
742 | * size values filled in. | |
743 | */ | |
744 | int of_property_read_reg(struct device_node *np, int idx, u64 *addr, u64 *size) | |
745 | { | |
746 | const __be32 *prop = of_get_address(np, idx, size, NULL); | |
747 | ||
748 | if (!prop) | |
749 | return -EINVAL; | |
750 | ||
751 | *addr = of_read_number(prop, of_n_addr_cells(np)); | |
752 | ||
753 | return 0; | |
754 | } | |
755 | EXPORT_SYMBOL(of_property_read_reg); | |
756 | ||
67ccd2b9 RH |
757 | static int parser_init(struct of_pci_range_parser *parser, |
758 | struct device_node *node, const char *name) | |
759 | { | |
67ccd2b9 RH |
760 | int rlen; |
761 | ||
762 | parser->node = node; | |
763 | parser->pna = of_n_addr_cells(node); | |
bc5e522e RH |
764 | parser->na = of_bus_n_addr_cells(node); |
765 | parser->ns = of_bus_n_size_cells(node); | |
67ccd2b9 | 766 | parser->dma = !strcmp(name, "dma-ranges"); |
2f96593e | 767 | parser->bus = of_match_bus(node); |
67ccd2b9 RH |
768 | |
769 | parser->range = of_get_property(node, name, &rlen); | |
770 | if (parser->range == NULL) | |
771 | return -ENOENT; | |
772 | ||
773 | parser->end = parser->range + rlen / sizeof(__be32); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | int of_pci_range_parser_init(struct of_pci_range_parser *parser, | |
779 | struct device_node *node) | |
780 | { | |
781 | return parser_init(parser, node, "ranges"); | |
782 | } | |
783 | EXPORT_SYMBOL_GPL(of_pci_range_parser_init); | |
784 | ||
785 | int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
786 | struct device_node *node) | |
787 | { | |
788 | return parser_init(parser, node, "dma-ranges"); | |
789 | } | |
790 | EXPORT_SYMBOL_GPL(of_pci_dma_range_parser_init); | |
bc5e522e | 791 | #define of_dma_range_parser_init of_pci_dma_range_parser_init |
67ccd2b9 RH |
792 | |
793 | struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, | |
794 | struct of_pci_range *range) | |
795 | { | |
bc5e522e RH |
796 | int na = parser->na; |
797 | int ns = parser->ns; | |
798 | int np = parser->pna + na + ns; | |
88696db0 | 799 | int busflag_na = parser->bus->flag_cells; |
67ccd2b9 RH |
800 | |
801 | if (!range) | |
802 | return NULL; | |
803 | ||
bc5e522e | 804 | if (!parser->range || parser->range + np > parser->end) |
67ccd2b9 RH |
805 | return NULL; |
806 | ||
2f96593e JY |
807 | range->flags = parser->bus->get_flags(parser->range); |
808 | ||
2f96593e | 809 | range->bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na); |
bc5e522e | 810 | |
67ccd2b9 RH |
811 | if (parser->dma) |
812 | range->cpu_addr = of_translate_dma_address(parser->node, | |
813 | parser->range + na); | |
814 | else | |
815 | range->cpu_addr = of_translate_address(parser->node, | |
816 | parser->range + na); | |
4dbf0155 FL |
817 | |
818 | range->parent_bus_addr = of_read_number(parser->range + na, parser->pna); | |
67ccd2b9 RH |
819 | range->size = of_read_number(parser->range + parser->pna + na, ns); |
820 | ||
bc5e522e | 821 | parser->range += np; |
67ccd2b9 RH |
822 | |
823 | /* Now consume following elements while they are contiguous */ | |
bc5e522e RH |
824 | while (parser->range + np <= parser->end) { |
825 | u32 flags = 0; | |
2f96593e | 826 | u64 bus_addr, cpu_addr, size; |
67ccd2b9 | 827 | |
2f96593e JY |
828 | flags = parser->bus->get_flags(parser->range); |
829 | bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na); | |
67ccd2b9 RH |
830 | if (parser->dma) |
831 | cpu_addr = of_translate_dma_address(parser->node, | |
832 | parser->range + na); | |
833 | else | |
834 | cpu_addr = of_translate_address(parser->node, | |
835 | parser->range + na); | |
836 | size = of_read_number(parser->range + parser->pna + na, ns); | |
837 | ||
838 | if (flags != range->flags) | |
839 | break; | |
2f96593e | 840 | if (bus_addr != range->bus_addr + range->size || |
67ccd2b9 RH |
841 | cpu_addr != range->cpu_addr + range->size) |
842 | break; | |
843 | ||
844 | range->size += size; | |
bc5e522e | 845 | parser->range += np; |
67ccd2b9 RH |
846 | } |
847 | ||
848 | return range; | |
849 | } | |
850 | EXPORT_SYMBOL_GPL(of_pci_range_parser_one); | |
851 | ||
65af618d ZY |
852 | static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr, |
853 | u64 size) | |
854 | { | |
855 | u64 taddr; | |
856 | unsigned long port; | |
857 | struct device_node *host; | |
858 | ||
95835a8d MR |
859 | taddr = __of_translate_address(dev, of_get_parent, |
860 | in_addr, "ranges", &host); | |
65af618d ZY |
861 | if (host) { |
862 | /* host-specific port access */ | |
863 | port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size); | |
864 | of_node_put(host); | |
865 | } else { | |
866 | /* memory-mapped I/O range */ | |
867 | port = pci_address_to_pio(taddr); | |
868 | } | |
869 | ||
870 | if (port == (unsigned long)-1) | |
871 | return OF_BAD_ADDR; | |
872 | ||
873 | return port; | |
874 | } | |
875 | ||
e0d07278 | 876 | #ifdef CONFIG_HAS_DMA |
18308c94 | 877 | /** |
e0d07278 | 878 | * of_dma_get_range - Get DMA range info and put it into a map array |
18308c94 | 879 | * @np: device node to get DMA range info |
e0d07278 | 880 | * @map: dma range structure to return |
18308c94 GS |
881 | * |
882 | * Look in bottom up direction for the first "dma-ranges" property | |
e0d07278 JQ |
883 | * and parse it. Put the information into a DMA offset map array. |
884 | * | |
885 | * dma-ranges format: | |
18308c94 GS |
886 | * DMA addr (dma_addr) : naddr cells |
887 | * CPU addr (phys_addr_t) : pna cells | |
888 | * size : nsize cells | |
889 | * | |
e0d07278 JQ |
890 | * It returns -ENODEV if "dma-ranges" property was not found for this |
891 | * device in the DT. | |
18308c94 | 892 | */ |
e0d07278 | 893 | int of_dma_get_range(struct device_node *np, const struct bus_dma_region **map) |
18308c94 | 894 | { |
a5737b21 | 895 | struct device_node *node __free(device_node) = of_node_get(np); |
18308c94 | 896 | const __be32 *ranges = NULL; |
951d4885 | 897 | bool found_dma_ranges = false; |
7a8b64d1 RH |
898 | struct of_range_parser parser; |
899 | struct of_range range; | |
e0d07278 JQ |
900 | struct bus_dma_region *r; |
901 | int len, num_ranges = 0; | |
18308c94 | 902 | |
951d4885 | 903 | while (node) { |
18308c94 GS |
904 | ranges = of_get_property(node, "dma-ranges", &len); |
905 | ||
906 | /* Ignore empty ranges, they imply no translation required */ | |
907 | if (ranges && len > 0) | |
908 | break; | |
909 | ||
951d4885 | 910 | /* Once we find 'dma-ranges', then a missing one is an error */ |
a5737b21 RH |
911 | if (found_dma_ranges && !ranges) |
912 | return -ENODEV; | |
913 | ||
951d4885 RM |
914 | found_dma_ranges = true; |
915 | ||
916 | node = of_get_next_dma_parent(node); | |
18308c94 GS |
917 | } |
918 | ||
951d4885 | 919 | if (!node || !ranges) { |
0d638a07 | 920 | pr_debug("no dma-ranges found for node(%pOF)\n", np); |
a5737b21 | 921 | return -ENODEV; |
18308c94 | 922 | } |
7a8b64d1 | 923 | of_dma_range_parser_init(&parser, node); |
f6933c01 MB |
924 | for_each_of_range(&parser, &range) { |
925 | if (range.cpu_addr == OF_BAD_ADDR) { | |
926 | pr_err("translation of DMA address(%llx) to CPU address failed node(%pOF)\n", | |
927 | range.bus_addr, node); | |
928 | continue; | |
929 | } | |
e0d07278 | 930 | num_ranges++; |
f6933c01 MB |
931 | } |
932 | ||
a5737b21 RH |
933 | if (!num_ranges) |
934 | return -EINVAL; | |
e0d07278 JQ |
935 | |
936 | r = kcalloc(num_ranges + 1, sizeof(*r), GFP_KERNEL); | |
a5737b21 RH |
937 | if (!r) |
938 | return -ENOMEM; | |
7a8b64d1 | 939 | |
e0d07278 | 940 | /* |
f6933c01 MB |
941 | * Record all info in the generic DMA ranges array for struct device, |
942 | * returning an error if we don't find any parsable ranges. | |
e0d07278 JQ |
943 | */ |
944 | *map = r; | |
945 | of_dma_range_parser_init(&parser, node); | |
7a8b64d1 RH |
946 | for_each_of_range(&parser, &range) { |
947 | pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n", | |
948 | range.bus_addr, range.cpu_addr, range.size); | |
f6933c01 | 949 | if (range.cpu_addr == OF_BAD_ADDR) |
f49c7faf | 950 | continue; |
e0d07278 JQ |
951 | r->cpu_start = range.cpu_addr; |
952 | r->dma_start = range.bus_addr; | |
953 | r->size = range.size; | |
e0d07278 | 954 | r++; |
18308c94 | 955 | } |
a5737b21 | 956 | return 0; |
18308c94 | 957 | } |
e0d07278 | 958 | #endif /* CONFIG_HAS_DMA */ |
92ea637e | 959 | |
964db79d NSJ |
960 | /** |
961 | * of_dma_get_max_cpu_address - Gets highest CPU address suitable for DMA | |
962 | * @np: The node to start searching from or NULL to start from the root | |
963 | * | |
964 | * Gets the highest CPU physical address that is addressable by all DMA masters | |
965 | * in the sub-tree pointed by np, or the whole tree if NULL is passed. If no | |
966 | * DMA constrained device is found, it returns PHYS_ADDR_MAX. | |
967 | */ | |
968 | phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np) | |
969 | { | |
970 | phys_addr_t max_cpu_addr = PHYS_ADDR_MAX; | |
971 | struct of_range_parser parser; | |
972 | phys_addr_t subtree_max_addr; | |
973 | struct device_node *child; | |
974 | struct of_range range; | |
975 | const __be32 *ranges; | |
976 | u64 cpu_end = 0; | |
977 | int len; | |
978 | ||
979 | if (!np) | |
980 | np = of_root; | |
981 | ||
982 | ranges = of_get_property(np, "dma-ranges", &len); | |
983 | if (ranges && len) { | |
984 | of_dma_range_parser_init(&parser, np); | |
985 | for_each_of_range(&parser, &range) | |
986 | if (range.cpu_addr + range.size > cpu_end) | |
987 | cpu_end = range.cpu_addr + range.size - 1; | |
988 | ||
989 | if (max_cpu_addr > cpu_end) | |
990 | max_cpu_addr = cpu_end; | |
991 | } | |
992 | ||
993 | for_each_available_child_of_node(np, child) { | |
994 | subtree_max_addr = of_dma_get_max_cpu_address(child); | |
995 | if (max_cpu_addr > subtree_max_addr) | |
996 | max_cpu_addr = subtree_max_addr; | |
997 | } | |
998 | ||
999 | return max_cpu_addr; | |
1000 | } | |
1001 | ||
92ea637e SS |
1002 | /** |
1003 | * of_dma_is_coherent - Check if device is coherent | |
1004 | * @np: device node | |
1005 | * | |
1006 | * It returns true if "dma-coherent" property was found | |
dabf6b36 | 1007 | * for this device in the DT, or if DMA is coherent by |
12b82775 HS |
1008 | * default for OF devices on the current platform and no |
1009 | * "dma-noncoherent" property was found for this device. | |
92ea637e SS |
1010 | */ |
1011 | bool of_dma_is_coherent(struct device_node *np) | |
1012 | { | |
a5737b21 | 1013 | struct device_node *node __free(device_node) = of_node_get(np); |
a5bea04f | 1014 | |
92ea637e | 1015 | while (node) { |
a5737b21 RH |
1016 | if (of_property_read_bool(node, "dma-coherent")) |
1017 | return true; | |
1018 | ||
1019 | if (of_property_read_bool(node, "dma-noncoherent")) | |
1020 | return false; | |
1021 | ||
c60bf3eb | 1022 | node = of_get_next_dma_parent(node); |
92ea637e | 1023 | } |
a5737b21 | 1024 | return dma_default_coherent; |
92ea637e | 1025 | } |
eb3d3ec5 | 1026 | EXPORT_SYMBOL_GPL(of_dma_is_coherent); |
89897f73 HM |
1027 | |
1028 | /** | |
1029 | * of_mmio_is_nonposted - Check if device uses non-posted MMIO | |
1030 | * @np: device node | |
1031 | * | |
1032 | * Returns true if the "nonposted-mmio" property was found for | |
1033 | * the device's bus. | |
89897f73 | 1034 | */ |
ec8c2329 | 1035 | static bool of_mmio_is_nonposted(const struct device_node *np) |
89897f73 | 1036 | { |
a5737b21 | 1037 | struct device_node *parent __free(device_node) = of_get_parent(np); |
89897f73 | 1038 | |
47026c4f KD |
1039 | if (of_property_read_bool(np, "nonposted-mmio")) |
1040 | return true; | |
1041 | ||
1042 | return parent && of_property_read_bool(parent, "nonposted-mmio"); | |
89897f73 | 1043 | } |
5eac0bdc GU |
1044 | |
1045 | static int __of_address_to_resource(struct device_node *dev, int index, int bar_no, | |
1046 | struct resource *r) | |
1047 | { | |
1048 | u64 taddr; | |
1049 | const __be32 *addrp; | |
1050 | u64 size; | |
1051 | unsigned int flags; | |
1052 | const char *name = NULL; | |
1053 | ||
1054 | addrp = __of_get_address(dev, index, bar_no, &size, &flags); | |
1055 | if (addrp == NULL) | |
1056 | return -EINVAL; | |
1057 | ||
1058 | /* Get optional "reg-names" property to add a name to a resource */ | |
1059 | if (index >= 0) | |
1060 | of_property_read_string_index(dev, "reg-names", index, &name); | |
1061 | ||
1062 | if (flags & IORESOURCE_MEM) | |
1063 | taddr = of_translate_address(dev, addrp); | |
1064 | else if (flags & IORESOURCE_IO) | |
1065 | taddr = of_translate_ioport(dev, addrp, size); | |
1066 | else | |
1067 | return -EINVAL; | |
1068 | ||
1069 | if (taddr == OF_BAD_ADDR) | |
1070 | return -EINVAL; | |
1071 | memset(r, 0, sizeof(struct resource)); | |
1072 | ||
1073 | if (of_mmio_is_nonposted(dev)) | |
1074 | flags |= IORESOURCE_MEM_NONPOSTED; | |
1075 | ||
5eac0bdc GU |
1076 | r->flags = flags; |
1077 | r->name = name ? name : dev->full_name; | |
1078 | ||
1a52a094 | 1079 | return __of_address_resource_bounds(r, taddr, size); |
5eac0bdc GU |
1080 | } |
1081 | ||
1082 | /** | |
1083 | * of_address_to_resource - Translate device tree address and return as resource | |
1084 | * @dev: Caller's Device Node | |
1085 | * @index: Index into the array | |
1086 | * @r: Pointer to resource array | |
1087 | * | |
1088 | * Returns -EINVAL if the range cannot be converted to resource. | |
1089 | * | |
1090 | * Note that if your address is a PIO address, the conversion will fail if | |
1091 | * the physical address can't be internally converted to an IO token with | |
1092 | * pci_address_to_pio(), that is because it's either called too early or it | |
1093 | * can't be matched to any host bridge IO space | |
1094 | */ | |
1095 | int of_address_to_resource(struct device_node *dev, int index, | |
1096 | struct resource *r) | |
1097 | { | |
1098 | return __of_address_to_resource(dev, index, -1, r); | |
1099 | } | |
1100 | EXPORT_SYMBOL_GPL(of_address_to_resource); | |
1101 | ||
1102 | int of_pci_address_to_resource(struct device_node *dev, int bar, | |
1103 | struct resource *r) | |
1104 | { | |
1105 | ||
1106 | if (!IS_ENABLED(CONFIG_PCI)) | |
1107 | return -ENOSYS; | |
1108 | ||
1109 | return __of_address_to_resource(dev, -1, bar, r); | |
1110 | } | |
1111 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); | |
1112 | ||
1113 | /** | |
1114 | * of_iomap - Maps the memory mapped IO for a given device_node | |
1115 | * @np: the device whose io range will be mapped | |
1116 | * @index: index of the io range | |
1117 | * | |
1118 | * Returns a pointer to the mapped memory | |
1119 | */ | |
1120 | void __iomem *of_iomap(struct device_node *np, int index) | |
1121 | { | |
1122 | struct resource res; | |
1123 | ||
1124 | if (of_address_to_resource(np, index, &res)) | |
1125 | return NULL; | |
1126 | ||
1127 | if (res.flags & IORESOURCE_MEM_NONPOSTED) | |
1128 | return ioremap_np(res.start, resource_size(&res)); | |
1129 | else | |
1130 | return ioremap(res.start, resource_size(&res)); | |
1131 | } | |
1132 | EXPORT_SYMBOL(of_iomap); | |
1133 | ||
1134 | /* | |
1135 | * of_io_request_and_map - Requests a resource and maps the memory mapped IO | |
1136 | * for a given device_node | |
1137 | * @device: the device whose io range will be mapped | |
1138 | * @index: index of the io range | |
1139 | * @name: name "override" for the memory region request or NULL | |
1140 | * | |
1141 | * Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded | |
1142 | * error code on failure. Usage example: | |
1143 | * | |
1144 | * base = of_io_request_and_map(node, 0, "foo"); | |
1145 | * if (IS_ERR(base)) | |
1146 | * return PTR_ERR(base); | |
1147 | */ | |
1148 | void __iomem *of_io_request_and_map(struct device_node *np, int index, | |
1149 | const char *name) | |
1150 | { | |
1151 | struct resource res; | |
1152 | void __iomem *mem; | |
1153 | ||
1154 | if (of_address_to_resource(np, index, &res)) | |
1155 | return IOMEM_ERR_PTR(-EINVAL); | |
1156 | ||
1157 | if (!name) | |
1158 | name = res.name; | |
1159 | if (!request_mem_region(res.start, resource_size(&res), name)) | |
1160 | return IOMEM_ERR_PTR(-EBUSY); | |
1161 | ||
1162 | if (res.flags & IORESOURCE_MEM_NONPOSTED) | |
1163 | mem = ioremap_np(res.start, resource_size(&res)); | |
1164 | else | |
1165 | mem = ioremap(res.start, resource_size(&res)); | |
1166 | ||
1167 | if (!mem) { | |
1168 | release_mem_region(res.start, resource_size(&res)); | |
1169 | return IOMEM_ERR_PTR(-ENOMEM); | |
1170 | } | |
1171 | ||
1172 | return mem; | |
1173 | } | |
1174 | EXPORT_SYMBOL(of_io_request_and_map); |