Commit | Line | Data |
---|---|---|
af6074fc | 1 | // SPDX-License-Identifier: GPL-2.0 |
606ad42a RH |
2 | #define pr_fmt(fmt) "OF: " fmt |
3 | ||
5019f0b1 | 4 | #include <linux/device.h> |
fcfaab30 | 5 | #include <linux/fwnode.h> |
6b884a8d GL |
6 | #include <linux/io.h> |
7 | #include <linux/ioport.h> | |
65af618d | 8 | #include <linux/logic_pio.h> |
dbbdee94 | 9 | #include <linux/module.h> |
6b884a8d | 10 | #include <linux/of_address.h> |
c5076cfe | 11 | #include <linux/pci.h> |
dbbdee94 | 12 | #include <linux/pci_regs.h> |
41f8bba7 LD |
13 | #include <linux/sizes.h> |
14 | #include <linux/slab.h> | |
dbbdee94 | 15 | #include <linux/string.h> |
e0d07278 | 16 | #include <linux/dma-direct.h> /* for bus_dma_region */ |
6b884a8d | 17 | |
b68ac8dc RM |
18 | #include "of_private.h" |
19 | ||
dbbdee94 GL |
20 | /* Max address size we deal with */ |
21 | #define OF_MAX_ADDR_CELLS 4 | |
5d61b165 SW |
22 | #define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) |
23 | #define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0) | |
dbbdee94 GL |
24 | |
25 | static struct of_bus *of_match_bus(struct device_node *np); | |
0131d897 SAS |
26 | static int __of_address_to_resource(struct device_node *dev, |
27 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 28 | const char *name, struct resource *r); |
dbbdee94 GL |
29 | |
30 | /* Debug utility */ | |
31 | #ifdef DEBUG | |
0131d897 | 32 | static void of_dump_addr(const char *s, const __be32 *addr, int na) |
dbbdee94 | 33 | { |
606ad42a | 34 | pr_debug("%s", s); |
dbbdee94 | 35 | while (na--) |
606ad42a RH |
36 | pr_cont(" %08x", be32_to_cpu(*(addr++))); |
37 | pr_cont("\n"); | |
dbbdee94 GL |
38 | } |
39 | #else | |
0131d897 | 40 | static void of_dump_addr(const char *s, const __be32 *addr, int na) { } |
dbbdee94 GL |
41 | #endif |
42 | ||
43 | /* Callbacks for bus specific translators */ | |
44 | struct of_bus { | |
45 | const char *name; | |
46 | const char *addresses; | |
47 | int (*match)(struct device_node *parent); | |
48 | void (*count_cells)(struct device_node *child, | |
49 | int *addrc, int *sizec); | |
47b1e689 | 50 | u64 (*map)(__be32 *addr, const __be32 *range, |
dbbdee94 | 51 | int na, int ns, int pna); |
47b1e689 | 52 | int (*translate)(__be32 *addr, u64 offset, int na); |
2f96593e | 53 | bool has_flags; |
0131d897 | 54 | unsigned int (*get_flags)(const __be32 *addr); |
dbbdee94 GL |
55 | }; |
56 | ||
57 | /* | |
58 | * Default translator (generic bus) | |
59 | */ | |
60 | ||
61 | static void of_bus_default_count_cells(struct device_node *dev, | |
62 | int *addrc, int *sizec) | |
63 | { | |
64 | if (addrc) | |
65 | *addrc = of_n_addr_cells(dev); | |
66 | if (sizec) | |
67 | *sizec = of_n_size_cells(dev); | |
68 | } | |
69 | ||
47b1e689 | 70 | static u64 of_bus_default_map(__be32 *addr, const __be32 *range, |
dbbdee94 GL |
71 | int na, int ns, int pna) |
72 | { | |
73 | u64 cp, s, da; | |
74 | ||
75 | cp = of_read_number(range, na); | |
76 | s = of_read_number(range + na + pna, ns); | |
77 | da = of_read_number(addr, na); | |
78 | ||
606ad42a | 79 | pr_debug("default map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
80 | (unsigned long long)cp, (unsigned long long)s, |
81 | (unsigned long long)da); | |
82 | ||
83 | if (da < cp || da >= (cp + s)) | |
84 | return OF_BAD_ADDR; | |
85 | return da - cp; | |
86 | } | |
87 | ||
47b1e689 | 88 | static int of_bus_default_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
89 | { |
90 | u64 a = of_read_number(addr, na); | |
91 | memset(addr, 0, na * 4); | |
92 | a += offset; | |
93 | if (na > 1) | |
154063a9 GL |
94 | addr[na - 2] = cpu_to_be32(a >> 32); |
95 | addr[na - 1] = cpu_to_be32(a & 0xffffffffu); | |
dbbdee94 GL |
96 | |
97 | return 0; | |
98 | } | |
99 | ||
0131d897 | 100 | static unsigned int of_bus_default_get_flags(const __be32 *addr) |
dbbdee94 GL |
101 | { |
102 | return IORESOURCE_MEM; | |
103 | } | |
104 | ||
0fc0ead3 | 105 | #ifdef CONFIG_PCI |
67ccd2b9 RH |
106 | static unsigned int of_bus_pci_get_flags(const __be32 *addr) |
107 | { | |
108 | unsigned int flags = 0; | |
109 | u32 w = be32_to_cpup(addr); | |
110 | ||
111 | if (!IS_ENABLED(CONFIG_PCI)) | |
112 | return 0; | |
113 | ||
114 | switch((w >> 24) & 0x03) { | |
115 | case 0x01: | |
116 | flags |= IORESOURCE_IO; | |
117 | break; | |
118 | case 0x02: /* 32 bits */ | |
119 | case 0x03: /* 64 bits */ | |
120 | flags |= IORESOURCE_MEM; | |
121 | break; | |
122 | } | |
123 | if (w & 0x40000000) | |
124 | flags |= IORESOURCE_PREFETCH; | |
125 | return flags; | |
126 | } | |
127 | ||
dbbdee94 GL |
128 | /* |
129 | * PCI bus specific translator | |
130 | */ | |
131 | ||
d1ac0002 MZ |
132 | static bool of_node_is_pcie(struct device_node *np) |
133 | { | |
134 | bool is_pcie = of_node_name_eq(np, "pcie"); | |
135 | ||
136 | if (is_pcie) | |
137 | pr_warn_once("%pOF: Missing device_type\n", np); | |
138 | ||
139 | return is_pcie; | |
140 | } | |
141 | ||
dbbdee94 GL |
142 | static int of_bus_pci_match(struct device_node *np) |
143 | { | |
6dd18e46 | 144 | /* |
14e2abb7 | 145 | * "pciex" is PCI Express |
6dd18e46 BH |
146 | * "vci" is for the /chaos bridge on 1st-gen PCI powermacs |
147 | * "ht" is hypertransport | |
d1ac0002 MZ |
148 | * |
149 | * If none of the device_type match, and that the node name is | |
150 | * "pcie", accept the device as PCI (with a warning). | |
6dd18e46 | 151 | */ |
e8b1dee2 | 152 | return of_node_is_type(np, "pci") || of_node_is_type(np, "pciex") || |
d1ac0002 MZ |
153 | of_node_is_type(np, "vci") || of_node_is_type(np, "ht") || |
154 | of_node_is_pcie(np); | |
dbbdee94 GL |
155 | } |
156 | ||
157 | static void of_bus_pci_count_cells(struct device_node *np, | |
158 | int *addrc, int *sizec) | |
159 | { | |
160 | if (addrc) | |
161 | *addrc = 3; | |
162 | if (sizec) | |
163 | *sizec = 2; | |
164 | } | |
165 | ||
47b1e689 | 166 | static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 167 | int pna) |
dbbdee94 GL |
168 | { |
169 | u64 cp, s, da; | |
170 | unsigned int af, rf; | |
171 | ||
172 | af = of_bus_pci_get_flags(addr); | |
173 | rf = of_bus_pci_get_flags(range); | |
174 | ||
175 | /* Check address type match */ | |
176 | if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO)) | |
177 | return OF_BAD_ADDR; | |
178 | ||
179 | /* Read address values, skipping high cell */ | |
180 | cp = of_read_number(range + 1, na - 1); | |
181 | s = of_read_number(range + na + pna, ns); | |
182 | da = of_read_number(addr + 1, na - 1); | |
183 | ||
606ad42a | 184 | pr_debug("PCI map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
185 | (unsigned long long)cp, (unsigned long long)s, |
186 | (unsigned long long)da); | |
187 | ||
188 | if (da < cp || da >= (cp + s)) | |
189 | return OF_BAD_ADDR; | |
190 | return da - cp; | |
191 | } | |
192 | ||
47b1e689 | 193 | static int of_bus_pci_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
194 | { |
195 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
196 | } | |
197 | ||
0131d897 | 198 | const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size, |
dbbdee94 GL |
199 | unsigned int *flags) |
200 | { | |
a9fadeef | 201 | const __be32 *prop; |
dbbdee94 GL |
202 | unsigned int psize; |
203 | struct device_node *parent; | |
204 | struct of_bus *bus; | |
205 | int onesize, i, na, ns; | |
206 | ||
207 | /* Get parent & match bus type */ | |
208 | parent = of_get_parent(dev); | |
209 | if (parent == NULL) | |
210 | return NULL; | |
211 | bus = of_match_bus(parent); | |
212 | if (strcmp(bus->name, "pci")) { | |
213 | of_node_put(parent); | |
214 | return NULL; | |
215 | } | |
216 | bus->count_cells(dev, &na, &ns); | |
217 | of_node_put(parent); | |
5d61b165 | 218 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
219 | return NULL; |
220 | ||
221 | /* Get "reg" or "assigned-addresses" property */ | |
222 | prop = of_get_property(dev, bus->addresses, &psize); | |
223 | if (prop == NULL) | |
224 | return NULL; | |
225 | psize /= 4; | |
226 | ||
227 | onesize = na + ns; | |
154063a9 GL |
228 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) { |
229 | u32 val = be32_to_cpu(prop[0]); | |
230 | if ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) { | |
dbbdee94 GL |
231 | if (size) |
232 | *size = of_read_number(prop + na, ns); | |
233 | if (flags) | |
234 | *flags = bus->get_flags(prop); | |
235 | return prop; | |
236 | } | |
154063a9 | 237 | } |
dbbdee94 GL |
238 | return NULL; |
239 | } | |
240 | EXPORT_SYMBOL(of_get_pci_address); | |
241 | ||
242 | int of_pci_address_to_resource(struct device_node *dev, int bar, | |
243 | struct resource *r) | |
244 | { | |
0131d897 | 245 | const __be32 *addrp; |
dbbdee94 GL |
246 | u64 size; |
247 | unsigned int flags; | |
248 | ||
249 | addrp = of_get_pci_address(dev, bar, &size, &flags); | |
250 | if (addrp == NULL) | |
251 | return -EINVAL; | |
35f3da32 | 252 | return __of_address_to_resource(dev, addrp, size, flags, NULL, r); |
dbbdee94 GL |
253 | } |
254 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); | |
29b635c0 | 255 | |
0b0b0893 LD |
256 | /* |
257 | * of_pci_range_to_resource - Create a resource from an of_pci_range | |
258 | * @range: the PCI range that describes the resource | |
259 | * @np: device node where the range belongs to | |
260 | * @res: pointer to a valid resource that will be updated to | |
261 | * reflect the values contained in the range. | |
262 | * | |
263 | * Returns EINVAL if the range cannot be converted to resource. | |
264 | * | |
265 | * Note that if the range is an IO range, the resource will be converted | |
266 | * using pci_address_to_pio() which can fail if it is called too early or | |
267 | * if the range cannot be matched to any host bridge IO space (our case here). | |
268 | * To guard against that we try to register the IO range first. | |
269 | * If that fails we know that pci_address_to_pio() will do too. | |
270 | */ | |
271 | int of_pci_range_to_resource(struct of_pci_range *range, | |
272 | struct device_node *np, struct resource *res) | |
83bbde1c | 273 | { |
0b0b0893 | 274 | int err; |
83bbde1c | 275 | res->flags = range->flags; |
83bbde1c LD |
276 | res->parent = res->child = res->sibling = NULL; |
277 | res->name = np->full_name; | |
0b0b0893 LD |
278 | |
279 | if (res->flags & IORESOURCE_IO) { | |
280 | unsigned long port; | |
fcfaab30 GP |
281 | err = pci_register_io_range(&np->fwnode, range->cpu_addr, |
282 | range->size); | |
0b0b0893 LD |
283 | if (err) |
284 | goto invalid_range; | |
285 | port = pci_address_to_pio(range->cpu_addr); | |
286 | if (port == (unsigned long)-1) { | |
287 | err = -EINVAL; | |
288 | goto invalid_range; | |
289 | } | |
290 | res->start = port; | |
291 | } else { | |
4af97106 PF |
292 | if ((sizeof(resource_size_t) < 8) && |
293 | upper_32_bits(range->cpu_addr)) { | |
294 | err = -EINVAL; | |
295 | goto invalid_range; | |
296 | } | |
297 | ||
0b0b0893 LD |
298 | res->start = range->cpu_addr; |
299 | } | |
300 | res->end = res->start + range->size - 1; | |
301 | return 0; | |
302 | ||
303 | invalid_range: | |
304 | res->start = (resource_size_t)OF_BAD_ADDR; | |
305 | res->end = (resource_size_t)OF_BAD_ADDR; | |
306 | return err; | |
83bbde1c | 307 | } |
bf6681ea | 308 | EXPORT_SYMBOL(of_pci_range_to_resource); |
dbbdee94 GL |
309 | #endif /* CONFIG_PCI */ |
310 | ||
311 | /* | |
312 | * ISA bus specific translator | |
313 | */ | |
314 | ||
315 | static int of_bus_isa_match(struct device_node *np) | |
316 | { | |
b3e46d1a | 317 | return of_node_name_eq(np, "isa"); |
dbbdee94 GL |
318 | } |
319 | ||
320 | static void of_bus_isa_count_cells(struct device_node *child, | |
321 | int *addrc, int *sizec) | |
322 | { | |
323 | if (addrc) | |
324 | *addrc = 2; | |
325 | if (sizec) | |
326 | *sizec = 1; | |
327 | } | |
328 | ||
47b1e689 | 329 | static u64 of_bus_isa_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 330 | int pna) |
dbbdee94 GL |
331 | { |
332 | u64 cp, s, da; | |
333 | ||
334 | /* Check address type match */ | |
0131d897 | 335 | if ((addr[0] ^ range[0]) & cpu_to_be32(1)) |
dbbdee94 GL |
336 | return OF_BAD_ADDR; |
337 | ||
338 | /* Read address values, skipping high cell */ | |
339 | cp = of_read_number(range + 1, na - 1); | |
340 | s = of_read_number(range + na + pna, ns); | |
341 | da = of_read_number(addr + 1, na - 1); | |
342 | ||
606ad42a | 343 | pr_debug("ISA map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
344 | (unsigned long long)cp, (unsigned long long)s, |
345 | (unsigned long long)da); | |
346 | ||
347 | if (da < cp || da >= (cp + s)) | |
348 | return OF_BAD_ADDR; | |
349 | return da - cp; | |
350 | } | |
351 | ||
47b1e689 | 352 | static int of_bus_isa_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
353 | { |
354 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
355 | } | |
356 | ||
0131d897 | 357 | static unsigned int of_bus_isa_get_flags(const __be32 *addr) |
dbbdee94 GL |
358 | { |
359 | unsigned int flags = 0; | |
0131d897 | 360 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
361 | |
362 | if (w & 1) | |
363 | flags |= IORESOURCE_IO; | |
364 | else | |
365 | flags |= IORESOURCE_MEM; | |
366 | return flags; | |
367 | } | |
368 | ||
369 | /* | |
370 | * Array of bus specific translators | |
371 | */ | |
372 | ||
373 | static struct of_bus of_busses[] = { | |
4670d610 | 374 | #ifdef CONFIG_PCI |
dbbdee94 GL |
375 | /* PCI */ |
376 | { | |
377 | .name = "pci", | |
378 | .addresses = "assigned-addresses", | |
379 | .match = of_bus_pci_match, | |
380 | .count_cells = of_bus_pci_count_cells, | |
381 | .map = of_bus_pci_map, | |
382 | .translate = of_bus_pci_translate, | |
2f96593e | 383 | .has_flags = true, |
dbbdee94 GL |
384 | .get_flags = of_bus_pci_get_flags, |
385 | }, | |
4670d610 | 386 | #endif /* CONFIG_PCI */ |
dbbdee94 GL |
387 | /* ISA */ |
388 | { | |
389 | .name = "isa", | |
390 | .addresses = "reg", | |
391 | .match = of_bus_isa_match, | |
392 | .count_cells = of_bus_isa_count_cells, | |
393 | .map = of_bus_isa_map, | |
394 | .translate = of_bus_isa_translate, | |
2f96593e | 395 | .has_flags = true, |
dbbdee94 GL |
396 | .get_flags = of_bus_isa_get_flags, |
397 | }, | |
398 | /* Default */ | |
399 | { | |
400 | .name = "default", | |
401 | .addresses = "reg", | |
402 | .match = NULL, | |
403 | .count_cells = of_bus_default_count_cells, | |
404 | .map = of_bus_default_map, | |
405 | .translate = of_bus_default_translate, | |
406 | .get_flags = of_bus_default_get_flags, | |
407 | }, | |
408 | }; | |
409 | ||
410 | static struct of_bus *of_match_bus(struct device_node *np) | |
411 | { | |
412 | int i; | |
413 | ||
414 | for (i = 0; i < ARRAY_SIZE(of_busses); i++) | |
415 | if (!of_busses[i].match || of_busses[i].match(np)) | |
416 | return &of_busses[i]; | |
417 | BUG(); | |
418 | return NULL; | |
419 | } | |
420 | ||
41d94893 | 421 | static int of_empty_ranges_quirk(struct device_node *np) |
746c9e9f BH |
422 | { |
423 | if (IS_ENABLED(CONFIG_PPC)) { | |
41d94893 | 424 | /* To save cycles, we cache the result for global "Mac" setting */ |
746c9e9f BH |
425 | static int quirk_state = -1; |
426 | ||
41d94893 BH |
427 | /* PA-SEMI sdc DT bug */ |
428 | if (of_device_is_compatible(np, "1682m-sdc")) | |
429 | return true; | |
430 | ||
431 | /* Make quirk cached */ | |
746c9e9f BH |
432 | if (quirk_state < 0) |
433 | quirk_state = | |
434 | of_machine_is_compatible("Power Macintosh") || | |
435 | of_machine_is_compatible("MacRISC"); | |
436 | return quirk_state; | |
437 | } | |
438 | return false; | |
439 | } | |
440 | ||
dbbdee94 | 441 | static int of_translate_one(struct device_node *parent, struct of_bus *bus, |
47b1e689 | 442 | struct of_bus *pbus, __be32 *addr, |
dbbdee94 GL |
443 | int na, int ns, int pna, const char *rprop) |
444 | { | |
0131d897 | 445 | const __be32 *ranges; |
dbbdee94 GL |
446 | unsigned int rlen; |
447 | int rone; | |
448 | u64 offset = OF_BAD_ADDR; | |
449 | ||
ba85edbe MY |
450 | /* |
451 | * Normally, an absence of a "ranges" property means we are | |
dbbdee94 | 452 | * crossing a non-translatable boundary, and thus the addresses |
ba85edbe | 453 | * below the current cannot be converted to CPU physical ones. |
dbbdee94 GL |
454 | * Unfortunately, while this is very clear in the spec, it's not |
455 | * what Apple understood, and they do have things like /uni-n or | |
456 | * /ht nodes with no "ranges" property and a lot of perfectly | |
457 | * useable mapped devices below them. Thus we treat the absence of | |
458 | * "ranges" as equivalent to an empty "ranges" property which means | |
459 | * a 1:1 translation at that level. It's up to the caller not to try | |
460 | * to translate addresses that aren't supposed to be translated in | |
461 | * the first place. --BenH. | |
3930f294 GL |
462 | * |
463 | * As far as we know, this damage only exists on Apple machines, so | |
464 | * This code is only enabled on powerpc. --gcl | |
81db12ee RH |
465 | * |
466 | * This quirk also applies for 'dma-ranges' which frequently exist in | |
467 | * child nodes without 'dma-ranges' in the parent nodes. --RobH | |
dbbdee94 GL |
468 | */ |
469 | ranges = of_get_property(parent, rprop, &rlen); | |
81db12ee RH |
470 | if (ranges == NULL && !of_empty_ranges_quirk(parent) && |
471 | strcmp(rprop, "dma-ranges")) { | |
606ad42a | 472 | pr_debug("no ranges; cannot translate\n"); |
3930f294 GL |
473 | return 1; |
474 | } | |
dbbdee94 GL |
475 | if (ranges == NULL || rlen == 0) { |
476 | offset = of_read_number(addr, na); | |
477 | memset(addr, 0, pna * 4); | |
606ad42a | 478 | pr_debug("empty ranges; 1:1 translation\n"); |
dbbdee94 GL |
479 | goto finish; |
480 | } | |
481 | ||
606ad42a | 482 | pr_debug("walking ranges...\n"); |
dbbdee94 GL |
483 | |
484 | /* Now walk through the ranges */ | |
485 | rlen /= 4; | |
486 | rone = na + pna + ns; | |
487 | for (; rlen >= rone; rlen -= rone, ranges += rone) { | |
488 | offset = bus->map(addr, ranges, na, ns, pna); | |
489 | if (offset != OF_BAD_ADDR) | |
490 | break; | |
491 | } | |
492 | if (offset == OF_BAD_ADDR) { | |
606ad42a | 493 | pr_debug("not found !\n"); |
dbbdee94 GL |
494 | return 1; |
495 | } | |
496 | memcpy(addr, ranges + na, 4 * pna); | |
497 | ||
498 | finish: | |
606ad42a RH |
499 | of_dump_addr("parent translation for:", addr, pna); |
500 | pr_debug("with offset: %llx\n", (unsigned long long)offset); | |
dbbdee94 GL |
501 | |
502 | /* Translate it into parent bus space */ | |
503 | return pbus->translate(addr, offset, pna); | |
504 | } | |
505 | ||
506 | /* | |
507 | * Translate an address from the device-tree into a CPU physical address, | |
508 | * this walks up the tree and applies the various bus mappings on the | |
509 | * way. | |
510 | * | |
511 | * Note: We consider that crossing any level with #size-cells == 0 to mean | |
512 | * that translation is impossible (that is we are not dealing with a value | |
513 | * that can be mapped to a cpu physical address). This is not really specified | |
514 | * that way, but this is traditionally the way IBM at least do things | |
65af618d ZY |
515 | * |
516 | * Whenever the translation fails, the *host pointer will be set to the | |
517 | * device that had registered logical PIO mapping, and the return code is | |
518 | * relative to that node. | |
dbbdee94 | 519 | */ |
47b1e689 | 520 | static u64 __of_translate_address(struct device_node *dev, |
95835a8d | 521 | struct device_node *(*get_parent)(const struct device_node *), |
65af618d ZY |
522 | const __be32 *in_addr, const char *rprop, |
523 | struct device_node **host) | |
dbbdee94 GL |
524 | { |
525 | struct device_node *parent = NULL; | |
526 | struct of_bus *bus, *pbus; | |
47b1e689 | 527 | __be32 addr[OF_MAX_ADDR_CELLS]; |
dbbdee94 GL |
528 | int na, ns, pna, pns; |
529 | u64 result = OF_BAD_ADDR; | |
530 | ||
0d638a07 | 531 | pr_debug("** translation for device %pOF **\n", dev); |
dbbdee94 GL |
532 | |
533 | /* Increase refcount at current level */ | |
534 | of_node_get(dev); | |
535 | ||
65af618d | 536 | *host = NULL; |
dbbdee94 | 537 | /* Get parent & match bus type */ |
95835a8d | 538 | parent = get_parent(dev); |
dbbdee94 GL |
539 | if (parent == NULL) |
540 | goto bail; | |
541 | bus = of_match_bus(parent); | |
542 | ||
59f5ca48 | 543 | /* Count address cells & copy address locally */ |
dbbdee94 GL |
544 | bus->count_cells(dev, &na, &ns); |
545 | if (!OF_CHECK_COUNTS(na, ns)) { | |
0d638a07 | 546 | pr_debug("Bad cell count for %pOF\n", dev); |
dbbdee94 GL |
547 | goto bail; |
548 | } | |
549 | memcpy(addr, in_addr, na * 4); | |
550 | ||
0d638a07 RH |
551 | pr_debug("bus is %s (na=%d, ns=%d) on %pOF\n", |
552 | bus->name, na, ns, parent); | |
606ad42a | 553 | of_dump_addr("translating address:", addr, na); |
dbbdee94 GL |
554 | |
555 | /* Translate */ | |
556 | for (;;) { | |
65af618d ZY |
557 | struct logic_pio_hwaddr *iorange; |
558 | ||
dbbdee94 GL |
559 | /* Switch to parent bus */ |
560 | of_node_put(dev); | |
561 | dev = parent; | |
95835a8d | 562 | parent = get_parent(dev); |
dbbdee94 GL |
563 | |
564 | /* If root, we have finished */ | |
565 | if (parent == NULL) { | |
606ad42a | 566 | pr_debug("reached root node\n"); |
dbbdee94 GL |
567 | result = of_read_number(addr, na); |
568 | break; | |
569 | } | |
570 | ||
65af618d ZY |
571 | /* |
572 | * For indirectIO device which has no ranges property, get | |
573 | * the address from reg directly. | |
574 | */ | |
575 | iorange = find_io_range_by_fwnode(&dev->fwnode); | |
576 | if (iorange && (iorange->flags != LOGIC_PIO_CPU_MMIO)) { | |
577 | result = of_read_number(addr + 1, na - 1); | |
578 | pr_debug("indirectIO matched(%pOF) 0x%llx\n", | |
579 | dev, result); | |
580 | *host = of_node_get(dev); | |
581 | break; | |
582 | } | |
583 | ||
dbbdee94 GL |
584 | /* Get new parent bus and counts */ |
585 | pbus = of_match_bus(parent); | |
586 | pbus->count_cells(dev, &pna, &pns); | |
587 | if (!OF_CHECK_COUNTS(pna, pns)) { | |
0d638a07 | 588 | pr_err("Bad cell count for %pOF\n", dev); |
dbbdee94 GL |
589 | break; |
590 | } | |
591 | ||
0d638a07 RH |
592 | pr_debug("parent bus is %s (na=%d, ns=%d) on %pOF\n", |
593 | pbus->name, pna, pns, parent); | |
dbbdee94 GL |
594 | |
595 | /* Apply bus translation */ | |
596 | if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) | |
597 | break; | |
598 | ||
599 | /* Complete the move up one level */ | |
600 | na = pna; | |
601 | ns = pns; | |
602 | bus = pbus; | |
603 | ||
606ad42a | 604 | of_dump_addr("one level translation:", addr, na); |
dbbdee94 GL |
605 | } |
606 | bail: | |
607 | of_node_put(parent); | |
608 | of_node_put(dev); | |
609 | ||
610 | return result; | |
611 | } | |
612 | ||
0131d897 | 613 | u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 614 | { |
65af618d ZY |
615 | struct device_node *host; |
616 | u64 ret; | |
617 | ||
95835a8d MR |
618 | ret = __of_translate_address(dev, of_get_parent, |
619 | in_addr, "ranges", &host); | |
65af618d ZY |
620 | if (host) { |
621 | of_node_put(host); | |
622 | return OF_BAD_ADDR; | |
623 | } | |
624 | ||
625 | return ret; | |
dbbdee94 GL |
626 | } |
627 | EXPORT_SYMBOL(of_translate_address); | |
628 | ||
f83a6e5d MR |
629 | static struct device_node *__of_get_dma_parent(const struct device_node *np) |
630 | { | |
631 | struct of_phandle_args args; | |
632 | int ret, index; | |
633 | ||
634 | index = of_property_match_string(np, "interconnect-names", "dma-mem"); | |
635 | if (index < 0) | |
636 | return of_get_parent(np); | |
637 | ||
638 | ret = of_parse_phandle_with_args(np, "interconnects", | |
639 | "#interconnect-cells", | |
640 | index, &args); | |
641 | if (ret < 0) | |
642 | return of_get_parent(np); | |
643 | ||
644 | return of_node_get(args.np); | |
645 | } | |
646 | ||
862ab557 RM |
647 | static struct device_node *of_get_next_dma_parent(struct device_node *np) |
648 | { | |
649 | struct device_node *parent; | |
650 | ||
651 | parent = __of_get_dma_parent(np); | |
652 | of_node_put(np); | |
653 | ||
654 | return parent; | |
655 | } | |
656 | ||
0131d897 | 657 | u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 658 | { |
65af618d ZY |
659 | struct device_node *host; |
660 | u64 ret; | |
661 | ||
f83a6e5d | 662 | ret = __of_translate_address(dev, __of_get_dma_parent, |
95835a8d | 663 | in_addr, "dma-ranges", &host); |
65af618d ZY |
664 | |
665 | if (host) { | |
666 | of_node_put(host); | |
667 | return OF_BAD_ADDR; | |
668 | } | |
669 | ||
670 | return ret; | |
dbbdee94 GL |
671 | } |
672 | EXPORT_SYMBOL(of_translate_dma_address); | |
673 | ||
0131d897 | 674 | const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, |
dbbdee94 GL |
675 | unsigned int *flags) |
676 | { | |
0131d897 | 677 | const __be32 *prop; |
dbbdee94 GL |
678 | unsigned int psize; |
679 | struct device_node *parent; | |
680 | struct of_bus *bus; | |
681 | int onesize, i, na, ns; | |
682 | ||
683 | /* Get parent & match bus type */ | |
684 | parent = of_get_parent(dev); | |
685 | if (parent == NULL) | |
686 | return NULL; | |
687 | bus = of_match_bus(parent); | |
688 | bus->count_cells(dev, &na, &ns); | |
689 | of_node_put(parent); | |
5d61b165 | 690 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
691 | return NULL; |
692 | ||
693 | /* Get "reg" or "assigned-addresses" property */ | |
694 | prop = of_get_property(dev, bus->addresses, &psize); | |
695 | if (prop == NULL) | |
696 | return NULL; | |
697 | psize /= 4; | |
698 | ||
699 | onesize = na + ns; | |
700 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) | |
701 | if (i == index) { | |
702 | if (size) | |
703 | *size = of_read_number(prop + na, ns); | |
704 | if (flags) | |
705 | *flags = bus->get_flags(prop); | |
706 | return prop; | |
707 | } | |
708 | return NULL; | |
709 | } | |
710 | EXPORT_SYMBOL(of_get_address); | |
711 | ||
67ccd2b9 RH |
712 | static int parser_init(struct of_pci_range_parser *parser, |
713 | struct device_node *node, const char *name) | |
714 | { | |
67ccd2b9 RH |
715 | int rlen; |
716 | ||
717 | parser->node = node; | |
718 | parser->pna = of_n_addr_cells(node); | |
bc5e522e RH |
719 | parser->na = of_bus_n_addr_cells(node); |
720 | parser->ns = of_bus_n_size_cells(node); | |
67ccd2b9 | 721 | parser->dma = !strcmp(name, "dma-ranges"); |
2f96593e | 722 | parser->bus = of_match_bus(node); |
67ccd2b9 RH |
723 | |
724 | parser->range = of_get_property(node, name, &rlen); | |
725 | if (parser->range == NULL) | |
726 | return -ENOENT; | |
727 | ||
728 | parser->end = parser->range + rlen / sizeof(__be32); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | int of_pci_range_parser_init(struct of_pci_range_parser *parser, | |
734 | struct device_node *node) | |
735 | { | |
736 | return parser_init(parser, node, "ranges"); | |
737 | } | |
738 | EXPORT_SYMBOL_GPL(of_pci_range_parser_init); | |
739 | ||
740 | int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
741 | struct device_node *node) | |
742 | { | |
743 | return parser_init(parser, node, "dma-ranges"); | |
744 | } | |
745 | EXPORT_SYMBOL_GPL(of_pci_dma_range_parser_init); | |
bc5e522e | 746 | #define of_dma_range_parser_init of_pci_dma_range_parser_init |
67ccd2b9 RH |
747 | |
748 | struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, | |
749 | struct of_pci_range *range) | |
750 | { | |
bc5e522e RH |
751 | int na = parser->na; |
752 | int ns = parser->ns; | |
753 | int np = parser->pna + na + ns; | |
2f96593e | 754 | int busflag_na = 0; |
67ccd2b9 RH |
755 | |
756 | if (!range) | |
757 | return NULL; | |
758 | ||
bc5e522e | 759 | if (!parser->range || parser->range + np > parser->end) |
67ccd2b9 RH |
760 | return NULL; |
761 | ||
2f96593e JY |
762 | range->flags = parser->bus->get_flags(parser->range); |
763 | ||
764 | /* A extra cell for resource flags */ | |
765 | if (parser->bus->has_flags) | |
766 | busflag_na = 1; | |
bc5e522e | 767 | |
2f96593e | 768 | range->bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na); |
bc5e522e | 769 | |
67ccd2b9 RH |
770 | if (parser->dma) |
771 | range->cpu_addr = of_translate_dma_address(parser->node, | |
772 | parser->range + na); | |
773 | else | |
774 | range->cpu_addr = of_translate_address(parser->node, | |
775 | parser->range + na); | |
776 | range->size = of_read_number(parser->range + parser->pna + na, ns); | |
777 | ||
bc5e522e | 778 | parser->range += np; |
67ccd2b9 RH |
779 | |
780 | /* Now consume following elements while they are contiguous */ | |
bc5e522e RH |
781 | while (parser->range + np <= parser->end) { |
782 | u32 flags = 0; | |
2f96593e | 783 | u64 bus_addr, cpu_addr, size; |
67ccd2b9 | 784 | |
2f96593e JY |
785 | flags = parser->bus->get_flags(parser->range); |
786 | bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na); | |
67ccd2b9 RH |
787 | if (parser->dma) |
788 | cpu_addr = of_translate_dma_address(parser->node, | |
789 | parser->range + na); | |
790 | else | |
791 | cpu_addr = of_translate_address(parser->node, | |
792 | parser->range + na); | |
793 | size = of_read_number(parser->range + parser->pna + na, ns); | |
794 | ||
795 | if (flags != range->flags) | |
796 | break; | |
2f96593e | 797 | if (bus_addr != range->bus_addr + range->size || |
67ccd2b9 RH |
798 | cpu_addr != range->cpu_addr + range->size) |
799 | break; | |
800 | ||
801 | range->size += size; | |
bc5e522e | 802 | parser->range += np; |
67ccd2b9 RH |
803 | } |
804 | ||
805 | return range; | |
806 | } | |
807 | EXPORT_SYMBOL_GPL(of_pci_range_parser_one); | |
808 | ||
65af618d ZY |
809 | static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr, |
810 | u64 size) | |
811 | { | |
812 | u64 taddr; | |
813 | unsigned long port; | |
814 | struct device_node *host; | |
815 | ||
95835a8d MR |
816 | taddr = __of_translate_address(dev, of_get_parent, |
817 | in_addr, "ranges", &host); | |
65af618d ZY |
818 | if (host) { |
819 | /* host-specific port access */ | |
820 | port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size); | |
821 | of_node_put(host); | |
822 | } else { | |
823 | /* memory-mapped I/O range */ | |
824 | port = pci_address_to_pio(taddr); | |
825 | } | |
826 | ||
827 | if (port == (unsigned long)-1) | |
828 | return OF_BAD_ADDR; | |
829 | ||
830 | return port; | |
831 | } | |
832 | ||
0131d897 SAS |
833 | static int __of_address_to_resource(struct device_node *dev, |
834 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 835 | const char *name, struct resource *r) |
1f5bef30 GL |
836 | { |
837 | u64 taddr; | |
838 | ||
65af618d ZY |
839 | if (flags & IORESOURCE_MEM) |
840 | taddr = of_translate_address(dev, addrp); | |
841 | else if (flags & IORESOURCE_IO) | |
842 | taddr = of_translate_ioport(dev, addrp, size); | |
843 | else | |
1f5bef30 | 844 | return -EINVAL; |
65af618d | 845 | |
1f5bef30 GL |
846 | if (taddr == OF_BAD_ADDR) |
847 | return -EINVAL; | |
848 | memset(r, 0, sizeof(struct resource)); | |
65af618d ZY |
849 | |
850 | r->start = taddr; | |
851 | r->end = taddr + size - 1; | |
1f5bef30 | 852 | r->flags = flags; |
35f3da32 BC |
853 | r->name = name ? name : dev->full_name; |
854 | ||
1f5bef30 GL |
855 | return 0; |
856 | } | |
857 | ||
858 | /** | |
859 | * of_address_to_resource - Translate device tree address and return as resource | |
860 | * | |
861 | * Note that if your address is a PIO address, the conversion will fail if | |
862 | * the physical address can't be internally converted to an IO token with | |
7602f422 | 863 | * pci_address_to_pio(), that is because it's either called too early or it |
1f5bef30 GL |
864 | * can't be matched to any host bridge IO space |
865 | */ | |
866 | int of_address_to_resource(struct device_node *dev, int index, | |
867 | struct resource *r) | |
868 | { | |
0131d897 | 869 | const __be32 *addrp; |
1f5bef30 GL |
870 | u64 size; |
871 | unsigned int flags; | |
35f3da32 | 872 | const char *name = NULL; |
1f5bef30 GL |
873 | |
874 | addrp = of_get_address(dev, index, &size, &flags); | |
875 | if (addrp == NULL) | |
876 | return -EINVAL; | |
35f3da32 BC |
877 | |
878 | /* Get optional "reg-names" property to add a name to a resource */ | |
879 | of_property_read_string_index(dev, "reg-names", index, &name); | |
880 | ||
881 | return __of_address_to_resource(dev, addrp, size, flags, name, r); | |
1f5bef30 GL |
882 | } |
883 | EXPORT_SYMBOL_GPL(of_address_to_resource); | |
884 | ||
6b884a8d GL |
885 | /** |
886 | * of_iomap - Maps the memory mapped IO for a given device_node | |
1094d5db | 887 | * @np: the device whose io range will be mapped |
6b884a8d GL |
888 | * @index: index of the io range |
889 | * | |
890 | * Returns a pointer to the mapped memory | |
891 | */ | |
892 | void __iomem *of_iomap(struct device_node *np, int index) | |
893 | { | |
894 | struct resource res; | |
895 | ||
896 | if (of_address_to_resource(np, index, &res)) | |
897 | return NULL; | |
898 | ||
28c1b6d6 | 899 | return ioremap(res.start, resource_size(&res)); |
6b884a8d GL |
900 | } |
901 | EXPORT_SYMBOL(of_iomap); | |
18308c94 | 902 | |
efd342fb MB |
903 | /* |
904 | * of_io_request_and_map - Requests a resource and maps the memory mapped IO | |
905 | * for a given device_node | |
906 | * @device: the device whose io range will be mapped | |
907 | * @index: index of the io range | |
b01dcdd8 | 908 | * @name: name "override" for the memory region request or NULL |
efd342fb MB |
909 | * |
910 | * Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded | |
911 | * error code on failure. Usage example: | |
912 | * | |
913 | * base = of_io_request_and_map(node, 0, "foo"); | |
914 | * if (IS_ERR(base)) | |
915 | * return PTR_ERR(base); | |
916 | */ | |
917 | void __iomem *of_io_request_and_map(struct device_node *np, int index, | |
b01dcdd8 | 918 | const char *name) |
efd342fb MB |
919 | { |
920 | struct resource res; | |
921 | void __iomem *mem; | |
922 | ||
923 | if (of_address_to_resource(np, index, &res)) | |
924 | return IOMEM_ERR_PTR(-EINVAL); | |
925 | ||
b01dcdd8 BH |
926 | if (!name) |
927 | name = res.name; | |
efd342fb MB |
928 | if (!request_mem_region(res.start, resource_size(&res), name)) |
929 | return IOMEM_ERR_PTR(-EBUSY); | |
930 | ||
931 | mem = ioremap(res.start, resource_size(&res)); | |
932 | if (!mem) { | |
933 | release_mem_region(res.start, resource_size(&res)); | |
934 | return IOMEM_ERR_PTR(-ENOMEM); | |
935 | } | |
936 | ||
937 | return mem; | |
938 | } | |
939 | EXPORT_SYMBOL(of_io_request_and_map); | |
940 | ||
e0d07278 | 941 | #ifdef CONFIG_HAS_DMA |
18308c94 | 942 | /** |
e0d07278 | 943 | * of_dma_get_range - Get DMA range info and put it into a map array |
18308c94 | 944 | * @np: device node to get DMA range info |
e0d07278 | 945 | * @map: dma range structure to return |
18308c94 GS |
946 | * |
947 | * Look in bottom up direction for the first "dma-ranges" property | |
e0d07278 JQ |
948 | * and parse it. Put the information into a DMA offset map array. |
949 | * | |
950 | * dma-ranges format: | |
18308c94 GS |
951 | * DMA addr (dma_addr) : naddr cells |
952 | * CPU addr (phys_addr_t) : pna cells | |
953 | * size : nsize cells | |
954 | * | |
e0d07278 JQ |
955 | * It returns -ENODEV if "dma-ranges" property was not found for this |
956 | * device in the DT. | |
18308c94 | 957 | */ |
e0d07278 | 958 | int of_dma_get_range(struct device_node *np, const struct bus_dma_region **map) |
18308c94 GS |
959 | { |
960 | struct device_node *node = of_node_get(np); | |
961 | const __be32 *ranges = NULL; | |
951d4885 | 962 | bool found_dma_ranges = false; |
7a8b64d1 RH |
963 | struct of_range_parser parser; |
964 | struct of_range range; | |
e0d07278 JQ |
965 | struct bus_dma_region *r; |
966 | int len, num_ranges = 0; | |
967 | int ret = 0; | |
18308c94 | 968 | |
951d4885 | 969 | while (node) { |
18308c94 GS |
970 | ranges = of_get_property(node, "dma-ranges", &len); |
971 | ||
972 | /* Ignore empty ranges, they imply no translation required */ | |
973 | if (ranges && len > 0) | |
974 | break; | |
975 | ||
951d4885 RM |
976 | /* Once we find 'dma-ranges', then a missing one is an error */ |
977 | if (found_dma_ranges && !ranges) { | |
978 | ret = -ENODEV; | |
979 | goto out; | |
980 | } | |
981 | found_dma_ranges = true; | |
982 | ||
983 | node = of_get_next_dma_parent(node); | |
18308c94 GS |
984 | } |
985 | ||
951d4885 | 986 | if (!node || !ranges) { |
0d638a07 | 987 | pr_debug("no dma-ranges found for node(%pOF)\n", np); |
18308c94 GS |
988 | ret = -ENODEV; |
989 | goto out; | |
990 | } | |
991 | ||
7a8b64d1 | 992 | of_dma_range_parser_init(&parser, node); |
e0d07278 JQ |
993 | for_each_of_range(&parser, &range) |
994 | num_ranges++; | |
995 | ||
996 | r = kcalloc(num_ranges + 1, sizeof(*r), GFP_KERNEL); | |
997 | if (!r) { | |
998 | ret = -ENOMEM; | |
999 | goto out; | |
1000 | } | |
7a8b64d1 | 1001 | |
e0d07278 JQ |
1002 | /* |
1003 | * Record all info in the generic DMA ranges array for struct device. | |
1004 | */ | |
1005 | *map = r; | |
1006 | of_dma_range_parser_init(&parser, node); | |
7a8b64d1 RH |
1007 | for_each_of_range(&parser, &range) { |
1008 | pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n", | |
1009 | range.bus_addr, range.cpu_addr, range.size); | |
f49c7faf CIK |
1010 | if (range.cpu_addr == OF_BAD_ADDR) { |
1011 | pr_err("translation of DMA address(%llx) to CPU address failed node(%pOF)\n", | |
1012 | range.bus_addr, node); | |
1013 | continue; | |
1014 | } | |
e0d07278 JQ |
1015 | r->cpu_start = range.cpu_addr; |
1016 | r->dma_start = range.bus_addr; | |
1017 | r->size = range.size; | |
1018 | r->offset = range.cpu_addr - range.bus_addr; | |
1019 | r++; | |
18308c94 | 1020 | } |
18308c94 GS |
1021 | out: |
1022 | of_node_put(node); | |
18308c94 GS |
1023 | return ret; |
1024 | } | |
e0d07278 | 1025 | #endif /* CONFIG_HAS_DMA */ |
92ea637e | 1026 | |
964db79d NSJ |
1027 | /** |
1028 | * of_dma_get_max_cpu_address - Gets highest CPU address suitable for DMA | |
1029 | * @np: The node to start searching from or NULL to start from the root | |
1030 | * | |
1031 | * Gets the highest CPU physical address that is addressable by all DMA masters | |
1032 | * in the sub-tree pointed by np, or the whole tree if NULL is passed. If no | |
1033 | * DMA constrained device is found, it returns PHYS_ADDR_MAX. | |
1034 | */ | |
1035 | phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np) | |
1036 | { | |
1037 | phys_addr_t max_cpu_addr = PHYS_ADDR_MAX; | |
1038 | struct of_range_parser parser; | |
1039 | phys_addr_t subtree_max_addr; | |
1040 | struct device_node *child; | |
1041 | struct of_range range; | |
1042 | const __be32 *ranges; | |
1043 | u64 cpu_end = 0; | |
1044 | int len; | |
1045 | ||
1046 | if (!np) | |
1047 | np = of_root; | |
1048 | ||
1049 | ranges = of_get_property(np, "dma-ranges", &len); | |
1050 | if (ranges && len) { | |
1051 | of_dma_range_parser_init(&parser, np); | |
1052 | for_each_of_range(&parser, &range) | |
1053 | if (range.cpu_addr + range.size > cpu_end) | |
1054 | cpu_end = range.cpu_addr + range.size - 1; | |
1055 | ||
1056 | if (max_cpu_addr > cpu_end) | |
1057 | max_cpu_addr = cpu_end; | |
1058 | } | |
1059 | ||
1060 | for_each_available_child_of_node(np, child) { | |
1061 | subtree_max_addr = of_dma_get_max_cpu_address(child); | |
1062 | if (max_cpu_addr > subtree_max_addr) | |
1063 | max_cpu_addr = subtree_max_addr; | |
1064 | } | |
1065 | ||
1066 | return max_cpu_addr; | |
1067 | } | |
1068 | ||
92ea637e SS |
1069 | /** |
1070 | * of_dma_is_coherent - Check if device is coherent | |
1071 | * @np: device node | |
1072 | * | |
1073 | * It returns true if "dma-coherent" property was found | |
dabf6b36 ME |
1074 | * for this device in the DT, or if DMA is coherent by |
1075 | * default for OF devices on the current platform. | |
92ea637e SS |
1076 | */ |
1077 | bool of_dma_is_coherent(struct device_node *np) | |
1078 | { | |
a5bea04f | 1079 | struct device_node *node; |
92ea637e | 1080 | |
dabf6b36 ME |
1081 | if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT)) |
1082 | return true; | |
1083 | ||
a5bea04f EN |
1084 | node = of_node_get(np); |
1085 | ||
92ea637e SS |
1086 | while (node) { |
1087 | if (of_property_read_bool(node, "dma-coherent")) { | |
1088 | of_node_put(node); | |
1089 | return true; | |
1090 | } | |
c60bf3eb | 1091 | node = of_get_next_dma_parent(node); |
92ea637e SS |
1092 | } |
1093 | of_node_put(node); | |
1094 | return false; | |
1095 | } | |
eb3d3ec5 | 1096 | EXPORT_SYMBOL_GPL(of_dma_is_coherent); |