Commit | Line | Data |
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af6074fc | 1 | // SPDX-License-Identifier: GPL-2.0 |
606ad42a RH |
2 | #define pr_fmt(fmt) "OF: " fmt |
3 | ||
5019f0b1 | 4 | #include <linux/device.h> |
fcfaab30 | 5 | #include <linux/fwnode.h> |
6b884a8d GL |
6 | #include <linux/io.h> |
7 | #include <linux/ioport.h> | |
65af618d | 8 | #include <linux/logic_pio.h> |
dbbdee94 | 9 | #include <linux/module.h> |
6b884a8d | 10 | #include <linux/of_address.h> |
c5076cfe | 11 | #include <linux/pci.h> |
dbbdee94 | 12 | #include <linux/pci_regs.h> |
41f8bba7 LD |
13 | #include <linux/sizes.h> |
14 | #include <linux/slab.h> | |
dbbdee94 | 15 | #include <linux/string.h> |
6b884a8d | 16 | |
b68ac8dc RM |
17 | #include "of_private.h" |
18 | ||
dbbdee94 GL |
19 | /* Max address size we deal with */ |
20 | #define OF_MAX_ADDR_CELLS 4 | |
5d61b165 SW |
21 | #define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) |
22 | #define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0) | |
dbbdee94 GL |
23 | |
24 | static struct of_bus *of_match_bus(struct device_node *np); | |
0131d897 SAS |
25 | static int __of_address_to_resource(struct device_node *dev, |
26 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 27 | const char *name, struct resource *r); |
dbbdee94 GL |
28 | |
29 | /* Debug utility */ | |
30 | #ifdef DEBUG | |
0131d897 | 31 | static void of_dump_addr(const char *s, const __be32 *addr, int na) |
dbbdee94 | 32 | { |
606ad42a | 33 | pr_debug("%s", s); |
dbbdee94 | 34 | while (na--) |
606ad42a RH |
35 | pr_cont(" %08x", be32_to_cpu(*(addr++))); |
36 | pr_cont("\n"); | |
dbbdee94 GL |
37 | } |
38 | #else | |
0131d897 | 39 | static void of_dump_addr(const char *s, const __be32 *addr, int na) { } |
dbbdee94 GL |
40 | #endif |
41 | ||
42 | /* Callbacks for bus specific translators */ | |
43 | struct of_bus { | |
44 | const char *name; | |
45 | const char *addresses; | |
46 | int (*match)(struct device_node *parent); | |
47 | void (*count_cells)(struct device_node *child, | |
48 | int *addrc, int *sizec); | |
47b1e689 | 49 | u64 (*map)(__be32 *addr, const __be32 *range, |
dbbdee94 | 50 | int na, int ns, int pna); |
47b1e689 | 51 | int (*translate)(__be32 *addr, u64 offset, int na); |
0131d897 | 52 | unsigned int (*get_flags)(const __be32 *addr); |
dbbdee94 GL |
53 | }; |
54 | ||
55 | /* | |
56 | * Default translator (generic bus) | |
57 | */ | |
58 | ||
59 | static void of_bus_default_count_cells(struct device_node *dev, | |
60 | int *addrc, int *sizec) | |
61 | { | |
62 | if (addrc) | |
63 | *addrc = of_n_addr_cells(dev); | |
64 | if (sizec) | |
65 | *sizec = of_n_size_cells(dev); | |
66 | } | |
67 | ||
47b1e689 | 68 | static u64 of_bus_default_map(__be32 *addr, const __be32 *range, |
dbbdee94 GL |
69 | int na, int ns, int pna) |
70 | { | |
71 | u64 cp, s, da; | |
72 | ||
73 | cp = of_read_number(range, na); | |
74 | s = of_read_number(range + na + pna, ns); | |
75 | da = of_read_number(addr, na); | |
76 | ||
606ad42a | 77 | pr_debug("default map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
78 | (unsigned long long)cp, (unsigned long long)s, |
79 | (unsigned long long)da); | |
80 | ||
81 | if (da < cp || da >= (cp + s)) | |
82 | return OF_BAD_ADDR; | |
83 | return da - cp; | |
84 | } | |
85 | ||
47b1e689 | 86 | static int of_bus_default_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
87 | { |
88 | u64 a = of_read_number(addr, na); | |
89 | memset(addr, 0, na * 4); | |
90 | a += offset; | |
91 | if (na > 1) | |
154063a9 GL |
92 | addr[na - 2] = cpu_to_be32(a >> 32); |
93 | addr[na - 1] = cpu_to_be32(a & 0xffffffffu); | |
dbbdee94 GL |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
0131d897 | 98 | static unsigned int of_bus_default_get_flags(const __be32 *addr) |
dbbdee94 GL |
99 | { |
100 | return IORESOURCE_MEM; | |
101 | } | |
102 | ||
4670d610 | 103 | #ifdef CONFIG_PCI |
dbbdee94 GL |
104 | /* |
105 | * PCI bus specific translator | |
106 | */ | |
107 | ||
108 | static int of_bus_pci_match(struct device_node *np) | |
109 | { | |
6dd18e46 | 110 | /* |
14e2abb7 | 111 | * "pciex" is PCI Express |
6dd18e46 BH |
112 | * "vci" is for the /chaos bridge on 1st-gen PCI powermacs |
113 | * "ht" is hypertransport | |
114 | */ | |
e8b1dee2 RH |
115 | return of_node_is_type(np, "pci") || of_node_is_type(np, "pciex") || |
116 | of_node_is_type(np, "vci") || of_node_is_type(np, "ht"); | |
dbbdee94 GL |
117 | } |
118 | ||
119 | static void of_bus_pci_count_cells(struct device_node *np, | |
120 | int *addrc, int *sizec) | |
121 | { | |
122 | if (addrc) | |
123 | *addrc = 3; | |
124 | if (sizec) | |
125 | *sizec = 2; | |
126 | } | |
127 | ||
0131d897 | 128 | static unsigned int of_bus_pci_get_flags(const __be32 *addr) |
dbbdee94 GL |
129 | { |
130 | unsigned int flags = 0; | |
0131d897 | 131 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
132 | |
133 | switch((w >> 24) & 0x03) { | |
134 | case 0x01: | |
135 | flags |= IORESOURCE_IO; | |
136 | break; | |
137 | case 0x02: /* 32 bits */ | |
138 | case 0x03: /* 64 bits */ | |
139 | flags |= IORESOURCE_MEM; | |
140 | break; | |
141 | } | |
142 | if (w & 0x40000000) | |
143 | flags |= IORESOURCE_PREFETCH; | |
144 | return flags; | |
145 | } | |
146 | ||
47b1e689 | 147 | static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 148 | int pna) |
dbbdee94 GL |
149 | { |
150 | u64 cp, s, da; | |
151 | unsigned int af, rf; | |
152 | ||
153 | af = of_bus_pci_get_flags(addr); | |
154 | rf = of_bus_pci_get_flags(range); | |
155 | ||
156 | /* Check address type match */ | |
157 | if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO)) | |
158 | return OF_BAD_ADDR; | |
159 | ||
160 | /* Read address values, skipping high cell */ | |
161 | cp = of_read_number(range + 1, na - 1); | |
162 | s = of_read_number(range + na + pna, ns); | |
163 | da = of_read_number(addr + 1, na - 1); | |
164 | ||
606ad42a | 165 | pr_debug("PCI map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
166 | (unsigned long long)cp, (unsigned long long)s, |
167 | (unsigned long long)da); | |
168 | ||
169 | if (da < cp || da >= (cp + s)) | |
170 | return OF_BAD_ADDR; | |
171 | return da - cp; | |
172 | } | |
173 | ||
47b1e689 | 174 | static int of_bus_pci_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
175 | { |
176 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
177 | } | |
178 | ||
0131d897 | 179 | const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size, |
dbbdee94 GL |
180 | unsigned int *flags) |
181 | { | |
a9fadeef | 182 | const __be32 *prop; |
dbbdee94 GL |
183 | unsigned int psize; |
184 | struct device_node *parent; | |
185 | struct of_bus *bus; | |
186 | int onesize, i, na, ns; | |
187 | ||
188 | /* Get parent & match bus type */ | |
189 | parent = of_get_parent(dev); | |
190 | if (parent == NULL) | |
191 | return NULL; | |
192 | bus = of_match_bus(parent); | |
193 | if (strcmp(bus->name, "pci")) { | |
194 | of_node_put(parent); | |
195 | return NULL; | |
196 | } | |
197 | bus->count_cells(dev, &na, &ns); | |
198 | of_node_put(parent); | |
5d61b165 | 199 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
200 | return NULL; |
201 | ||
202 | /* Get "reg" or "assigned-addresses" property */ | |
203 | prop = of_get_property(dev, bus->addresses, &psize); | |
204 | if (prop == NULL) | |
205 | return NULL; | |
206 | psize /= 4; | |
207 | ||
208 | onesize = na + ns; | |
154063a9 GL |
209 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) { |
210 | u32 val = be32_to_cpu(prop[0]); | |
211 | if ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) { | |
dbbdee94 GL |
212 | if (size) |
213 | *size = of_read_number(prop + na, ns); | |
214 | if (flags) | |
215 | *flags = bus->get_flags(prop); | |
216 | return prop; | |
217 | } | |
154063a9 | 218 | } |
dbbdee94 GL |
219 | return NULL; |
220 | } | |
221 | EXPORT_SYMBOL(of_get_pci_address); | |
222 | ||
223 | int of_pci_address_to_resource(struct device_node *dev, int bar, | |
224 | struct resource *r) | |
225 | { | |
0131d897 | 226 | const __be32 *addrp; |
dbbdee94 GL |
227 | u64 size; |
228 | unsigned int flags; | |
229 | ||
230 | addrp = of_get_pci_address(dev, bar, &size, &flags); | |
231 | if (addrp == NULL) | |
232 | return -EINVAL; | |
35f3da32 | 233 | return __of_address_to_resource(dev, addrp, size, flags, NULL, r); |
dbbdee94 GL |
234 | } |
235 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); | |
29b635c0 | 236 | |
a060c210 MG |
237 | static int parser_init(struct of_pci_range_parser *parser, |
238 | struct device_node *node, const char *name) | |
29b635c0 AM |
239 | { |
240 | const int na = 3, ns = 2; | |
241 | int rlen; | |
242 | ||
243 | parser->node = node; | |
244 | parser->pna = of_n_addr_cells(node); | |
245 | parser->np = parser->pna + na + ns; | |
645c1386 | 246 | parser->dma = !strcmp(name, "dma-ranges"); |
29b635c0 | 247 | |
a060c210 | 248 | parser->range = of_get_property(node, name, &rlen); |
29b635c0 AM |
249 | if (parser->range == NULL) |
250 | return -ENOENT; | |
251 | ||
252 | parser->end = parser->range + rlen / sizeof(__be32); | |
253 | ||
254 | return 0; | |
255 | } | |
a060c210 MG |
256 | |
257 | int of_pci_range_parser_init(struct of_pci_range_parser *parser, | |
258 | struct device_node *node) | |
259 | { | |
260 | return parser_init(parser, node, "ranges"); | |
261 | } | |
29b635c0 AM |
262 | EXPORT_SYMBOL_GPL(of_pci_range_parser_init); |
263 | ||
a060c210 MG |
264 | int of_pci_dma_range_parser_init(struct of_pci_range_parser *parser, |
265 | struct device_node *node) | |
266 | { | |
267 | return parser_init(parser, node, "dma-ranges"); | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(of_pci_dma_range_parser_init); | |
270 | ||
29b635c0 AM |
271 | struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, |
272 | struct of_pci_range *range) | |
273 | { | |
274 | const int na = 3, ns = 2; | |
275 | ||
276 | if (!range) | |
277 | return NULL; | |
278 | ||
279 | if (!parser->range || parser->range + parser->np > parser->end) | |
280 | return NULL; | |
281 | ||
eb310036 | 282 | range->pci_space = be32_to_cpup(parser->range); |
29b635c0 AM |
283 | range->flags = of_bus_pci_get_flags(parser->range); |
284 | range->pci_addr = of_read_number(parser->range + 1, ns); | |
645c1386 RH |
285 | if (parser->dma) |
286 | range->cpu_addr = of_translate_dma_address(parser->node, | |
287 | parser->range + na); | |
288 | else | |
289 | range->cpu_addr = of_translate_address(parser->node, | |
29b635c0 AM |
290 | parser->range + na); |
291 | range->size = of_read_number(parser->range + parser->pna + na, ns); | |
292 | ||
293 | parser->range += parser->np; | |
294 | ||
295 | /* Now consume following elements while they are contiguous */ | |
296 | while (parser->range + parser->np <= parser->end) { | |
fda9f5d4 | 297 | u32 flags; |
29b635c0 AM |
298 | u64 pci_addr, cpu_addr, size; |
299 | ||
29b635c0 AM |
300 | flags = of_bus_pci_get_flags(parser->range); |
301 | pci_addr = of_read_number(parser->range + 1, ns); | |
645c1386 RH |
302 | if (parser->dma) |
303 | cpu_addr = of_translate_dma_address(parser->node, | |
304 | parser->range + na); | |
305 | else | |
306 | cpu_addr = of_translate_address(parser->node, | |
307 | parser->range + na); | |
29b635c0 AM |
308 | size = of_read_number(parser->range + parser->pna + na, ns); |
309 | ||
310 | if (flags != range->flags) | |
311 | break; | |
312 | if (pci_addr != range->pci_addr + range->size || | |
313 | cpu_addr != range->cpu_addr + range->size) | |
314 | break; | |
315 | ||
316 | range->size += size; | |
317 | parser->range += parser->np; | |
318 | } | |
319 | ||
320 | return range; | |
321 | } | |
322 | EXPORT_SYMBOL_GPL(of_pci_range_parser_one); | |
323 | ||
0b0b0893 LD |
324 | /* |
325 | * of_pci_range_to_resource - Create a resource from an of_pci_range | |
326 | * @range: the PCI range that describes the resource | |
327 | * @np: device node where the range belongs to | |
328 | * @res: pointer to a valid resource that will be updated to | |
329 | * reflect the values contained in the range. | |
330 | * | |
331 | * Returns EINVAL if the range cannot be converted to resource. | |
332 | * | |
333 | * Note that if the range is an IO range, the resource will be converted | |
334 | * using pci_address_to_pio() which can fail if it is called too early or | |
335 | * if the range cannot be matched to any host bridge IO space (our case here). | |
336 | * To guard against that we try to register the IO range first. | |
337 | * If that fails we know that pci_address_to_pio() will do too. | |
338 | */ | |
339 | int of_pci_range_to_resource(struct of_pci_range *range, | |
340 | struct device_node *np, struct resource *res) | |
83bbde1c | 341 | { |
0b0b0893 | 342 | int err; |
83bbde1c | 343 | res->flags = range->flags; |
83bbde1c LD |
344 | res->parent = res->child = res->sibling = NULL; |
345 | res->name = np->full_name; | |
0b0b0893 LD |
346 | |
347 | if (res->flags & IORESOURCE_IO) { | |
348 | unsigned long port; | |
fcfaab30 GP |
349 | err = pci_register_io_range(&np->fwnode, range->cpu_addr, |
350 | range->size); | |
0b0b0893 LD |
351 | if (err) |
352 | goto invalid_range; | |
353 | port = pci_address_to_pio(range->cpu_addr); | |
354 | if (port == (unsigned long)-1) { | |
355 | err = -EINVAL; | |
356 | goto invalid_range; | |
357 | } | |
358 | res->start = port; | |
359 | } else { | |
4af97106 PF |
360 | if ((sizeof(resource_size_t) < 8) && |
361 | upper_32_bits(range->cpu_addr)) { | |
362 | err = -EINVAL; | |
363 | goto invalid_range; | |
364 | } | |
365 | ||
0b0b0893 LD |
366 | res->start = range->cpu_addr; |
367 | } | |
368 | res->end = res->start + range->size - 1; | |
369 | return 0; | |
370 | ||
371 | invalid_range: | |
372 | res->start = (resource_size_t)OF_BAD_ADDR; | |
373 | res->end = (resource_size_t)OF_BAD_ADDR; | |
374 | return err; | |
83bbde1c | 375 | } |
bf6681ea | 376 | EXPORT_SYMBOL(of_pci_range_to_resource); |
dbbdee94 GL |
377 | #endif /* CONFIG_PCI */ |
378 | ||
379 | /* | |
380 | * ISA bus specific translator | |
381 | */ | |
382 | ||
383 | static int of_bus_isa_match(struct device_node *np) | |
384 | { | |
b3e46d1a | 385 | return of_node_name_eq(np, "isa"); |
dbbdee94 GL |
386 | } |
387 | ||
388 | static void of_bus_isa_count_cells(struct device_node *child, | |
389 | int *addrc, int *sizec) | |
390 | { | |
391 | if (addrc) | |
392 | *addrc = 2; | |
393 | if (sizec) | |
394 | *sizec = 1; | |
395 | } | |
396 | ||
47b1e689 | 397 | static u64 of_bus_isa_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 398 | int pna) |
dbbdee94 GL |
399 | { |
400 | u64 cp, s, da; | |
401 | ||
402 | /* Check address type match */ | |
0131d897 | 403 | if ((addr[0] ^ range[0]) & cpu_to_be32(1)) |
dbbdee94 GL |
404 | return OF_BAD_ADDR; |
405 | ||
406 | /* Read address values, skipping high cell */ | |
407 | cp = of_read_number(range + 1, na - 1); | |
408 | s = of_read_number(range + na + pna, ns); | |
409 | da = of_read_number(addr + 1, na - 1); | |
410 | ||
606ad42a | 411 | pr_debug("ISA map, cp=%llx, s=%llx, da=%llx\n", |
dbbdee94 GL |
412 | (unsigned long long)cp, (unsigned long long)s, |
413 | (unsigned long long)da); | |
414 | ||
415 | if (da < cp || da >= (cp + s)) | |
416 | return OF_BAD_ADDR; | |
417 | return da - cp; | |
418 | } | |
419 | ||
47b1e689 | 420 | static int of_bus_isa_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
421 | { |
422 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
423 | } | |
424 | ||
0131d897 | 425 | static unsigned int of_bus_isa_get_flags(const __be32 *addr) |
dbbdee94 GL |
426 | { |
427 | unsigned int flags = 0; | |
0131d897 | 428 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
429 | |
430 | if (w & 1) | |
431 | flags |= IORESOURCE_IO; | |
432 | else | |
433 | flags |= IORESOURCE_MEM; | |
434 | return flags; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Array of bus specific translators | |
439 | */ | |
440 | ||
441 | static struct of_bus of_busses[] = { | |
4670d610 | 442 | #ifdef CONFIG_PCI |
dbbdee94 GL |
443 | /* PCI */ |
444 | { | |
445 | .name = "pci", | |
446 | .addresses = "assigned-addresses", | |
447 | .match = of_bus_pci_match, | |
448 | .count_cells = of_bus_pci_count_cells, | |
449 | .map = of_bus_pci_map, | |
450 | .translate = of_bus_pci_translate, | |
451 | .get_flags = of_bus_pci_get_flags, | |
452 | }, | |
4670d610 | 453 | #endif /* CONFIG_PCI */ |
dbbdee94 GL |
454 | /* ISA */ |
455 | { | |
456 | .name = "isa", | |
457 | .addresses = "reg", | |
458 | .match = of_bus_isa_match, | |
459 | .count_cells = of_bus_isa_count_cells, | |
460 | .map = of_bus_isa_map, | |
461 | .translate = of_bus_isa_translate, | |
462 | .get_flags = of_bus_isa_get_flags, | |
463 | }, | |
464 | /* Default */ | |
465 | { | |
466 | .name = "default", | |
467 | .addresses = "reg", | |
468 | .match = NULL, | |
469 | .count_cells = of_bus_default_count_cells, | |
470 | .map = of_bus_default_map, | |
471 | .translate = of_bus_default_translate, | |
472 | .get_flags = of_bus_default_get_flags, | |
473 | }, | |
474 | }; | |
475 | ||
476 | static struct of_bus *of_match_bus(struct device_node *np) | |
477 | { | |
478 | int i; | |
479 | ||
480 | for (i = 0; i < ARRAY_SIZE(of_busses); i++) | |
481 | if (!of_busses[i].match || of_busses[i].match(np)) | |
482 | return &of_busses[i]; | |
483 | BUG(); | |
484 | return NULL; | |
485 | } | |
486 | ||
41d94893 | 487 | static int of_empty_ranges_quirk(struct device_node *np) |
746c9e9f BH |
488 | { |
489 | if (IS_ENABLED(CONFIG_PPC)) { | |
41d94893 | 490 | /* To save cycles, we cache the result for global "Mac" setting */ |
746c9e9f BH |
491 | static int quirk_state = -1; |
492 | ||
41d94893 BH |
493 | /* PA-SEMI sdc DT bug */ |
494 | if (of_device_is_compatible(np, "1682m-sdc")) | |
495 | return true; | |
496 | ||
497 | /* Make quirk cached */ | |
746c9e9f BH |
498 | if (quirk_state < 0) |
499 | quirk_state = | |
500 | of_machine_is_compatible("Power Macintosh") || | |
501 | of_machine_is_compatible("MacRISC"); | |
502 | return quirk_state; | |
503 | } | |
504 | return false; | |
505 | } | |
506 | ||
dbbdee94 | 507 | static int of_translate_one(struct device_node *parent, struct of_bus *bus, |
47b1e689 | 508 | struct of_bus *pbus, __be32 *addr, |
dbbdee94 GL |
509 | int na, int ns, int pna, const char *rprop) |
510 | { | |
0131d897 | 511 | const __be32 *ranges; |
dbbdee94 GL |
512 | unsigned int rlen; |
513 | int rone; | |
514 | u64 offset = OF_BAD_ADDR; | |
515 | ||
ba85edbe MY |
516 | /* |
517 | * Normally, an absence of a "ranges" property means we are | |
dbbdee94 | 518 | * crossing a non-translatable boundary, and thus the addresses |
ba85edbe | 519 | * below the current cannot be converted to CPU physical ones. |
dbbdee94 GL |
520 | * Unfortunately, while this is very clear in the spec, it's not |
521 | * what Apple understood, and they do have things like /uni-n or | |
522 | * /ht nodes with no "ranges" property and a lot of perfectly | |
523 | * useable mapped devices below them. Thus we treat the absence of | |
524 | * "ranges" as equivalent to an empty "ranges" property which means | |
525 | * a 1:1 translation at that level. It's up to the caller not to try | |
526 | * to translate addresses that aren't supposed to be translated in | |
527 | * the first place. --BenH. | |
3930f294 GL |
528 | * |
529 | * As far as we know, this damage only exists on Apple machines, so | |
530 | * This code is only enabled on powerpc. --gcl | |
81db12ee RH |
531 | * |
532 | * This quirk also applies for 'dma-ranges' which frequently exist in | |
533 | * child nodes without 'dma-ranges' in the parent nodes. --RobH | |
dbbdee94 GL |
534 | */ |
535 | ranges = of_get_property(parent, rprop, &rlen); | |
81db12ee RH |
536 | if (ranges == NULL && !of_empty_ranges_quirk(parent) && |
537 | strcmp(rprop, "dma-ranges")) { | |
606ad42a | 538 | pr_debug("no ranges; cannot translate\n"); |
3930f294 GL |
539 | return 1; |
540 | } | |
dbbdee94 GL |
541 | if (ranges == NULL || rlen == 0) { |
542 | offset = of_read_number(addr, na); | |
543 | memset(addr, 0, pna * 4); | |
606ad42a | 544 | pr_debug("empty ranges; 1:1 translation\n"); |
dbbdee94 GL |
545 | goto finish; |
546 | } | |
547 | ||
606ad42a | 548 | pr_debug("walking ranges...\n"); |
dbbdee94 GL |
549 | |
550 | /* Now walk through the ranges */ | |
551 | rlen /= 4; | |
552 | rone = na + pna + ns; | |
553 | for (; rlen >= rone; rlen -= rone, ranges += rone) { | |
554 | offset = bus->map(addr, ranges, na, ns, pna); | |
555 | if (offset != OF_BAD_ADDR) | |
556 | break; | |
557 | } | |
558 | if (offset == OF_BAD_ADDR) { | |
606ad42a | 559 | pr_debug("not found !\n"); |
dbbdee94 GL |
560 | return 1; |
561 | } | |
562 | memcpy(addr, ranges + na, 4 * pna); | |
563 | ||
564 | finish: | |
606ad42a RH |
565 | of_dump_addr("parent translation for:", addr, pna); |
566 | pr_debug("with offset: %llx\n", (unsigned long long)offset); | |
dbbdee94 GL |
567 | |
568 | /* Translate it into parent bus space */ | |
569 | return pbus->translate(addr, offset, pna); | |
570 | } | |
571 | ||
572 | /* | |
573 | * Translate an address from the device-tree into a CPU physical address, | |
574 | * this walks up the tree and applies the various bus mappings on the | |
575 | * way. | |
576 | * | |
577 | * Note: We consider that crossing any level with #size-cells == 0 to mean | |
578 | * that translation is impossible (that is we are not dealing with a value | |
579 | * that can be mapped to a cpu physical address). This is not really specified | |
580 | * that way, but this is traditionally the way IBM at least do things | |
65af618d ZY |
581 | * |
582 | * Whenever the translation fails, the *host pointer will be set to the | |
583 | * device that had registered logical PIO mapping, and the return code is | |
584 | * relative to that node. | |
dbbdee94 | 585 | */ |
47b1e689 | 586 | static u64 __of_translate_address(struct device_node *dev, |
95835a8d | 587 | struct device_node *(*get_parent)(const struct device_node *), |
65af618d ZY |
588 | const __be32 *in_addr, const char *rprop, |
589 | struct device_node **host) | |
dbbdee94 GL |
590 | { |
591 | struct device_node *parent = NULL; | |
592 | struct of_bus *bus, *pbus; | |
47b1e689 | 593 | __be32 addr[OF_MAX_ADDR_CELLS]; |
dbbdee94 GL |
594 | int na, ns, pna, pns; |
595 | u64 result = OF_BAD_ADDR; | |
596 | ||
0d638a07 | 597 | pr_debug("** translation for device %pOF **\n", dev); |
dbbdee94 GL |
598 | |
599 | /* Increase refcount at current level */ | |
600 | of_node_get(dev); | |
601 | ||
65af618d | 602 | *host = NULL; |
dbbdee94 | 603 | /* Get parent & match bus type */ |
95835a8d | 604 | parent = get_parent(dev); |
dbbdee94 GL |
605 | if (parent == NULL) |
606 | goto bail; | |
607 | bus = of_match_bus(parent); | |
608 | ||
59f5ca48 | 609 | /* Count address cells & copy address locally */ |
dbbdee94 GL |
610 | bus->count_cells(dev, &na, &ns); |
611 | if (!OF_CHECK_COUNTS(na, ns)) { | |
0d638a07 | 612 | pr_debug("Bad cell count for %pOF\n", dev); |
dbbdee94 GL |
613 | goto bail; |
614 | } | |
615 | memcpy(addr, in_addr, na * 4); | |
616 | ||
0d638a07 RH |
617 | pr_debug("bus is %s (na=%d, ns=%d) on %pOF\n", |
618 | bus->name, na, ns, parent); | |
606ad42a | 619 | of_dump_addr("translating address:", addr, na); |
dbbdee94 GL |
620 | |
621 | /* Translate */ | |
622 | for (;;) { | |
65af618d ZY |
623 | struct logic_pio_hwaddr *iorange; |
624 | ||
dbbdee94 GL |
625 | /* Switch to parent bus */ |
626 | of_node_put(dev); | |
627 | dev = parent; | |
95835a8d | 628 | parent = get_parent(dev); |
dbbdee94 GL |
629 | |
630 | /* If root, we have finished */ | |
631 | if (parent == NULL) { | |
606ad42a | 632 | pr_debug("reached root node\n"); |
dbbdee94 GL |
633 | result = of_read_number(addr, na); |
634 | break; | |
635 | } | |
636 | ||
65af618d ZY |
637 | /* |
638 | * For indirectIO device which has no ranges property, get | |
639 | * the address from reg directly. | |
640 | */ | |
641 | iorange = find_io_range_by_fwnode(&dev->fwnode); | |
642 | if (iorange && (iorange->flags != LOGIC_PIO_CPU_MMIO)) { | |
643 | result = of_read_number(addr + 1, na - 1); | |
644 | pr_debug("indirectIO matched(%pOF) 0x%llx\n", | |
645 | dev, result); | |
646 | *host = of_node_get(dev); | |
647 | break; | |
648 | } | |
649 | ||
dbbdee94 GL |
650 | /* Get new parent bus and counts */ |
651 | pbus = of_match_bus(parent); | |
652 | pbus->count_cells(dev, &pna, &pns); | |
653 | if (!OF_CHECK_COUNTS(pna, pns)) { | |
0d638a07 | 654 | pr_err("Bad cell count for %pOF\n", dev); |
dbbdee94 GL |
655 | break; |
656 | } | |
657 | ||
0d638a07 RH |
658 | pr_debug("parent bus is %s (na=%d, ns=%d) on %pOF\n", |
659 | pbus->name, pna, pns, parent); | |
dbbdee94 GL |
660 | |
661 | /* Apply bus translation */ | |
662 | if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) | |
663 | break; | |
664 | ||
665 | /* Complete the move up one level */ | |
666 | na = pna; | |
667 | ns = pns; | |
668 | bus = pbus; | |
669 | ||
606ad42a | 670 | of_dump_addr("one level translation:", addr, na); |
dbbdee94 GL |
671 | } |
672 | bail: | |
673 | of_node_put(parent); | |
674 | of_node_put(dev); | |
675 | ||
676 | return result; | |
677 | } | |
678 | ||
0131d897 | 679 | u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 680 | { |
65af618d ZY |
681 | struct device_node *host; |
682 | u64 ret; | |
683 | ||
95835a8d MR |
684 | ret = __of_translate_address(dev, of_get_parent, |
685 | in_addr, "ranges", &host); | |
65af618d ZY |
686 | if (host) { |
687 | of_node_put(host); | |
688 | return OF_BAD_ADDR; | |
689 | } | |
690 | ||
691 | return ret; | |
dbbdee94 GL |
692 | } |
693 | EXPORT_SYMBOL(of_translate_address); | |
694 | ||
f83a6e5d MR |
695 | static struct device_node *__of_get_dma_parent(const struct device_node *np) |
696 | { | |
697 | struct of_phandle_args args; | |
698 | int ret, index; | |
699 | ||
700 | index = of_property_match_string(np, "interconnect-names", "dma-mem"); | |
701 | if (index < 0) | |
702 | return of_get_parent(np); | |
703 | ||
704 | ret = of_parse_phandle_with_args(np, "interconnects", | |
705 | "#interconnect-cells", | |
706 | index, &args); | |
707 | if (ret < 0) | |
708 | return of_get_parent(np); | |
709 | ||
710 | return of_node_get(args.np); | |
711 | } | |
712 | ||
862ab557 RM |
713 | static struct device_node *of_get_next_dma_parent(struct device_node *np) |
714 | { | |
715 | struct device_node *parent; | |
716 | ||
717 | parent = __of_get_dma_parent(np); | |
718 | of_node_put(np); | |
719 | ||
720 | return parent; | |
721 | } | |
722 | ||
0131d897 | 723 | u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 | 724 | { |
65af618d ZY |
725 | struct device_node *host; |
726 | u64 ret; | |
727 | ||
f83a6e5d | 728 | ret = __of_translate_address(dev, __of_get_dma_parent, |
95835a8d | 729 | in_addr, "dma-ranges", &host); |
65af618d ZY |
730 | |
731 | if (host) { | |
732 | of_node_put(host); | |
733 | return OF_BAD_ADDR; | |
734 | } | |
735 | ||
736 | return ret; | |
dbbdee94 GL |
737 | } |
738 | EXPORT_SYMBOL(of_translate_dma_address); | |
739 | ||
0131d897 | 740 | const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, |
dbbdee94 GL |
741 | unsigned int *flags) |
742 | { | |
0131d897 | 743 | const __be32 *prop; |
dbbdee94 GL |
744 | unsigned int psize; |
745 | struct device_node *parent; | |
746 | struct of_bus *bus; | |
747 | int onesize, i, na, ns; | |
748 | ||
749 | /* Get parent & match bus type */ | |
750 | parent = of_get_parent(dev); | |
751 | if (parent == NULL) | |
752 | return NULL; | |
753 | bus = of_match_bus(parent); | |
754 | bus->count_cells(dev, &na, &ns); | |
755 | of_node_put(parent); | |
5d61b165 | 756 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
757 | return NULL; |
758 | ||
759 | /* Get "reg" or "assigned-addresses" property */ | |
760 | prop = of_get_property(dev, bus->addresses, &psize); | |
761 | if (prop == NULL) | |
762 | return NULL; | |
763 | psize /= 4; | |
764 | ||
765 | onesize = na + ns; | |
766 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) | |
767 | if (i == index) { | |
768 | if (size) | |
769 | *size = of_read_number(prop + na, ns); | |
770 | if (flags) | |
771 | *flags = bus->get_flags(prop); | |
772 | return prop; | |
773 | } | |
774 | return NULL; | |
775 | } | |
776 | EXPORT_SYMBOL(of_get_address); | |
777 | ||
65af618d ZY |
778 | static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr, |
779 | u64 size) | |
780 | { | |
781 | u64 taddr; | |
782 | unsigned long port; | |
783 | struct device_node *host; | |
784 | ||
95835a8d MR |
785 | taddr = __of_translate_address(dev, of_get_parent, |
786 | in_addr, "ranges", &host); | |
65af618d ZY |
787 | if (host) { |
788 | /* host-specific port access */ | |
789 | port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size); | |
790 | of_node_put(host); | |
791 | } else { | |
792 | /* memory-mapped I/O range */ | |
793 | port = pci_address_to_pio(taddr); | |
794 | } | |
795 | ||
796 | if (port == (unsigned long)-1) | |
797 | return OF_BAD_ADDR; | |
798 | ||
799 | return port; | |
800 | } | |
801 | ||
0131d897 SAS |
802 | static int __of_address_to_resource(struct device_node *dev, |
803 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 804 | const char *name, struct resource *r) |
1f5bef30 GL |
805 | { |
806 | u64 taddr; | |
807 | ||
65af618d ZY |
808 | if (flags & IORESOURCE_MEM) |
809 | taddr = of_translate_address(dev, addrp); | |
810 | else if (flags & IORESOURCE_IO) | |
811 | taddr = of_translate_ioport(dev, addrp, size); | |
812 | else | |
1f5bef30 | 813 | return -EINVAL; |
65af618d | 814 | |
1f5bef30 GL |
815 | if (taddr == OF_BAD_ADDR) |
816 | return -EINVAL; | |
817 | memset(r, 0, sizeof(struct resource)); | |
65af618d ZY |
818 | |
819 | r->start = taddr; | |
820 | r->end = taddr + size - 1; | |
1f5bef30 | 821 | r->flags = flags; |
35f3da32 BC |
822 | r->name = name ? name : dev->full_name; |
823 | ||
1f5bef30 GL |
824 | return 0; |
825 | } | |
826 | ||
827 | /** | |
828 | * of_address_to_resource - Translate device tree address and return as resource | |
829 | * | |
830 | * Note that if your address is a PIO address, the conversion will fail if | |
831 | * the physical address can't be internally converted to an IO token with | |
7602f422 | 832 | * pci_address_to_pio(), that is because it's either called too early or it |
1f5bef30 GL |
833 | * can't be matched to any host bridge IO space |
834 | */ | |
835 | int of_address_to_resource(struct device_node *dev, int index, | |
836 | struct resource *r) | |
837 | { | |
0131d897 | 838 | const __be32 *addrp; |
1f5bef30 GL |
839 | u64 size; |
840 | unsigned int flags; | |
35f3da32 | 841 | const char *name = NULL; |
1f5bef30 GL |
842 | |
843 | addrp = of_get_address(dev, index, &size, &flags); | |
844 | if (addrp == NULL) | |
845 | return -EINVAL; | |
35f3da32 BC |
846 | |
847 | /* Get optional "reg-names" property to add a name to a resource */ | |
848 | of_property_read_string_index(dev, "reg-names", index, &name); | |
849 | ||
850 | return __of_address_to_resource(dev, addrp, size, flags, name, r); | |
1f5bef30 GL |
851 | } |
852 | EXPORT_SYMBOL_GPL(of_address_to_resource); | |
853 | ||
6b884a8d GL |
854 | /** |
855 | * of_iomap - Maps the memory mapped IO for a given device_node | |
856 | * @device: the device whose io range will be mapped | |
857 | * @index: index of the io range | |
858 | * | |
859 | * Returns a pointer to the mapped memory | |
860 | */ | |
861 | void __iomem *of_iomap(struct device_node *np, int index) | |
862 | { | |
863 | struct resource res; | |
864 | ||
865 | if (of_address_to_resource(np, index, &res)) | |
866 | return NULL; | |
867 | ||
28c1b6d6 | 868 | return ioremap(res.start, resource_size(&res)); |
6b884a8d GL |
869 | } |
870 | EXPORT_SYMBOL(of_iomap); | |
18308c94 | 871 | |
efd342fb MB |
872 | /* |
873 | * of_io_request_and_map - Requests a resource and maps the memory mapped IO | |
874 | * for a given device_node | |
875 | * @device: the device whose io range will be mapped | |
876 | * @index: index of the io range | |
b01dcdd8 | 877 | * @name: name "override" for the memory region request or NULL |
efd342fb MB |
878 | * |
879 | * Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded | |
880 | * error code on failure. Usage example: | |
881 | * | |
882 | * base = of_io_request_and_map(node, 0, "foo"); | |
883 | * if (IS_ERR(base)) | |
884 | * return PTR_ERR(base); | |
885 | */ | |
886 | void __iomem *of_io_request_and_map(struct device_node *np, int index, | |
b01dcdd8 | 887 | const char *name) |
efd342fb MB |
888 | { |
889 | struct resource res; | |
890 | void __iomem *mem; | |
891 | ||
892 | if (of_address_to_resource(np, index, &res)) | |
893 | return IOMEM_ERR_PTR(-EINVAL); | |
894 | ||
b01dcdd8 BH |
895 | if (!name) |
896 | name = res.name; | |
efd342fb MB |
897 | if (!request_mem_region(res.start, resource_size(&res), name)) |
898 | return IOMEM_ERR_PTR(-EBUSY); | |
899 | ||
900 | mem = ioremap(res.start, resource_size(&res)); | |
901 | if (!mem) { | |
902 | release_mem_region(res.start, resource_size(&res)); | |
903 | return IOMEM_ERR_PTR(-ENOMEM); | |
904 | } | |
905 | ||
906 | return mem; | |
907 | } | |
908 | EXPORT_SYMBOL(of_io_request_and_map); | |
909 | ||
18308c94 GS |
910 | /** |
911 | * of_dma_get_range - Get DMA range info | |
912 | * @np: device node to get DMA range info | |
913 | * @dma_addr: pointer to store initial DMA address of DMA range | |
914 | * @paddr: pointer to store initial CPU address of DMA range | |
915 | * @size: pointer to store size of DMA range | |
916 | * | |
917 | * Look in bottom up direction for the first "dma-ranges" property | |
918 | * and parse it. | |
919 | * dma-ranges format: | |
920 | * DMA addr (dma_addr) : naddr cells | |
921 | * CPU addr (phys_addr_t) : pna cells | |
922 | * size : nsize cells | |
923 | * | |
924 | * It returns -ENODEV if "dma-ranges" property was not found | |
925 | * for this device in DT. | |
926 | */ | |
927 | int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *size) | |
928 | { | |
929 | struct device_node *node = of_node_get(np); | |
930 | const __be32 *ranges = NULL; | |
931 | int len, naddr, nsize, pna; | |
932 | int ret = 0; | |
933 | u64 dmaaddr; | |
934 | ||
935 | if (!node) | |
936 | return -EINVAL; | |
937 | ||
938 | while (1) { | |
f83a6e5d MR |
939 | struct device_node *parent; |
940 | ||
18308c94 GS |
941 | naddr = of_n_addr_cells(node); |
942 | nsize = of_n_size_cells(node); | |
f83a6e5d MR |
943 | |
944 | parent = __of_get_dma_parent(node); | |
945 | of_node_put(node); | |
946 | ||
947 | node = parent; | |
18308c94 GS |
948 | if (!node) |
949 | break; | |
950 | ||
951 | ranges = of_get_property(node, "dma-ranges", &len); | |
952 | ||
953 | /* Ignore empty ranges, they imply no translation required */ | |
954 | if (ranges && len > 0) | |
955 | break; | |
956 | ||
957 | /* | |
958 | * At least empty ranges has to be defined for parent node if | |
959 | * DMA is supported | |
960 | */ | |
961 | if (!ranges) | |
962 | break; | |
963 | } | |
964 | ||
965 | if (!ranges) { | |
0d638a07 | 966 | pr_debug("no dma-ranges found for node(%pOF)\n", np); |
18308c94 GS |
967 | ret = -ENODEV; |
968 | goto out; | |
969 | } | |
970 | ||
971 | len /= sizeof(u32); | |
972 | ||
973 | pna = of_n_addr_cells(node); | |
974 | ||
975 | /* dma-ranges format: | |
976 | * DMA addr : naddr cells | |
977 | * CPU addr : pna cells | |
978 | * size : nsize cells | |
979 | */ | |
980 | dmaaddr = of_read_number(ranges, naddr); | |
981 | *paddr = of_translate_dma_address(np, ranges); | |
982 | if (*paddr == OF_BAD_ADDR) { | |
76dd7068 RM |
983 | pr_err("translation of DMA address(%llx) to CPU address failed node(%pOF)\n", |
984 | dmaaddr, np); | |
18308c94 GS |
985 | ret = -EINVAL; |
986 | goto out; | |
987 | } | |
988 | *dma_addr = dmaaddr; | |
989 | ||
990 | *size = of_read_number(ranges + naddr + pna, nsize); | |
991 | ||
992 | pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n", | |
993 | *dma_addr, *paddr, *size); | |
994 | ||
995 | out: | |
996 | of_node_put(node); | |
997 | ||
998 | return ret; | |
999 | } | |
92ea637e SS |
1000 | |
1001 | /** | |
1002 | * of_dma_is_coherent - Check if device is coherent | |
1003 | * @np: device node | |
1004 | * | |
1005 | * It returns true if "dma-coherent" property was found | |
1006 | * for this device in DT. | |
1007 | */ | |
1008 | bool of_dma_is_coherent(struct device_node *np) | |
1009 | { | |
1010 | struct device_node *node = of_node_get(np); | |
1011 | ||
1012 | while (node) { | |
1013 | if (of_property_read_bool(node, "dma-coherent")) { | |
1014 | of_node_put(node); | |
1015 | return true; | |
1016 | } | |
c60bf3eb | 1017 | node = of_get_next_dma_parent(node); |
92ea637e SS |
1018 | } |
1019 | of_node_put(node); | |
1020 | return false; | |
1021 | } | |
eb3d3ec5 | 1022 | EXPORT_SYMBOL_GPL(of_dma_is_coherent); |