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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
988437ae OR |
2 | /* |
3 | * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de> | |
4 | * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> | |
988437ae OR |
5 | */ |
6 | ||
7 | #include <linux/mfd/syscon.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/nvmem-provider.h> | |
10 | #include <linux/of_device.h> | |
11 | #include <linux/regmap.h> | |
12 | ||
13 | #define IMX6Q_SNVS_HPLR 0x00 | |
988437ae | 14 | #define IMX6Q_SNVS_LPLR 0x34 |
988437ae OR |
15 | #define IMX6Q_SNVS_LPGPR 0x68 |
16 | ||
80b820ca AY |
17 | #define IMX7D_SNVS_HPLR 0x00 |
18 | #define IMX7D_SNVS_LPLR 0x34 | |
19 | #define IMX7D_SNVS_LPGPR 0x90 | |
20 | ||
21 | #define IMX_GPR_SL BIT(5) | |
22 | #define IMX_GPR_HL BIT(5) | |
23 | ||
988437ae OR |
24 | struct snvs_lpgpr_cfg { |
25 | int offset; | |
26 | int offset_hplr; | |
27 | int offset_lplr; | |
80b820ca | 28 | int size; |
988437ae OR |
29 | }; |
30 | ||
31 | struct snvs_lpgpr_priv { | |
32 | struct device_d *dev; | |
33 | struct regmap *regmap; | |
34 | struct nvmem_config cfg; | |
35 | const struct snvs_lpgpr_cfg *dcfg; | |
36 | }; | |
37 | ||
38 | static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = { | |
39 | .offset = IMX6Q_SNVS_LPGPR, | |
40 | .offset_hplr = IMX6Q_SNVS_HPLR, | |
41 | .offset_lplr = IMX6Q_SNVS_LPLR, | |
80b820ca AY |
42 | .size = 4, |
43 | }; | |
44 | ||
45 | static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = { | |
46 | .offset = IMX7D_SNVS_LPGPR, | |
47 | .offset_hplr = IMX7D_SNVS_HPLR, | |
48 | .offset_lplr = IMX7D_SNVS_LPLR, | |
49 | .size = 16, | |
988437ae OR |
50 | }; |
51 | ||
52 | static int snvs_lpgpr_write(void *context, unsigned int offset, void *val, | |
53 | size_t bytes) | |
54 | { | |
55 | struct snvs_lpgpr_priv *priv = context; | |
56 | const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; | |
57 | unsigned int lock_reg; | |
58 | int ret; | |
59 | ||
60 | ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); | |
61 | if (ret < 0) | |
62 | return ret; | |
63 | ||
80b820ca | 64 | if (lock_reg & IMX_GPR_SL) |
988437ae OR |
65 | return -EPERM; |
66 | ||
67 | ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); | |
68 | if (ret < 0) | |
69 | return ret; | |
70 | ||
80b820ca | 71 | if (lock_reg & IMX_GPR_HL) |
988437ae OR |
72 | return -EPERM; |
73 | ||
74 | return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, | |
75 | bytes / 4); | |
76 | } | |
77 | ||
78 | static int snvs_lpgpr_read(void *context, unsigned int offset, void *val, | |
79 | size_t bytes) | |
80 | { | |
81 | struct snvs_lpgpr_priv *priv = context; | |
82 | const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; | |
83 | ||
84 | return regmap_bulk_read(priv->regmap, dcfg->offset + offset, | |
85 | val, bytes / 4); | |
86 | } | |
87 | ||
88 | static int snvs_lpgpr_probe(struct platform_device *pdev) | |
89 | { | |
90 | struct device *dev = &pdev->dev; | |
91 | struct device_node *node = dev->of_node; | |
92 | struct device_node *syscon_node; | |
93 | struct snvs_lpgpr_priv *priv; | |
94 | struct nvmem_config *cfg; | |
95 | struct nvmem_device *nvmem; | |
96 | const struct snvs_lpgpr_cfg *dcfg; | |
97 | ||
98 | if (!node) | |
99 | return -ENOENT; | |
100 | ||
101 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
102 | if (!priv) | |
103 | return -ENOMEM; | |
104 | ||
105 | dcfg = of_device_get_match_data(dev); | |
106 | if (!dcfg) | |
107 | return -EINVAL; | |
108 | ||
109 | syscon_node = of_get_parent(node); | |
110 | if (!syscon_node) | |
111 | return -ENODEV; | |
112 | ||
113 | priv->regmap = syscon_node_to_regmap(syscon_node); | |
114 | of_node_put(syscon_node); | |
115 | if (IS_ERR(priv->regmap)) | |
116 | return PTR_ERR(priv->regmap); | |
117 | ||
118 | priv->dcfg = dcfg; | |
119 | ||
120 | cfg = &priv->cfg; | |
121 | cfg->priv = priv; | |
122 | cfg->name = dev_name(dev); | |
123 | cfg->dev = dev; | |
0e189891 AS |
124 | cfg->stride = 4; |
125 | cfg->word_size = 4; | |
80b820ca | 126 | cfg->size = dcfg->size, |
0e189891 AS |
127 | cfg->owner = THIS_MODULE; |
128 | cfg->reg_read = snvs_lpgpr_read; | |
129 | cfg->reg_write = snvs_lpgpr_write; | |
988437ae | 130 | |
5557acf6 | 131 | nvmem = devm_nvmem_register(dev, cfg); |
988437ae | 132 | |
5557acf6 | 133 | return PTR_ERR_OR_ZERO(nvmem); |
988437ae OR |
134 | } |
135 | ||
136 | static const struct of_device_id snvs_lpgpr_dt_ids[] = { | |
137 | { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q }, | |
138 | { .compatible = "fsl,imx6ul-snvs-lpgpr", | |
139 | .data = &snvs_lpgpr_cfg_imx6q }, | |
80b820ca | 140 | { .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d }, |
988437ae OR |
141 | { }, |
142 | }; | |
143 | MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids); | |
144 | ||
145 | static struct platform_driver snvs_lpgpr_driver = { | |
146 | .probe = snvs_lpgpr_probe, | |
988437ae OR |
147 | .driver = { |
148 | .name = "snvs_lpgpr", | |
149 | .of_match_table = snvs_lpgpr_dt_ids, | |
150 | }, | |
151 | }; | |
152 | module_platform_driver(snvs_lpgpr_driver); | |
153 | ||
154 | MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); | |
80b820ca | 155 | MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Storage"); |
988437ae | 156 | MODULE_LICENSE("GPL v2"); |