[linux-block.git] / drivers / nvmem / rockchip-efuse.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Rockchip eFuse Driver
 *
 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
 * Author: Caesar Wang <wxt@rock-chips.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>

#define RK3288_A_SHIFT		6
#define RK3288_A_MASK		0x3ff
#define RK3288_PGENB		BIT(3)
#define RK3288_LOAD		BIT(2)
#define RK3288_STROBE		BIT(1)
#define RK3288_CSB		BIT(0)

#define RK3328_SECURE_SIZES	96
#define RK3328_INT_STATUS	0x0018
#define RK3328_DOUT		0x0020
#define RK3328_AUTO_CTRL	0x0024
#define RK3328_INT_FINISH	BIT(0)
#define RK3328_AUTO_ENB		BIT(0)
#define RK3328_AUTO_RD		BIT(1)

#define RK3399_A_SHIFT		16
#define RK3399_A_MASK		0x3ff
#define RK3399_NBYTES		4
#define RK3399_STROBSFTSEL	BIT(9)
#define RK3399_RSB		BIT(7)
#define RK3399_PD		BIT(5)
#define RK3399_PGENB		BIT(3)
#define RK3399_LOAD		BIT(2)
#define RK3399_STROBE		BIT(1)
#define RK3399_CSB		BIT(0)

#define REG_EFUSE_CTRL		0x0000
#define REG_EFUSE_DOUT		0x0004

struct rockchip_efuse_chip {
	struct device *dev;
	void __iomem *base;
	struct clk *clk;
};

static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
				      void *val, size_t bytes)
{
	struct rockchip_efuse_chip *efuse = context;
	u8 *buf = val;
	int ret;

	ret = clk_prepare_enable(efuse->clk);
	if (ret < 0) {
		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
		return ret;
	}

	writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
	udelay(1);
	while (bytes--) {
		writel(readl(efuse->base + REG_EFUSE_CTRL) &
			     (~(RK3288_A_MASK << RK3288_A_SHIFT)),
			     efuse->base + REG_EFUSE_CTRL);
		writel(readl(efuse->base + REG_EFUSE_CTRL) |
			     ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
			     efuse->base + REG_EFUSE_CTRL);
		udelay(1);
		writel(readl(efuse->base + REG_EFUSE_CTRL) |
			     RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
		udelay(1);
		*buf++ = readb(efuse->base + REG_EFUSE_DOUT);
		writel(readl(efuse->base + REG_EFUSE_CTRL) &
		       (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
		udelay(1);
	}

	/* Switch to standby mode */
	writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);

	clk_disable_unprepare(efuse->clk);

	return 0;
}

static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
				      void *val, size_t bytes)
{
	struct rockchip_efuse_chip *efuse = context;
	unsigned int addr_start, addr_end, addr_offset, addr_len;
	u32 out_value, status;
	u8 *buf;
	int ret, i = 0;

	ret = clk_prepare_enable(efuse->clk);
	if (ret < 0) {
		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
		return ret;
	}

	/* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
	offset += RK3328_SECURE_SIZES;
	addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
	addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
	addr_offset = offset % RK3399_NBYTES;
	addr_len = addr_end - addr_start;

	buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
		      GFP_KERNEL);
	if (!buf) {
		ret = -ENOMEM;
		goto nomem;
	}

	while (addr_len--) {
		writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
		       ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
		       efuse->base + RK3328_AUTO_CTRL);
		udelay(4);
		status = readl(efuse->base + RK3328_INT_STATUS);
		if (!(status & RK3328_INT_FINISH)) {
			ret = -EIO;
			goto err;
		}
		out_value = readl(efuse->base + RK3328_DOUT);
		writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);

		memcpy(&buf[i], &out_value, RK3399_NBYTES);
		i += RK3399_NBYTES;
	}

	memcpy(val, buf + addr_offset, bytes);
err:
	kfree(buf);
nomem:
	clk_disable_unprepare(efuse->clk);

	return ret;
}

static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
				      void *val, size_t bytes)
{
	struct rockchip_efuse_chip *efuse = context;
	unsigned int addr_start, addr_end, addr_offset, addr_len;
	u32 out_value;
	u8 *buf;
	int ret, i = 0;

	ret = clk_prepare_enable(efuse->clk);
	if (ret < 0) {
		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
		return ret;
	}

	addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
	addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
	addr_offset = offset % RK3399_NBYTES;
	addr_len = addr_end - addr_start;

	buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
		      GFP_KERNEL);
	if (!buf) {
		clk_disable_unprepare(efuse->clk);
		return -ENOMEM;
	}

	writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
	       efuse->base + REG_EFUSE_CTRL);
	udelay(1);
	while (addr_len--) {
		writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
		       ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
		       efuse->base + REG_EFUSE_CTRL);
		udelay(1);
		out_value = readl(efuse->base + REG_EFUSE_DOUT);
		writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
		       efuse->base + REG_EFUSE_CTRL);
		udelay(1);

		memcpy(&buf[i], &out_value, RK3399_NBYTES);
		i += RK3399_NBYTES;
	}

	/* Switch to standby mode */
	writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);

	memcpy(val, buf + addr_offset, bytes);

	kfree(buf);

	clk_disable_unprepare(efuse->clk);

	return 0;
}

static struct nvmem_config econfig = {
	.name = "rockchip-efuse",
	.stride = 1,
	.word_size = 1,
	.read_only = true,
};

static const struct of_device_id rockchip_efuse_match[] = {
	/* deprecated but kept around for dts binding compatibility */
	{
		.compatible = "rockchip,rockchip-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3066a-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3188-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3228-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3288-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3368-efuse",
		.data = (void *)&rockchip_rk3288_efuse_read,
	},
	{
		.compatible = "rockchip,rk3328-efuse",
		.data = (void *)&rockchip_rk3328_efuse_read,
	},
	{
		.compatible = "rockchip,rk3399-efuse",
		.data = (void *)&rockchip_rk3399_efuse_read,
	},
	{ /* sentinel */},
};
MODULE_DEVICE_TABLE(of, rockchip_efuse_match);

static int rockchip_efuse_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct nvmem_device *nvmem;
	struct rockchip_efuse_chip *efuse;
	const void *data;
	struct device *dev = &pdev->dev;

	data = of_device_get_match_data(dev);
	if (!data) {
		dev_err(dev, "failed to get match data\n");
		return -EINVAL;
	}

	efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
			     GFP_KERNEL);
	if (!efuse)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	efuse->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(efuse->base))
		return PTR_ERR(efuse->base);

	efuse->clk = devm_clk_get(dev, "pclk_efuse");
	if (IS_ERR(efuse->clk))
		return PTR_ERR(efuse->clk);

	efuse->dev = dev;
	if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
				 &econfig.size))
		econfig.size = resource_size(res);
	econfig.reg_read = data;
	econfig.priv = efuse;
	econfig.dev = efuse->dev;
	nvmem = devm_nvmem_register(dev, &econfig);

	return PTR_ERR_OR_ZERO(nvmem);
}

static struct platform_driver rockchip_efuse_driver = {
	.probe = rockchip_efuse_probe,
	.driver = {
		.name = "rockchip-efuse",
		.of_match_table = rockchip_efuse_match,
	},
};

module_platform_driver(rockchip_efuse_driver);
MODULE_DESCRIPTION("rockchip_efuse driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5b497af4	1	// SPDX-License-Identifier: GPL-2.0-only
03a69568 Z	2	/*
	3	* Rockchip eFuse Driver
	4	*
	5	* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
	6	* Author: Caesar Wang <wxt@rock-chips.com>
03a69568 Z	7	*/
03a69568 Z	8
c37ff3fb CW	9	#include <linux/clk.h>
c37ff3fb CW	10	#include <linux/delay.h>
03a69568 Z	11	#include <linux/device.h>
	12	#include <linux/io.h>
	13	#include <linux/module.h>
c37ff3fb CW	14	#include <linux/nvmem-provider.h>
c37ff3fb CW	15	#include <linux/slab.h>
03a69568	16	#include <linux/of.h>
02baff32	17	#include <linux/of_platform.h>
c37ff3fb	18	#include <linux/platform_device.h>
03a69568	19
02baff32 FX	20	#define RK3288_A_SHIFT 6
	21	#define RK3288_A_MASK 0x3ff
	22	#define RK3288_PGENB BIT(3)
	23	#define RK3288_LOAD BIT(2)
	24	#define RK3288_STROBE BIT(1)
	25	#define RK3288_CSB BIT(0)
	26
9a479b08 FX	27	#define RK3328_SECURE_SIZES 96
	28	#define RK3328_INT_STATUS 0x0018
	29	#define RK3328_DOUT 0x0020
	30	#define RK3328_AUTO_CTRL 0x0024
	31	#define RK3328_INT_FINISH BIT(0)
	32	#define RK3328_AUTO_ENB BIT(0)
	33	#define RK3328_AUTO_RD BIT(1)
	34
02baff32 FX	35	#define RK3399_A_SHIFT 16
	36	#define RK3399_A_MASK 0x3ff
	37	#define RK3399_NBYTES 4
	38	#define RK3399_STROBSFTSEL BIT(9)
	39	#define RK3399_RSB BIT(7)
	40	#define RK3399_PD BIT(5)
	41	#define RK3399_PGENB BIT(3)
	42	#define RK3399_LOAD BIT(2)
	43	#define RK3399_STROBE BIT(1)
	44	#define RK3399_CSB BIT(0)
	45
	46	#define REG_EFUSE_CTRL 0x0000
	47	#define REG_EFUSE_DOUT 0x0004
03a69568	48
c37ff3fb	49	struct rockchip_efuse_chip {
03a69568 Z	50	struct device *dev;
03a69568 Z	51	void __iomem *base;
c37ff3fb	52	struct clk *clk;
03a69568 Z	53	};
03a69568 Z	54
02baff32 FX	55	static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
02baff32 FX	56	void *val, size_t bytes)
03a69568	57	{
c37ff3fb	58	struct rockchip_efuse_chip *efuse = context;
03a69568 Z	59	u8 *buf = val;
	60	int ret;
	61
c37ff3fb	62	ret = clk_prepare_enable(efuse->clk);
03a69568	63	if (ret < 0) {
c37ff3fb	64	dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
03a69568 Z	65	return ret;
	66	}
	67
02baff32	68	writel(RK3288_LOAD \| RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
03a69568	69	udelay(1);
cc907553	70	while (bytes--) {
c37ff3fb	71	writel(readl(efuse->base + REG_EFUSE_CTRL) &
02baff32	72	(~(RK3288_A_MASK << RK3288_A_SHIFT)),
c37ff3fb CW	73	efuse->base + REG_EFUSE_CTRL);
c37ff3fb CW	74	writel(readl(efuse->base + REG_EFUSE_CTRL) \|
02baff32	75	((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
c37ff3fb	76	efuse->base + REG_EFUSE_CTRL);
03a69568	77	udelay(1);
c37ff3fb	78	writel(readl(efuse->base + REG_EFUSE_CTRL) \|
02baff32	79	RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
03a69568	80	udelay(1);
c37ff3fb CW	81	*buf++ = readb(efuse->base + REG_EFUSE_DOUT);
c37ff3fb CW	82	writel(readl(efuse->base + REG_EFUSE_CTRL) &
02baff32 FX	83	(~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
	84	udelay(1);
	85	}
	86
	87	/* Switch to standby mode */
	88	writel(RK3288_PGENB \| RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
	89
	90	clk_disable_unprepare(efuse->clk);
	91
	92	return 0;
	93	}
	94
9a479b08 FX	95	static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
	96	void *val, size_t bytes)
	97	{
	98	struct rockchip_efuse_chip *efuse = context;
	99	unsigned int addr_start, addr_end, addr_offset, addr_len;
	100	u32 out_value, status;
	101	u8 *buf;
	102	int ret, i = 0;
	103
	104	ret = clk_prepare_enable(efuse->clk);
	105	if (ret < 0) {
	106	dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
	107	return ret;
	108	}
	109
	110	/* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
	111	offset += RK3328_SECURE_SIZES;
	112	addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
	113	addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
	114	addr_offset = offset % RK3399_NBYTES;
	115	addr_len = addr_end - addr_start;
	116
6396bb22 KC	117	buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
6396bb22 KC	118	GFP_KERNEL);
9a479b08 FX	119	if (!buf) {
	120	ret = -ENOMEM;
	121	goto nomem;
	122	}
	123
	124	while (addr_len--) {
	125	writel(RK3328_AUTO_RD \| RK3328_AUTO_ENB \|
	126	((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
	127	efuse->base + RK3328_AUTO_CTRL);
	128	udelay(4);
	129	status = readl(efuse->base + RK3328_INT_STATUS);
	130	if (!(status & RK3328_INT_FINISH)) {
	131	ret = -EIO;
	132	goto err;
	133	}
	134	out_value = readl(efuse->base + RK3328_DOUT);
	135	writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
	136
	137	memcpy(&buf[i], &out_value, RK3399_NBYTES);
	138	i += RK3399_NBYTES;
	139	}
	140
	141	memcpy(val, buf + addr_offset, bytes);
	142	err:
	143	kfree(buf);
	144	nomem:
	145	clk_disable_unprepare(efuse->clk);
	146
	147	return ret;
	148	}
	149
02baff32 FX	150	static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
	151	void *val, size_t bytes)
	152	{
	153	struct rockchip_efuse_chip *efuse = context;
	154	unsigned int addr_start, addr_end, addr_offset, addr_len;
	155	u32 out_value;
	156	u8 *buf;
	157	int ret, i = 0;
	158
	159	ret = clk_prepare_enable(efuse->clk);
	160	if (ret < 0) {
	161	dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
	162	return ret;
	163	}
	164
	165	addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
	166	addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
	167	addr_offset = offset % RK3399_NBYTES;
	168	addr_len = addr_end - addr_start;
	169
6396bb22 KC	170	buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
6396bb22 KC	171	GFP_KERNEL);
02baff32 FX	172	if (!buf) {
	173	clk_disable_unprepare(efuse->clk);
	174	return -ENOMEM;
	175	}
	176
	177	writel(RK3399_LOAD \| RK3399_PGENB \| RK3399_STROBSFTSEL \| RK3399_RSB,
	178	efuse->base + REG_EFUSE_CTRL);
	179	udelay(1);
	180	while (addr_len--) {
	181	writel(readl(efuse->base + REG_EFUSE_CTRL) \| RK3399_STROBE \|
	182	((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
	183	efuse->base + REG_EFUSE_CTRL);
03a69568	184	udelay(1);
02baff32 FX	185	out_value = readl(efuse->base + REG_EFUSE_DOUT);
	186	writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
	187	efuse->base + REG_EFUSE_CTRL);
	188	udelay(1);
	189
	190	memcpy(&buf[i], &out_value, RK3399_NBYTES);
	191	i += RK3399_NBYTES;
03a69568 Z	192	}
	193
	194	/* Switch to standby mode */
02baff32 FX	195	writel(RK3399_PD \| RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
	196
	197	memcpy(val, buf + addr_offset, bytes);
	198
	199	kfree(buf);
03a69568	200
c37ff3fb	201	clk_disable_unprepare(efuse->clk);
03a69568 Z	202
	203	return 0;
	204	}
	205
03a69568 Z	206	static struct nvmem_config econfig = {
03a69568 Z	207	.name = "rockchip-efuse",
cc907553 SK	208	.stride = 1,
cc907553 SK	209	.word_size = 1,
03a69568 Z	210	.read_only = true,
	211	};
	212
	213	static const struct of_device_id rockchip_efuse_match[] = {
02baff32 FX	214	/* deprecated but kept around for dts binding compatibility */
	215	{
	216	.compatible = "rockchip,rockchip-efuse",
	217	.data = (void *)&rockchip_rk3288_efuse_read,
	218	},
	219	{
	220	.compatible = "rockchip,rk3066a-efuse",
	221	.data = (void *)&rockchip_rk3288_efuse_read,
	222	},
	223	{
	224	.compatible = "rockchip,rk3188-efuse",
	225	.data = (void *)&rockchip_rk3288_efuse_read,
	226	},
820de1fb	227	{
d6e4bd1b	228	.compatible = "rockchip,rk3228-efuse",
820de1fb FX	229	.data = (void *)&rockchip_rk3288_efuse_read,
820de1fb FX	230	},
02baff32 FX	231	{
	232	.compatible = "rockchip,rk3288-efuse",
	233	.data = (void *)&rockchip_rk3288_efuse_read,
	234	},
7a15cf2a RP	235	{
	236	.compatible = "rockchip,rk3368-efuse",
	237	.data = (void *)&rockchip_rk3288_efuse_read,
	238	},
9a479b08 FX	239	{
	240	.compatible = "rockchip,rk3328-efuse",
	241	.data = (void *)&rockchip_rk3328_efuse_read,
	242	},
02baff32 FX	243	{
	244	.compatible = "rockchip,rk3399-efuse",
	245	.data = (void *)&rockchip_rk3399_efuse_read,
	246	},
03a69568 Z	247	{ /* sentinel */},
	248	};
	249	MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
	250
7e532f79	251	static int rockchip_efuse_probe(struct platform_device *pdev)
03a69568	252	{
03a69568 Z	253	struct resource *res;
03a69568 Z	254	struct nvmem_device *nvmem;
c37ff3fb	255	struct rockchip_efuse_chip *efuse;
7b4e76cb	256	const void *data;
02baff32 FX	257	struct device *dev = &pdev->dev;
02baff32 FX	258
7b4e76cb AS	259	data = of_device_get_match_data(dev);
7b4e76cb AS	260	if (!data) {
02baff32 FX	261	dev_err(dev, "failed to get match data\n");
	262	return -EINVAL;
	263	}
03a69568	264
e84d1f96	265	efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
c37ff3fb CW	266	GFP_KERNEL);
	267	if (!efuse)
	268	return -ENOMEM;
03a69568	269
c37ff3fb	270	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e84d1f96	271	efuse->base = devm_ioremap_resource(dev, res);
c37ff3fb CW	272	if (IS_ERR(efuse->base))
c37ff3fb CW	273	return PTR_ERR(efuse->base);
03a69568	274
e84d1f96	275	efuse->clk = devm_clk_get(dev, "pclk_efuse");
c37ff3fb CW	276	if (IS_ERR(efuse->clk))
c37ff3fb CW	277	return PTR_ERR(efuse->clk);
03a69568	278
e84d1f96	279	efuse->dev = dev;
32277723 FX	280	if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
	281	&econfig.size))
	282	econfig.size = resource_size(res);
7b4e76cb	283	econfig.reg_read = data;
cc907553	284	econfig.priv = efuse;
c37ff3fb	285	econfig.dev = efuse->dev;
f4bec713	286	nvmem = devm_nvmem_register(dev, &econfig);
03a69568	287
f4bec713	288	return PTR_ERR_OR_ZERO(nvmem);
03a69568 Z	289	}
	290
	291	static struct platform_driver rockchip_efuse_driver = {
	292	.probe = rockchip_efuse_probe,
03a69568 Z	293	.driver = {
	294	.name = "rockchip-efuse",
	295	.of_match_table = rockchip_efuse_match,
	296	},
	297	};
	298
	299	module_platform_driver(rockchip_efuse_driver);
	300	MODULE_DESCRIPTION("rockchip_efuse driver");
	301	MODULE_LICENSE("GPL v2");