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c01e9a11 SW |
1 | /* |
2 | * Freescale MXS On-Chip OTP driver | |
3 | * | |
4 | * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com> | |
5 | * | |
6 | * Based on the driver from Huang Shijie and Christoph G. Baumann | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | #include <linux/clk.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/nvmem-provider.h> | |
26 | #include <linux/of_device.h> | |
27 | #include <linux/platform_device.h> | |
c01e9a11 SW |
28 | #include <linux/slab.h> |
29 | #include <linux/stmp_device.h> | |
30 | ||
31 | /* OCOTP registers and bits */ | |
32 | ||
33 | #define BM_OCOTP_CTRL_RD_BANK_OPEN BIT(12) | |
34 | #define BM_OCOTP_CTRL_ERROR BIT(9) | |
35 | #define BM_OCOTP_CTRL_BUSY BIT(8) | |
36 | ||
37 | #define OCOTP_TIMEOUT 10000 | |
38 | #define OCOTP_DATA_OFFSET 0x20 | |
39 | ||
40 | struct mxs_ocotp { | |
41 | struct clk *clk; | |
42 | void __iomem *base; | |
43 | struct nvmem_device *nvmem; | |
44 | }; | |
45 | ||
46 | static int mxs_ocotp_wait(struct mxs_ocotp *otp) | |
47 | { | |
48 | int timeout = OCOTP_TIMEOUT; | |
49 | unsigned int status = 0; | |
50 | ||
51 | while (timeout--) { | |
52 | status = readl(otp->base); | |
53 | ||
54 | if (!(status & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR))) | |
55 | break; | |
56 | ||
57 | cpu_relax(); | |
58 | } | |
59 | ||
60 | if (status & BM_OCOTP_CTRL_BUSY) | |
61 | return -EBUSY; | |
62 | else if (status & BM_OCOTP_CTRL_ERROR) | |
63 | return -EIO; | |
64 | ||
65 | return 0; | |
66 | } | |
67 | ||
7d8867d7 SK |
68 | static int mxs_ocotp_read(void *context, unsigned int offset, |
69 | void *val, size_t bytes) | |
c01e9a11 SW |
70 | { |
71 | struct mxs_ocotp *otp = context; | |
c01e9a11 SW |
72 | u32 *buf = val; |
73 | int ret; | |
74 | ||
75 | ret = clk_enable(otp->clk); | |
76 | if (ret) | |
77 | return ret; | |
78 | ||
79 | writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); | |
80 | ||
81 | ret = mxs_ocotp_wait(otp); | |
82 | if (ret) | |
83 | goto disable_clk; | |
84 | ||
85 | /* open OCOTP banks for read */ | |
86 | writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); | |
87 | ||
88 | /* approximately wait 33 hclk cycles */ | |
89 | udelay(1); | |
90 | ||
91 | ret = mxs_ocotp_wait(otp); | |
92 | if (ret) | |
93 | goto close_banks; | |
94 | ||
7d8867d7 | 95 | while (bytes) { |
c01e9a11 SW |
96 | if ((offset < OCOTP_DATA_OFFSET) || (offset % 16)) { |
97 | /* fill up non-data register */ | |
7d8867d7 | 98 | *buf++ = 0; |
c01e9a11 | 99 | } else { |
7d8867d7 | 100 | *buf++ = readl(otp->base + offset); |
c01e9a11 SW |
101 | } |
102 | ||
7d8867d7 SK |
103 | bytes -= 4; |
104 | offset += 4; | |
c01e9a11 SW |
105 | } |
106 | ||
107 | close_banks: | |
108 | /* close banks for power saving */ | |
109 | writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR); | |
110 | ||
111 | disable_clk: | |
112 | clk_disable(otp->clk); | |
113 | ||
114 | return ret; | |
115 | } | |
116 | ||
c01e9a11 SW |
117 | static struct nvmem_config ocotp_config = { |
118 | .name = "mxs-ocotp", | |
7d8867d7 SK |
119 | .stride = 16, |
120 | .word_size = 4, | |
c01e9a11 | 121 | .owner = THIS_MODULE, |
7d8867d7 | 122 | .reg_read = mxs_ocotp_read, |
c01e9a11 SW |
123 | }; |
124 | ||
7d8867d7 SK |
125 | struct mxs_data { |
126 | int size; | |
c01e9a11 SW |
127 | }; |
128 | ||
7d8867d7 SK |
129 | static const struct mxs_data imx23_data = { |
130 | .size = 0x220, | |
c01e9a11 SW |
131 | }; |
132 | ||
7d8867d7 SK |
133 | static const struct mxs_data imx28_data = { |
134 | .size = 0x2a0, | |
c01e9a11 SW |
135 | }; |
136 | ||
137 | static const struct of_device_id mxs_ocotp_match[] = { | |
7d8867d7 SK |
138 | { .compatible = "fsl,imx23-ocotp", .data = &imx23_data }, |
139 | { .compatible = "fsl,imx28-ocotp", .data = &imx28_data }, | |
c01e9a11 SW |
140 | { /* sentinel */}, |
141 | }; | |
142 | MODULE_DEVICE_TABLE(of, mxs_ocotp_match); | |
143 | ||
144 | static int mxs_ocotp_probe(struct platform_device *pdev) | |
145 | { | |
146 | struct device *dev = &pdev->dev; | |
7d8867d7 | 147 | const struct mxs_data *data; |
c01e9a11 SW |
148 | struct mxs_ocotp *otp; |
149 | struct resource *res; | |
150 | const struct of_device_id *match; | |
c01e9a11 SW |
151 | int ret; |
152 | ||
153 | match = of_match_device(dev->driver->of_match_table, dev); | |
154 | if (!match || !match->data) | |
155 | return -EINVAL; | |
156 | ||
157 | otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL); | |
158 | if (!otp) | |
159 | return -ENOMEM; | |
160 | ||
161 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
162 | otp->base = devm_ioremap_resource(dev, res); | |
163 | if (IS_ERR(otp->base)) | |
164 | return PTR_ERR(otp->base); | |
165 | ||
166 | otp->clk = devm_clk_get(&pdev->dev, NULL); | |
167 | if (IS_ERR(otp->clk)) | |
168 | return PTR_ERR(otp->clk); | |
169 | ||
170 | ret = clk_prepare(otp->clk); | |
171 | if (ret < 0) { | |
172 | dev_err(dev, "failed to prepare clk: %d\n", ret); | |
173 | return ret; | |
174 | } | |
175 | ||
7d8867d7 | 176 | data = match->data; |
c01e9a11 | 177 | |
7d8867d7 SK |
178 | ocotp_config.size = data->size; |
179 | ocotp_config.priv = otp; | |
c01e9a11 SW |
180 | ocotp_config.dev = dev; |
181 | otp->nvmem = nvmem_register(&ocotp_config); | |
182 | if (IS_ERR(otp->nvmem)) { | |
183 | ret = PTR_ERR(otp->nvmem); | |
184 | goto err_clk; | |
185 | } | |
186 | ||
187 | platform_set_drvdata(pdev, otp); | |
188 | ||
189 | return 0; | |
190 | ||
191 | err_clk: | |
192 | clk_unprepare(otp->clk); | |
193 | ||
194 | return ret; | |
195 | } | |
196 | ||
197 | static int mxs_ocotp_remove(struct platform_device *pdev) | |
198 | { | |
199 | struct mxs_ocotp *otp = platform_get_drvdata(pdev); | |
200 | ||
201 | clk_unprepare(otp->clk); | |
202 | ||
203 | return nvmem_unregister(otp->nvmem); | |
204 | } | |
205 | ||
206 | static struct platform_driver mxs_ocotp_driver = { | |
207 | .probe = mxs_ocotp_probe, | |
208 | .remove = mxs_ocotp_remove, | |
209 | .driver = { | |
210 | .name = "mxs-ocotp", | |
211 | .of_match_table = mxs_ocotp_match, | |
212 | }, | |
213 | }; | |
214 | ||
215 | module_platform_driver(mxs_ocotp_driver); | |
216 | MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>"); | |
217 | MODULE_DESCRIPTION("driver for OCOTP in i.MX23/i.MX28"); | |
218 | MODULE_LICENSE("GPL v2"); |