Commit | Line | Data |
---|---|---|
acee2e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
3edba6b4 PZ |
2 | /* |
3 | * i.MX6 OCOTP fusebox driver | |
4 | * | |
5 | * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> | |
6 | * | |
3311bf18 PF |
7 | * Copyright 2019 NXP |
8 | * | |
3edba6b4 PZ |
9 | * Based on the barebox ocotp driver, |
10 | * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, | |
11 | * Orex Computed Radiography | |
12 | * | |
0642bac7 RL |
13 | * Write support based on the fsl_otp driver, |
14 | * Copyright (C) 2010-2013 Freescale Semiconductor, Inc | |
3edba6b4 PZ |
15 | */ |
16 | ||
deb31970 | 17 | #include <linux/clk.h> |
3edba6b4 PZ |
18 | #include <linux/device.h> |
19 | #include <linux/io.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/nvmem-provider.h> | |
22 | #include <linux/of.h> | |
3edba6b4 | 23 | #include <linux/platform_device.h> |
3edba6b4 | 24 | #include <linux/slab.h> |
0642bac7 | 25 | #include <linux/delay.h> |
3edba6b4 | 26 | |
9b66587e RL |
27 | #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the |
28 | * OTP Bank0 Word0 | |
29 | */ | |
30 | #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr | |
31 | * of two consecutive OTP words. | |
32 | */ | |
0642bac7 | 33 | |
9b66587e | 34 | #define IMX_OCOTP_ADDR_CTRL 0x0000 |
0642bac7 | 35 | #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 |
9b66587e | 36 | #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 |
0642bac7 | 37 | #define IMX_OCOTP_ADDR_TIMING 0x0010 |
ffd9115f BD |
38 | #define IMX_OCOTP_ADDR_DATA0 0x0020 |
39 | #define IMX_OCOTP_ADDR_DATA1 0x0030 | |
40 | #define IMX_OCOTP_ADDR_DATA2 0x0040 | |
41 | #define IMX_OCOTP_ADDR_DATA3 0x0050 | |
9b66587e | 42 | |
c03bb448 | 43 | #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF |
0642bac7 | 44 | #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 |
9b66587e | 45 | #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 |
0642bac7 | 46 | #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 |
9b66587e | 47 | |
c3f4af8b PF |
48 | #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF |
49 | #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200 | |
50 | #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400 | |
51 | #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800 | |
52 | ||
226c5126 PF |
53 | #define IMX_OCOTP_BM_CTRL_DEFAULT \ |
54 | { \ | |
55 | .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \ | |
56 | .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \ | |
57 | .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \ | |
58 | .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\ | |
59 | } | |
60 | ||
c3f4af8b PF |
61 | #define IMX_OCOTP_BM_CTRL_8MP \ |
62 | { \ | |
63 | .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \ | |
64 | .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \ | |
65 | .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \ | |
66 | .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\ | |
67 | } | |
68 | ||
159dbaf5 BD |
69 | #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ |
70 | #define TIMING_STROBE_READ_NS 37 /* Min time before read */ | |
71 | #define TIMING_RELAX_NS 17 | |
828ae7a4 BD |
72 | #define DEF_FSOURCE 1001 /* > 1000 ns */ |
73 | #define DEF_STROBE_PROG 10000 /* IPG clocks */ | |
0642bac7 | 74 | #define IMX_OCOTP_WR_UNLOCK 0x3E770000 |
9b66587e RL |
75 | #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA |
76 | ||
0642bac7 RL |
77 | static DEFINE_MUTEX(ocotp_mutex); |
78 | ||
3edba6b4 PZ |
79 | struct ocotp_priv { |
80 | struct device *dev; | |
deb31970 | 81 | struct clk *clk; |
3edba6b4 | 82 | void __iomem *base; |
e20d2b29 | 83 | const struct ocotp_params *params; |
0642bac7 | 84 | struct nvmem_config *config; |
3edba6b4 PZ |
85 | }; |
86 | ||
226c5126 PF |
87 | struct ocotp_ctrl_reg { |
88 | u32 bm_addr; | |
89 | u32 bm_busy; | |
90 | u32 bm_error; | |
91 | u32 bm_rel_shadows; | |
92 | }; | |
93 | ||
828ae7a4 BD |
94 | struct ocotp_params { |
95 | unsigned int nregs; | |
96 | unsigned int bank_address_words; | |
97 | void (*set_timing)(struct ocotp_priv *priv); | |
226c5126 | 98 | struct ocotp_ctrl_reg ctrl; |
828ae7a4 BD |
99 | }; |
100 | ||
226c5126 | 101 | static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) |
0642bac7 RL |
102 | { |
103 | int count; | |
104 | u32 c, mask; | |
226c5126 PF |
105 | u32 bm_ctrl_busy, bm_ctrl_error; |
106 | void __iomem *base = priv->base; | |
0642bac7 | 107 | |
226c5126 PF |
108 | bm_ctrl_busy = priv->params->ctrl.bm_busy; |
109 | bm_ctrl_error = priv->params->ctrl.bm_error; | |
110 | ||
111 | mask = bm_ctrl_busy | bm_ctrl_error | flags; | |
0642bac7 RL |
112 | |
113 | for (count = 10000; count >= 0; count--) { | |
114 | c = readl(base + IMX_OCOTP_ADDR_CTRL); | |
115 | if (!(c & mask)) | |
116 | break; | |
117 | cpu_relax(); | |
118 | } | |
119 | ||
120 | if (count < 0) { | |
121 | /* HW_OCOTP_CTRL[ERROR] will be set under the following | |
122 | * conditions: | |
123 | * - A write is performed to a shadow register during a shadow | |
124 | * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is | |
125 | * set. In addition, the contents of the shadow register shall | |
126 | * not be updated. | |
127 | * - A write is performed to a shadow register which has been | |
128 | * locked. | |
129 | * - A read is performed to from a shadow register which has | |
130 | * been read locked. | |
131 | * - A program is performed to a fuse word which has been locked | |
132 | * - A read is performed to from a fuse word which has been read | |
133 | * locked. | |
134 | */ | |
226c5126 | 135 | if (c & bm_ctrl_error) |
0642bac7 RL |
136 | return -EPERM; |
137 | return -ETIMEDOUT; | |
138 | } | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
226c5126 | 143 | static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv) |
9b66587e | 144 | { |
226c5126 PF |
145 | u32 c, bm_ctrl_error; |
146 | void __iomem *base = priv->base; | |
147 | ||
148 | bm_ctrl_error = priv->params->ctrl.bm_error; | |
9b66587e RL |
149 | |
150 | c = readl(base + IMX_OCOTP_ADDR_CTRL); | |
226c5126 | 151 | if (!(c & bm_ctrl_error)) |
9b66587e RL |
152 | return; |
153 | ||
226c5126 | 154 | writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR); |
9b66587e RL |
155 | } |
156 | ||
33e5e29c SK |
157 | static int imx_ocotp_read(void *context, unsigned int offset, |
158 | void *val, size_t bytes) | |
3edba6b4 PZ |
159 | { |
160 | struct ocotp_priv *priv = context; | |
3edba6b4 | 161 | unsigned int count; |
3311bf18 | 162 | u8 *buf, *p; |
deb31970 | 163 | int i, ret; |
3311bf18 | 164 | u32 index, num_bytes; |
3edba6b4 PZ |
165 | |
166 | index = offset >> 2; | |
3311bf18 PF |
167 | num_bytes = round_up((offset % 4) + bytes, 4); |
168 | count = num_bytes >> 2; | |
3edba6b4 | 169 | |
e20d2b29 BD |
170 | if (count > (priv->params->nregs - index)) |
171 | count = priv->params->nregs - index; | |
3edba6b4 | 172 | |
3311bf18 PF |
173 | p = kzalloc(num_bytes, GFP_KERNEL); |
174 | if (!p) | |
175 | return -ENOMEM; | |
176 | ||
0642bac7 RL |
177 | mutex_lock(&ocotp_mutex); |
178 | ||
3311bf18 PF |
179 | buf = p; |
180 | ||
deb31970 PF |
181 | ret = clk_prepare_enable(priv->clk); |
182 | if (ret < 0) { | |
0642bac7 | 183 | mutex_unlock(&ocotp_mutex); |
deb31970 | 184 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); |
3311bf18 | 185 | kfree(p); |
deb31970 PF |
186 | return ret; |
187 | } | |
3edba6b4 | 188 | |
226c5126 | 189 | ret = imx_ocotp_wait_for_busy(priv, 0); |
0642bac7 RL |
190 | if (ret < 0) { |
191 | dev_err(priv->dev, "timeout during read setup\n"); | |
192 | goto read_end; | |
193 | } | |
194 | ||
9b66587e | 195 | for (i = index; i < (index + count); i++) { |
3311bf18 | 196 | *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + |
9b66587e | 197 | i * IMX_OCOTP_OFFSET_PER_WORD); |
deb31970 | 198 | |
9b66587e RL |
199 | /* 47.3.1.2 |
200 | * For "read locked" registers 0xBADABADA will be returned and | |
201 | * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by | |
202 | * software before any new write, read or reload access can be | |
203 | * issued | |
204 | */ | |
3311bf18 | 205 | if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL) |
226c5126 | 206 | imx_ocotp_clr_err_if_set(priv); |
3311bf18 PF |
207 | |
208 | buf += 4; | |
9b66587e RL |
209 | } |
210 | ||
3311bf18 PF |
211 | index = offset % 4; |
212 | memcpy(val, &p[index], bytes); | |
213 | ||
0642bac7 | 214 | read_end: |
9b66587e | 215 | clk_disable_unprepare(priv->clk); |
0642bac7 | 216 | mutex_unlock(&ocotp_mutex); |
3311bf18 PF |
217 | |
218 | kfree(p); | |
219 | ||
0642bac7 RL |
220 | return ret; |
221 | } | |
222 | ||
5d8e6e6c MW |
223 | static int imx_ocotp_cell_pp(void *context, const char *id, int index, |
224 | unsigned int offset, void *data, size_t bytes) | |
d0221a78 | 225 | { |
6c56a82d MW |
226 | u8 *buf = data; |
227 | int i; | |
d0221a78 SK |
228 | |
229 | /* Deal with some post processing of nvmem cell data */ | |
6c56a82d MW |
230 | if (id && !strcmp(id, "mac-address")) |
231 | for (i = 0; i < bytes / 2; i++) | |
232 | swap(buf[i], buf[bytes - i - 1]); | |
d0221a78 SK |
233 | |
234 | return 0; | |
235 | } | |
236 | ||
b50cb68f BD |
237 | static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) |
238 | { | |
13d588ba | 239 | unsigned long clk_rate; |
b50cb68f | 240 | unsigned long strobe_read, relax, strobe_prog; |
13d588ba | 241 | u32 timing; |
b50cb68f BD |
242 | |
243 | /* 47.3.1.3.1 | |
244 | * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] | |
245 | * fields with timing values to match the current frequency of the | |
246 | * ipg_clk. OTP writes will work at maximum bus frequencies as long | |
247 | * as the HW_OCOTP_TIMING parameters are set correctly. | |
159dbaf5 BD |
248 | * |
249 | * Note: there are minimum timings required to ensure an OTP fuse burns | |
250 | * correctly that are independent of the ipg_clk. Those values are not | |
251 | * formally documented anywhere however, working from the minimum | |
252 | * timings given in u-boot we can say: | |
253 | * | |
254 | * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 | |
255 | * microseconds feels about right as representative of a minimum time | |
256 | * to physically burn out a fuse. | |
257 | * | |
258 | * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before | |
259 | * performing another read is 37 nanoseconds | |
260 | * | |
261 | * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum | |
262 | * timing is not entirely clear the documentation says "This | |
263 | * count value specifies the time to add to all default timing | |
264 | * parameters other than the Tpgm and Trd. It is given in number | |
265 | * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG | |
266 | * and STROBE_READ respectively. What the other timing parameters | |
267 | * are though, is not specified. Experience shows a zero RELAX | |
268 | * value will mess up a re-load of the shadow registers post OTP | |
269 | * burn. | |
b50cb68f BD |
270 | */ |
271 | clk_rate = clk_get_rate(priv->clk); | |
272 | ||
159dbaf5 BD |
273 | relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; |
274 | strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, | |
275 | 1000000000); | |
276 | strobe_read += 2 * (relax + 1) - 1; | |
277 | strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, | |
278 | 1000000); | |
279 | strobe_prog += 2 * (relax + 1) - 1; | |
b50cb68f | 280 | |
0493c479 BD |
281 | timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; |
282 | timing |= strobe_prog & 0x00000FFF; | |
b50cb68f BD |
283 | timing |= (relax << 12) & 0x0000F000; |
284 | timing |= (strobe_read << 16) & 0x003F0000; | |
285 | ||
286 | writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); | |
287 | } | |
288 | ||
828ae7a4 BD |
289 | static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) |
290 | { | |
13d588ba | 291 | unsigned long clk_rate; |
828ae7a4 | 292 | u64 fsource, strobe_prog; |
13d588ba | 293 | u32 timing; |
828ae7a4 BD |
294 | |
295 | /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 | |
296 | * 6.4.3.3 | |
297 | */ | |
298 | clk_rate = clk_get_rate(priv->clk); | |
299 | fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, | |
300 | NSEC_PER_SEC) + 1; | |
301 | strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, | |
302 | NSEC_PER_SEC) + 1; | |
303 | ||
304 | timing = strobe_prog & 0x00000FFF; | |
305 | timing |= (fsource << 12) & 0x000FF000; | |
306 | ||
307 | writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); | |
308 | } | |
309 | ||
0642bac7 RL |
310 | static int imx_ocotp_write(void *context, unsigned int offset, void *val, |
311 | size_t bytes) | |
312 | { | |
313 | struct ocotp_priv *priv = context; | |
314 | u32 *buf = val; | |
315 | int ret; | |
316 | ||
0642bac7 RL |
317 | u32 ctrl; |
318 | u8 waddr; | |
ffd9115f | 319 | u8 word = 0; |
0642bac7 RL |
320 | |
321 | /* allow only writing one complete OTP word at a time */ | |
322 | if ((bytes != priv->config->word_size) || | |
323 | (offset % priv->config->word_size)) | |
324 | return -EINVAL; | |
325 | ||
326 | mutex_lock(&ocotp_mutex); | |
327 | ||
328 | ret = clk_prepare_enable(priv->clk); | |
329 | if (ret < 0) { | |
330 | mutex_unlock(&ocotp_mutex); | |
331 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); | |
332 | return ret; | |
333 | } | |
334 | ||
b50cb68f | 335 | /* Setup the write timing values */ |
828ae7a4 | 336 | priv->params->set_timing(priv); |
0642bac7 RL |
337 | |
338 | /* 47.3.1.3.2 | |
339 | * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. | |
340 | * Overlapped accesses are not supported by the controller. Any pending | |
341 | * write or reload must be completed before a write access can be | |
342 | * requested. | |
343 | */ | |
226c5126 | 344 | ret = imx_ocotp_wait_for_busy(priv, 0); |
0642bac7 RL |
345 | if (ret < 0) { |
346 | dev_err(priv->dev, "timeout during timing setup\n"); | |
347 | goto write_end; | |
348 | } | |
349 | ||
350 | /* 47.3.1.3.3 | |
351 | * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the | |
352 | * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed | |
353 | * for each write access. The lock code is documented in the register | |
354 | * description. Both the unlock code and address can be written in the | |
355 | * same operation. | |
356 | */ | |
ffd9115f BD |
357 | if (priv->params->bank_address_words != 0) { |
358 | /* | |
359 | * In banked/i.MX7 mode the OTP register bank goes into waddr | |
360 | * see i.MX 7Solo Applications Processor Reference Manual, Rev. | |
361 | * 0.1 section 6.4.3.1 | |
362 | */ | |
363 | offset = offset / priv->config->word_size; | |
364 | waddr = offset / priv->params->bank_address_words; | |
365 | word = offset & (priv->params->bank_address_words - 1); | |
366 | } else { | |
367 | /* | |
368 | * Non-banked i.MX6 mode. | |
369 | * OTP write/read address specifies one of 128 word address | |
370 | * locations | |
371 | */ | |
372 | waddr = offset / 4; | |
373 | } | |
0642bac7 RL |
374 | |
375 | ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); | |
226c5126 PF |
376 | ctrl &= ~priv->params->ctrl.bm_addr; |
377 | ctrl |= waddr & priv->params->ctrl.bm_addr; | |
0642bac7 RL |
378 | ctrl |= IMX_OCOTP_WR_UNLOCK; |
379 | ||
380 | writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); | |
381 | ||
382 | /* 47.3.1.3.4 | |
383 | * Write the data to the HW_OCOTP_DATA register. This will automatically | |
384 | * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To | |
385 | * protect programming same OTP bit twice, before program OCOTP will | |
386 | * automatically read fuse value in OTP and use read value to mask | |
387 | * program data. The controller will use masked program data to program | |
388 | * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit | |
389 | * fields with 1's will result in that OTP bit being programmed. Bit | |
390 | * fields with 0's will be ignored. At the same time that the write is | |
391 | * accepted, the controller makes an internal copy of | |
392 | * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write | |
393 | * sequence is initiated. This copy guarantees that erroneous writes to | |
394 | * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It | |
395 | * should also be noted that during the programming HW_OCOTP_DATA will | |
396 | * shift right (with zero fill). This shifting is required to program | |
397 | * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be | |
398 | * modified. | |
ffd9115f BD |
399 | * Note: on i.MX7 there are four data fields to write for banked write |
400 | * with the fuse blowing operation only taking place after data0 | |
401 | * has been written. This is why data0 must always be the last | |
402 | * register written. | |
0642bac7 | 403 | */ |
ffd9115f BD |
404 | if (priv->params->bank_address_words != 0) { |
405 | /* Banked/i.MX7 mode */ | |
406 | switch (word) { | |
407 | case 0: | |
408 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
409 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
410 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
411 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); | |
412 | break; | |
413 | case 1: | |
414 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); | |
415 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
416 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
417 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
418 | break; | |
419 | case 2: | |
420 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
421 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); | |
422 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
423 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
424 | break; | |
425 | case 3: | |
426 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
427 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
428 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); | |
429 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
430 | break; | |
431 | } | |
432 | } else { | |
433 | /* Non-banked i.MX6 mode */ | |
434 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); | |
435 | } | |
0642bac7 RL |
436 | |
437 | /* 47.4.1.4.5 | |
438 | * Once complete, the controller will clear BUSY. A write request to a | |
439 | * protected or locked region will result in no OTP access and no | |
440 | * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will | |
441 | * be set. It must be cleared by software before any new write access | |
442 | * can be issued. | |
443 | */ | |
226c5126 | 444 | ret = imx_ocotp_wait_for_busy(priv, 0); |
0642bac7 RL |
445 | if (ret < 0) { |
446 | if (ret == -EPERM) { | |
447 | dev_err(priv->dev, "failed write to locked region"); | |
226c5126 | 448 | imx_ocotp_clr_err_if_set(priv); |
0642bac7 RL |
449 | } else { |
450 | dev_err(priv->dev, "timeout during data write\n"); | |
451 | } | |
452 | goto write_end; | |
453 | } | |
454 | ||
455 | /* 47.3.1.4 | |
456 | * Write Postamble: Due to internal electrical characteristics of the | |
457 | * OTP during writes, all OTP operations following a write must be | |
458 | * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following | |
459 | * the write. | |
460 | */ | |
461 | udelay(2); | |
462 | ||
463 | /* reload all shadow registers */ | |
226c5126 | 464 | writel(priv->params->ctrl.bm_rel_shadows, |
0642bac7 | 465 | priv->base + IMX_OCOTP_ADDR_CTRL_SET); |
226c5126 PF |
466 | ret = imx_ocotp_wait_for_busy(priv, |
467 | priv->params->ctrl.bm_rel_shadows); | |
0e2abffd | 468 | if (ret < 0) |
0642bac7 | 469 | dev_err(priv->dev, "timeout during shadow register reload\n"); |
0642bac7 RL |
470 | |
471 | write_end: | |
472 | clk_disable_unprepare(priv->clk); | |
473 | mutex_unlock(&ocotp_mutex); | |
0e2abffd | 474 | return ret < 0 ? ret : bytes; |
3edba6b4 PZ |
475 | } |
476 | ||
3edba6b4 PZ |
477 | static struct nvmem_config imx_ocotp_nvmem_config = { |
478 | .name = "imx-ocotp", | |
0642bac7 | 479 | .read_only = false, |
33e5e29c | 480 | .word_size = 4, |
3311bf18 | 481 | .stride = 1, |
33e5e29c | 482 | .reg_read = imx_ocotp_read, |
0642bac7 | 483 | .reg_write = imx_ocotp_write, |
3edba6b4 PZ |
484 | }; |
485 | ||
e20d2b29 BD |
486 | static const struct ocotp_params imx6q_params = { |
487 | .nregs = 128, | |
ffd9115f | 488 | .bank_address_words = 0, |
828ae7a4 | 489 | .set_timing = imx_ocotp_set_imx6_timing, |
226c5126 | 490 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
e20d2b29 BD |
491 | }; |
492 | ||
493 | static const struct ocotp_params imx6sl_params = { | |
494 | .nregs = 64, | |
ffd9115f | 495 | .bank_address_words = 0, |
828ae7a4 | 496 | .set_timing = imx_ocotp_set_imx6_timing, |
226c5126 | 497 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
e20d2b29 BD |
498 | }; |
499 | ||
6da27821 AH |
500 | static const struct ocotp_params imx6sll_params = { |
501 | .nregs = 128, | |
502 | .bank_address_words = 0, | |
503 | .set_timing = imx_ocotp_set_imx6_timing, | |
226c5126 | 504 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
6da27821 AH |
505 | }; |
506 | ||
e20d2b29 BD |
507 | static const struct ocotp_params imx6sx_params = { |
508 | .nregs = 128, | |
ffd9115f | 509 | .bank_address_words = 0, |
828ae7a4 | 510 | .set_timing = imx_ocotp_set_imx6_timing, |
226c5126 | 511 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
e20d2b29 BD |
512 | }; |
513 | ||
514 | static const struct ocotp_params imx6ul_params = { | |
515 | .nregs = 128, | |
ffd9115f | 516 | .bank_address_words = 0, |
828ae7a4 | 517 | .set_timing = imx_ocotp_set_imx6_timing, |
226c5126 | 518 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
e20d2b29 BD |
519 | }; |
520 | ||
ffbc34bf SW |
521 | static const struct ocotp_params imx6ull_params = { |
522 | .nregs = 64, | |
523 | .bank_address_words = 0, | |
524 | .set_timing = imx_ocotp_set_imx6_timing, | |
226c5126 | 525 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
ffbc34bf SW |
526 | }; |
527 | ||
e20d2b29 BD |
528 | static const struct ocotp_params imx7d_params = { |
529 | .nregs = 64, | |
ffd9115f | 530 | .bank_address_words = 4, |
828ae7a4 | 531 | .set_timing = imx_ocotp_set_imx7_timing, |
226c5126 | 532 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
e20d2b29 BD |
533 | }; |
534 | ||
c8b63ddc AH |
535 | static const struct ocotp_params imx7ulp_params = { |
536 | .nregs = 256, | |
537 | .bank_address_words = 0, | |
226c5126 | 538 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
c8b63ddc AH |
539 | }; |
540 | ||
38e7b6ef LS |
541 | static const struct ocotp_params imx8mq_params = { |
542 | .nregs = 256, | |
5a1c1724 LC |
543 | .bank_address_words = 0, |
544 | .set_timing = imx_ocotp_set_imx6_timing, | |
226c5126 | 545 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
38e7b6ef LS |
546 | }; |
547 | ||
4112c853 BD |
548 | static const struct ocotp_params imx8mm_params = { |
549 | .nregs = 256, | |
550 | .bank_address_words = 0, | |
551 | .set_timing = imx_ocotp_set_imx6_timing, | |
226c5126 | 552 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
4112c853 BD |
553 | }; |
554 | ||
d93b5d4a AH |
555 | static const struct ocotp_params imx8mn_params = { |
556 | .nregs = 256, | |
557 | .bank_address_words = 0, | |
558 | .set_timing = imx_ocotp_set_imx6_timing, | |
226c5126 | 559 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
d93b5d4a AH |
560 | }; |
561 | ||
c3f4af8b PF |
562 | static const struct ocotp_params imx8mp_params = { |
563 | .nregs = 384, | |
564 | .bank_address_words = 0, | |
565 | .set_timing = imx_ocotp_set_imx6_timing, | |
566 | .ctrl = IMX_OCOTP_BM_CTRL_8MP, | |
567 | }; | |
568 | ||
3edba6b4 | 569 | static const struct of_device_id imx_ocotp_dt_ids[] = { |
e20d2b29 BD |
570 | { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, |
571 | { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, | |
572 | { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params }, | |
573 | { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params }, | |
ffbc34bf | 574 | { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params }, |
e20d2b29 | 575 | { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, |
6da27821 | 576 | { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, |
c8b63ddc | 577 | { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, |
38e7b6ef | 578 | { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, |
4112c853 | 579 | { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, |
d93b5d4a | 580 | { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params }, |
c3f4af8b | 581 | { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params }, |
3edba6b4 PZ |
582 | { }, |
583 | }; | |
584 | MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); | |
585 | ||
6c56a82d MW |
586 | static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem, |
587 | struct nvmem_layout *layout, | |
588 | struct nvmem_cell_info *cell) | |
589 | { | |
590 | cell->read_post_process = imx_ocotp_cell_pp; | |
591 | } | |
592 | ||
eebc6573 | 593 | static struct nvmem_layout imx_ocotp_layout = { |
6c56a82d MW |
594 | .fixup_cell_info = imx_ocotp_fixup_cell_info, |
595 | }; | |
596 | ||
3edba6b4 PZ |
597 | static int imx_ocotp_probe(struct platform_device *pdev) |
598 | { | |
3edba6b4 | 599 | struct device *dev = &pdev->dev; |
3edba6b4 PZ |
600 | struct ocotp_priv *priv; |
601 | struct nvmem_device *nvmem; | |
602 | ||
603 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
604 | if (!priv) | |
605 | return -ENOMEM; | |
606 | ||
4cefb74a RL |
607 | priv->dev = dev; |
608 | ||
3b26cd88 | 609 | priv->base = devm_platform_ioremap_resource(pdev, 0); |
3edba6b4 PZ |
610 | if (IS_ERR(priv->base)) |
611 | return PTR_ERR(priv->base); | |
612 | ||
4cefb74a | 613 | priv->clk = devm_clk_get(dev, NULL); |
deb31970 PF |
614 | if (IS_ERR(priv->clk)) |
615 | return PTR_ERR(priv->clk); | |
616 | ||
e20d2b29 BD |
617 | priv->params = of_device_get_match_data(&pdev->dev); |
618 | imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; | |
3edba6b4 | 619 | imx_ocotp_nvmem_config.dev = dev; |
33e5e29c | 620 | imx_ocotp_nvmem_config.priv = priv; |
8a00fc60 | 621 | imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; |
6c56a82d | 622 | |
0642bac7 | 623 | priv->config = &imx_ocotp_nvmem_config; |
0642bac7 | 624 | |
226c5126 PF |
625 | clk_prepare_enable(priv->clk); |
626 | imx_ocotp_clr_err_if_set(priv); | |
627 | clk_disable_unprepare(priv->clk); | |
628 | ||
629 | nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); | |
3edba6b4 | 630 | |
a830274f | 631 | return PTR_ERR_OR_ZERO(nvmem); |
3edba6b4 PZ |
632 | } |
633 | ||
634 | static struct platform_driver imx_ocotp_driver = { | |
635 | .probe = imx_ocotp_probe, | |
3edba6b4 PZ |
636 | .driver = { |
637 | .name = "imx_ocotp", | |
638 | .of_match_table = imx_ocotp_dt_ids, | |
639 | }, | |
640 | }; | |
641 | module_platform_driver(imx_ocotp_driver); | |
642 | ||
643 | MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); | |
aef9a4de | 644 | MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver"); |
3edba6b4 | 645 | MODULE_LICENSE("GPL v2"); |