nvme: ensure reset state check ordering
[linux-2.6-block.git] / drivers / nvme / host / rdma.c
CommitLineData
5d8762d5 1// SPDX-License-Identifier: GPL-2.0
71102307
CH
2/*
3 * NVMe over Fabrics RDMA host code.
4 * Copyright (c) 2015-2016 HGST, a Western Digital Company.
71102307
CH
5 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
71102307
CH
7#include <linux/module.h>
8#include <linux/init.h>
9#include <linux/slab.h>
f41725bb 10#include <rdma/mr_pool.h>
71102307
CH
11#include <linux/err.h>
12#include <linux/string.h>
71102307
CH
13#include <linux/atomic.h>
14#include <linux/blk-mq.h>
fe45e630 15#include <linux/blk-integrity.h>
71102307
CH
16#include <linux/types.h>
17#include <linux/list.h>
18#include <linux/mutex.h>
19#include <linux/scatterlist.h>
20#include <linux/nvme.h>
71102307
CH
21#include <asm/unaligned.h>
22
23#include <rdma/ib_verbs.h>
24#include <rdma/rdma_cm.h>
71102307
CH
25#include <linux/nvme-rdma.h>
26
27#include "nvme.h"
28#include "fabrics.h"
29
30
0525af71 31#define NVME_RDMA_CM_TIMEOUT_MS 3000 /* 3 second */
71102307 32
71102307
CH
33#define NVME_RDMA_MAX_SEGMENTS 256
34
64a741c1 35#define NVME_RDMA_MAX_INLINE_SEGMENTS 4
71102307 36
5ec5d3bd
MG
37#define NVME_RDMA_DATA_SGL_SIZE \
38 (sizeof(struct scatterlist) * NVME_INLINE_SG_CNT)
39#define NVME_RDMA_METADATA_SGL_SIZE \
40 (sizeof(struct scatterlist) * NVME_INLINE_METADATA_SG_CNT)
41
71102307 42struct nvme_rdma_device {
f87c89ad
MG
43 struct ib_device *dev;
44 struct ib_pd *pd;
71102307
CH
45 struct kref ref;
46 struct list_head entry;
64a741c1 47 unsigned int num_inline_segments;
71102307
CH
48};
49
50struct nvme_rdma_qe {
51 struct ib_cqe cqe;
52 void *data;
53 u64 dma;
54};
55
324d9e78
IR
56struct nvme_rdma_sgl {
57 int nents;
58 struct sg_table sg_table;
59};
60
71102307
CH
61struct nvme_rdma_queue;
62struct nvme_rdma_request {
d49187e9 63 struct nvme_request req;
71102307
CH
64 struct ib_mr *mr;
65 struct nvme_rdma_qe sqe;
4af7f7ff
SG
66 union nvme_result result;
67 __le16 status;
68 refcount_t ref;
71102307
CH
69 struct ib_sge sge[1 + NVME_RDMA_MAX_INLINE_SEGMENTS];
70 u32 num_sge;
71102307
CH
71 struct ib_reg_wr reg_wr;
72 struct ib_cqe reg_cqe;
73 struct nvme_rdma_queue *queue;
324d9e78 74 struct nvme_rdma_sgl data_sgl;
5ec5d3bd
MG
75 struct nvme_rdma_sgl *metadata_sgl;
76 bool use_sig_mr;
71102307
CH
77};
78
79enum nvme_rdma_queue_flags {
5013e98b
SG
80 NVME_RDMA_Q_ALLOCATED = 0,
81 NVME_RDMA_Q_LIVE = 1,
eb1bd249 82 NVME_RDMA_Q_TR_READY = 2,
71102307
CH
83};
84
85struct nvme_rdma_queue {
86 struct nvme_rdma_qe *rsp_ring;
71102307
CH
87 int queue_size;
88 size_t cmnd_capsule_len;
89 struct nvme_rdma_ctrl *ctrl;
90 struct nvme_rdma_device *device;
91 struct ib_cq *ib_cq;
92 struct ib_qp *qp;
93
94 unsigned long flags;
95 struct rdma_cm_id *cm_id;
96 int cm_error;
97 struct completion cm_done;
5ec5d3bd 98 bool pi_support;
287f329e 99 int cq_size;
7674073b 100 struct mutex queue_lock;
71102307
CH
101};
102
103struct nvme_rdma_ctrl {
71102307
CH
104 /* read only in the hot path */
105 struct nvme_rdma_queue *queues;
71102307
CH
106
107 /* other member variables */
71102307 108 struct blk_mq_tag_set tag_set;
71102307
CH
109 struct work_struct err_work;
110
111 struct nvme_rdma_qe async_event_sqe;
112
71102307
CH
113 struct delayed_work reconnect_work;
114
115 struct list_head list;
116
117 struct blk_mq_tag_set admin_tag_set;
118 struct nvme_rdma_device *device;
119
71102307
CH
120 u32 max_fr_pages;
121
0928f9b4
SG
122 struct sockaddr_storage addr;
123 struct sockaddr_storage src_addr;
71102307
CH
124
125 struct nvme_ctrl ctrl;
64a741c1 126 bool use_inline_data;
b1064d3e 127 u32 io_queues[HCTX_MAX_TYPES];
71102307
CH
128};
129
130static inline struct nvme_rdma_ctrl *to_rdma_ctrl(struct nvme_ctrl *ctrl)
131{
132 return container_of(ctrl, struct nvme_rdma_ctrl, ctrl);
133}
134
135static LIST_HEAD(device_list);
136static DEFINE_MUTEX(device_list_mutex);
137
138static LIST_HEAD(nvme_rdma_ctrl_list);
139static DEFINE_MUTEX(nvme_rdma_ctrl_mutex);
140
71102307
CH
141/*
142 * Disabling this option makes small I/O goes faster, but is fundamentally
143 * unsafe. With it turned off we will have to register a global rkey that
144 * allows read and write access to all physical memory.
145 */
146static bool register_always = true;
147module_param(register_always, bool, 0444);
148MODULE_PARM_DESC(register_always,
149 "Use memory registration even for contiguous memory regions");
150
151static int nvme_rdma_cm_handler(struct rdma_cm_id *cm_id,
152 struct rdma_cm_event *event);
153static void nvme_rdma_recv_done(struct ib_cq *cq, struct ib_wc *wc);
ff029451 154static void nvme_rdma_complete_rq(struct request *rq);
71102307 155
90af3512
SG
156static const struct blk_mq_ops nvme_rdma_mq_ops;
157static const struct blk_mq_ops nvme_rdma_admin_mq_ops;
158
71102307
CH
159static inline int nvme_rdma_queue_idx(struct nvme_rdma_queue *queue)
160{
161 return queue - queue->ctrl->queues;
162}
163
ff8519f9
SG
164static bool nvme_rdma_poll_queue(struct nvme_rdma_queue *queue)
165{
166 return nvme_rdma_queue_idx(queue) >
b1064d3e
SG
167 queue->ctrl->io_queues[HCTX_TYPE_DEFAULT] +
168 queue->ctrl->io_queues[HCTX_TYPE_READ];
ff8519f9
SG
169}
170
71102307
CH
171static inline size_t nvme_rdma_inline_data_size(struct nvme_rdma_queue *queue)
172{
173 return queue->cmnd_capsule_len - sizeof(struct nvme_command);
174}
175
176static void nvme_rdma_free_qe(struct ib_device *ibdev, struct nvme_rdma_qe *qe,
177 size_t capsule_size, enum dma_data_direction dir)
178{
179 ib_dma_unmap_single(ibdev, qe->dma, capsule_size, dir);
180 kfree(qe->data);
181}
182
183static int nvme_rdma_alloc_qe(struct ib_device *ibdev, struct nvme_rdma_qe *qe,
184 size_t capsule_size, enum dma_data_direction dir)
185{
186 qe->data = kzalloc(capsule_size, GFP_KERNEL);
187 if (!qe->data)
188 return -ENOMEM;
189
190 qe->dma = ib_dma_map_single(ibdev, qe->data, capsule_size, dir);
191 if (ib_dma_mapping_error(ibdev, qe->dma)) {
192 kfree(qe->data);
6344d02d 193 qe->data = NULL;
71102307
CH
194 return -ENOMEM;
195 }
196
197 return 0;
198}
199
200static void nvme_rdma_free_ring(struct ib_device *ibdev,
201 struct nvme_rdma_qe *ring, size_t ib_queue_size,
202 size_t capsule_size, enum dma_data_direction dir)
203{
204 int i;
205
206 for (i = 0; i < ib_queue_size; i++)
207 nvme_rdma_free_qe(ibdev, &ring[i], capsule_size, dir);
208 kfree(ring);
209}
210
211static struct nvme_rdma_qe *nvme_rdma_alloc_ring(struct ib_device *ibdev,
212 size_t ib_queue_size, size_t capsule_size,
213 enum dma_data_direction dir)
214{
215 struct nvme_rdma_qe *ring;
216 int i;
217
218 ring = kcalloc(ib_queue_size, sizeof(struct nvme_rdma_qe), GFP_KERNEL);
219 if (!ring)
220 return NULL;
221
62f99b62
MG
222 /*
223 * Bind the CQEs (post recv buffers) DMA mapping to the RDMA queue
224 * lifetime. It's safe, since any chage in the underlying RDMA device
225 * will issue error recovery and queue re-creation.
226 */
71102307
CH
227 for (i = 0; i < ib_queue_size; i++) {
228 if (nvme_rdma_alloc_qe(ibdev, &ring[i], capsule_size, dir))
229 goto out_free_ring;
230 }
231
232 return ring;
233
234out_free_ring:
235 nvme_rdma_free_ring(ibdev, ring, i, capsule_size, dir);
236 return NULL;
237}
238
239static void nvme_rdma_qp_event(struct ib_event *event, void *context)
240{
27a4beef
MG
241 pr_debug("QP event %s (%d)\n",
242 ib_event_msg(event->event), event->event);
243
71102307
CH
244}
245
246static int nvme_rdma_wait_for_cm(struct nvme_rdma_queue *queue)
247{
35da77d5
BVA
248 int ret;
249
0525af71
IR
250 ret = wait_for_completion_interruptible(&queue->cm_done);
251 if (ret)
35da77d5 252 return ret;
35da77d5 253 WARN_ON_ONCE(queue->cm_error > 0);
71102307
CH
254 return queue->cm_error;
255}
256
257static int nvme_rdma_create_qp(struct nvme_rdma_queue *queue, const int factor)
258{
259 struct nvme_rdma_device *dev = queue->device;
260 struct ib_qp_init_attr init_attr;
261 int ret;
262
263 memset(&init_attr, 0, sizeof(init_attr));
264 init_attr.event_handler = nvme_rdma_qp_event;
265 /* +1 for drain */
266 init_attr.cap.max_send_wr = factor * queue->queue_size + 1;
267 /* +1 for drain */
268 init_attr.cap.max_recv_wr = queue->queue_size + 1;
269 init_attr.cap.max_recv_sge = 1;
64a741c1 270 init_attr.cap.max_send_sge = 1 + dev->num_inline_segments;
71102307
CH
271 init_attr.sq_sig_type = IB_SIGNAL_REQ_WR;
272 init_attr.qp_type = IB_QPT_RC;
273 init_attr.send_cq = queue->ib_cq;
274 init_attr.recv_cq = queue->ib_cq;
5ec5d3bd
MG
275 if (queue->pi_support)
276 init_attr.create_flags |= IB_QP_CREATE_INTEGRITY_EN;
287f329e 277 init_attr.qp_context = queue;
71102307
CH
278
279 ret = rdma_create_qp(queue->cm_id, dev->pd, &init_attr);
280
281 queue->qp = queue->cm_id->qp;
282 return ret;
283}
284
385475ee
CH
285static void nvme_rdma_exit_request(struct blk_mq_tag_set *set,
286 struct request *rq, unsigned int hctx_idx)
71102307
CH
287{
288 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
71102307 289
62f99b62 290 kfree(req->sqe.data);
71102307
CH
291}
292
385475ee
CH
293static int nvme_rdma_init_request(struct blk_mq_tag_set *set,
294 struct request *rq, unsigned int hctx_idx,
295 unsigned int numa_node)
71102307 296{
2d60738c 297 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(set->driver_data);
71102307 298 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
385475ee 299 int queue_idx = (set == &ctrl->tag_set) ? hctx_idx + 1 : 0;
71102307 300 struct nvme_rdma_queue *queue = &ctrl->queues[queue_idx];
71102307 301
59e29ce6 302 nvme_req(rq)->ctrl = &ctrl->ctrl;
62f99b62
MG
303 req->sqe.data = kzalloc(sizeof(struct nvme_command), GFP_KERNEL);
304 if (!req->sqe.data)
305 return -ENOMEM;
71102307 306
5ec5d3bd
MG
307 /* metadata nvme_rdma_sgl struct is located after command's data SGL */
308 if (queue->pi_support)
309 req->metadata_sgl = (void *)nvme_req(rq) +
310 sizeof(struct nvme_rdma_request) +
311 NVME_RDMA_DATA_SGL_SIZE;
312
71102307 313 req->queue = queue;
f4b9e6c9 314 nvme_req(rq)->cmd = req->sqe.data;
71102307
CH
315
316 return 0;
71102307
CH
317}
318
71102307
CH
319static int nvme_rdma_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
320 unsigned int hctx_idx)
321{
2d60738c 322 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(data);
71102307
CH
323 struct nvme_rdma_queue *queue = &ctrl->queues[hctx_idx + 1];
324
d858e5f0 325 BUG_ON(hctx_idx >= ctrl->ctrl.queue_count);
71102307
CH
326
327 hctx->driver_data = queue;
328 return 0;
329}
330
331static int nvme_rdma_init_admin_hctx(struct blk_mq_hw_ctx *hctx, void *data,
332 unsigned int hctx_idx)
333{
2d60738c 334 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(data);
71102307
CH
335 struct nvme_rdma_queue *queue = &ctrl->queues[0];
336
337 BUG_ON(hctx_idx != 0);
338
339 hctx->driver_data = queue;
340 return 0;
341}
342
343static void nvme_rdma_free_dev(struct kref *ref)
344{
345 struct nvme_rdma_device *ndev =
346 container_of(ref, struct nvme_rdma_device, ref);
347
348 mutex_lock(&device_list_mutex);
349 list_del(&ndev->entry);
350 mutex_unlock(&device_list_mutex);
351
71102307 352 ib_dealloc_pd(ndev->pd);
71102307
CH
353 kfree(ndev);
354}
355
356static void nvme_rdma_dev_put(struct nvme_rdma_device *dev)
357{
358 kref_put(&dev->ref, nvme_rdma_free_dev);
359}
360
361static int nvme_rdma_dev_get(struct nvme_rdma_device *dev)
362{
363 return kref_get_unless_zero(&dev->ref);
364}
365
366static struct nvme_rdma_device *
367nvme_rdma_find_get_device(struct rdma_cm_id *cm_id)
368{
369 struct nvme_rdma_device *ndev;
370
371 mutex_lock(&device_list_mutex);
372 list_for_each_entry(ndev, &device_list, entry) {
373 if (ndev->dev->node_guid == cm_id->device->node_guid &&
374 nvme_rdma_dev_get(ndev))
375 goto out_unlock;
376 }
377
378 ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
379 if (!ndev)
380 goto out_err;
381
382 ndev->dev = cm_id->device;
383 kref_init(&ndev->ref);
384
11975e01
CH
385 ndev->pd = ib_alloc_pd(ndev->dev,
386 register_always ? 0 : IB_PD_UNSAFE_GLOBAL_RKEY);
71102307
CH
387 if (IS_ERR(ndev->pd))
388 goto out_free_dev;
389
71102307
CH
390 if (!(ndev->dev->attrs.device_cap_flags &
391 IB_DEVICE_MEM_MGT_EXTENSIONS)) {
392 dev_err(&ndev->dev->dev,
393 "Memory registrations not supported.\n");
11975e01 394 goto out_free_pd;
71102307
CH
395 }
396
64a741c1 397 ndev->num_inline_segments = min(NVME_RDMA_MAX_INLINE_SEGMENTS,
0a3173a5 398 ndev->dev->attrs.max_send_sge - 1);
71102307
CH
399 list_add(&ndev->entry, &device_list);
400out_unlock:
401 mutex_unlock(&device_list_mutex);
402 return ndev;
403
71102307
CH
404out_free_pd:
405 ib_dealloc_pd(ndev->pd);
406out_free_dev:
407 kfree(ndev);
408out_err:
409 mutex_unlock(&device_list_mutex);
410 return NULL;
411}
412
287f329e
YF
413static void nvme_rdma_free_cq(struct nvme_rdma_queue *queue)
414{
415 if (nvme_rdma_poll_queue(queue))
416 ib_free_cq(queue->ib_cq);
417 else
418 ib_cq_pool_put(queue->ib_cq, queue->cq_size);
419}
420
71102307
CH
421static void nvme_rdma_destroy_queue_ib(struct nvme_rdma_queue *queue)
422{
eb1bd249
MG
423 struct nvme_rdma_device *dev;
424 struct ib_device *ibdev;
425
426 if (!test_and_clear_bit(NVME_RDMA_Q_TR_READY, &queue->flags))
427 return;
428
429 dev = queue->device;
430 ibdev = dev->dev;
71102307 431
5ec5d3bd
MG
432 if (queue->pi_support)
433 ib_mr_pool_destroy(queue->qp, &queue->qp->sig_mrs);
f41725bb
IR
434 ib_mr_pool_destroy(queue->qp, &queue->qp->rdma_mrs);
435
eb1bd249
MG
436 /*
437 * The cm_id object might have been destroyed during RDMA connection
438 * establishment error flow to avoid getting other cma events, thus
439 * the destruction of the QP shouldn't use rdma_cm API.
440 */
441 ib_destroy_qp(queue->qp);
287f329e 442 nvme_rdma_free_cq(queue);
71102307
CH
443
444 nvme_rdma_free_ring(ibdev, queue->rsp_ring, queue->queue_size,
445 sizeof(struct nvme_completion), DMA_FROM_DEVICE);
446
447 nvme_rdma_dev_put(dev);
448}
449
5ec5d3bd 450static int nvme_rdma_get_max_fr_pages(struct ib_device *ibdev, bool pi_support)
f41725bb 451{
5ec5d3bd
MG
452 u32 max_page_list_len;
453
454 if (pi_support)
455 max_page_list_len = ibdev->attrs.max_pi_fast_reg_page_list_len;
456 else
457 max_page_list_len = ibdev->attrs.max_fast_reg_page_list_len;
458
459 return min_t(u32, NVME_RDMA_MAX_SEGMENTS, max_page_list_len - 1);
f41725bb
IR
460}
461
287f329e
YF
462static int nvme_rdma_create_cq(struct ib_device *ibdev,
463 struct nvme_rdma_queue *queue)
464{
465 int ret, comp_vector, idx = nvme_rdma_queue_idx(queue);
287f329e
YF
466
467 /*
468 * Spread I/O queues completion vectors according their queue index.
469 * Admin queues can always go on completion vector 0.
470 */
471 comp_vector = (idx == 0 ? idx : idx - 1) % ibdev->num_comp_vectors;
472
473 /* Polling queues need direct cq polling context */
015ad2b1 474 if (nvme_rdma_poll_queue(queue))
287f329e 475 queue->ib_cq = ib_alloc_cq(ibdev, queue, queue->cq_size,
015ad2b1 476 comp_vector, IB_POLL_DIRECT);
477 else
287f329e 478 queue->ib_cq = ib_cq_pool_get(ibdev, queue->cq_size,
015ad2b1 479 comp_vector, IB_POLL_SOFTIRQ);
287f329e
YF
480
481 if (IS_ERR(queue->ib_cq)) {
482 ret = PTR_ERR(queue->ib_cq);
483 return ret;
484 }
485
486 return 0;
487}
488
ca6e95bb 489static int nvme_rdma_create_queue_ib(struct nvme_rdma_queue *queue)
71102307 490{
ca6e95bb 491 struct ib_device *ibdev;
71102307
CH
492 const int send_wr_factor = 3; /* MR, SEND, INV */
493 const int cq_factor = send_wr_factor + 1; /* + RECV */
ff13c1b8 494 int ret, pages_per_mr;
71102307 495
ca6e95bb
SG
496 queue->device = nvme_rdma_find_get_device(queue->cm_id);
497 if (!queue->device) {
498 dev_err(queue->cm_id->device->dev.parent,
499 "no client data found!\n");
500 return -ECONNREFUSED;
501 }
502 ibdev = queue->device->dev;
71102307 503
f3f28373 504 /* +1 for ib_drain_qp */
287f329e
YF
505 queue->cq_size = cq_factor * queue->queue_size + 1;
506
507 ret = nvme_rdma_create_cq(ibdev, queue);
508 if (ret)
ca6e95bb 509 goto out_put_dev;
71102307
CH
510
511 ret = nvme_rdma_create_qp(queue, send_wr_factor);
512 if (ret)
513 goto out_destroy_ib_cq;
514
515 queue->rsp_ring = nvme_rdma_alloc_ring(ibdev, queue->queue_size,
516 sizeof(struct nvme_completion), DMA_FROM_DEVICE);
517 if (!queue->rsp_ring) {
518 ret = -ENOMEM;
519 goto out_destroy_qp;
520 }
521
ff13c1b8
MG
522 /*
523 * Currently we don't use SG_GAPS MR's so if the first entry is
524 * misaligned we'll end up using two entries for a single data page,
525 * so one additional entry is required.
526 */
5ec5d3bd 527 pages_per_mr = nvme_rdma_get_max_fr_pages(ibdev, queue->pi_support) + 1;
f41725bb
IR
528 ret = ib_mr_pool_init(queue->qp, &queue->qp->rdma_mrs,
529 queue->queue_size,
530 IB_MR_TYPE_MEM_REG,
ff13c1b8 531 pages_per_mr, 0);
f41725bb
IR
532 if (ret) {
533 dev_err(queue->ctrl->ctrl.device,
534 "failed to initialize MR pool sized %d for QID %d\n",
287f329e 535 queue->queue_size, nvme_rdma_queue_idx(queue));
f41725bb
IR
536 goto out_destroy_ring;
537 }
538
5ec5d3bd
MG
539 if (queue->pi_support) {
540 ret = ib_mr_pool_init(queue->qp, &queue->qp->sig_mrs,
541 queue->queue_size, IB_MR_TYPE_INTEGRITY,
542 pages_per_mr, pages_per_mr);
543 if (ret) {
544 dev_err(queue->ctrl->ctrl.device,
545 "failed to initialize PI MR pool sized %d for QID %d\n",
287f329e 546 queue->queue_size, nvme_rdma_queue_idx(queue));
5ec5d3bd
MG
547 goto out_destroy_mr_pool;
548 }
549 }
550
eb1bd249
MG
551 set_bit(NVME_RDMA_Q_TR_READY, &queue->flags);
552
71102307
CH
553 return 0;
554
5ec5d3bd
MG
555out_destroy_mr_pool:
556 ib_mr_pool_destroy(queue->qp, &queue->qp->rdma_mrs);
f41725bb
IR
557out_destroy_ring:
558 nvme_rdma_free_ring(ibdev, queue->rsp_ring, queue->queue_size,
559 sizeof(struct nvme_completion), DMA_FROM_DEVICE);
71102307 560out_destroy_qp:
1f61def9 561 rdma_destroy_qp(queue->cm_id);
71102307 562out_destroy_ib_cq:
287f329e 563 nvme_rdma_free_cq(queue);
ca6e95bb
SG
564out_put_dev:
565 nvme_rdma_dev_put(queue->device);
71102307
CH
566 return ret;
567}
568
41e8cfa1 569static int nvme_rdma_alloc_queue(struct nvme_rdma_ctrl *ctrl,
71102307
CH
570 int idx, size_t queue_size)
571{
572 struct nvme_rdma_queue *queue;
8f4e8dac 573 struct sockaddr *src_addr = NULL;
71102307
CH
574 int ret;
575
576 queue = &ctrl->queues[idx];
7674073b 577 mutex_init(&queue->queue_lock);
71102307 578 queue->ctrl = ctrl;
5ec5d3bd
MG
579 if (idx && ctrl->ctrl.max_integrity_segments)
580 queue->pi_support = true;
581 else
582 queue->pi_support = false;
71102307
CH
583 init_completion(&queue->cm_done);
584
585 if (idx > 0)
586 queue->cmnd_capsule_len = ctrl->ctrl.ioccsz * 16;
587 else
588 queue->cmnd_capsule_len = sizeof(struct nvme_command);
589
590 queue->queue_size = queue_size;
591
592 queue->cm_id = rdma_create_id(&init_net, nvme_rdma_cm_handler, queue,
593 RDMA_PS_TCP, IB_QPT_RC);
594 if (IS_ERR(queue->cm_id)) {
595 dev_info(ctrl->ctrl.device,
596 "failed to create CM ID: %ld\n", PTR_ERR(queue->cm_id));
7674073b
CL
597 ret = PTR_ERR(queue->cm_id);
598 goto out_destroy_mutex;
71102307
CH
599 }
600
8f4e8dac 601 if (ctrl->ctrl.opts->mask & NVMF_OPT_HOST_TRADDR)
0928f9b4 602 src_addr = (struct sockaddr *)&ctrl->src_addr;
8f4e8dac 603
0928f9b4
SG
604 queue->cm_error = -ETIMEDOUT;
605 ret = rdma_resolve_addr(queue->cm_id, src_addr,
606 (struct sockaddr *)&ctrl->addr,
0525af71 607 NVME_RDMA_CM_TIMEOUT_MS);
71102307
CH
608 if (ret) {
609 dev_info(ctrl->ctrl.device,
610 "rdma_resolve_addr failed (%d).\n", ret);
611 goto out_destroy_cm_id;
612 }
613
614 ret = nvme_rdma_wait_for_cm(queue);
615 if (ret) {
616 dev_info(ctrl->ctrl.device,
d8bfceeb 617 "rdma connection establishment failed (%d)\n", ret);
71102307
CH
618 goto out_destroy_cm_id;
619 }
620
5013e98b 621 set_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags);
71102307
CH
622
623 return 0;
624
625out_destroy_cm_id:
626 rdma_destroy_id(queue->cm_id);
eb1bd249 627 nvme_rdma_destroy_queue_ib(queue);
7674073b
CL
628out_destroy_mutex:
629 mutex_destroy(&queue->queue_lock);
71102307
CH
630 return ret;
631}
632
d94211b8
SG
633static void __nvme_rdma_stop_queue(struct nvme_rdma_queue *queue)
634{
635 rdma_disconnect(queue->cm_id);
636 ib_drain_qp(queue->qp);
637}
638
71102307
CH
639static void nvme_rdma_stop_queue(struct nvme_rdma_queue *queue)
640{
3820c4fd
ML
641 if (!test_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
642 return;
643
7674073b
CL
644 mutex_lock(&queue->queue_lock);
645 if (test_and_clear_bit(NVME_RDMA_Q_LIVE, &queue->flags))
646 __nvme_rdma_stop_queue(queue);
647 mutex_unlock(&queue->queue_lock);
71102307
CH
648}
649
650static void nvme_rdma_free_queue(struct nvme_rdma_queue *queue)
651{
5013e98b 652 if (!test_and_clear_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
a57bd541
SG
653 return;
654
71102307 655 rdma_destroy_id(queue->cm_id);
9817d763 656 nvme_rdma_destroy_queue_ib(queue);
7674073b 657 mutex_destroy(&queue->queue_lock);
71102307
CH
658}
659
a57bd541 660static void nvme_rdma_free_io_queues(struct nvme_rdma_ctrl *ctrl)
71102307 661{
a57bd541
SG
662 int i;
663
664 for (i = 1; i < ctrl->ctrl.queue_count; i++)
665 nvme_rdma_free_queue(&ctrl->queues[i]);
71102307
CH
666}
667
a57bd541 668static void nvme_rdma_stop_io_queues(struct nvme_rdma_ctrl *ctrl)
71102307
CH
669{
670 int i;
671
d858e5f0 672 for (i = 1; i < ctrl->ctrl.queue_count; i++)
a57bd541 673 nvme_rdma_stop_queue(&ctrl->queues[i]);
71102307
CH
674}
675
68e16fcf
SG
676static int nvme_rdma_start_queue(struct nvme_rdma_ctrl *ctrl, int idx)
677{
ff8519f9 678 struct nvme_rdma_queue *queue = &ctrl->queues[idx];
68e16fcf
SG
679 int ret;
680
681 if (idx)
be42a33b 682 ret = nvmf_connect_io_queue(&ctrl->ctrl, idx);
68e16fcf
SG
683 else
684 ret = nvmf_connect_admin_queue(&ctrl->ctrl);
685
d94211b8 686 if (!ret) {
ff8519f9 687 set_bit(NVME_RDMA_Q_LIVE, &queue->flags);
d94211b8 688 } else {
67b483dd
SG
689 if (test_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
690 __nvme_rdma_stop_queue(queue);
68e16fcf
SG
691 dev_info(ctrl->ctrl.device,
692 "failed to connect queue: %d ret=%d\n", idx, ret);
d94211b8 693 }
68e16fcf
SG
694 return ret;
695}
696
1c467e25
DW
697static int nvme_rdma_start_io_queues(struct nvme_rdma_ctrl *ctrl,
698 int first, int last)
71102307
CH
699{
700 int i, ret = 0;
701
1c467e25 702 for (i = first; i < last; i++) {
68e16fcf
SG
703 ret = nvme_rdma_start_queue(ctrl, i);
704 if (ret)
a57bd541 705 goto out_stop_queues;
71102307
CH
706 }
707
c8dbc37c
SW
708 return 0;
709
a57bd541 710out_stop_queues:
1c467e25 711 for (i--; i >= first; i--)
68e16fcf 712 nvme_rdma_stop_queue(&ctrl->queues[i]);
71102307
CH
713 return ret;
714}
715
41e8cfa1 716static int nvme_rdma_alloc_io_queues(struct nvme_rdma_ctrl *ctrl)
71102307 717{
c248c643 718 struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
a249d306 719 unsigned int nr_io_queues;
71102307
CH
720 int i, ret;
721
a249d306 722 nr_io_queues = nvmf_nr_io_queues(opts);
c248c643
SG
723 ret = nvme_set_queue_count(&ctrl->ctrl, &nr_io_queues);
724 if (ret)
725 return ret;
726
85032874 727 if (nr_io_queues == 0) {
c4c6df5f
SG
728 dev_err(ctrl->ctrl.device,
729 "unable to set any I/O queues\n");
730 return -ENOMEM;
731 }
c248c643 732
85032874 733 ctrl->ctrl.queue_count = nr_io_queues + 1;
c248c643
SG
734 dev_info(ctrl->ctrl.device,
735 "creating %d I/O queues.\n", nr_io_queues);
736
a249d306 737 nvmf_set_io_queues(opts, nr_io_queues, ctrl->io_queues);
d858e5f0 738 for (i = 1; i < ctrl->ctrl.queue_count; i++) {
41e8cfa1
SG
739 ret = nvme_rdma_alloc_queue(ctrl, i,
740 ctrl->ctrl.sqsize + 1);
741 if (ret)
71102307 742 goto out_free_queues;
71102307
CH
743 }
744
745 return 0;
746
747out_free_queues:
f361e5a0 748 for (i--; i >= 1; i--)
a57bd541 749 nvme_rdma_free_queue(&ctrl->queues[i]);
71102307
CH
750
751 return ret;
752}
753
cefa1032 754static int nvme_rdma_alloc_tag_set(struct nvme_ctrl *ctrl)
b28a308e 755{
cefa1032
CH
756 unsigned int cmd_size = sizeof(struct nvme_rdma_request) +
757 NVME_RDMA_DATA_SGL_SIZE;
b28a308e 758
cefa1032
CH
759 if (ctrl->max_integrity_segments)
760 cmd_size += sizeof(struct nvme_rdma_sgl) +
761 NVME_RDMA_METADATA_SGL_SIZE;
a7f7b711 762
cefa1032 763 return nvme_alloc_io_tag_set(ctrl, &to_rdma_ctrl(ctrl)->tag_set,
db45e1a5 764 &nvme_rdma_mq_ops,
dcef7727
CH
765 ctrl->opts->nr_poll_queues ? HCTX_MAX_TYPES : 2,
766 cmd_size);
b28a308e
SG
767}
768
cefa1032 769static void nvme_rdma_destroy_admin_queue(struct nvme_rdma_ctrl *ctrl)
71102307 770{
682630f0 771 if (ctrl->async_event_sqe.data) {
925dd04c 772 cancel_work_sync(&ctrl->ctrl.async_event_work);
682630f0
SG
773 nvme_rdma_free_qe(ctrl->device->dev, &ctrl->async_event_sqe,
774 sizeof(struct nvme_command), DMA_TO_DEVICE);
775 ctrl->async_event_sqe.data = NULL;
776 }
a57bd541 777 nvme_rdma_free_queue(&ctrl->queues[0]);
71102307
CH
778}
779
3f02fffb
SG
780static int nvme_rdma_configure_admin_queue(struct nvme_rdma_ctrl *ctrl,
781 bool new)
90af3512 782{
5ec5d3bd 783 bool pi_capable = false;
90af3512
SG
784 int error;
785
41e8cfa1 786 error = nvme_rdma_alloc_queue(ctrl, 0, NVME_AQ_DEPTH);
90af3512
SG
787 if (error)
788 return error;
789
790 ctrl->device = ctrl->queues[0].device;
22dd4c70 791 ctrl->ctrl.numa_node = ibdev_to_node(ctrl->device->dev);
90af3512 792
5ec5d3bd 793 /* T10-PI support */
e945c653
JG
794 if (ctrl->device->dev->attrs.kernel_cap_flags &
795 IBK_INTEGRITY_HANDOVER)
5ec5d3bd
MG
796 pi_capable = true;
797
798 ctrl->max_fr_pages = nvme_rdma_get_max_fr_pages(ctrl->device->dev,
799 pi_capable);
90af3512 800
62f99b62
MG
801 /*
802 * Bind the async event SQE DMA mapping to the admin queue lifetime.
803 * It's safe, since any chage in the underlying RDMA device will issue
804 * error recovery and queue re-creation.
805 */
94e42213
SG
806 error = nvme_rdma_alloc_qe(ctrl->device->dev, &ctrl->async_event_sqe,
807 sizeof(struct nvme_command), DMA_TO_DEVICE);
808 if (error)
809 goto out_free_queue;
810
3f02fffb 811 if (new) {
cefa1032
CH
812 error = nvme_alloc_admin_tag_set(&ctrl->ctrl,
813 &ctrl->admin_tag_set, &nvme_rdma_admin_mq_ops,
cefa1032
CH
814 sizeof(struct nvme_rdma_request) +
815 NVME_RDMA_DATA_SGL_SIZE);
a7f7b711 816 if (error)
94e42213 817 goto out_free_async_qe;
90af3512 818
90af3512
SG
819 }
820
68e16fcf 821 error = nvme_rdma_start_queue(ctrl, 0);
90af3512 822 if (error)
cefa1032 823 goto out_remove_admin_tag_set;
90af3512 824
c0f2f45b 825 error = nvme_enable_ctrl(&ctrl->ctrl);
90af3512 826 if (error)
2e050f00 827 goto out_stop_queue;
90af3512 828
ff13c1b8
MG
829 ctrl->ctrl.max_segments = ctrl->max_fr_pages;
830 ctrl->ctrl.max_hw_sectors = ctrl->max_fr_pages << (ilog2(SZ_4K) - 9);
5ec5d3bd
MG
831 if (pi_capable)
832 ctrl->ctrl.max_integrity_segments = ctrl->max_fr_pages;
833 else
834 ctrl->ctrl.max_integrity_segments = 0;
90af3512 835
9f27bd70 836 nvme_unquiesce_admin_queue(&ctrl->ctrl);
e7832cb4 837
94cc781f 838 error = nvme_init_ctrl_finish(&ctrl->ctrl, false);
90af3512 839 if (error)
958dc1d3 840 goto out_quiesce_queue;
90af3512 841
90af3512
SG
842 return 0;
843
958dc1d3 844out_quiesce_queue:
9f27bd70 845 nvme_quiesce_admin_queue(&ctrl->ctrl);
958dc1d3 846 blk_sync_queue(ctrl->ctrl.admin_q);
2e050f00
JW
847out_stop_queue:
848 nvme_rdma_stop_queue(&ctrl->queues[0]);
958dc1d3 849 nvme_cancel_admin_tagset(&ctrl->ctrl);
cefa1032 850out_remove_admin_tag_set:
3f02fffb 851 if (new)
cefa1032 852 nvme_remove_admin_tag_set(&ctrl->ctrl);
94e42213 853out_free_async_qe:
9134ae2a
PS
854 if (ctrl->async_event_sqe.data) {
855 nvme_rdma_free_qe(ctrl->device->dev, &ctrl->async_event_sqe,
856 sizeof(struct nvme_command), DMA_TO_DEVICE);
857 ctrl->async_event_sqe.data = NULL;
858 }
90af3512
SG
859out_free_queue:
860 nvme_rdma_free_queue(&ctrl->queues[0]);
861 return error;
862}
863
a57bd541
SG
864static int nvme_rdma_configure_io_queues(struct nvme_rdma_ctrl *ctrl, bool new)
865{
1c467e25 866 int ret, nr_queues;
a57bd541 867
41e8cfa1 868 ret = nvme_rdma_alloc_io_queues(ctrl);
a57bd541
SG
869 if (ret)
870 return ret;
871
872 if (new) {
a7f7b711
CH
873 ret = nvme_rdma_alloc_tag_set(&ctrl->ctrl);
874 if (ret)
a57bd541 875 goto out_free_io_queues;
a57bd541
SG
876 }
877
1c467e25
DW
878 /*
879 * Only start IO queues for which we have allocated the tagset
880 * and limitted it to the available queues. On reconnects, the
881 * queue number might have changed.
882 */
883 nr_queues = min(ctrl->tag_set.nr_hw_queues + 1, ctrl->ctrl.queue_count);
884 ret = nvme_rdma_start_io_queues(ctrl, 1, nr_queues);
a57bd541 885 if (ret)
cefa1032 886 goto out_cleanup_tagset;
a57bd541 887
9f98772b 888 if (!new) {
29b434d1 889 nvme_start_freeze(&ctrl->ctrl);
9f27bd70 890 nvme_unquiesce_io_queues(&ctrl->ctrl);
2362acb6
SG
891 if (!nvme_wait_freeze_timeout(&ctrl->ctrl, NVME_IO_TIMEOUT)) {
892 /*
893 * If we timed out waiting for freeze we are likely to
894 * be stuck. Fail the controller initialization just
895 * to be safe.
896 */
897 ret = -ENODEV;
29b434d1 898 nvme_unfreeze(&ctrl->ctrl);
2362acb6
SG
899 goto out_wait_freeze_timed_out;
900 }
9f98772b
SG
901 blk_mq_update_nr_hw_queues(ctrl->ctrl.tagset,
902 ctrl->ctrl.queue_count - 1);
903 nvme_unfreeze(&ctrl->ctrl);
904 }
905
1c467e25
DW
906 /*
907 * If the number of queues has increased (reconnect case)
908 * start all new queues now.
909 */
910 ret = nvme_rdma_start_io_queues(ctrl, nr_queues,
911 ctrl->tag_set.nr_hw_queues + 1);
912 if (ret)
913 goto out_wait_freeze_timed_out;
914
a57bd541
SG
915 return 0;
916
2362acb6 917out_wait_freeze_timed_out:
9f27bd70 918 nvme_quiesce_io_queues(&ctrl->ctrl);
958dc1d3 919 nvme_sync_io_queues(&ctrl->ctrl);
2362acb6 920 nvme_rdma_stop_io_queues(ctrl);
cefa1032 921out_cleanup_tagset:
958dc1d3 922 nvme_cancel_tagset(&ctrl->ctrl);
a57bd541 923 if (new)
cefa1032 924 nvme_remove_io_tag_set(&ctrl->ctrl);
a57bd541
SG
925out_free_io_queues:
926 nvme_rdma_free_io_queues(ctrl);
927 return ret;
71102307
CH
928}
929
75862c72
SG
930static void nvme_rdma_teardown_admin_queue(struct nvme_rdma_ctrl *ctrl,
931 bool remove)
932{
9f27bd70 933 nvme_quiesce_admin_queue(&ctrl->ctrl);
3017013d 934 blk_sync_queue(ctrl->ctrl.admin_q);
75862c72 935 nvme_rdma_stop_queue(&ctrl->queues[0]);
c4189d68 936 nvme_cancel_admin_tagset(&ctrl->ctrl);
cefa1032 937 if (remove) {
9f27bd70 938 nvme_unquiesce_admin_queue(&ctrl->ctrl);
cefa1032
CH
939 nvme_remove_admin_tag_set(&ctrl->ctrl);
940 }
941 nvme_rdma_destroy_admin_queue(ctrl);
75862c72
SG
942}
943
944static void nvme_rdma_teardown_io_queues(struct nvme_rdma_ctrl *ctrl,
945 bool remove)
946{
947 if (ctrl->ctrl.queue_count > 1) {
9f27bd70 948 nvme_quiesce_io_queues(&ctrl->ctrl);
3017013d 949 nvme_sync_io_queues(&ctrl->ctrl);
75862c72 950 nvme_rdma_stop_io_queues(ctrl);
c4189d68 951 nvme_cancel_tagset(&ctrl->ctrl);
cefa1032 952 if (remove) {
9f27bd70 953 nvme_unquiesce_io_queues(&ctrl->ctrl);
cefa1032
CH
954 nvme_remove_io_tag_set(&ctrl->ctrl);
955 }
956 nvme_rdma_free_io_queues(ctrl);
75862c72
SG
957 }
958}
959
f7f70f4a
RL
960static void nvme_rdma_stop_ctrl(struct nvme_ctrl *nctrl)
961{
962 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
963
a1ae8d4d 964 flush_work(&ctrl->err_work);
f7f70f4a
RL
965 cancel_delayed_work_sync(&ctrl->reconnect_work);
966}
967
71102307
CH
968static void nvme_rdma_free_ctrl(struct nvme_ctrl *nctrl)
969{
970 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
971
972 if (list_empty(&ctrl->list))
973 goto free_ctrl;
974
975 mutex_lock(&nvme_rdma_ctrl_mutex);
976 list_del(&ctrl->list);
977 mutex_unlock(&nvme_rdma_ctrl_mutex);
978
71102307
CH
979 nvmf_free_options(nctrl->opts);
980free_ctrl:
3d064101 981 kfree(ctrl->queues);
71102307
CH
982 kfree(ctrl);
983}
984
fd8563ce
SG
985static void nvme_rdma_reconnect_or_remove(struct nvme_rdma_ctrl *ctrl)
986{
e6e7f7ac
KB
987 enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
988
fd8563ce 989 /* If we are resetting/deleting then do nothing */
e6e7f7ac
KB
990 if (state != NVME_CTRL_CONNECTING) {
991 WARN_ON_ONCE(state == NVME_CTRL_NEW || state == NVME_CTRL_LIVE);
fd8563ce
SG
992 return;
993 }
994
995 if (nvmf_should_reconnect(&ctrl->ctrl)) {
996 dev_info(ctrl->ctrl.device, "Reconnecting in %d seconds...\n",
997 ctrl->ctrl.opts->reconnect_delay);
9a6327d2 998 queue_delayed_work(nvme_wq, &ctrl->reconnect_work,
fd8563ce
SG
999 ctrl->ctrl.opts->reconnect_delay * HZ);
1000 } else {
12fa1304 1001 nvme_delete_ctrl(&ctrl->ctrl);
fd8563ce
SG
1002 }
1003}
1004
c66e2998 1005static int nvme_rdma_setup_ctrl(struct nvme_rdma_ctrl *ctrl, bool new)
71102307 1006{
13ce7e62 1007 int ret;
71102307 1008 bool changed;
71102307 1009
c66e2998 1010 ret = nvme_rdma_configure_admin_queue(ctrl, new);
71102307 1011 if (ret)
c66e2998
SG
1012 return ret;
1013
1014 if (ctrl->ctrl.icdoff) {
09748122 1015 ret = -EOPNOTSUPP;
c66e2998
SG
1016 dev_err(ctrl->ctrl.device, "icdoff is not supported!\n");
1017 goto destroy_admin;
1018 }
1019
1020 if (!(ctrl->ctrl.sgls & (1 << 2))) {
09748122 1021 ret = -EOPNOTSUPP;
c66e2998
SG
1022 dev_err(ctrl->ctrl.device,
1023 "Mandatory keyed sgls are not supported!\n");
1024 goto destroy_admin;
1025 }
1026
1027 if (ctrl->ctrl.opts->queue_size > ctrl->ctrl.sqsize + 1) {
1028 dev_warn(ctrl->ctrl.device,
1029 "queue_size %zu > ctrl sqsize %u, clamping down\n",
1030 ctrl->ctrl.opts->queue_size, ctrl->ctrl.sqsize + 1);
1031 }
1032
44c3c625
MG
1033 if (ctrl->ctrl.sqsize + 1 > NVME_RDMA_MAX_QUEUE_SIZE) {
1034 dev_warn(ctrl->ctrl.device,
1035 "ctrl sqsize %u > max queue size %u, clamping down\n",
1036 ctrl->ctrl.sqsize + 1, NVME_RDMA_MAX_QUEUE_SIZE);
1037 ctrl->ctrl.sqsize = NVME_RDMA_MAX_QUEUE_SIZE - 1;
1038 }
1039
c66e2998
SG
1040 if (ctrl->ctrl.sqsize + 1 > ctrl->ctrl.maxcmd) {
1041 dev_warn(ctrl->ctrl.device,
1042 "sqsize %u > ctrl maxcmd %u, clamping down\n",
1043 ctrl->ctrl.sqsize + 1, ctrl->ctrl.maxcmd);
1044 ctrl->ctrl.sqsize = ctrl->ctrl.maxcmd - 1;
1045 }
71102307 1046
64a741c1
SW
1047 if (ctrl->ctrl.sgls & (1 << 20))
1048 ctrl->use_inline_data = true;
71102307 1049
d858e5f0 1050 if (ctrl->ctrl.queue_count > 1) {
c66e2998 1051 ret = nvme_rdma_configure_io_queues(ctrl, new);
71102307 1052 if (ret)
5e1fe61d 1053 goto destroy_admin;
71102307
CH
1054 }
1055
1056 changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);
0a960afd 1057 if (!changed) {
96135862 1058 /*
ecca390e 1059 * state change failure is ok if we started ctrl delete,
96135862
IR
1060 * unless we're during creation of a new controller to
1061 * avoid races with teardown flow.
1062 */
e6e7f7ac
KB
1063 enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
1064
1065 WARN_ON_ONCE(state != NVME_CTRL_DELETING &&
1066 state != NVME_CTRL_DELETING_NOIO);
96135862 1067 WARN_ON_ONCE(new);
c66e2998
SG
1068 ret = -EINVAL;
1069 goto destroy_io;
0a960afd
SG
1070 }
1071
d09f2b45 1072 nvme_start_ctrl(&ctrl->ctrl);
c66e2998
SG
1073 return 0;
1074
1075destroy_io:
958dc1d3 1076 if (ctrl->ctrl.queue_count > 1) {
9f27bd70 1077 nvme_quiesce_io_queues(&ctrl->ctrl);
958dc1d3
CL
1078 nvme_sync_io_queues(&ctrl->ctrl);
1079 nvme_rdma_stop_io_queues(ctrl);
1080 nvme_cancel_tagset(&ctrl->ctrl);
cefa1032
CH
1081 if (new)
1082 nvme_remove_io_tag_set(&ctrl->ctrl);
1083 nvme_rdma_free_io_queues(ctrl);
958dc1d3 1084 }
c66e2998 1085destroy_admin:
3af755a4 1086 nvme_stop_keep_alive(&ctrl->ctrl);
9f27bd70 1087 nvme_quiesce_admin_queue(&ctrl->ctrl);
958dc1d3 1088 blk_sync_queue(ctrl->ctrl.admin_q);
c66e2998 1089 nvme_rdma_stop_queue(&ctrl->queues[0]);
958dc1d3 1090 nvme_cancel_admin_tagset(&ctrl->ctrl);
cefa1032
CH
1091 if (new)
1092 nvme_remove_admin_tag_set(&ctrl->ctrl);
1093 nvme_rdma_destroy_admin_queue(ctrl);
c66e2998
SG
1094 return ret;
1095}
1096
1097static void nvme_rdma_reconnect_ctrl_work(struct work_struct *work)
1098{
1099 struct nvme_rdma_ctrl *ctrl = container_of(to_delayed_work(work),
1100 struct nvme_rdma_ctrl, reconnect_work);
1101
1102 ++ctrl->ctrl.nr_reconnects;
1103
1104 if (nvme_rdma_setup_ctrl(ctrl, false))
1105 goto requeue;
71102307 1106
5e1fe61d
SG
1107 dev_info(ctrl->ctrl.device, "Successfully reconnected (%d attempts)\n",
1108 ctrl->ctrl.nr_reconnects);
1109
1110 ctrl->ctrl.nr_reconnects = 0;
71102307
CH
1111
1112 return;
1113
71102307 1114requeue:
fd8563ce 1115 dev_info(ctrl->ctrl.device, "Failed reconnect attempt %d\n",
fdf9dfa8 1116 ctrl->ctrl.nr_reconnects);
fd8563ce 1117 nvme_rdma_reconnect_or_remove(ctrl);
71102307
CH
1118}
1119
1120static void nvme_rdma_error_recovery_work(struct work_struct *work)
1121{
1122 struct nvme_rdma_ctrl *ctrl = container_of(work,
1123 struct nvme_rdma_ctrl, err_work);
1124
e4d753d7 1125 nvme_stop_keep_alive(&ctrl->ctrl);
b6bb1722 1126 flush_work(&ctrl->ctrl.async_event_work);
75862c72 1127 nvme_rdma_teardown_io_queues(ctrl, false);
9f27bd70 1128 nvme_unquiesce_io_queues(&ctrl->ctrl);
75862c72 1129 nvme_rdma_teardown_admin_queue(ctrl, false);
9f27bd70 1130 nvme_unquiesce_admin_queue(&ctrl->ctrl);
91c11d5f 1131 nvme_auth_stop(&ctrl->ctrl);
e818a5b4 1132
ad6a0a52 1133 if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
ecca390e 1134 /* state change failure is ok if we started ctrl delete */
e6e7f7ac
KB
1135 enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
1136
1137 WARN_ON_ONCE(state != NVME_CTRL_DELETING &&
1138 state != NVME_CTRL_DELETING_NOIO);
d5bf4b7f
SG
1139 return;
1140 }
1141
fd8563ce 1142 nvme_rdma_reconnect_or_remove(ctrl);
71102307
CH
1143}
1144
1145static void nvme_rdma_error_recovery(struct nvme_rdma_ctrl *ctrl)
1146{
d5bf4b7f 1147 if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_RESETTING))
71102307
CH
1148 return;
1149
0475a8dc 1150 dev_warn(ctrl->ctrl.device, "starting error recovery\n");
97b2512a 1151 queue_work(nvme_reset_wq, &ctrl->err_work);
71102307
CH
1152}
1153
8446546c
CH
1154static void nvme_rdma_end_request(struct nvme_rdma_request *req)
1155{
1156 struct request *rq = blk_mq_rq_from_pdu(req);
1157
1158 if (!refcount_dec_and_test(&req->ref))
1159 return;
2eb81a33 1160 if (!nvme_try_complete_req(rq, req->status, req->result))
ff029451 1161 nvme_rdma_complete_rq(rq);
8446546c
CH
1162}
1163
71102307
CH
1164static void nvme_rdma_wr_error(struct ib_cq *cq, struct ib_wc *wc,
1165 const char *op)
1166{
287f329e 1167 struct nvme_rdma_queue *queue = wc->qp->qp_context;
71102307
CH
1168 struct nvme_rdma_ctrl *ctrl = queue->ctrl;
1169
e6e7f7ac 1170 if (nvme_ctrl_state(&ctrl->ctrl) == NVME_CTRL_LIVE)
71102307
CH
1171 dev_info(ctrl->ctrl.device,
1172 "%s for CQE 0x%p failed with status %s (%d)\n",
1173 op, wc->wr_cqe,
1174 ib_wc_status_msg(wc->status), wc->status);
1175 nvme_rdma_error_recovery(ctrl);
1176}
1177
1178static void nvme_rdma_memreg_done(struct ib_cq *cq, struct ib_wc *wc)
1179{
1180 if (unlikely(wc->status != IB_WC_SUCCESS))
1181 nvme_rdma_wr_error(cq, wc, "MEMREG");
1182}
1183
1184static void nvme_rdma_inv_rkey_done(struct ib_cq *cq, struct ib_wc *wc)
1185{
2f122e4f
SG
1186 struct nvme_rdma_request *req =
1187 container_of(wc->wr_cqe, struct nvme_rdma_request, reg_cqe);
2f122e4f 1188
8446546c 1189 if (unlikely(wc->status != IB_WC_SUCCESS))
71102307 1190 nvme_rdma_wr_error(cq, wc, "LOCAL_INV");
8446546c
CH
1191 else
1192 nvme_rdma_end_request(req);
71102307
CH
1193}
1194
1195static int nvme_rdma_inv_rkey(struct nvme_rdma_queue *queue,
1196 struct nvme_rdma_request *req)
1197{
71102307
CH
1198 struct ib_send_wr wr = {
1199 .opcode = IB_WR_LOCAL_INV,
1200 .next = NULL,
1201 .num_sge = 0,
2f122e4f 1202 .send_flags = IB_SEND_SIGNALED,
71102307
CH
1203 .ex.invalidate_rkey = req->mr->rkey,
1204 };
1205
1206 req->reg_cqe.done = nvme_rdma_inv_rkey_done;
1207 wr.wr_cqe = &req->reg_cqe;
1208
45e3cc1a 1209 return ib_post_send(queue->qp, &wr, NULL);
71102307
CH
1210}
1211
4686af88
MG
1212static void nvme_rdma_dma_unmap_req(struct ib_device *ibdev, struct request *rq)
1213{
1214 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
1215
1216 if (blk_integrity_rq(rq)) {
1217 ib_dma_unmap_sg(ibdev, req->metadata_sgl->sg_table.sgl,
1218 req->metadata_sgl->nents, rq_dma_dir(rq));
1219 sg_free_table_chained(&req->metadata_sgl->sg_table,
1220 NVME_INLINE_METADATA_SG_CNT);
1221 }
1222
1223 ib_dma_unmap_sg(ibdev, req->data_sgl.sg_table.sgl, req->data_sgl.nents,
1224 rq_dma_dir(rq));
1225 sg_free_table_chained(&req->data_sgl.sg_table, NVME_INLINE_SG_CNT);
1226}
1227
71102307
CH
1228static void nvme_rdma_unmap_data(struct nvme_rdma_queue *queue,
1229 struct request *rq)
1230{
1231 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
71102307
CH
1232 struct nvme_rdma_device *dev = queue->device;
1233 struct ib_device *ibdev = dev->dev;
5ec5d3bd 1234 struct list_head *pool = &queue->qp->rdma_mrs;
71102307 1235
34e08191 1236 if (!blk_rq_nr_phys_segments(rq))
71102307
CH
1237 return;
1238
5ec5d3bd
MG
1239 if (req->use_sig_mr)
1240 pool = &queue->qp->sig_mrs;
1241
f41725bb 1242 if (req->mr) {
5ec5d3bd 1243 ib_mr_pool_put(queue->qp, pool, req->mr);
f41725bb
IR
1244 req->mr = NULL;
1245 }
1246
4686af88 1247 nvme_rdma_dma_unmap_req(ibdev, rq);
71102307
CH
1248}
1249
1250static int nvme_rdma_set_sg_null(struct nvme_command *c)
1251{
1252 struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
1253
1254 sg->addr = 0;
1255 put_unaligned_le24(0, sg->length);
1256 put_unaligned_le32(0, sg->key);
1257 sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
1258 return 0;
1259}
1260
1261static int nvme_rdma_map_sg_inline(struct nvme_rdma_queue *queue,
64a741c1
SW
1262 struct nvme_rdma_request *req, struct nvme_command *c,
1263 int count)
71102307
CH
1264{
1265 struct nvme_sgl_desc *sg = &c->common.dptr.sgl;
64a741c1 1266 struct ib_sge *sge = &req->sge[1];
12b2aaad 1267 struct scatterlist *sgl;
64a741c1
SW
1268 u32 len = 0;
1269 int i;
71102307 1270
12b2aaad 1271 for_each_sg(req->data_sgl.sg_table.sgl, sgl, count, i) {
64a741c1
SW
1272 sge->addr = sg_dma_address(sgl);
1273 sge->length = sg_dma_len(sgl);
1274 sge->lkey = queue->device->pd->local_dma_lkey;
1275 len += sge->length;
12b2aaad 1276 sge++;
64a741c1 1277 }
71102307
CH
1278
1279 sg->addr = cpu_to_le64(queue->ctrl->ctrl.icdoff);
64a741c1 1280 sg->length = cpu_to_le32(len);
71102307
CH
1281 sg->type = (NVME_SGL_FMT_DATA_DESC << 4) | NVME_SGL_FMT_OFFSET;
1282
64a741c1 1283 req->num_sge += count;
71102307
CH
1284 return 0;
1285}
1286
1287static int nvme_rdma_map_sg_single(struct nvme_rdma_queue *queue,
1288 struct nvme_rdma_request *req, struct nvme_command *c)
1289{
1290 struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
1291
324d9e78
IR
1292 sg->addr = cpu_to_le64(sg_dma_address(req->data_sgl.sg_table.sgl));
1293 put_unaligned_le24(sg_dma_len(req->data_sgl.sg_table.sgl), sg->length);
11975e01 1294 put_unaligned_le32(queue->device->pd->unsafe_global_rkey, sg->key);
71102307
CH
1295 sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
1296 return 0;
1297}
1298
1299static int nvme_rdma_map_sg_fr(struct nvme_rdma_queue *queue,
1300 struct nvme_rdma_request *req, struct nvme_command *c,
1301 int count)
1302{
1303 struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
1304 int nr;
1305
f41725bb
IR
1306 req->mr = ib_mr_pool_get(queue->qp, &queue->qp->rdma_mrs);
1307 if (WARN_ON_ONCE(!req->mr))
1308 return -EAGAIN;
1309
b925a2dc
MG
1310 /*
1311 * Align the MR to a 4K page size to match the ctrl page size and
1312 * the block virtual boundary.
1313 */
324d9e78
IR
1314 nr = ib_map_mr_sg(req->mr, req->data_sgl.sg_table.sgl, count, NULL,
1315 SZ_4K);
a7b7c7a1 1316 if (unlikely(nr < count)) {
f41725bb
IR
1317 ib_mr_pool_put(queue->qp, &queue->qp->rdma_mrs, req->mr);
1318 req->mr = NULL;
71102307
CH
1319 if (nr < 0)
1320 return nr;
1321 return -EINVAL;
1322 }
1323
1324 ib_update_fast_reg_key(req->mr, ib_inc_rkey(req->mr->rkey));
1325
1326 req->reg_cqe.done = nvme_rdma_memreg_done;
1327 memset(&req->reg_wr, 0, sizeof(req->reg_wr));
1328 req->reg_wr.wr.opcode = IB_WR_REG_MR;
1329 req->reg_wr.wr.wr_cqe = &req->reg_cqe;
1330 req->reg_wr.wr.num_sge = 0;
1331 req->reg_wr.mr = req->mr;
1332 req->reg_wr.key = req->mr->rkey;
1333 req->reg_wr.access = IB_ACCESS_LOCAL_WRITE |
1334 IB_ACCESS_REMOTE_READ |
1335 IB_ACCESS_REMOTE_WRITE;
1336
71102307
CH
1337 sg->addr = cpu_to_le64(req->mr->iova);
1338 put_unaligned_le24(req->mr->length, sg->length);
1339 put_unaligned_le32(req->mr->rkey, sg->key);
1340 sg->type = (NVME_KEY_SGL_FMT_DATA_DESC << 4) |
1341 NVME_SGL_FMT_INVALIDATE;
1342
1343 return 0;
1344}
1345
5ec5d3bd
MG
1346static void nvme_rdma_set_sig_domain(struct blk_integrity *bi,
1347 struct nvme_command *cmd, struct ib_sig_domain *domain,
1348 u16 control, u8 pi_type)
1349{
1350 domain->sig_type = IB_SIG_TYPE_T10_DIF;
1351 domain->sig.dif.bg_type = IB_T10DIF_CRC;
1352 domain->sig.dif.pi_interval = 1 << bi->interval_exp;
1353 domain->sig.dif.ref_tag = le32_to_cpu(cmd->rw.reftag);
1354 if (control & NVME_RW_PRINFO_PRCHK_REF)
1355 domain->sig.dif.ref_remap = true;
1356
1357 domain->sig.dif.app_tag = le16_to_cpu(cmd->rw.apptag);
1358 domain->sig.dif.apptag_check_mask = le16_to_cpu(cmd->rw.appmask);
1359 domain->sig.dif.app_escape = true;
1360 if (pi_type == NVME_NS_DPS_PI_TYPE3)
1361 domain->sig.dif.ref_escape = true;
1362}
1363
1364static void nvme_rdma_set_sig_attrs(struct blk_integrity *bi,
1365 struct nvme_command *cmd, struct ib_sig_attrs *sig_attrs,
1366 u8 pi_type)
1367{
1368 u16 control = le16_to_cpu(cmd->rw.control);
1369
1370 memset(sig_attrs, 0, sizeof(*sig_attrs));
1371 if (control & NVME_RW_PRINFO_PRACT) {
1372 /* for WRITE_INSERT/READ_STRIP no memory domain */
1373 sig_attrs->mem.sig_type = IB_SIG_TYPE_NONE;
1374 nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->wire, control,
1375 pi_type);
1376 /* Clear the PRACT bit since HCA will generate/verify the PI */
1377 control &= ~NVME_RW_PRINFO_PRACT;
1378 cmd->rw.control = cpu_to_le16(control);
1379 } else {
1380 /* for WRITE_PASS/READ_PASS both wire/memory domains exist */
1381 nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->wire, control,
1382 pi_type);
1383 nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->mem, control,
1384 pi_type);
1385 }
1386}
1387
1388static void nvme_rdma_set_prot_checks(struct nvme_command *cmd, u8 *mask)
1389{
1390 *mask = 0;
1391 if (le16_to_cpu(cmd->rw.control) & NVME_RW_PRINFO_PRCHK_REF)
1392 *mask |= IB_SIG_CHECK_REFTAG;
1393 if (le16_to_cpu(cmd->rw.control) & NVME_RW_PRINFO_PRCHK_GUARD)
1394 *mask |= IB_SIG_CHECK_GUARD;
1395}
1396
1397static void nvme_rdma_sig_done(struct ib_cq *cq, struct ib_wc *wc)
1398{
1399 if (unlikely(wc->status != IB_WC_SUCCESS))
1400 nvme_rdma_wr_error(cq, wc, "SIG");
1401}
1402
1403static int nvme_rdma_map_sg_pi(struct nvme_rdma_queue *queue,
1404 struct nvme_rdma_request *req, struct nvme_command *c,
1405 int count, int pi_count)
1406{
1407 struct nvme_rdma_sgl *sgl = &req->data_sgl;
1408 struct ib_reg_wr *wr = &req->reg_wr;
1409 struct request *rq = blk_mq_rq_from_pdu(req);
1410 struct nvme_ns *ns = rq->q->queuedata;
1411 struct bio *bio = rq->bio;
1412 struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
1413 int nr;
1414
1415 req->mr = ib_mr_pool_get(queue->qp, &queue->qp->sig_mrs);
1416 if (WARN_ON_ONCE(!req->mr))
1417 return -EAGAIN;
1418
1419 nr = ib_map_mr_sg_pi(req->mr, sgl->sg_table.sgl, count, NULL,
1420 req->metadata_sgl->sg_table.sgl, pi_count, NULL,
1421 SZ_4K);
1422 if (unlikely(nr))
1423 goto mr_put;
1424
309dca30 1425 nvme_rdma_set_sig_attrs(blk_get_integrity(bio->bi_bdev->bd_disk), c,
5ec5d3bd
MG
1426 req->mr->sig_attrs, ns->pi_type);
1427 nvme_rdma_set_prot_checks(c, &req->mr->sig_attrs->check_mask);
1428
1429 ib_update_fast_reg_key(req->mr, ib_inc_rkey(req->mr->rkey));
1430
1431 req->reg_cqe.done = nvme_rdma_sig_done;
1432 memset(wr, 0, sizeof(*wr));
1433 wr->wr.opcode = IB_WR_REG_MR_INTEGRITY;
1434 wr->wr.wr_cqe = &req->reg_cqe;
1435 wr->wr.num_sge = 0;
1436 wr->wr.send_flags = 0;
1437 wr->mr = req->mr;
1438 wr->key = req->mr->rkey;
1439 wr->access = IB_ACCESS_LOCAL_WRITE |
1440 IB_ACCESS_REMOTE_READ |
1441 IB_ACCESS_REMOTE_WRITE;
1442
1443 sg->addr = cpu_to_le64(req->mr->iova);
1444 put_unaligned_le24(req->mr->length, sg->length);
1445 put_unaligned_le32(req->mr->rkey, sg->key);
1446 sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
1447
1448 return 0;
1449
1450mr_put:
1451 ib_mr_pool_put(queue->qp, &queue->qp->sig_mrs, req->mr);
1452 req->mr = NULL;
1453 if (nr < 0)
1454 return nr;
1455 return -EINVAL;
1456}
1457
4686af88
MG
1458static int nvme_rdma_dma_map_req(struct ib_device *ibdev, struct request *rq,
1459 int *count, int *pi_count)
71102307
CH
1460{
1461 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
4686af88 1462 int ret;
71102307 1463
324d9e78
IR
1464 req->data_sgl.sg_table.sgl = (struct scatterlist *)(req + 1);
1465 ret = sg_alloc_table_chained(&req->data_sgl.sg_table,
1466 blk_rq_nr_phys_segments(rq), req->data_sgl.sg_table.sgl,
38e18002 1467 NVME_INLINE_SG_CNT);
71102307
CH
1468 if (ret)
1469 return -ENOMEM;
1470
324d9e78
IR
1471 req->data_sgl.nents = blk_rq_map_sg(rq->q, rq,
1472 req->data_sgl.sg_table.sgl);
71102307 1473
4686af88
MG
1474 *count = ib_dma_map_sg(ibdev, req->data_sgl.sg_table.sgl,
1475 req->data_sgl.nents, rq_dma_dir(rq));
1476 if (unlikely(*count <= 0)) {
94423a8f
MG
1477 ret = -EIO;
1478 goto out_free_table;
71102307
CH
1479 }
1480
5ec5d3bd
MG
1481 if (blk_integrity_rq(rq)) {
1482 req->metadata_sgl->sg_table.sgl =
1483 (struct scatterlist *)(req->metadata_sgl + 1);
1484 ret = sg_alloc_table_chained(&req->metadata_sgl->sg_table,
1485 blk_rq_count_integrity_sg(rq->q, rq->bio),
1486 req->metadata_sgl->sg_table.sgl,
1487 NVME_INLINE_METADATA_SG_CNT);
1488 if (unlikely(ret)) {
1489 ret = -ENOMEM;
1490 goto out_unmap_sg;
1491 }
1492
1493 req->metadata_sgl->nents = blk_rq_map_integrity_sg(rq->q,
1494 rq->bio, req->metadata_sgl->sg_table.sgl);
4686af88
MG
1495 *pi_count = ib_dma_map_sg(ibdev,
1496 req->metadata_sgl->sg_table.sgl,
1497 req->metadata_sgl->nents,
1498 rq_dma_dir(rq));
1499 if (unlikely(*pi_count <= 0)) {
5ec5d3bd
MG
1500 ret = -EIO;
1501 goto out_free_pi_table;
1502 }
1503 }
1504
4686af88
MG
1505 return 0;
1506
1507out_free_pi_table:
1508 sg_free_table_chained(&req->metadata_sgl->sg_table,
1509 NVME_INLINE_METADATA_SG_CNT);
1510out_unmap_sg:
1511 ib_dma_unmap_sg(ibdev, req->data_sgl.sg_table.sgl, req->data_sgl.nents,
1512 rq_dma_dir(rq));
1513out_free_table:
1514 sg_free_table_chained(&req->data_sgl.sg_table, NVME_INLINE_SG_CNT);
1515 return ret;
1516}
1517
1518static int nvme_rdma_map_data(struct nvme_rdma_queue *queue,
1519 struct request *rq, struct nvme_command *c)
1520{
1521 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
1522 struct nvme_rdma_device *dev = queue->device;
1523 struct ib_device *ibdev = dev->dev;
1524 int pi_count = 0;
1525 int count, ret;
1526
1527 req->num_sge = 1;
1528 refcount_set(&req->ref, 2); /* send and recv completions */
1529
1530 c->common.flags |= NVME_CMD_SGL_METABUF;
1531
1532 if (!blk_rq_nr_phys_segments(rq))
1533 return nvme_rdma_set_sg_null(c);
1534
1535 ret = nvme_rdma_dma_map_req(ibdev, rq, &count, &pi_count);
1536 if (unlikely(ret))
1537 return ret;
1538
5ec5d3bd
MG
1539 if (req->use_sig_mr) {
1540 ret = nvme_rdma_map_sg_pi(queue, req, c, count, pi_count);
1541 goto out;
1542 }
1543
64a741c1 1544 if (count <= dev->num_inline_segments) {
b131c61d 1545 if (rq_data_dir(rq) == WRITE && nvme_rdma_queue_idx(queue) &&
64a741c1 1546 queue->ctrl->use_inline_data &&
b131c61d 1547 blk_rq_payload_bytes(rq) <=
94423a8f 1548 nvme_rdma_inline_data_size(queue)) {
64a741c1 1549 ret = nvme_rdma_map_sg_inline(queue, req, c, count);
94423a8f
MG
1550 goto out;
1551 }
71102307 1552
64a741c1 1553 if (count == 1 && dev->pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) {
94423a8f
MG
1554 ret = nvme_rdma_map_sg_single(queue, req, c);
1555 goto out;
1556 }
71102307
CH
1557 }
1558
94423a8f
MG
1559 ret = nvme_rdma_map_sg_fr(queue, req, c, count);
1560out:
1561 if (unlikely(ret))
4686af88 1562 goto out_dma_unmap_req;
94423a8f
MG
1563
1564 return 0;
1565
4686af88
MG
1566out_dma_unmap_req:
1567 nvme_rdma_dma_unmap_req(ibdev, rq);
94423a8f 1568 return ret;
71102307
CH
1569}
1570
1571static void nvme_rdma_send_done(struct ib_cq *cq, struct ib_wc *wc)
1572{
4af7f7ff
SG
1573 struct nvme_rdma_qe *qe =
1574 container_of(wc->wr_cqe, struct nvme_rdma_qe, cqe);
1575 struct nvme_rdma_request *req =
1576 container_of(qe, struct nvme_rdma_request, sqe);
4af7f7ff 1577
8446546c 1578 if (unlikely(wc->status != IB_WC_SUCCESS))
71102307 1579 nvme_rdma_wr_error(cq, wc, "SEND");
8446546c
CH
1580 else
1581 nvme_rdma_end_request(req);
71102307
CH
1582}
1583
1584static int nvme_rdma_post_send(struct nvme_rdma_queue *queue,
1585 struct nvme_rdma_qe *qe, struct ib_sge *sge, u32 num_sge,
b4b591c8 1586 struct ib_send_wr *first)
71102307 1587{
45e3cc1a 1588 struct ib_send_wr wr;
71102307
CH
1589 int ret;
1590
1591 sge->addr = qe->dma;
a62315b8 1592 sge->length = sizeof(struct nvme_command);
71102307
CH
1593 sge->lkey = queue->device->pd->local_dma_lkey;
1594
71102307
CH
1595 wr.next = NULL;
1596 wr.wr_cqe = &qe->cqe;
1597 wr.sg_list = sge;
1598 wr.num_sge = num_sge;
1599 wr.opcode = IB_WR_SEND;
b4b591c8 1600 wr.send_flags = IB_SEND_SIGNALED;
71102307
CH
1601
1602 if (first)
1603 first->next = &wr;
1604 else
1605 first = &wr;
1606
45e3cc1a 1607 ret = ib_post_send(queue->qp, first, NULL);
a7b7c7a1 1608 if (unlikely(ret)) {
71102307
CH
1609 dev_err(queue->ctrl->ctrl.device,
1610 "%s failed with error code %d\n", __func__, ret);
1611 }
1612 return ret;
1613}
1614
1615static int nvme_rdma_post_recv(struct nvme_rdma_queue *queue,
1616 struct nvme_rdma_qe *qe)
1617{
45e3cc1a 1618 struct ib_recv_wr wr;
71102307
CH
1619 struct ib_sge list;
1620 int ret;
1621
1622 list.addr = qe->dma;
1623 list.length = sizeof(struct nvme_completion);
1624 list.lkey = queue->device->pd->local_dma_lkey;
1625
1626 qe->cqe.done = nvme_rdma_recv_done;
1627
1628 wr.next = NULL;
1629 wr.wr_cqe = &qe->cqe;
1630 wr.sg_list = &list;
1631 wr.num_sge = 1;
1632
45e3cc1a 1633 ret = ib_post_recv(queue->qp, &wr, NULL);
a7b7c7a1 1634 if (unlikely(ret)) {
71102307
CH
1635 dev_err(queue->ctrl->ctrl.device,
1636 "%s failed with error code %d\n", __func__, ret);
1637 }
1638 return ret;
1639}
1640
1641static struct blk_mq_tags *nvme_rdma_tagset(struct nvme_rdma_queue *queue)
1642{
1643 u32 queue_idx = nvme_rdma_queue_idx(queue);
1644
1645 if (queue_idx == 0)
1646 return queue->ctrl->admin_tag_set.tags[queue_idx];
1647 return queue->ctrl->tag_set.tags[queue_idx - 1];
1648}
1649
b4b591c8
SG
1650static void nvme_rdma_async_done(struct ib_cq *cq, struct ib_wc *wc)
1651{
1652 if (unlikely(wc->status != IB_WC_SUCCESS))
1653 nvme_rdma_wr_error(cq, wc, "ASYNC");
1654}
1655
ad22c355 1656static void nvme_rdma_submit_async_event(struct nvme_ctrl *arg)
71102307
CH
1657{
1658 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(arg);
1659 struct nvme_rdma_queue *queue = &ctrl->queues[0];
1660 struct ib_device *dev = queue->device->dev;
1661 struct nvme_rdma_qe *sqe = &ctrl->async_event_sqe;
1662 struct nvme_command *cmd = sqe->data;
1663 struct ib_sge sge;
1664 int ret;
1665
71102307
CH
1666 ib_dma_sync_single_for_cpu(dev, sqe->dma, sizeof(*cmd), DMA_TO_DEVICE);
1667
1668 memset(cmd, 0, sizeof(*cmd));
1669 cmd->common.opcode = nvme_admin_async_event;
38dabe21 1670 cmd->common.command_id = NVME_AQ_BLK_MQ_DEPTH;
71102307
CH
1671 cmd->common.flags |= NVME_CMD_SGL_METABUF;
1672 nvme_rdma_set_sg_null(cmd);
1673
b4b591c8
SG
1674 sqe->cqe.done = nvme_rdma_async_done;
1675
71102307
CH
1676 ib_dma_sync_single_for_device(dev, sqe->dma, sizeof(*cmd),
1677 DMA_TO_DEVICE);
1678
b4b591c8 1679 ret = nvme_rdma_post_send(queue, sqe, &sge, 1, NULL);
71102307
CH
1680 WARN_ON_ONCE(ret);
1681}
1682
1052b8ac
JA
1683static void nvme_rdma_process_nvme_rsp(struct nvme_rdma_queue *queue,
1684 struct nvme_completion *cqe, struct ib_wc *wc)
71102307 1685{
71102307
CH
1686 struct request *rq;
1687 struct nvme_rdma_request *req;
71102307 1688
e7006de6 1689 rq = nvme_find_rq(nvme_rdma_tagset(queue), cqe->command_id);
71102307
CH
1690 if (!rq) {
1691 dev_err(queue->ctrl->ctrl.device,
e7006de6 1692 "got bad command_id %#x on QP %#x\n",
71102307
CH
1693 cqe->command_id, queue->qp->qp_num);
1694 nvme_rdma_error_recovery(queue->ctrl);
1052b8ac 1695 return;
71102307
CH
1696 }
1697 req = blk_mq_rq_to_pdu(rq);
1698
4af7f7ff
SG
1699 req->status = cqe->status;
1700 req->result = cqe->result;
71102307 1701
3ef0279b 1702 if (wc->wc_flags & IB_WC_WITH_INVALIDATE) {
a87da50f
CL
1703 if (unlikely(!req->mr ||
1704 wc->ex.invalidate_rkey != req->mr->rkey)) {
3ef0279b
SG
1705 dev_err(queue->ctrl->ctrl.device,
1706 "Bogus remote invalidation for rkey %#x\n",
a87da50f 1707 req->mr ? req->mr->rkey : 0);
3ef0279b
SG
1708 nvme_rdma_error_recovery(queue->ctrl);
1709 }
f41725bb 1710 } else if (req->mr) {
1052b8ac
JA
1711 int ret;
1712
2f122e4f
SG
1713 ret = nvme_rdma_inv_rkey(queue, req);
1714 if (unlikely(ret < 0)) {
1715 dev_err(queue->ctrl->ctrl.device,
1716 "Queueing INV WR for rkey %#x failed (%d)\n",
1717 req->mr->rkey, ret);
1718 nvme_rdma_error_recovery(queue->ctrl);
1719 }
1720 /* the local invalidation completion will end the request */
7a804c34 1721 return;
2f122e4f 1722 }
7a804c34
CH
1723
1724 nvme_rdma_end_request(req);
71102307
CH
1725}
1726
1052b8ac 1727static void nvme_rdma_recv_done(struct ib_cq *cq, struct ib_wc *wc)
71102307
CH
1728{
1729 struct nvme_rdma_qe *qe =
1730 container_of(wc->wr_cqe, struct nvme_rdma_qe, cqe);
287f329e 1731 struct nvme_rdma_queue *queue = wc->qp->qp_context;
71102307
CH
1732 struct ib_device *ibdev = queue->device->dev;
1733 struct nvme_completion *cqe = qe->data;
1734 const size_t len = sizeof(struct nvme_completion);
71102307
CH
1735
1736 if (unlikely(wc->status != IB_WC_SUCCESS)) {
1737 nvme_rdma_wr_error(cq, wc, "RECV");
1052b8ac 1738 return;
71102307
CH
1739 }
1740
25c1ca6e 1741 /* sanity checking for received data length */
1742 if (unlikely(wc->byte_len < len)) {
1743 dev_err(queue->ctrl->ctrl.device,
1744 "Unexpected nvme completion length(%d)\n", wc->byte_len);
1745 nvme_rdma_error_recovery(queue->ctrl);
1746 return;
1747 }
1748
71102307
CH
1749 ib_dma_sync_single_for_cpu(ibdev, qe->dma, len, DMA_FROM_DEVICE);
1750 /*
1751 * AEN requests are special as they don't time out and can
1752 * survive any kind of queue freeze and often don't respond to
1753 * aborts. We don't even bother to allocate a struct request
1754 * for them but rather special case them here.
1755 */
58a8df67
IR
1756 if (unlikely(nvme_is_aen_req(nvme_rdma_queue_idx(queue),
1757 cqe->command_id)))
7bf58533
CH
1758 nvme_complete_async_event(&queue->ctrl->ctrl, cqe->status,
1759 &cqe->result);
71102307 1760 else
1052b8ac 1761 nvme_rdma_process_nvme_rsp(queue, cqe, wc);
71102307
CH
1762 ib_dma_sync_single_for_device(ibdev, qe->dma, len, DMA_FROM_DEVICE);
1763
1764 nvme_rdma_post_recv(queue, qe);
71102307
CH
1765}
1766
1767static int nvme_rdma_conn_established(struct nvme_rdma_queue *queue)
1768{
1769 int ret, i;
1770
1771 for (i = 0; i < queue->queue_size; i++) {
1772 ret = nvme_rdma_post_recv(queue, &queue->rsp_ring[i]);
1773 if (ret)
9817d763 1774 return ret;
71102307
CH
1775 }
1776
1777 return 0;
71102307
CH
1778}
1779
1780static int nvme_rdma_conn_rejected(struct nvme_rdma_queue *queue,
1781 struct rdma_cm_event *ev)
1782{
7f03953c
SW
1783 struct rdma_cm_id *cm_id = queue->cm_id;
1784 int status = ev->status;
1785 const char *rej_msg;
1786 const struct nvme_rdma_cm_rej *rej_data;
1787 u8 rej_data_len;
1788
1789 rej_msg = rdma_reject_msg(cm_id, status);
1790 rej_data = rdma_consumer_reject_data(cm_id, ev, &rej_data_len);
1791
1792 if (rej_data && rej_data_len >= sizeof(u16)) {
1793 u16 sts = le16_to_cpu(rej_data->sts);
71102307
CH
1794
1795 dev_err(queue->ctrl->ctrl.device,
7f03953c
SW
1796 "Connect rejected: status %d (%s) nvme status %d (%s).\n",
1797 status, rej_msg, sts, nvme_rdma_cm_msg(sts));
71102307
CH
1798 } else {
1799 dev_err(queue->ctrl->ctrl.device,
7f03953c 1800 "Connect rejected: status %d (%s).\n", status, rej_msg);
71102307
CH
1801 }
1802
1803 return -ECONNRESET;
1804}
1805
1806static int nvme_rdma_addr_resolved(struct nvme_rdma_queue *queue)
1807{
e63440d6 1808 struct nvme_ctrl *ctrl = &queue->ctrl->ctrl;
71102307
CH
1809 int ret;
1810
ca6e95bb
SG
1811 ret = nvme_rdma_create_queue_ib(queue);
1812 if (ret)
1813 return ret;
71102307 1814
e63440d6
IR
1815 if (ctrl->opts->tos >= 0)
1816 rdma_set_service_type(queue->cm_id, ctrl->opts->tos);
0525af71 1817 ret = rdma_resolve_route(queue->cm_id, NVME_RDMA_CM_TIMEOUT_MS);
71102307 1818 if (ret) {
e63440d6 1819 dev_err(ctrl->device, "rdma_resolve_route failed (%d).\n",
71102307
CH
1820 queue->cm_error);
1821 goto out_destroy_queue;
1822 }
1823
1824 return 0;
1825
1826out_destroy_queue:
1827 nvme_rdma_destroy_queue_ib(queue);
71102307
CH
1828 return ret;
1829}
1830
1831static int nvme_rdma_route_resolved(struct nvme_rdma_queue *queue)
1832{
1833 struct nvme_rdma_ctrl *ctrl = queue->ctrl;
1834 struct rdma_conn_param param = { };
0b857b44 1835 struct nvme_rdma_cm_req priv = { };
71102307
CH
1836 int ret;
1837
1838 param.qp_num = queue->qp->qp_num;
1839 param.flow_control = 1;
1840
1841 param.responder_resources = queue->device->dev->attrs.max_qp_rd_atom;
2ac17c28
SG
1842 /* maximum retry count */
1843 param.retry_count = 7;
71102307
CH
1844 param.rnr_retry_count = 7;
1845 param.private_data = &priv;
1846 param.private_data_len = sizeof(priv);
1847
1848 priv.recfmt = cpu_to_le16(NVME_RDMA_CM_FMT_1_0);
1849 priv.qid = cpu_to_le16(nvme_rdma_queue_idx(queue));
f994d9dc
JF
1850 /*
1851 * set the admin queue depth to the minimum size
1852 * specified by the Fabrics standard.
1853 */
1854 if (priv.qid == 0) {
7aa1f427
SG
1855 priv.hrqsize = cpu_to_le16(NVME_AQ_DEPTH);
1856 priv.hsqsize = cpu_to_le16(NVME_AQ_DEPTH - 1);
f994d9dc 1857 } else {
c5af8654
JF
1858 /*
1859 * current interpretation of the fabrics spec
1860 * is at minimum you make hrqsize sqsize+1, or a
1861 * 1's based representation of sqsize.
1862 */
f994d9dc 1863 priv.hrqsize = cpu_to_le16(queue->queue_size);
c5af8654 1864 priv.hsqsize = cpu_to_le16(queue->ctrl->ctrl.sqsize);
f994d9dc 1865 }
71102307 1866
071ba4cc 1867 ret = rdma_connect_locked(queue->cm_id, &param);
71102307
CH
1868 if (ret) {
1869 dev_err(ctrl->ctrl.device,
071ba4cc 1870 "rdma_connect_locked failed (%d).\n", ret);
9817d763 1871 return ret;
71102307
CH
1872 }
1873
1874 return 0;
71102307
CH
1875}
1876
71102307
CH
1877static int nvme_rdma_cm_handler(struct rdma_cm_id *cm_id,
1878 struct rdma_cm_event *ev)
1879{
1880 struct nvme_rdma_queue *queue = cm_id->context;
1881 int cm_error = 0;
1882
1883 dev_dbg(queue->ctrl->ctrl.device, "%s (%d): status %d id %p\n",
1884 rdma_event_msg(ev->event), ev->event,
1885 ev->status, cm_id);
1886
1887 switch (ev->event) {
1888 case RDMA_CM_EVENT_ADDR_RESOLVED:
1889 cm_error = nvme_rdma_addr_resolved(queue);
1890 break;
1891 case RDMA_CM_EVENT_ROUTE_RESOLVED:
1892 cm_error = nvme_rdma_route_resolved(queue);
1893 break;
1894 case RDMA_CM_EVENT_ESTABLISHED:
1895 queue->cm_error = nvme_rdma_conn_established(queue);
1896 /* complete cm_done regardless of success/failure */
1897 complete(&queue->cm_done);
1898 return 0;
1899 case RDMA_CM_EVENT_REJECTED:
1900 cm_error = nvme_rdma_conn_rejected(queue, ev);
1901 break;
71102307
CH
1902 case RDMA_CM_EVENT_ROUTE_ERROR:
1903 case RDMA_CM_EVENT_CONNECT_ERROR:
1904 case RDMA_CM_EVENT_UNREACHABLE:
abf87d5e 1905 case RDMA_CM_EVENT_ADDR_ERROR:
71102307
CH
1906 dev_dbg(queue->ctrl->ctrl.device,
1907 "CM error event %d\n", ev->event);
1908 cm_error = -ECONNRESET;
1909 break;
1910 case RDMA_CM_EVENT_DISCONNECTED:
1911 case RDMA_CM_EVENT_ADDR_CHANGE:
1912 case RDMA_CM_EVENT_TIMEWAIT_EXIT:
1913 dev_dbg(queue->ctrl->ctrl.device,
1914 "disconnect received - connection closed\n");
1915 nvme_rdma_error_recovery(queue->ctrl);
1916 break;
1917 case RDMA_CM_EVENT_DEVICE_REMOVAL:
e87a911f
SW
1918 /* device removal is handled via the ib_client API */
1919 break;
71102307
CH
1920 default:
1921 dev_err(queue->ctrl->ctrl.device,
1922 "Unexpected RDMA CM event (%d)\n", ev->event);
1923 nvme_rdma_error_recovery(queue->ctrl);
1924 break;
1925 }
1926
1927 if (cm_error) {
1928 queue->cm_error = cm_error;
1929 complete(&queue->cm_done);
1930 }
1931
1932 return 0;
1933}
1934
0475a8dc
SG
1935static void nvme_rdma_complete_timed_out(struct request *rq)
1936{
1937 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
1938 struct nvme_rdma_queue *queue = req->queue;
0475a8dc 1939
0475a8dc 1940 nvme_rdma_stop_queue(queue);
93ba75c9 1941 nvmf_complete_timed_out_request(rq);
0475a8dc
SG
1942}
1943
9bdb4833 1944static enum blk_eh_timer_return nvme_rdma_timeout(struct request *rq)
71102307
CH
1945{
1946 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
4c174e63
SG
1947 struct nvme_rdma_queue *queue = req->queue;
1948 struct nvme_rdma_ctrl *ctrl = queue->ctrl;
71102307 1949
4c174e63
SG
1950 dev_warn(ctrl->ctrl.device, "I/O %d QID %d timeout\n",
1951 rq->tag, nvme_rdma_queue_idx(queue));
e62a538d 1952
e6e7f7ac 1953 if (nvme_ctrl_state(&ctrl->ctrl) != NVME_CTRL_LIVE) {
4c174e63 1954 /*
0475a8dc
SG
1955 * If we are resetting, connecting or deleting we should
1956 * complete immediately because we may block controller
1957 * teardown or setup sequence
1958 * - ctrl disable/shutdown fabrics requests
1959 * - connect requests
1960 * - initialization admin requests
1961 * - I/O requests that entered after unquiescing and
1962 * the controller stopped responding
1963 *
1964 * All other requests should be cancelled by the error
1965 * recovery work, so it's fine that we fail it here.
4c174e63 1966 */
0475a8dc 1967 nvme_rdma_complete_timed_out(rq);
4c174e63
SG
1968 return BLK_EH_DONE;
1969 }
71102307 1970
0475a8dc
SG
1971 /*
1972 * LIVE state should trigger the normal error recovery which will
1973 * handle completing this request.
1974 */
4c174e63 1975 nvme_rdma_error_recovery(ctrl);
4c174e63 1976 return BLK_EH_RESET_TIMER;
71102307
CH
1977}
1978
fc17b653 1979static blk_status_t nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx,
71102307
CH
1980 const struct blk_mq_queue_data *bd)
1981{
1982 struct nvme_ns *ns = hctx->queue->queuedata;
1983 struct nvme_rdma_queue *queue = hctx->driver_data;
1984 struct request *rq = bd->rq;
1985 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
1986 struct nvme_rdma_qe *sqe = &req->sqe;
f4b9e6c9 1987 struct nvme_command *c = nvme_req(rq)->cmd;
71102307 1988 struct ib_device *dev;
3bc32bb1 1989 bool queue_ready = test_bit(NVME_RDMA_Q_LIVE, &queue->flags);
fc17b653
CH
1990 blk_status_t ret;
1991 int err;
71102307
CH
1992
1993 WARN_ON_ONCE(rq->tag < 0);
1994
a9715744
TC
1995 if (!nvme_check_ready(&queue->ctrl->ctrl, rq, queue_ready))
1996 return nvme_fail_nonready_command(&queue->ctrl->ctrl, rq);
553cd9ef 1997
71102307 1998 dev = queue->device->dev;
62f99b62
MG
1999
2000 req->sqe.dma = ib_dma_map_single(dev, req->sqe.data,
2001 sizeof(struct nvme_command),
2002 DMA_TO_DEVICE);
2003 err = ib_dma_mapping_error(dev, req->sqe.dma);
2004 if (unlikely(err))
2005 return BLK_STS_RESOURCE;
2006
71102307
CH
2007 ib_dma_sync_single_for_cpu(dev, sqe->dma,
2008 sizeof(struct nvme_command), DMA_TO_DEVICE);
2009
f4b9e6c9 2010 ret = nvme_setup_cmd(ns, rq);
fc17b653 2011 if (ret)
62f99b62 2012 goto unmap_qe;
71102307 2013
6887fc64 2014 nvme_start_request(rq);
71102307 2015
5ec5d3bd
MG
2016 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) &&
2017 queue->pi_support &&
2018 (c->common.opcode == nvme_cmd_write ||
2019 c->common.opcode == nvme_cmd_read) &&
2020 nvme_ns_has_pi(ns))
2021 req->use_sig_mr = true;
2022 else
2023 req->use_sig_mr = false;
2024
fc17b653 2025 err = nvme_rdma_map_data(queue, rq, c);
a7b7c7a1 2026 if (unlikely(err < 0)) {
71102307 2027 dev_err(queue->ctrl->ctrl.device,
fc17b653 2028 "Failed to map data (%d)\n", err);
71102307
CH
2029 goto err;
2030 }
2031
b4b591c8
SG
2032 sqe->cqe.done = nvme_rdma_send_done;
2033
71102307
CH
2034 ib_dma_sync_single_for_device(dev, sqe->dma,
2035 sizeof(struct nvme_command), DMA_TO_DEVICE);
2036
fc17b653 2037 err = nvme_rdma_post_send(queue, sqe, req->sge, req->num_sge,
f41725bb 2038 req->mr ? &req->reg_wr.wr : NULL);
16686f3a
MG
2039 if (unlikely(err))
2040 goto err_unmap;
71102307 2041
fc17b653 2042 return BLK_STS_OK;
62f99b62 2043
16686f3a
MG
2044err_unmap:
2045 nvme_rdma_unmap_data(queue, rq);
71102307 2046err:
62eca397
CL
2047 if (err == -EIO)
2048 ret = nvme_host_path_error(rq);
2049 else if (err == -ENOMEM || err == -EAGAIN)
62f99b62
MG
2050 ret = BLK_STS_RESOURCE;
2051 else
2052 ret = BLK_STS_IOERR;
16686f3a 2053 nvme_cleanup_cmd(rq);
62f99b62
MG
2054unmap_qe:
2055 ib_dma_unmap_single(dev, req->sqe.dma, sizeof(struct nvme_command),
2056 DMA_TO_DEVICE);
2057 return ret;
71102307
CH
2058}
2059
5a72e899 2060static int nvme_rdma_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
ff8519f9
SG
2061{
2062 struct nvme_rdma_queue *queue = hctx->driver_data;
2063
2064 return ib_process_cq_direct(queue->ib_cq, -1);
2065}
2066
5ec5d3bd
MG
2067static void nvme_rdma_check_pi_status(struct nvme_rdma_request *req)
2068{
2069 struct request *rq = blk_mq_rq_from_pdu(req);
2070 struct ib_mr_status mr_status;
2071 int ret;
2072
2073 ret = ib_check_mr_status(req->mr, IB_MR_CHECK_SIG_STATUS, &mr_status);
2074 if (ret) {
2075 pr_err("ib_check_mr_status failed, ret %d\n", ret);
2076 nvme_req(rq)->status = NVME_SC_INVALID_PI;
2077 return;
2078 }
2079
2080 if (mr_status.fail_status & IB_MR_CHECK_SIG_STATUS) {
2081 switch (mr_status.sig_err.err_type) {
2082 case IB_SIG_BAD_GUARD:
2083 nvme_req(rq)->status = NVME_SC_GUARD_CHECK;
2084 break;
2085 case IB_SIG_BAD_REFTAG:
2086 nvme_req(rq)->status = NVME_SC_REFTAG_CHECK;
2087 break;
2088 case IB_SIG_BAD_APPTAG:
2089 nvme_req(rq)->status = NVME_SC_APPTAG_CHECK;
2090 break;
2091 }
2092 pr_err("PI error found type %d expected 0x%x vs actual 0x%x\n",
2093 mr_status.sig_err.err_type, mr_status.sig_err.expected,
2094 mr_status.sig_err.actual);
2095 }
2096}
2097
71102307
CH
2098static void nvme_rdma_complete_rq(struct request *rq)
2099{
2100 struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
62f99b62
MG
2101 struct nvme_rdma_queue *queue = req->queue;
2102 struct ib_device *ibdev = queue->device->dev;
71102307 2103
5ec5d3bd
MG
2104 if (req->use_sig_mr)
2105 nvme_rdma_check_pi_status(req);
2106
62f99b62
MG
2107 nvme_rdma_unmap_data(queue, rq);
2108 ib_dma_unmap_single(ibdev, req->sqe.dma, sizeof(struct nvme_command),
2109 DMA_TO_DEVICE);
77f02a7a 2110 nvme_complete_rq(rq);
71102307
CH
2111}
2112
a4e1d0b7 2113static void nvme_rdma_map_queues(struct blk_mq_tag_set *set)
0b36658c 2114{
2d60738c 2115 struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(set->driver_data);
5651cd3c 2116
a249d306 2117 nvmf_map_queues(set, &ctrl->ctrl, ctrl->io_queues);
0b36658c
SG
2118}
2119
f363b089 2120static const struct blk_mq_ops nvme_rdma_mq_ops = {
71102307
CH
2121 .queue_rq = nvme_rdma_queue_rq,
2122 .complete = nvme_rdma_complete_rq,
71102307
CH
2123 .init_request = nvme_rdma_init_request,
2124 .exit_request = nvme_rdma_exit_request,
71102307 2125 .init_hctx = nvme_rdma_init_hctx,
71102307 2126 .timeout = nvme_rdma_timeout,
0b36658c 2127 .map_queues = nvme_rdma_map_queues,
ff8519f9 2128 .poll = nvme_rdma_poll,
71102307
CH
2129};
2130
f363b089 2131static const struct blk_mq_ops nvme_rdma_admin_mq_ops = {
71102307
CH
2132 .queue_rq = nvme_rdma_queue_rq,
2133 .complete = nvme_rdma_complete_rq,
385475ee
CH
2134 .init_request = nvme_rdma_init_request,
2135 .exit_request = nvme_rdma_exit_request,
71102307
CH
2136 .init_hctx = nvme_rdma_init_admin_hctx,
2137 .timeout = nvme_rdma_timeout,
2138};
2139
18398af2 2140static void nvme_rdma_shutdown_ctrl(struct nvme_rdma_ctrl *ctrl, bool shutdown)
71102307 2141{
75862c72 2142 nvme_rdma_teardown_io_queues(ctrl, shutdown);
9f27bd70 2143 nvme_quiesce_admin_queue(&ctrl->ctrl);
285b6e9b 2144 nvme_disable_ctrl(&ctrl->ctrl, shutdown);
75862c72 2145 nvme_rdma_teardown_admin_queue(ctrl, shutdown);
71102307
CH
2146}
2147
c5017e85 2148static void nvme_rdma_delete_ctrl(struct nvme_ctrl *ctrl)
2461a8dd 2149{
e9bc2587 2150 nvme_rdma_shutdown_ctrl(to_rdma_ctrl(ctrl), true);
71102307
CH
2151}
2152
71102307
CH
2153static void nvme_rdma_reset_ctrl_work(struct work_struct *work)
2154{
d86c4d8e
CH
2155 struct nvme_rdma_ctrl *ctrl =
2156 container_of(work, struct nvme_rdma_ctrl, ctrl.reset_work);
71102307 2157
d09f2b45 2158 nvme_stop_ctrl(&ctrl->ctrl);
18398af2 2159 nvme_rdma_shutdown_ctrl(ctrl, false);
71102307 2160
ad6a0a52 2161 if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
d5bf4b7f
SG
2162 /* state change failure should never happen */
2163 WARN_ON_ONCE(1);
2164 return;
2165 }
2166
c66e2998 2167 if (nvme_rdma_setup_ctrl(ctrl, false))
370ae6e4 2168 goto out_fail;
71102307 2169
71102307
CH
2170 return;
2171
370ae6e4 2172out_fail:
8000d1fd
NC
2173 ++ctrl->ctrl.nr_reconnects;
2174 nvme_rdma_reconnect_or_remove(ctrl);
71102307
CH
2175}
2176
71102307
CH
2177static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = {
2178 .name = "rdma",
2179 .module = THIS_MODULE,
5ec5d3bd 2180 .flags = NVME_F_FABRICS | NVME_F_METADATA_SUPPORTED,
71102307
CH
2181 .reg_read32 = nvmf_reg_read32,
2182 .reg_read64 = nvmf_reg_read64,
2183 .reg_write32 = nvmf_reg_write32,
71102307
CH
2184 .free_ctrl = nvme_rdma_free_ctrl,
2185 .submit_async_event = nvme_rdma_submit_async_event,
c5017e85 2186 .delete_ctrl = nvme_rdma_delete_ctrl,
71102307 2187 .get_address = nvmf_get_address,
f7f70f4a 2188 .stop_ctrl = nvme_rdma_stop_ctrl,
71102307
CH
2189};
2190
36e835f2
JS
2191/*
2192 * Fails a connection request if it matches an existing controller
2193 * (association) with the same tuple:
2194 * <Host NQN, Host ID, local address, remote address, remote port, SUBSYS NQN>
2195 *
2196 * if local address is not specified in the request, it will match an
2197 * existing controller with all the other parameters the same and no
2198 * local port address specified as well.
2199 *
2200 * The ports don't need to be compared as they are intrinsically
2201 * already matched by the port pointers supplied.
2202 */
2203static bool
2204nvme_rdma_existing_controller(struct nvmf_ctrl_options *opts)
2205{
2206 struct nvme_rdma_ctrl *ctrl;
2207 bool found = false;
2208
2209 mutex_lock(&nvme_rdma_ctrl_mutex);
2210 list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list) {
b7c7be6f 2211 found = nvmf_ip_options_match(&ctrl->ctrl, opts);
36e835f2
JS
2212 if (found)
2213 break;
2214 }
2215 mutex_unlock(&nvme_rdma_ctrl_mutex);
2216
2217 return found;
2218}
2219
71102307
CH
2220static struct nvme_ctrl *nvme_rdma_create_ctrl(struct device *dev,
2221 struct nvmf_ctrl_options *opts)
2222{
2223 struct nvme_rdma_ctrl *ctrl;
2224 int ret;
2225 bool changed;
2226
2227 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
2228 if (!ctrl)
2229 return ERR_PTR(-ENOMEM);
2230 ctrl->ctrl.opts = opts;
2231 INIT_LIST_HEAD(&ctrl->list);
2232
bb59b8e5
SG
2233 if (!(opts->mask & NVMF_OPT_TRSVCID)) {
2234 opts->trsvcid =
2235 kstrdup(__stringify(NVME_RDMA_IP_PORT), GFP_KERNEL);
2236 if (!opts->trsvcid) {
2237 ret = -ENOMEM;
2238 goto out_free_ctrl;
2239 }
2240 opts->mask |= NVMF_OPT_TRSVCID;
2241 }
0928f9b4
SG
2242
2243 ret = inet_pton_with_scope(&init_net, AF_UNSPEC,
bb59b8e5 2244 opts->traddr, opts->trsvcid, &ctrl->addr);
71102307 2245 if (ret) {
bb59b8e5
SG
2246 pr_err("malformed address passed: %s:%s\n",
2247 opts->traddr, opts->trsvcid);
71102307
CH
2248 goto out_free_ctrl;
2249 }
2250
8f4e8dac 2251 if (opts->mask & NVMF_OPT_HOST_TRADDR) {
0928f9b4
SG
2252 ret = inet_pton_with_scope(&init_net, AF_UNSPEC,
2253 opts->host_traddr, NULL, &ctrl->src_addr);
8f4e8dac 2254 if (ret) {
0928f9b4 2255 pr_err("malformed src address passed: %s\n",
8f4e8dac
MG
2256 opts->host_traddr);
2257 goto out_free_ctrl;
2258 }
2259 }
2260
36e835f2
JS
2261 if (!opts->duplicate_connect && nvme_rdma_existing_controller(opts)) {
2262 ret = -EALREADY;
2263 goto out_free_ctrl;
2264 }
2265
71102307
CH
2266 INIT_DELAYED_WORK(&ctrl->reconnect_work,
2267 nvme_rdma_reconnect_ctrl_work);
2268 INIT_WORK(&ctrl->err_work, nvme_rdma_error_recovery_work);
d86c4d8e 2269 INIT_WORK(&ctrl->ctrl.reset_work, nvme_rdma_reset_ctrl_work);
71102307 2270
ff8519f9
SG
2271 ctrl->ctrl.queue_count = opts->nr_io_queues + opts->nr_write_queues +
2272 opts->nr_poll_queues + 1;
c5af8654 2273 ctrl->ctrl.sqsize = opts->queue_size - 1;
71102307
CH
2274 ctrl->ctrl.kato = opts->kato;
2275
2276 ret = -ENOMEM;
d858e5f0 2277 ctrl->queues = kcalloc(ctrl->ctrl.queue_count, sizeof(*ctrl->queues),
71102307
CH
2278 GFP_KERNEL);
2279 if (!ctrl->queues)
3d064101
SG
2280 goto out_free_ctrl;
2281
2282 ret = nvme_init_ctrl(&ctrl->ctrl, dev, &nvme_rdma_ctrl_ops,
2283 0 /* no quirks, we're perfect! */);
2284 if (ret)
2285 goto out_kfree_queues;
71102307 2286
b754a32c
MG
2287 changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING);
2288 WARN_ON_ONCE(!changed);
2289
c66e2998 2290 ret = nvme_rdma_setup_ctrl(ctrl, true);
71102307 2291 if (ret)
3d064101 2292 goto out_uninit_ctrl;
71102307 2293
0928f9b4 2294 dev_info(ctrl->ctrl.device, "new ctrl: NQN \"%s\", addr %pISpcs\n",
e5ea42fa 2295 nvmf_ctrl_subsysnqn(&ctrl->ctrl), &ctrl->addr);
71102307 2296
71102307
CH
2297 mutex_lock(&nvme_rdma_ctrl_mutex);
2298 list_add_tail(&ctrl->list, &nvme_rdma_ctrl_list);
2299 mutex_unlock(&nvme_rdma_ctrl_mutex);
2300
71102307
CH
2301 return &ctrl->ctrl;
2302
71102307
CH
2303out_uninit_ctrl:
2304 nvme_uninit_ctrl(&ctrl->ctrl);
2305 nvme_put_ctrl(&ctrl->ctrl);
2306 if (ret > 0)
2307 ret = -EIO;
2308 return ERR_PTR(ret);
3d064101
SG
2309out_kfree_queues:
2310 kfree(ctrl->queues);
71102307
CH
2311out_free_ctrl:
2312 kfree(ctrl);
2313 return ERR_PTR(ret);
2314}
2315
2316static struct nvmf_transport_ops nvme_rdma_transport = {
2317 .name = "rdma",
0de5cd36 2318 .module = THIS_MODULE,
71102307 2319 .required_opts = NVMF_OPT_TRADDR,
8f4e8dac 2320 .allowed_opts = NVMF_OPT_TRSVCID | NVMF_OPT_RECONNECT_DELAY |
b65bb777 2321 NVMF_OPT_HOST_TRADDR | NVMF_OPT_CTRL_LOSS_TMO |
e63440d6
IR
2322 NVMF_OPT_NR_WRITE_QUEUES | NVMF_OPT_NR_POLL_QUEUES |
2323 NVMF_OPT_TOS,
71102307
CH
2324 .create_ctrl = nvme_rdma_create_ctrl,
2325};
2326
e87a911f
SW
2327static void nvme_rdma_remove_one(struct ib_device *ib_device, void *client_data)
2328{
2329 struct nvme_rdma_ctrl *ctrl;
9bad0404
MG
2330 struct nvme_rdma_device *ndev;
2331 bool found = false;
2332
2333 mutex_lock(&device_list_mutex);
2334 list_for_each_entry(ndev, &device_list, entry) {
2335 if (ndev->dev == ib_device) {
2336 found = true;
2337 break;
2338 }
2339 }
2340 mutex_unlock(&device_list_mutex);
2341
2342 if (!found)
2343 return;
e87a911f
SW
2344
2345 /* Delete all controllers using this device */
2346 mutex_lock(&nvme_rdma_ctrl_mutex);
2347 list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list) {
2348 if (ctrl->device->dev != ib_device)
2349 continue;
c5017e85 2350 nvme_delete_ctrl(&ctrl->ctrl);
e87a911f
SW
2351 }
2352 mutex_unlock(&nvme_rdma_ctrl_mutex);
2353
b227c59b 2354 flush_workqueue(nvme_delete_wq);
e87a911f
SW
2355}
2356
2357static struct ib_client nvme_rdma_ib_client = {
2358 .name = "nvme_rdma",
e87a911f
SW
2359 .remove = nvme_rdma_remove_one
2360};
2361
71102307
CH
2362static int __init nvme_rdma_init_module(void)
2363{
e87a911f
SW
2364 int ret;
2365
e87a911f 2366 ret = ib_register_client(&nvme_rdma_ib_client);
a56c79cf 2367 if (ret)
9a6327d2 2368 return ret;
a56c79cf
SG
2369
2370 ret = nvmf_register_transport(&nvme_rdma_transport);
2371 if (ret)
2372 goto err_unreg_client;
e87a911f 2373
a56c79cf 2374 return 0;
e87a911f 2375
a56c79cf
SG
2376err_unreg_client:
2377 ib_unregister_client(&nvme_rdma_ib_client);
a56c79cf 2378 return ret;
71102307
CH
2379}
2380
2381static void __exit nvme_rdma_cleanup_module(void)
2382{
9ad9e8d6
MG
2383 struct nvme_rdma_ctrl *ctrl;
2384
71102307 2385 nvmf_unregister_transport(&nvme_rdma_transport);
e87a911f 2386 ib_unregister_client(&nvme_rdma_ib_client);
9ad9e8d6
MG
2387
2388 mutex_lock(&nvme_rdma_ctrl_mutex);
2389 list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list)
2390 nvme_delete_ctrl(&ctrl->ctrl);
2391 mutex_unlock(&nvme_rdma_ctrl_mutex);
2392 flush_workqueue(nvme_delete_wq);
71102307
CH
2393}
2394
2395module_init(nvme_rdma_init_module);
2396module_exit(nvme_rdma_cleanup_module);
2397
2398MODULE_LICENSE("GPL v2");