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nvme-rdma: implement polling queue map
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
f11bb3e2
CH		 35#include "nvme.h"
36
b60503ba
MW		 37#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 39
a7a7cbe3 40#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 41
943e942e
JA		 42/*
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
45 */
46#define NVME_MAX_KB_SZ 4096
47#define NVME_MAX_SEGS 127
48
58ffacb5
MW		 49static int use_threaded_interrupts;
50module_param(use_threaded_interrupts, int, 0);
51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_int,
71};
72
73static int io_queue_depth = 1024;
74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
3b6592f7
JA		 77static int queue_count_set(const char *val, const struct kernel_param *kp);
78static const struct kernel_param_ops queue_count_ops = {
79 .set = queue_count_set,
80 .get = param_get_int,
81};
82
83static int write_queues;
84module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
85MODULE_PARM_DESC(write_queues,
86 "Number of queues to use for writes. If not set, reads and writes "
87 "will share a queue set.");
88
a4668d9b 89static int poll_queues = 0;
4b04cc6a
JA		 90module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
91MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
92
1c63dc66
CH		 93struct nvme_dev;
94struct nvme_queue;
b3fffdef 95
a5cdb68c 96static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 97
1c63dc66
CH		 98/*
99 * Represents an NVM Express device. Each nvme_dev is a PCI function.
100 */
101struct nvme_dev {
147b27e4 102 struct nvme_queue *queues;
1c63dc66
CH		 103 struct blk_mq_tag_set tagset;
104 struct blk_mq_tag_set admin_tagset;
105 u32 __iomem *dbs;
106 struct device *dev;
107 struct dma_pool *prp_page_pool;
108 struct dma_pool *prp_small_pool;
1c63dc66
CH		 109 unsigned online_queues;
110 unsigned max_qid;
e20ba6e1 111 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 112 unsigned int num_vecs;
1c63dc66
CH		 113 int q_depth;
114 u32 db_stride;
1c63dc66 115 void __iomem *bar;
97f6ef64 116 unsigned long bar_mapped_size;
5c8809e6 117 struct work_struct remove_work;
77bf25ea 118 struct mutex shutdown_lock;
1c63dc66 119 bool subsystem;
1c63dc66 120 u64 cmb_size;
0f238ff5 121 bool cmb_use_sqes;
1c63dc66 122 u32 cmbsz;
202021c1 123 u32 cmbloc;
1c63dc66 124 struct nvme_ctrl ctrl;
87ad72a5 125
943e942e
JA		 126 mempool_t *iod_mempool;
127
87ad72a5 128 /* shadow doorbell buffer support: */
f9f38e33
HK		 129 u32 *dbbuf_dbs;
130 dma_addr_t dbbuf_dbs_dma_addr;
131 u32 *dbbuf_eis;
132 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 133
134 /* host memory buffer support: */
135 u64 host_mem_size;
136 u32 nr_host_mem_descs;
4033f35d 137 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 138 struct nvme_host_mem_buf_desc *host_mem_descs;
139 void **host_mem_desc_bufs;
4d115420 140};
1fa6aead 141
b27c1e68 142static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
143{
144 int n = 0, ret;
145
146 ret = kstrtoint(val, 10, &n);
147 if (ret != 0 || n < 2)
148 return -EINVAL;
149
150 return param_set_int(val, kp);
151}
152
3b6592f7
JA		 153static int queue_count_set(const char *val, const struct kernel_param *kp)
154{
155 int n = 0, ret;
156
157 ret = kstrtoint(val, 10, &n);
158 if (n > num_possible_cpus())
159 n = num_possible_cpus();
160
161 return param_set_int(val, kp);
162}
163
f9f38e33
HK		 164static inline unsigned int sq_idx(unsigned int qid, u32 stride)
165{
166 return qid * 2 * stride;
167}
168
169static inline unsigned int cq_idx(unsigned int qid, u32 stride)
170{
171 return (qid * 2 + 1) * stride;
172}
173
1c63dc66
CH		 174static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
175{
176 return container_of(ctrl, struct nvme_dev, ctrl);
177}
178
b60503ba
MW		 179/*
180 * An NVM Express queue. Each device has at least two (one for admin
181 * commands and one for I/O commands).
182 */
183struct nvme_queue {
184 struct device *q_dmadev;
091b6092 185 struct nvme_dev *dev;
1ab0cd69 186 spinlock_t sq_lock;
b60503ba 187 struct nvme_command *sq_cmds;
3a7afd8e
CH		 188 /* only used for poll queues: */
189 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 190 volatile struct nvme_completion *cqes;
42483228 191 struct blk_mq_tags **tags;
b60503ba
MW		 192 dma_addr_t sq_dma_addr;
193 dma_addr_t cq_dma_addr;
b60503ba
MW		 194 u32 __iomem *q_db;
195 u16 q_depth;
6222d172 196 s16 cq_vector;
b60503ba 197 u16 sq_tail;
04f3eafd 198 u16 last_sq_tail;
b60503ba 199 u16 cq_head;
68fa9dbe 200 u16 last_cq_head;
c30341dc 201 u16 qid;
e9539f47 202 u8 cq_phase;
4e224106
CH		 203 unsigned long flags;
204#define NVMEQ_ENABLED 0
63223078 205#define NVMEQ_SQ_CMB 1
d1ed6aa1 206#define NVMEQ_DELETE_ERROR 2
f9f38e33
HK		 207 u32 *dbbuf_sq_db;
208 u32 *dbbuf_cq_db;
209 u32 *dbbuf_sq_ei;
210 u32 *dbbuf_cq_ei;
d1ed6aa1 211 struct completion delete_done;
b60503ba
MW		 212};
213
71bd150c
CH		 214/*
215 * The nvme_iod describes the data in an I/O, including the list of PRP
216 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 217 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 218 * allocated to store the PRP list.
219 */
220struct nvme_iod {
d49187e9 221 struct nvme_request req;
f4800d6d 222 struct nvme_queue *nvmeq;
a7a7cbe3 223 bool use_sgl;
f4800d6d 224 int aborted;
71bd150c 225 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 226 int nents; /* Used in scatterlist */
227 int length; /* Of data, in bytes */
228 dma_addr_t first_dma;
bf684057 229 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 230 struct scatterlist *sg;
231 struct scatterlist inline_sg[0];
b60503ba
MW		 232};
233
234/*
235 * Check we didin't inadvertently grow the command struct
236 */
237static inline void _nvme_check_size(void)
238{
239 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 244 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 245 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 246 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 247 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
248 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 249 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 250 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 251 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
252}
253
3b6592f7
JA		 254static unsigned int max_io_queues(void)
255{
4b04cc6a 256 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 257}
258
259static unsigned int max_queue_count(void)
260{
261 /* IO queues + admin queue */
262 return 1 + max_io_queues();
263}
264
f9f38e33
HK		 265static inline unsigned int nvme_dbbuf_size(u32 stride)
266{
3b6592f7 267 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 268}
269
270static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
271{
272 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
273
274 if (dev->dbbuf_dbs)
275 return 0;
276
277 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_dbs_dma_addr,
279 GFP_KERNEL);
280 if (!dev->dbbuf_dbs)
281 return -ENOMEM;
282 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
283 &dev->dbbuf_eis_dma_addr,
284 GFP_KERNEL);
285 if (!dev->dbbuf_eis) {
286 dma_free_coherent(dev->dev, mem_size,
287 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
288 dev->dbbuf_dbs = NULL;
289 return -ENOMEM;
290 }
291
292 return 0;
293}
294
295static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
296{
297 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
298
299 if (dev->dbbuf_dbs) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
302 dev->dbbuf_dbs = NULL;
303 }
304 if (dev->dbbuf_eis) {
305 dma_free_coherent(dev->dev, mem_size,
306 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
307 dev->dbbuf_eis = NULL;
308 }
309}
310
311static void nvme_dbbuf_init(struct nvme_dev *dev,
312 struct nvme_queue *nvmeq, int qid)
313{
314 if (!dev->dbbuf_dbs || !qid)
315 return;
316
317 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
318 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
319 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
321}
322
323static void nvme_dbbuf_set(struct nvme_dev *dev)
324{
325 struct nvme_command c;
326
327 if (!dev->dbbuf_dbs)
328 return;
329
330 memset(&c, 0, sizeof(c));
331 c.dbbuf.opcode = nvme_admin_dbbuf;
332 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
333 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
334
335 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 336 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 337 /* Free memory and continue on */
338 nvme_dbbuf_dma_free(dev);
339 }
340}
341
342static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
343{
344 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
345}
346
347/* Update dbbuf and return true if an MMIO is required */
348static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
349 volatile u32 *dbbuf_ei)
350{
351 if (dbbuf_db) {
352 u16 old_value;
353
354 /*
355 * Ensure that the queue is written before updating
356 * the doorbell in memory
357 */
358 wmb();
359
360 old_value = *dbbuf_db;
361 *dbbuf_db = value;
362
f1ed3df2
MW		 363 /*
364 * Ensure that the doorbell is updated before reading the event
365 * index from memory. The controller needs to provide similar
366 * ordering to ensure the envent index is updated before reading
367 * the doorbell.
368 */
369 mb();
370
f9f38e33
HK		 371 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
372 return false;
373 }
374
375 return true;
b60503ba
MW		 376}
377
ac3dd5bd
JA		 378/*
379 * Max size of iod being embedded in the request payload
380 */
381#define NVME_INT_PAGES 2
5fd4ce1b 382#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 383
384/*
385 * Will slightly overestimate the number of pages needed. This is OK
386 * as it only leads to a small amount of wasted memory for the lifetime of
387 * the I/O.
388 */
389static int nvme_npages(unsigned size, struct nvme_dev *dev)
390{
5fd4ce1b
CH		 391 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
392 dev->ctrl.page_size);
ac3dd5bd
JA		 393 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
394}
395
a7a7cbe3
CK		 396/*
397 * Calculates the number of pages needed for the SGL segments. For example a 4k
398 * page can accommodate 256 SGL descriptors.
399 */
400static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 401{
a7a7cbe3 402 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 403}
ac3dd5bd 404
a7a7cbe3
CK		 405static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
406 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 407{
a7a7cbe3
CK		 408 size_t alloc_size;
409
410 if (use_sgl)
411 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
412 else
413 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
414
415 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 416}
ac3dd5bd 417
a7a7cbe3 418static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 419{
a7a7cbe3
CK		 420 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
421 NVME_INT_BYTES(dev), NVME_INT_PAGES,
422 use_sgl);
423
424 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 425}
426
a4aea562
MB		 427static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
428 unsigned int hctx_idx)
e85248e5 429{
a4aea562 430 struct nvme_dev *dev = data;
147b27e4 431 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 432
42483228
KB		 433 WARN_ON(hctx_idx != 0);
434 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
435 WARN_ON(nvmeq->tags);
436
a4aea562 437 hctx->driver_data = nvmeq;
42483228 438 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 439 return 0;
e85248e5
MW		 440}
441
4af0e21c
KB		 442static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
443{
444 struct nvme_queue *nvmeq = hctx->driver_data;
445
446 nvmeq->tags = NULL;
447}
448
a4aea562
MB		 449static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
450 unsigned int hctx_idx)
b60503ba 451{
a4aea562 452 struct nvme_dev *dev = data;
147b27e4 453 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 454
42483228
KB		 455 if (!nvmeq->tags)
456 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 457
42483228 458 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 459 hctx->driver_data = nvmeq;
460 return 0;
b60503ba
MW		 461}
462
d6296d39
CH		 463static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
464 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 465{
d6296d39 466 struct nvme_dev *dev = set->driver_data;
f4800d6d 467 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 468 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 469 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 470
471 BUG_ON(!nvmeq);
f4800d6d 472 iod->nvmeq = nvmeq;
59e29ce6
SG		 473
474 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 475 return 0;
476}
477
3b6592f7
JA		 478static int queue_irq_offset(struct nvme_dev *dev)
479{
480 /* if we have more than 1 vec, admin queue offsets us by 1 */
481 if (dev->num_vecs > 1)
482 return 1;
483
484 return 0;
485}
486
dca51e78
CH		 487static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
488{
489 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 490 int i, qoff, offset;
491
492 offset = queue_irq_offset(dev);
493 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
494 struct blk_mq_queue_map *map = &set->map[i];
495
496 map->nr_queues = dev->io_queues[i];
497 if (!map->nr_queues) {
e20ba6e1 498 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 499 continue;
3b6592f7
JA		 500 }
501
4b04cc6a
JA		 502 /*
503 * The poll queue(s) doesn't have an IRQ (and hence IRQ
504 * affinity), so use the regular blk-mq cpu mapping
505 */
3b6592f7 506 map->queue_offset = qoff;
e20ba6e1 507 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 508 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
509 else
510 blk_mq_map_queues(map);
3b6592f7
JA		 511 qoff += map->nr_queues;
512 offset += map->nr_queues;
513 }
514
515 return 0;
dca51e78
CH		 516}
517
04f3eafd
JA		 518/*
519 * Write sq tail if we are asked to, or if the next command would wrap.
520 */
521static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
522{
523 if (!write_sq) {
524 u16 next_tail = nvmeq->sq_tail + 1;
525
526 if (next_tail == nvmeq->q_depth)
527 next_tail = 0;
528 if (next_tail != nvmeq->last_sq_tail)
529 return;
530 }
531
532 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
533 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
534 writel(nvmeq->sq_tail, nvmeq->q_db);
535 nvmeq->last_sq_tail = nvmeq->sq_tail;
536}
537
b60503ba 538/**
90ea5ca4 539 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 540 * @nvmeq: The queue to use
541 * @cmd: The command to send
04f3eafd 542 * @write_sq: whether to write to the SQ doorbell
b60503ba 543 */
04f3eafd
JA		 544static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
545 bool write_sq)
b60503ba 546{
90ea5ca4 547 spin_lock(&nvmeq->sq_lock);
0f238ff5 548 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 549 if (++nvmeq->sq_tail == nvmeq->q_depth)
550 nvmeq->sq_tail = 0;
04f3eafd
JA		 551 nvme_write_sq_db(nvmeq, write_sq);
552 spin_unlock(&nvmeq->sq_lock);
553}
554
555static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
556{
557 struct nvme_queue *nvmeq = hctx->driver_data;
558
559 spin_lock(&nvmeq->sq_lock);
560 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
561 nvme_write_sq_db(nvmeq, true);
90ea5ca4 562 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 563}
564
a7a7cbe3 565static void **nvme_pci_iod_list(struct request *req)
b60503ba 566{
f4800d6d 567 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 568 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 569}
570
955b1b5a
MI		 571static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
572{
573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 574 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 575 unsigned int avg_seg_size;
576
20469a37
KB		 577 if (nseg == 0)
578 return false;
579
580 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 581
582 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
583 return false;
584 if (!iod->nvmeq->qid)
585 return false;
586 if (!sgl_threshold || avg_seg_size < sgl_threshold)
587 return false;
588 return true;
589}
590
fc17b653 591static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 592{
f4800d6d 593 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 594 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 595 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 596
955b1b5a
MI		 597 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
598
f4800d6d 599 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 600 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 601 if (!iod->sg)
fc17b653 602 return BLK_STS_RESOURCE;
f4800d6d
CH		 603 } else {
604 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 605 }
606
f4800d6d
CH		 607 iod->aborted = 0;
608 iod->npages = -1;
609 iod->nents = 0;
610 iod->length = size;
f80ec966 611
fc17b653 612 return BLK_STS_OK;
ac3dd5bd
JA		 613}
614
f4800d6d 615static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 616{
f4800d6d 617 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 618 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
619 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
620
eca18b23 621 int i;
eca18b23
MW		 622
623 if (iod->npages == 0)
a7a7cbe3
CK		 624 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
625 dma_addr);
626
eca18b23 627 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 628 void *addr = nvme_pci_iod_list(req)[i];
629
630 if (iod->use_sgl) {
631 struct nvme_sgl_desc *sg_list = addr;
632
633 next_dma_addr =
634 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
635 } else {
636 __le64 *prp_list = addr;
637
638 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
639 }
640
641 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
642 dma_addr = next_dma_addr;
eca18b23 643 }
ac3dd5bd 644
f4800d6d 645 if (iod->sg != iod->inline_sg)
943e942e 646 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 647}
648
d0877473
KB		 649static void nvme_print_sgl(struct scatterlist *sgl, int nents)
650{
651 int i;
652 struct scatterlist *sg;
653
654 for_each_sg(sgl, sg, nents, i) {
655 dma_addr_t phys = sg_phys(sg);
656 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
657 "dma_address:%pad dma_length:%d\n",
658 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
659 sg_dma_len(sg));
660 }
661}
662
a7a7cbe3
CK		 663static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
664 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 665{
f4800d6d 666 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 667 struct dma_pool *pool;
b131c61d 668 int length = blk_rq_payload_bytes(req);
eca18b23 669 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 670 int dma_len = sg_dma_len(sg);
671 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 672 u32 page_size = dev->ctrl.page_size;
f137e0f1 673 int offset = dma_addr & (page_size - 1);
e025344c 674 __le64 *prp_list;
a7a7cbe3 675 void **list = nvme_pci_iod_list(req);
e025344c 676 dma_addr_t prp_dma;
eca18b23 677 int nprps, i;
ff22b54f 678
1d090624 679 length -= (page_size - offset);
5228b328
JS		 680 if (length <= 0) {
681 iod->first_dma = 0;
a7a7cbe3 682 goto done;
5228b328 683 }
ff22b54f 684
1d090624 685 dma_len -= (page_size - offset);
ff22b54f 686 if (dma_len) {
1d090624 687 dma_addr += (page_size - offset);
ff22b54f
MW		 688 } else {
689 sg = sg_next(sg);
690 dma_addr = sg_dma_address(sg);
691 dma_len = sg_dma_len(sg);
692 }
693
1d090624 694 if (length <= page_size) {
edd10d33 695 iod->first_dma = dma_addr;
a7a7cbe3 696 goto done;
e025344c
SMM		 697 }
698
1d090624 699 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 700 if (nprps <= (256 / 8)) {
701 pool = dev->prp_small_pool;
eca18b23 702 iod->npages = 0;
99802a7a
MW		 703 } else {
704 pool = dev->prp_page_pool;
eca18b23 705 iod->npages = 1;
99802a7a
MW		 706 }
707
69d2b571 708 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 709 if (!prp_list) {
edd10d33 710 iod->first_dma = dma_addr;
eca18b23 711 iod->npages = -1;
86eea289 712 return BLK_STS_RESOURCE;
b77954cb 713 }
eca18b23
MW		 714 list[0] = prp_list;
715 iod->first_dma = prp_dma;
e025344c
SMM		 716 i = 0;
717 for (;;) {
1d090624 718 if (i == page_size >> 3) {
e025344c 719 __le64 *old_prp_list = prp_list;
69d2b571 720 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 721 if (!prp_list)
86eea289 722 return BLK_STS_RESOURCE;
eca18b23 723 list[iod->npages++] = prp_list;
7523d834
MW		 724 prp_list[0] = old_prp_list[i - 1];
725 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
726 i = 1;
e025344c
SMM		 727 }
728 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 729 dma_len -= page_size;
730 dma_addr += page_size;
731 length -= page_size;
e025344c
SMM		 732 if (length <= 0)
733 break;
734 if (dma_len > 0)
735 continue;
86eea289
KB		 736 if (unlikely(dma_len < 0))
737 goto bad_sgl;
e025344c
SMM		 738 sg = sg_next(sg);
739 dma_addr = sg_dma_address(sg);
740 dma_len = sg_dma_len(sg);
ff22b54f
MW		 741 }
742
a7a7cbe3
CK		 743done:
744 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
746
86eea289
KB		 747 return BLK_STS_OK;
748
749 bad_sgl:
d0877473
KB		 750 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
751 "Invalid SGL for payload:%d nents:%d\n",
752 blk_rq_payload_bytes(req), iod->nents);
86eea289 753 return BLK_STS_IOERR;
ff22b54f
MW		 754}
755
a7a7cbe3
CK		 756static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
757 struct scatterlist *sg)
758{
759 sge->addr = cpu_to_le64(sg_dma_address(sg));
760 sge->length = cpu_to_le32(sg_dma_len(sg));
761 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
762}
763
764static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
765 dma_addr_t dma_addr, int entries)
766{
767 sge->addr = cpu_to_le64(dma_addr);
768 if (entries < SGES_PER_PAGE) {
769 sge->length = cpu_to_le32(entries * sizeof(*sge));
770 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
771 } else {
772 sge->length = cpu_to_le32(PAGE_SIZE);
773 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
774 }
775}
776
777static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 778 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 779{
780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 781 struct dma_pool *pool;
782 struct nvme_sgl_desc *sg_list;
783 struct scatterlist *sg = iod->sg;
a7a7cbe3 784 dma_addr_t sgl_dma;
b0f2853b 785 int i = 0;
a7a7cbe3 786
a7a7cbe3
CK		 787 /* setting the transfer type as SGL */
788 cmd->flags = NVME_CMD_SGL_METABUF;
789
b0f2853b 790 if (entries == 1) {
a7a7cbe3
CK		 791 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
792 return BLK_STS_OK;
793 }
794
795 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
796 pool = dev->prp_small_pool;
797 iod->npages = 0;
798 } else {
799 pool = dev->prp_page_pool;
800 iod->npages = 1;
801 }
802
803 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
804 if (!sg_list) {
805 iod->npages = -1;
806 return BLK_STS_RESOURCE;
807 }
808
809 nvme_pci_iod_list(req)[0] = sg_list;
810 iod->first_dma = sgl_dma;
811
812 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
813
814 do {
815 if (i == SGES_PER_PAGE) {
816 struct nvme_sgl_desc *old_sg_desc = sg_list;
817 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
818
819 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
820 if (!sg_list)
821 return BLK_STS_RESOURCE;
822
823 i = 0;
824 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
825 sg_list[i++] = *link;
826 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
827 }
828
829 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 830 sg = sg_next(sg);
b0f2853b 831 } while (--entries > 0);
a7a7cbe3 832
a7a7cbe3
CK		 833 return BLK_STS_OK;
834}
835
fc17b653 836static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 837 struct nvme_command *cmnd)
d29ec824 838{
f4800d6d 839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 840 struct request_queue *q = req->q;
841 enum dma_data_direction dma_dir = rq_data_dir(req) ?
842 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 843 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 844 int nr_mapped;
d29ec824 845
f9d03f96 846 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 847 iod->nents = blk_rq_map_sg(q, req, iod->sg);
848 if (!iod->nents)
849 goto out;
d29ec824 850
fc17b653 851 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 852
853 if (is_pci_p2pdma_page(sg_page(iod->sg)))
854 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
855 dma_dir);
856 else
857 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
858 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 859 if (!nr_mapped)
ba1ca37e 860 goto out;
d29ec824 861
955b1b5a 862 if (iod->use_sgl)
b0f2853b 863 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 864 else
865 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
866
86eea289 867 if (ret != BLK_STS_OK)
ba1ca37e 868 goto out_unmap;
0e5e4f0e 869
fc17b653 870 ret = BLK_STS_IOERR;
ba1ca37e
CH		 871 if (blk_integrity_rq(req)) {
872 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
873 goto out_unmap;
0e5e4f0e 874
bf684057
CH		 875 sg_init_table(&iod->meta_sg, 1);
876 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 877 goto out_unmap;
0e5e4f0e 878
bf684057 879 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 880 goto out_unmap;
00df5cb4 881
bf684057 882 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 883 }
884
fc17b653 885 return BLK_STS_OK;
00df5cb4 886
ba1ca37e
CH		 887out_unmap:
888 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
889out:
890 return ret;
00df5cb4
MW		 891}
892
f4800d6d 893static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 894{
f4800d6d 895 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 896 enum dma_data_direction dma_dir = rq_data_dir(req) ?
897 DMA_TO_DEVICE : DMA_FROM_DEVICE;
898
899 if (iod->nents) {
e0596ab2
LG		 900 /* P2PDMA requests do not need to be unmapped */
901 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
902 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
903
f7f1fc36 904 if (blk_integrity_rq(req))
bf684057 905 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 906 }
e1e5e564 907
f9d03f96 908 nvme_cleanup_cmd(req);
f4800d6d 909 nvme_free_iod(dev, req);
d4f6c3ab 910}
b60503ba 911
d29ec824
CH		 912/*
913 * NOTE: ns is NULL when called on the admin queue.
914 */
fc17b653 915static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 916 const struct blk_mq_queue_data *bd)
edd10d33 917{
a4aea562
MB		 918 struct nvme_ns *ns = hctx->queue->queuedata;
919 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 920 struct nvme_dev *dev = nvmeq->dev;
a4aea562 921 struct request *req = bd->rq;
ba1ca37e 922 struct nvme_command cmnd;
ebe6d874 923 blk_status_t ret;
e1e5e564 924
d1f06f4a
JA		 925 /*
926 * We should not need to do this, but we're still using this to
927 * ensure we can drain requests on a dying queue.
928 */
4e224106 929 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 930 return BLK_STS_IOERR;
931
f9d03f96 932 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 933 if (ret)
f4800d6d 934 return ret;
a4aea562 935
b131c61d 936 ret = nvme_init_iod(req, dev);
fc17b653 937 if (ret)
f9d03f96 938 goto out_free_cmd;
a4aea562 939
fc17b653 940 if (blk_rq_nr_phys_segments(req)) {
b131c61d 941 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 942 if (ret)
943 goto out_cleanup_iod;
944 }
a4aea562 945
aae239e1 946 blk_mq_start_request(req);
04f3eafd 947 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 948 return BLK_STS_OK;
f9d03f96 949out_cleanup_iod:
f4800d6d 950 nvme_free_iod(dev, req);
f9d03f96
CH		 951out_free_cmd:
952 nvme_cleanup_cmd(req);
ba1ca37e 953 return ret;
b60503ba 954}
e1e5e564 955
77f02a7a 956static void nvme_pci_complete_rq(struct request *req)
eee417b0 957{
f4800d6d 958 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 959
77f02a7a
CH		 960 nvme_unmap_data(iod->nvmeq->dev, req);
961 nvme_complete_rq(req);
b60503ba
MW		 962}
963
d783e0bd 964/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 965static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 966{
750dde44
CH		 967 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
968 nvmeq->cq_phase;
d783e0bd
MR		 969}
970
eb281c82 971static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 972{
eb281c82 973 u16 head = nvmeq->cq_head;
adf68f21 974
397c699f
KB		 975 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
976 nvmeq->dbbuf_cq_ei))
977 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 978}
aae239e1 979
5cb525c8 980static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 981{
5cb525c8 982 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 983 struct request *req;
adf68f21 984
83a12fb7
SG		 985 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
986 dev_warn(nvmeq->dev->ctrl.device,
987 "invalid id %d completed on queue %d\n",
988 cqe->command_id, le16_to_cpu(cqe->sq_id));
989 return;
b60503ba
MW		 990 }
991
83a12fb7
SG		 992 /*
993 * AEN requests are special as they don't time out and can
994 * survive any kind of queue freeze and often don't respond to
995 * aborts. We don't even bother to allocate a struct request
996 * for them but rather special case them here.
997 */
998 if (unlikely(nvmeq->qid == 0 &&
38dabe21 999 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1000 nvme_complete_async_event(&nvmeq->dev->ctrl,
1001 cqe->status, &cqe->result);
a0fa9647 1002 return;
83a12fb7 1003 }
b60503ba 1004
83a12fb7
SG		 1005 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1006 nvme_end_request(req, cqe->status, cqe->result);
1007}
b60503ba 1008
5cb525c8 1009static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1010{
5cb525c8
JA		 1011 while (start != end) {
1012 nvme_handle_cqe(nvmeq, start);
1013 if (++start == nvmeq->q_depth)
1014 start = 0;
1015 }
1016}
adf68f21 1017
5cb525c8
JA		 1018static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1019{
1020 if (++nvmeq->cq_head == nvmeq->q_depth) {
1021 nvmeq->cq_head = 0;
1022 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 1023 }
a0fa9647
JA		 1024}
1025
1052b8ac
JA		 1026static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1027 u16 *end, unsigned int tag)
a0fa9647 1028{
1052b8ac 1029 int found = 0;
b60503ba 1030
5cb525c8 1031 *start = nvmeq->cq_head;
1052b8ac
JA		 1032 while (nvme_cqe_pending(nvmeq)) {
1033 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1034 found++;
5cb525c8 1035 nvme_update_cq_head(nvmeq);
920d13a8 1036 }
5cb525c8 1037 *end = nvmeq->cq_head;
eb281c82 1038
5cb525c8 1039 if (*start != *end)
920d13a8 1040 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1041 return found;
b60503ba
MW		 1042}
1043
1044static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1045{
58ffacb5 1046 struct nvme_queue *nvmeq = data;
68fa9dbe 1047 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1048 u16 start, end;
1049
3a7afd8e
CH		 1050 /*
1051 * The rmb/wmb pair ensures we see all updates from a previous run of
1052 * the irq handler, even if that was on another CPU.
1053 */
1054 rmb();
68fa9dbe
JA		 1055 if (nvmeq->cq_head != nvmeq->last_cq_head)
1056 ret = IRQ_HANDLED;
5cb525c8 1057 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1058 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1059 wmb();
5cb525c8 1060
68fa9dbe
JA		 1061 if (start != end) {
1062 nvme_complete_cqes(nvmeq, start, end);
1063 return IRQ_HANDLED;
1064 }
1065
1066 return ret;
58ffacb5
MW		 1067}
1068
1069static irqreturn_t nvme_irq_check(int irq, void *data)
1070{
1071 struct nvme_queue *nvmeq = data;
750dde44 1072 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1073 return IRQ_WAKE_THREAD;
1074 return IRQ_NONE;
58ffacb5
MW		 1075}
1076
0b2a8a9f
CH		 1077/*
1078 * Poll for completions any queue, including those not dedicated to polling.
1079 * Can be called from any context.
1080 */
1081static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1082{
3a7afd8e 1083 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1084 u16 start, end;
1052b8ac 1085 int found;
a0fa9647 1086
3a7afd8e
CH		 1087 /*
1088 * For a poll queue we need to protect against the polling thread
1089 * using the CQ lock. For normal interrupt driven threads we have
1090 * to disable the interrupt to avoid racing with it.
1091 */
91a509f8 1092 if (nvmeq->cq_vector == -1) {
3a7afd8e 1093 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1094 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1095 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1096 } else {
1097 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1098 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1099 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1100 }
442e19b7 1101
5cb525c8 1102 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1103 return found;
a0fa9647
JA		 1104}
1105
9743139c 1106static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1107{
1108 struct nvme_queue *nvmeq = hctx->driver_data;
1109 u16 start, end;
1110 bool found;
1111
1112 if (!nvme_cqe_pending(nvmeq))
1113 return 0;
1114
3a7afd8e 1115 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1116 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1117 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1118
1119 nvme_complete_cqes(nvmeq, start, end);
1120 return found;
1121}
1122
ad22c355 1123static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1124{
f866fc42 1125 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1126 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1127 struct nvme_command c;
b60503ba 1128
a4aea562
MB		 1129 memset(&c, 0, sizeof(c));
1130 c.common.opcode = nvme_admin_async_event;
ad22c355 1131 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1132 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1133}
1134
b60503ba 1135static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1136{
b60503ba
MW		 1137 struct nvme_command c;
1138
1139 memset(&c, 0, sizeof(c));
1140 c.delete_queue.opcode = opcode;
1141 c.delete_queue.qid = cpu_to_le16(id);
1142
1c63dc66 1143 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1144}
1145
b60503ba 1146static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1147 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1148{
b60503ba 1149 struct nvme_command c;
4b04cc6a
JA		 1150 int flags = NVME_QUEUE_PHYS_CONTIG;
1151
1152 if (vector != -1)
1153 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1154
d29ec824 1155 /*
16772ae6 1156 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1157 * is attached to the request.
1158 */
b60503ba
MW		 1159 memset(&c, 0, sizeof(c));
1160 c.create_cq.opcode = nvme_admin_create_cq;
1161 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1162 c.create_cq.cqid = cpu_to_le16(qid);
1163 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1165 if (vector != -1)
1166 c.create_cq.irq_vector = cpu_to_le16(vector);
1167 else
1168 c.create_cq.irq_vector = 0;
b60503ba 1169
1c63dc66 1170 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1171}
1172
1173static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1174 struct nvme_queue *nvmeq)
1175{
9abd68ef 1176 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1177 struct nvme_command c;
81c1cd98 1178 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1179
9abd68ef
JA		 1180 /*
1181 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1182 * set. Since URGENT priority is zeroes, it makes all queues
1183 * URGENT.
1184 */
1185 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1186 flags |= NVME_SQ_PRIO_MEDIUM;
1187
d29ec824 1188 /*
16772ae6 1189 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1190 * is attached to the request.
1191 */
b60503ba
MW		 1192 memset(&c, 0, sizeof(c));
1193 c.create_sq.opcode = nvme_admin_create_sq;
1194 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1195 c.create_sq.sqid = cpu_to_le16(qid);
1196 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1197 c.create_sq.sq_flags = cpu_to_le16(flags);
1198 c.create_sq.cqid = cpu_to_le16(qid);
1199
1c63dc66 1200 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1201}
1202
1203static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1204{
1205 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1206}
1207
1208static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1209{
1210 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1211}
1212
2a842aca 1213static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1214{
f4800d6d
CH		 1215 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1216 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1217
27fa9bc5
CH		 1218 dev_warn(nvmeq->dev->ctrl.device,
1219 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1220 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1221 blk_mq_free_request(req);
bc5fc7e4
MW		 1222}
1223
b2a0eb1a
KB		 1224static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1225{
1226
1227 /* If true, indicates loss of adapter communication, possibly by a
1228 * NVMe Subsystem reset.
1229 */
1230 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1231
ad70062c
JW		 1232 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1233 switch (dev->ctrl.state) {
1234 case NVME_CTRL_RESETTING:
ad6a0a52 1235 case NVME_CTRL_CONNECTING:
b2a0eb1a 1236 return false;
ad70062c
JW		 1237 default:
1238 break;
1239 }
b2a0eb1a
KB		 1240
1241 /* We shouldn't reset unless the controller is on fatal error state
1242 * _or_ if we lost the communication with it.
1243 */
1244 if (!(csts & NVME_CSTS_CFS) && !nssro)
1245 return false;
1246
b2a0eb1a
KB		 1247 return true;
1248}
1249
1250static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1251{
1252 /* Read a config register to help see what died. */
1253 u16 pci_status;
1254 int result;
1255
1256 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1257 &pci_status);
1258 if (result == PCIBIOS_SUCCESSFUL)
1259 dev_warn(dev->ctrl.device,
1260 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1261 csts, pci_status);
1262 else
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1265 csts, result);
1266}
1267
31c7c7d2 1268static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1269{
f4800d6d
CH		 1270 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1271 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1272 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1273 struct request *abort_req;
a4aea562 1274 struct nvme_command cmd;
b2a0eb1a
KB		 1275 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1276
651438bb
WX		 1277 /* If PCI error recovery process is happening, we cannot reset or
1278 * the recovery mechanism will surely fail.
1279 */
1280 mb();
1281 if (pci_channel_offline(to_pci_dev(dev->dev)))
1282 return BLK_EH_RESET_TIMER;
1283
b2a0eb1a
KB		 1284 /*
1285 * Reset immediately if the controller is failed
1286 */
1287 if (nvme_should_reset(dev, csts)) {
1288 nvme_warn_reset(dev, csts);
1289 nvme_dev_disable(dev, false);
d86c4d8e 1290 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1291 return BLK_EH_DONE;
b2a0eb1a 1292 }
c30341dc 1293
7776db1c
KB		 1294 /*
1295 * Did we miss an interrupt?
1296 */
0b2a8a9f 1297 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1298 dev_warn(dev->ctrl.device,
1299 "I/O %d QID %d timeout, completion polled\n",
1300 req->tag, nvmeq->qid);
db8c48e4 1301 return BLK_EH_DONE;
7776db1c
KB		 1302 }
1303
31c7c7d2 1304 /*
fd634f41
CH		 1305 * Shutdown immediately if controller times out while starting. The
1306 * reset work will see the pci device disabled when it gets the forced
1307 * cancellation error. All outstanding requests are completed on
db8c48e4 1308 * shutdown, so we return BLK_EH_DONE.
fd634f41 1309 */
4244140d
KB		 1310 switch (dev->ctrl.state) {
1311 case NVME_CTRL_CONNECTING:
1312 case NVME_CTRL_RESETTING:
b9cac43c 1313 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1314 "I/O %d QID %d timeout, disable controller\n",
1315 req->tag, nvmeq->qid);
a5cdb68c 1316 nvme_dev_disable(dev, false);
27fa9bc5 1317 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1318 return BLK_EH_DONE;
4244140d
KB		 1319 default:
1320 break;
c30341dc
KB		 1321 }
1322
fd634f41
CH		 1323 /*
1324 * Shutdown the controller immediately and schedule a reset if the
1325 * command was already aborted once before and still hasn't been
1326 * returned to the driver, or if this is the admin queue.
31c7c7d2 1327 */
f4800d6d 1328 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1329 dev_warn(dev->ctrl.device,
e1569a16
KB		 1330 "I/O %d QID %d timeout, reset controller\n",
1331 req->tag, nvmeq->qid);
a5cdb68c 1332 nvme_dev_disable(dev, false);
d86c4d8e 1333 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1334
27fa9bc5 1335 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1336 return BLK_EH_DONE;
c30341dc 1337 }
c30341dc 1338
e7a2a87d 1339 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1340 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1341 return BLK_EH_RESET_TIMER;
6bf25d16 1342 }
7bf7d778 1343 iod->aborted = 1;
a4aea562 1344
c30341dc
KB		 1345 memset(&cmd, 0, sizeof(cmd));
1346 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1347 cmd.abort.cid = req->tag;
c30341dc 1348 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1349
1b3c47c1
SG		 1350 dev_warn(nvmeq->dev->ctrl.device,
1351 "I/O %d QID %d timeout, aborting\n",
1352 req->tag, nvmeq->qid);
e7a2a87d
CH		 1353
1354 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1355 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1356 if (IS_ERR(abort_req)) {
1357 atomic_inc(&dev->ctrl.abort_limit);
1358 return BLK_EH_RESET_TIMER;
1359 }
1360
1361 abort_req->timeout = ADMIN_TIMEOUT;
1362 abort_req->end_io_data = NULL;
1363 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1364
31c7c7d2
CH		 1365 /*
1366 * The aborted req will be completed on receiving the abort req.
1367 * We enable the timer again. If hit twice, it'll cause a device reset,
1368 * as the device then is in a faulty state.
1369 */
1370 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1371}
1372
a4aea562
MB		 1373static void nvme_free_queue(struct nvme_queue *nvmeq)
1374{
9e866774
MW		 1375 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1376 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1377 if (!nvmeq->sq_cmds)
1378 return;
0f238ff5 1379
63223078
CH		 1380 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1381 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1382 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1383 } else {
1384 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1385 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1386 }
9e866774
MW		 1387}
1388
a1a5ef99 1389static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1390{
1391 int i;
1392
d858e5f0 1393 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1394 dev->ctrl.queue_count--;
147b27e4 1395 nvme_free_queue(&dev->queues[i]);
121c7ad4 1396 }
22404274
KB		 1397}
1398
4d115420
KB		 1399/**
1400 * nvme_suspend_queue - put queue into suspended state
40581d1a 1401 * @nvmeq: queue to suspend
4d115420
KB		 1402 */
1403static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1404{
4e224106 1405 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1406 return 1;
a09115b2 1407
4e224106 1408 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1409 mb();
a09115b2 1410
4e224106 1411 nvmeq->dev->online_queues--;
1c63dc66 1412 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1413 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH		 1414 if (nvmeq->cq_vector == -1)
1415 return 0;
1416 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1417 nvmeq->cq_vector = -1;
4d115420
KB		 1418 return 0;
1419}
b60503ba 1420
a5cdb68c 1421static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1422{
147b27e4 1423 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1424
a5cdb68c
KB		 1425 if (shutdown)
1426 nvme_shutdown_ctrl(&dev->ctrl);
1427 else
20d0dfe6 1428 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1429
0b2a8a9f 1430 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1431}
1432
8ffaadf7
JD		 1433static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1434 int entry_size)
1435{
1436 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1437 unsigned q_size_aligned = roundup(q_depth * entry_size,
1438 dev->ctrl.page_size);
8ffaadf7
JD		 1439
1440 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1441 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1442 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1443 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1444
1445 /*
1446 * Ensure the reduced q_depth is above some threshold where it
1447 * would be better to map queues in system memory with the
1448 * original depth
1449 */
1450 if (q_depth < 64)
1451 return -ENOMEM;
1452 }
1453
1454 return q_depth;
1455}
1456
1457static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1458 int qid, int depth)
1459{
0f238ff5
LG		 1460 struct pci_dev *pdev = to_pci_dev(dev->dev);
1461
1462 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1463 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1464 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1465 nvmeq->sq_cmds);
63223078
CH		 1466 if (nvmeq->sq_dma_addr) {
1467 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1468 return 0;
1469 }
0f238ff5 1470 }
8ffaadf7 1471
63223078
CH		 1472 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1473 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1474 if (!nvmeq->sq_cmds)
1475 return -ENOMEM;
8ffaadf7
JD		 1476 return 0;
1477}
1478
a6ff7262 1479static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1480{
147b27e4 1481 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1482
62314e40
KB		 1483 if (dev->ctrl.queue_count > qid)
1484 return 0;
b60503ba 1485
e75ec752 1486 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1487 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1488 if (!nvmeq->cqes)
1489 goto free_nvmeq;
b60503ba 1490
8ffaadf7 1491 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1492 goto free_cqdma;
1493
e75ec752 1494 nvmeq->q_dmadev = dev->dev;
091b6092 1495 nvmeq->dev = dev;
1ab0cd69 1496 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1497 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1498 nvmeq->cq_head = 0;
82123460 1499 nvmeq->cq_phase = 1;
b80d5ccc 1500 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1501 nvmeq->q_depth = depth;
c30341dc 1502 nvmeq->qid = qid;
758dd7fd 1503 nvmeq->cq_vector = -1;
d858e5f0 1504 dev->ctrl.queue_count++;
36a7e993 1505
147b27e4 1506 return 0;
b60503ba
MW		 1507
1508 free_cqdma:
e75ec752 1509 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1510 nvmeq->cq_dma_addr);
1511 free_nvmeq:
147b27e4 1512 return -ENOMEM;
b60503ba
MW		 1513}
1514
dca51e78 1515static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1516{
0ff199cb
CH		 1517 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1518 int nr = nvmeq->dev->ctrl.instance;
1519
1520 if (use_threaded_interrupts) {
1521 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1522 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1523 } else {
1524 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1525 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1526 }
3001082c
MW		 1527}
1528
22404274 1529static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1530{
22404274 1531 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1532
22404274 1533 nvmeq->sq_tail = 0;
04f3eafd 1534 nvmeq->last_sq_tail = 0;
22404274
KB		 1535 nvmeq->cq_head = 0;
1536 nvmeq->cq_phase = 1;
b80d5ccc 1537 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1538 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1539 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1540 dev->online_queues++;
3a7afd8e 1541 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1542}
1543
4b04cc6a 1544static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1545{
1546 struct nvme_dev *dev = nvmeq->dev;
1547 int result;
a8e3e0bb 1548 s16 vector;
3f85d50b 1549
d1ed6aa1
CH		 1550 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1551
22b55601
KB		 1552 /*
1553 * A queue's vector matches the queue identifier unless the controller
1554 * has only one vector available.
1555 */
4b04cc6a
JA		 1556 if (!polled)
1557 vector = dev->num_vecs == 1 ? 0 : qid;
1558 else
1559 vector = -1;
1560
a8e3e0bb 1561 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1562 if (result)
1563 return result;
b60503ba
MW		 1564
1565 result = adapter_alloc_sq(dev, qid, nvmeq);
1566 if (result < 0)
ded45505
KB		 1567 return result;
1568 else if (result)
b60503ba
MW		 1569 goto release_cq;
1570
a8e3e0bb 1571 nvmeq->cq_vector = vector;
161b8be2 1572 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1573
1574 if (vector != -1) {
1575 result = queue_request_irq(nvmeq);
1576 if (result < 0)
1577 goto release_sq;
1578 }
b60503ba 1579
4e224106 1580 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1581 return result;
b60503ba 1582
a8e3e0bb
JW		 1583release_sq:
1584 nvmeq->cq_vector = -1;
f25a2dfc 1585 dev->online_queues--;
b60503ba 1586 adapter_delete_sq(dev, qid);
a8e3e0bb 1587release_cq:
b60503ba 1588 adapter_delete_cq(dev, qid);
22404274 1589 return result;
b60503ba
MW		 1590}
1591
f363b089 1592static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1593 .queue_rq = nvme_queue_rq,
77f02a7a 1594 .complete = nvme_pci_complete_rq,
a4aea562 1595 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1596 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1597 .init_request = nvme_init_request,
a4aea562
MB		 1598 .timeout = nvme_timeout,
1599};
1600
f363b089 1601static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1602 .queue_rq = nvme_queue_rq,
1603 .complete = nvme_pci_complete_rq,
1604 .commit_rqs = nvme_commit_rqs,
1605 .init_hctx = nvme_init_hctx,
1606 .init_request = nvme_init_request,
1607 .map_queues = nvme_pci_map_queues,
1608 .timeout = nvme_timeout,
1609 .poll = nvme_poll,
dabcefab
JA		 1610};
1611
ea191d2f
KB		 1612static void nvme_dev_remove_admin(struct nvme_dev *dev)
1613{
1c63dc66 1614 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1615 /*
1616 * If the controller was reset during removal, it's possible
1617 * user requests may be waiting on a stopped queue. Start the
1618 * queue to flush these to completion.
1619 */
c81545f9 1620 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1621 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1622 blk_mq_free_tag_set(&dev->admin_tagset);
1623 }
1624}
1625
a4aea562
MB		 1626static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1627{
1c63dc66 1628 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1629 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1630 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1631
38dabe21 1632 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1633 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1634 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1635 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1636 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1637 dev->admin_tagset.driver_data = dev;
1638
1639 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1640 return -ENOMEM;
34b6c231 1641 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1642
1c63dc66
CH		 1643 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1644 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1645 blk_mq_free_tag_set(&dev->admin_tagset);
1646 return -ENOMEM;
1647 }
1c63dc66 1648 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1649 nvme_dev_remove_admin(dev);
1c63dc66 1650 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1651 return -ENODEV;
1652 }
0fb59cbc 1653 } else
c81545f9 1654 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1655
1656 return 0;
1657}
1658
97f6ef64
XY		 1659static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1660{
1661 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1662}
1663
1664static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1665{
1666 struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668 if (size <= dev->bar_mapped_size)
1669 return 0;
1670 if (size > pci_resource_len(pdev, 0))
1671 return -ENOMEM;
1672 if (dev->bar)
1673 iounmap(dev->bar);
1674 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1675 if (!dev->bar) {
1676 dev->bar_mapped_size = 0;
1677 return -ENOMEM;
1678 }
1679 dev->bar_mapped_size = size;
1680 dev->dbs = dev->bar + NVME_REG_DBS;
1681
1682 return 0;
1683}
1684
01ad0990 1685static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1686{
ba47e386 1687 int result;
b60503ba
MW		 1688 u32 aqa;
1689 struct nvme_queue *nvmeq;
1690
97f6ef64
XY		 1691 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1692 if (result < 0)
1693 return result;
1694
8ef2074d 1695 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1696 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1697
7a67cbea
CH		 1698 if (dev->subsystem &&
1699 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1700 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1701
20d0dfe6 1702 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1703 if (result < 0)
1704 return result;
b60503ba 1705
a6ff7262 1706 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1707 if (result)
1708 return result;
b60503ba 1709
147b27e4 1710 nvmeq = &dev->queues[0];
b60503ba
MW		 1711 aqa = nvmeq->q_depth - 1;
1712 aqa |= aqa << 16;
1713
7a67cbea
CH		 1714 writel(aqa, dev->bar + NVME_REG_AQA);
1715 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1716 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1717
20d0dfe6 1718 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1719 if (result)
d4875622 1720 return result;
a4aea562 1721
2b25d981 1722 nvmeq->cq_vector = 0;
161b8be2 1723 nvme_init_queue(nvmeq, 0);
dca51e78 1724 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1725 if (result) {
1726 nvmeq->cq_vector = -1;
d4875622 1727 return result;
758dd7fd 1728 }
025c557a 1729
4e224106 1730 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1731 return result;
1732}
1733
749941f2 1734static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1735{
4b04cc6a 1736 unsigned i, max, rw_queues;
749941f2 1737 int ret = 0;
42f61420 1738
d858e5f0 1739 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1740 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1741 ret = -ENOMEM;
42f61420 1742 break;
749941f2
CH		 1743 }
1744 }
42f61420 1745
d858e5f0 1746 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1747 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1748 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1749 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1750 } else {
1751 rw_queues = max;
1752 }
1753
949928c1 1754 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1755 bool polled = i > rw_queues;
1756
1757 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1758 if (ret)
42f61420 1759 break;
27e8166c 1760 }
749941f2
CH		 1761
1762 /*
1763 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1764 * than the desired amount of queues, and even a controller without
1765 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1766 * be useful to upgrade a buggy firmware for example.
1767 */
1768 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1769}
1770
202021c1
SB		 1771static ssize_t nvme_cmb_show(struct device *dev,
1772 struct device_attribute *attr,
1773 char *buf)
1774{
1775 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1776
c965809c 1777 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1778 ndev->cmbloc, ndev->cmbsz);
1779}
1780static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1781
88de4598 1782static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1783{
88de4598
CH		 1784 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1785
1786 return 1ULL << (12 + 4 * szu);
1787}
1788
1789static u32 nvme_cmb_size(struct nvme_dev *dev)
1790{
1791 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1792}
1793
f65efd6d 1794static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1795{
88de4598 1796 u64 size, offset;
8ffaadf7
JD		 1797 resource_size_t bar_size;
1798 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1799 int bar;
8ffaadf7 1800
9fe5c59f
KB		 1801 if (dev->cmb_size)
1802 return;
1803
7a67cbea 1804 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1805 if (!dev->cmbsz)
1806 return;
202021c1 1807 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1808
88de4598
CH		 1809 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1810 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1811 bar = NVME_CMB_BIR(dev->cmbloc);
1812 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1813
1814 if (offset > bar_size)
f65efd6d 1815 return;
8ffaadf7
JD		 1816
1817 /*
1818 * Controllers may support a CMB size larger than their BAR,
1819 * for example, due to being behind a bridge. Reduce the CMB to
1820 * the reported size of the BAR
1821 */
1822 if (size > bar_size - offset)
1823 size = bar_size - offset;
1824
0f238ff5
LG		 1825 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1826 dev_warn(dev->ctrl.device,
1827 "failed to register the CMB\n");
f65efd6d 1828 return;
0f238ff5
LG		 1829 }
1830
8ffaadf7 1831 dev->cmb_size = size;
0f238ff5
LG		 1832 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1833
1834 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1835 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1836 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1837
1838 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1839 &dev_attr_cmb.attr, NULL))
1840 dev_warn(dev->ctrl.device,
1841 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1842}
1843
1844static inline void nvme_release_cmb(struct nvme_dev *dev)
1845{
0f238ff5 1846 if (dev->cmb_size) {
1c78f773
MG		 1847 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1848 &dev_attr_cmb.attr, NULL);
0f238ff5 1849 dev->cmb_size = 0;
8ffaadf7
JD		 1850 }
1851}
1852
87ad72a5
CH		 1853static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1854{
4033f35d 1855 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1856 struct nvme_command c;
87ad72a5
CH		 1857 int ret;
1858
87ad72a5
CH		 1859 memset(&c, 0, sizeof(c));
1860 c.features.opcode = nvme_admin_set_features;
1861 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1862 c.features.dword11 = cpu_to_le32(bits);
1863 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1864 ilog2(dev->ctrl.page_size));
1865 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1866 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1867 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1868
1869 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1870 if (ret) {
1871 dev_warn(dev->ctrl.device,
1872 "failed to set host mem (err %d, flags %#x).\n",
1873 ret, bits);
1874 }
87ad72a5
CH		 1875 return ret;
1876}
1877
1878static void nvme_free_host_mem(struct nvme_dev *dev)
1879{
1880 int i;
1881
1882 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1883 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1884 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1885
1886 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1887 le64_to_cpu(desc->addr));
1888 }
1889
1890 kfree(dev->host_mem_desc_bufs);
1891 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1892 dma_free_coherent(dev->dev,
1893 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1894 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1895 dev->host_mem_descs = NULL;
7e5dd57e 1896 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1897}
1898
92dc6895
CH		 1899static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1900 u32 chunk_size)
9d713c2b 1901{
87ad72a5 1902 struct nvme_host_mem_buf_desc *descs;
92dc6895 1903 u32 max_entries, len;
4033f35d 1904 dma_addr_t descs_dma;
2ee0e4ed 1905 int i = 0;
87ad72a5 1906 void **bufs;
6fbcde66 1907 u64 size, tmp;
87ad72a5 1908
87ad72a5
CH		 1909 tmp = (preferred + chunk_size - 1);
1910 do_div(tmp, chunk_size);
1911 max_entries = tmp;
044a9df1
CH		 1912
1913 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1914 max_entries = dev->ctrl.hmmaxd;
1915
4033f35d
CH		 1916 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1917 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1918 if (!descs)
1919 goto out;
1920
1921 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1922 if (!bufs)
1923 goto out_free_descs;
1924
244a8fe4 1925 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1926 dma_addr_t dma_addr;
1927
50cdb7c6 1928 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1929 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1930 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1931 if (!bufs[i])
1932 break;
1933
1934 descs[i].addr = cpu_to_le64(dma_addr);
1935 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1936 i++;
1937 }
1938
92dc6895 1939 if (!size)
87ad72a5 1940 goto out_free_bufs;
87ad72a5 1941
87ad72a5
CH		 1942 dev->nr_host_mem_descs = i;
1943 dev->host_mem_size = size;
1944 dev->host_mem_descs = descs;
4033f35d 1945 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1946 dev->host_mem_desc_bufs = bufs;
1947 return 0;
1948
1949out_free_bufs:
1950 while (--i >= 0) {
1951 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1952
1953 dma_free_coherent(dev->dev, size, bufs[i],
1954 le64_to_cpu(descs[i].addr));
1955 }
1956
1957 kfree(bufs);
1958out_free_descs:
4033f35d
CH		 1959 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1960 descs_dma);
87ad72a5 1961out:
87ad72a5
CH		 1962 dev->host_mem_descs = NULL;
1963 return -ENOMEM;
1964}
1965
92dc6895
CH		 1966static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1967{
1968 u32 chunk_size;
1969
1970 /* start big and work our way down */
30f92d62 1971 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1972 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1973 chunk_size /= 2) {
1974 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1975 if (!min || dev->host_mem_size >= min)
1976 return 0;
1977 nvme_free_host_mem(dev);
1978 }
1979 }
1980
1981 return -ENOMEM;
1982}
1983
9620cfba 1984static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1985{
1986 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1987 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1988 u64 min = (u64)dev->ctrl.hmmin * 4096;
1989 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1990 int ret;
87ad72a5
CH		 1991
1992 preferred = min(preferred, max);
1993 if (min > max) {
1994 dev_warn(dev->ctrl.device,
1995 "min host memory (%lld MiB) above limit (%d MiB).\n",
1996 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1997 nvme_free_host_mem(dev);
9620cfba 1998 return 0;
87ad72a5
CH		 1999 }
2000
2001 /*
2002 * If we already have a buffer allocated check if we can reuse it.
2003 */
2004 if (dev->host_mem_descs) {
2005 if (dev->host_mem_size >= min)
2006 enable_bits |= NVME_HOST_MEM_RETURN;
2007 else
2008 nvme_free_host_mem(dev);
2009 }
2010
2011 if (!dev->host_mem_descs) {
92dc6895
CH		 2012 if (nvme_alloc_host_mem(dev, min, preferred)) {
2013 dev_warn(dev->ctrl.device,
2014 "failed to allocate host memory buffer.\n");
9620cfba 2015 return 0; /* controller must work without HMB */
92dc6895
CH		 2016 }
2017
2018 dev_info(dev->ctrl.device,
2019 "allocated %lld MiB host memory buffer.\n",
2020 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2021 }
2022
9620cfba
CH		 2023 ret = nvme_set_host_mem(dev, enable_bits);
2024 if (ret)
87ad72a5 2025 nvme_free_host_mem(dev);
9620cfba 2026 return ret;
9d713c2b
KB		 2027}
2028
6451fe73 2029static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
3b6592f7
JA		 2030{
2031 unsigned int this_w_queues = write_queues;
2032
2033 /*
2034 * Setup read/write queue split
2035 */
6451fe73 2036 if (irq_queues == 1) {
e20ba6e1
CH		 2037 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2038 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7
JA		 2039 return;
2040 }
2041
2042 /*
2043 * If 'write_queues' is set, ensure it leaves room for at least
2044 * one read queue
2045 */
6451fe73
JA		 2046 if (this_w_queues >= irq_queues)
2047 this_w_queues = irq_queues - 1;
3b6592f7
JA		 2048
2049 /*
2050 * If 'write_queues' is set to zero, reads and writes will share
2051 * a queue set.
2052 */
2053 if (!this_w_queues) {
6451fe73 2054 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues;
e20ba6e1 2055 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2056 } else {
e20ba6e1 2057 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
6451fe73 2058 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues;
3b6592f7
JA		 2059 }
2060}
2061
6451fe73 2062static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2063{
2064 struct pci_dev *pdev = to_pci_dev(dev->dev);
2065 int irq_sets[2];
2066 struct irq_affinity affd = {
2067 .pre_vectors = 1,
2068 .nr_sets = ARRAY_SIZE(irq_sets),
2069 .sets = irq_sets,
2070 };
30e06628 2071 int result = 0;
6451fe73
JA		 2072 unsigned int irq_queues, this_p_queues;
2073
2074 /*
2075 * Poll queues don't need interrupts, but we need at least one IO
2076 * queue left over for non-polled IO.
2077 */
2078 this_p_queues = poll_queues;
2079 if (this_p_queues >= nr_io_queues) {
2080 this_p_queues = nr_io_queues - 1;
2081 irq_queues = 1;
2082 } else {
2083 irq_queues = nr_io_queues - this_p_queues;
2084 }
2085 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7
JA		 2086
2087 /*
2088 * For irq sets, we have to ask for minvec == maxvec. This passes
2089 * any reduction back to us, so we can adjust our queue counts and
2090 * IRQ vector needs.
2091 */
2092 do {
6451fe73 2093 nvme_calc_io_queues(dev, irq_queues);
e20ba6e1
CH		 2094 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2095 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
3b6592f7
JA		 2096 if (!irq_sets[1])
2097 affd.nr_sets = 1;
2098
2099 /*
db29eb05
JA		 2100 * If we got a failure and we're down to asking for just
2101 * 1 + 1 queues, just ask for a single vector. We'll share
2102 * that between the single IO queue and the admin queue.
3b6592f7 2103 */
6451fe73
JA		 2104 if (result >= 0 && irq_queues > 1)
2105 irq_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7 2106
6451fe73
JA		 2107 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2108 irq_queues,
3b6592f7
JA		 2109 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2110
2111 /*
db29eb05
JA		 2112 * Need to reduce our vec counts. If we get ENOSPC, the
2113 * platform should support mulitple vecs, we just need
2114 * to decrease our ask. If we get EINVAL, the platform
2115 * likely does not. Back down to ask for just one vector.
3b6592f7
JA		 2116 */
2117 if (result == -ENOSPC) {
6451fe73
JA		 2118 irq_queues--;
2119 if (!irq_queues)
3b6592f7
JA		 2120 return result;
2121 continue;
db29eb05 2122 } else if (result == -EINVAL) {
6451fe73 2123 irq_queues = 1;
db29eb05 2124 continue;
3b6592f7
JA		 2125 } else if (result <= 0)
2126 return -EIO;
2127 break;
2128 } while (1);
2129
2130 return result;
2131}
2132
8d85fce7 2133static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2134{
147b27e4 2135 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2136 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2137 int result, nr_io_queues;
2138 unsigned long size;
b60503ba 2139
3b6592f7 2140 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2141 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2142 if (result < 0)
1b23484b 2143 return result;
9a0be7ab 2144
f5fa90dc 2145 if (nr_io_queues == 0)
a5229050 2146 return 0;
4e224106
CH		 2147
2148 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2149
0f238ff5 2150 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2151 result = nvme_cmb_qdepth(dev, nr_io_queues,
2152 sizeof(struct nvme_command));
2153 if (result > 0)
2154 dev->q_depth = result;
2155 else
0f238ff5 2156 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2157 }
2158
97f6ef64
XY		 2159 do {
2160 size = db_bar_size(dev, nr_io_queues);
2161 result = nvme_remap_bar(dev, size);
2162 if (!result)
2163 break;
2164 if (!--nr_io_queues)
2165 return -ENOMEM;
2166 } while (1);
2167 adminq->q_db = dev->dbs;
f1938f6e 2168
9d713c2b 2169 /* Deregister the admin queue's interrupt */
0ff199cb 2170 pci_free_irq(pdev, 0, adminq);
9d713c2b 2171
e32efbfc
JA		 2172 /*
2173 * If we enable msix early due to not intx, disable it again before
2174 * setting up the full range we need.
2175 */
dca51e78 2176 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2177
2178 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2179 if (result <= 0)
dca51e78 2180 return -EIO;
3b6592f7 2181
22b55601 2182 dev->num_vecs = result;
4b04cc6a 2183 result = max(result - 1, 1);
e20ba6e1 2184 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2185
e20ba6e1
CH		 2186 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2187 dev->io_queues[HCTX_TYPE_DEFAULT],
2188 dev->io_queues[HCTX_TYPE_READ],
2189 dev->io_queues[HCTX_TYPE_POLL]);
3b6592f7 2190
063a8096
MW		 2191 /*
2192 * Should investigate if there's a performance win from allocating
2193 * more queues than interrupt vectors; it might allow the submission
2194 * path to scale better, even if the receive path is limited by the
2195 * number of interrupts.
2196 */
063a8096 2197
dca51e78 2198 result = queue_request_irq(adminq);
758dd7fd
JD		 2199 if (result) {
2200 adminq->cq_vector = -1;
d4875622 2201 return result;
758dd7fd 2202 }
4e224106 2203 set_bit(NVMEQ_ENABLED, &adminq->flags);
749941f2 2204 return nvme_create_io_queues(dev);
b60503ba
MW		 2205}
2206
2a842aca 2207static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2208{
db3cbfff 2209 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2210
db3cbfff 2211 blk_mq_free_request(req);
d1ed6aa1 2212 complete(&nvmeq->delete_done);
a5768aa8
KB		 2213}
2214
2a842aca 2215static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2216{
db3cbfff 2217 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2218
d1ed6aa1
CH		 2219 if (error)
2220 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2221
2222 nvme_del_queue_end(req, error);
a5768aa8
KB		 2223}
2224
db3cbfff 2225static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2226{
db3cbfff
KB		 2227 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2228 struct request *req;
2229 struct nvme_command cmd;
bda4e0fb 2230
db3cbfff
KB		 2231 memset(&cmd, 0, sizeof(cmd));
2232 cmd.delete_queue.opcode = opcode;
2233 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2234
eb71f435 2235 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2236 if (IS_ERR(req))
2237 return PTR_ERR(req);
bda4e0fb 2238
db3cbfff
KB		 2239 req->timeout = ADMIN_TIMEOUT;
2240 req->end_io_data = nvmeq;
2241
d1ed6aa1 2242 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2243 blk_execute_rq_nowait(q, NULL, req, false,
2244 opcode == nvme_admin_delete_cq ?
2245 nvme_del_cq_end : nvme_del_queue_end);
2246 return 0;
bda4e0fb
KB		 2247}
2248
5271edd4 2249static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2250{
5271edd4 2251 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2252 unsigned long timeout;
a5768aa8 2253
db3cbfff 2254 retry:
5271edd4
CH		 2255 timeout = ADMIN_TIMEOUT;
2256 while (nr_queues > 0) {
2257 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2258 break;
2259 nr_queues--;
2260 sent++;
db3cbfff 2261 }
d1ed6aa1
CH		 2262 while (sent) {
2263 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2264
2265 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2266 timeout);
2267 if (timeout == 0)
2268 return false;
d1ed6aa1
CH		 2269
2270 /* handle any remaining CQEs */
2271 if (opcode == nvme_admin_delete_cq &&
2272 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2273 nvme_poll_irqdisable(nvmeq, -1);
2274
2275 sent--;
5271edd4
CH		 2276 if (nr_queues)
2277 goto retry;
2278 }
2279 return true;
a5768aa8
KB		 2280}
2281
422ef0c7 2282/*
2b1b7e78 2283 * return error value only when tagset allocation failed
422ef0c7 2284 */
8d85fce7 2285static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2286{
2b1b7e78
JW		 2287 int ret;
2288
5bae7f73 2289 if (!dev->ctrl.tagset) {
376f7ef8 2290 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2291 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2292 dev->tagset.nr_maps = 2; /* default + read */
2293 if (dev->io_queues[HCTX_TYPE_POLL])
2294 dev->tagset.nr_maps++;
e20ba6e1 2295 dev->tagset.nr_maps = HCTX_MAX_TYPES;
ffe7704d
KB		 2296 dev->tagset.timeout = NVME_IO_TIMEOUT;
2297 dev->tagset.numa_node = dev_to_node(dev->dev);
2298 dev->tagset.queue_depth =
a4aea562 2299 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2300 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2301 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2302 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2303 nvme_pci_cmd_size(dev, true));
2304 }
ffe7704d
KB		 2305 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2306 dev->tagset.driver_data = dev;
b60503ba 2307
2b1b7e78
JW		 2308 ret = blk_mq_alloc_tag_set(&dev->tagset);
2309 if (ret) {
2310 dev_warn(dev->ctrl.device,
2311 "IO queues tagset allocation failed %d\n", ret);
2312 return ret;
2313 }
5bae7f73 2314 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2315
2316 nvme_dbbuf_set(dev);
949928c1
KB		 2317 } else {
2318 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2319
2320 /* Free previously allocated queues that are no longer usable */
2321 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2322 }
949928c1 2323
e1e5e564 2324 return 0;
b60503ba
MW		 2325}
2326
b00a726a 2327static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2328{
b00a726a 2329 int result = -ENOMEM;
e75ec752 2330 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2331
2332 if (pci_enable_device_mem(pdev))
2333 return result;
2334
0877cb0d 2335 pci_set_master(pdev);
0877cb0d 2336
e75ec752
CH		 2337 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2338 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2339 goto disable;
0877cb0d 2340
7a67cbea 2341 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2342 result = -ENODEV;
b00a726a 2343 goto disable;
0e53d180 2344 }
e32efbfc
JA		 2345
2346 /*
a5229050
KB		 2347 * Some devices and/or platforms don't advertise or work with INTx
2348 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2349 * adjust this later.
e32efbfc 2350 */
dca51e78
CH		 2351 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2352 if (result < 0)
2353 return result;
e32efbfc 2354
20d0dfe6 2355 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2356
20d0dfe6 2357 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2358 io_queue_depth);
20d0dfe6 2359 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2360 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2361
2362 /*
2363 * Temporary fix for the Apple controller found in the MacBook8,1 and
2364 * some MacBook7,1 to avoid controller resets and data loss.
2365 */
2366 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2367 dev->q_depth = 2;
9bdcfb10
CH		 2368 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2369 "set queue depth=%u to work around controller resets\n",
1f390c1f 2370 dev->q_depth);
d554b5e1
MP		 2371 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2372 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2373 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2374 dev->q_depth = 64;
2375 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2376 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2377 }
2378
f65efd6d 2379 nvme_map_cmb(dev);
202021c1 2380
a0a3408e
KB		 2381 pci_enable_pcie_error_reporting(pdev);
2382 pci_save_state(pdev);
0877cb0d
KB		 2383 return 0;
2384
2385 disable:
0877cb0d
KB		 2386 pci_disable_device(pdev);
2387 return result;
2388}
2389
2390static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2391{
2392 if (dev->bar)
2393 iounmap(dev->bar);
a1f447b3 2394 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2395}
2396
2397static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2398{
e75ec752
CH		 2399 struct pci_dev *pdev = to_pci_dev(dev->dev);
2400
dca51e78 2401 pci_free_irq_vectors(pdev);
0877cb0d 2402
a0a3408e
KB		 2403 if (pci_is_enabled(pdev)) {
2404 pci_disable_pcie_error_reporting(pdev);
e75ec752 2405 pci_disable_device(pdev);
4d115420 2406 }
4d115420
KB		 2407}
2408
a5cdb68c 2409static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2410{
ee9aebb2 2411 int i;
302ad8cc
KB		 2412 bool dead = true;
2413 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2414
77bf25ea 2415 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2416 if (pci_is_enabled(pdev)) {
2417 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2418
ebef7368
KB		 2419 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2420 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2421 nvme_start_freeze(&dev->ctrl);
2422 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2423 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2424 }
c21377f8 2425
302ad8cc
KB		 2426 /*
2427 * Give the controller a chance to complete all entered requests if
2428 * doing a safe shutdown.
2429 */
87ad72a5
CH		 2430 if (!dead) {
2431 if (shutdown)
2432 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2433 }
2434
2435 nvme_stop_queues(&dev->ctrl);
87ad72a5 2436
64ee0ac0 2437 if (!dead && dev->ctrl.queue_count > 0) {
5271edd4
CH		 2438 if (nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2439 nvme_disable_io_queues(dev, nvme_admin_delete_cq);
a5cdb68c 2440 nvme_disable_admin_queue(dev, shutdown);
4d115420 2441 }
ee9aebb2
KB		 2442 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2443 nvme_suspend_queue(&dev->queues[i]);
2444
b00a726a 2445 nvme_pci_disable(dev);
07836e65 2446
e1958e65
ML		 2447 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2448 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2449
2450 /*
2451 * The driver will not be starting up queues again if shutting down so
2452 * must flush all entered requests to their failed completion to avoid
2453 * deadlocking blk-mq hot-cpu notifier.
2454 */
2455 if (shutdown)
2456 nvme_start_queues(&dev->ctrl);
77bf25ea 2457 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2458}
2459
091b6092
MW		 2460static int nvme_setup_prp_pools(struct nvme_dev *dev)
2461{
e75ec752 2462 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2463 PAGE_SIZE, PAGE_SIZE, 0);
2464 if (!dev->prp_page_pool)
2465 return -ENOMEM;
2466
99802a7a 2467 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2468 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2469 256, 256, 0);
2470 if (!dev->prp_small_pool) {
2471 dma_pool_destroy(dev->prp_page_pool);
2472 return -ENOMEM;
2473 }
091b6092
MW		 2474 return 0;
2475}
2476
2477static void nvme_release_prp_pools(struct nvme_dev *dev)
2478{
2479 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2480 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2481}
2482
1673f1f0 2483static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2484{
1673f1f0 2485 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2486
f9f38e33 2487 nvme_dbbuf_dma_free(dev);
e75ec752 2488 put_device(dev->dev);
4af0e21c
KB		 2489 if (dev->tagset.tags)
2490 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2491 if (dev->ctrl.admin_q)
2492 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2493 kfree(dev->queues);
e286bcfc 2494 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2495 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2496 kfree(dev);
2497}
2498
f58944e2
KB		 2499static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2500{
237045fc 2501 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2502
d22524a4 2503 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2504 nvme_dev_disable(dev, false);
9f9cafc1 2505 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2506 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2507 nvme_put_ctrl(&dev->ctrl);
2508}
2509
fd634f41 2510static void nvme_reset_work(struct work_struct *work)
5e82e952 2511{
d86c4d8e
CH		 2512 struct nvme_dev *dev =
2513 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2514 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2515 int result = -ENODEV;
2b1b7e78 2516 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2517
82b057ca 2518 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2519 goto out;
5e82e952 2520
fd634f41
CH		 2521 /*
2522 * If we're called to reset a live controller first shut it down before
2523 * moving on.
2524 */
b00a726a 2525 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2526 nvme_dev_disable(dev, false);
5e82e952 2527
ad70062c 2528 /*
ad6a0a52 2529 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2530 * initializing procedure here.
2531 */
ad6a0a52 2532 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2533 dev_warn(dev->ctrl.device,
ad6a0a52 2534 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2535 goto out;
2536 }
2537
b00a726a 2538 result = nvme_pci_enable(dev);
f0b50732 2539 if (result)
3cf519b5 2540 goto out;
f0b50732 2541
01ad0990 2542 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2543 if (result)
f58944e2 2544 goto out;
f0b50732 2545
0fb59cbc
KB		 2546 result = nvme_alloc_admin_tags(dev);
2547 if (result)
f58944e2 2548 goto out;
b9afca3e 2549
943e942e
JA		 2550 /*
2551 * Limit the max command size to prevent iod->sg allocations going
2552 * over a single page.
2553 */
2554 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2555 dev->ctrl.max_segments = NVME_MAX_SEGS;
2556
ce4541f4
CH		 2557 result = nvme_init_identify(&dev->ctrl);
2558 if (result)
f58944e2 2559 goto out;
ce4541f4 2560
e286bcfc
SB		 2561 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2562 if (!dev->ctrl.opal_dev)
2563 dev->ctrl.opal_dev =
2564 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2565 else if (was_suspend)
2566 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2567 } else {
2568 free_opal_dev(dev->ctrl.opal_dev);
2569 dev->ctrl.opal_dev = NULL;
4f1244c8 2570 }
a98e58e5 2571
f9f38e33
HK		 2572 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2573 result = nvme_dbbuf_dma_alloc(dev);
2574 if (result)
2575 dev_warn(dev->dev,
2576 "unable to allocate dma for dbbuf\n");
2577 }
2578
9620cfba
CH		 2579 if (dev->ctrl.hmpre) {
2580 result = nvme_setup_host_mem(dev);
2581 if (result < 0)
2582 goto out;
2583 }
87ad72a5 2584
f0b50732 2585 result = nvme_setup_io_queues(dev);
badc34d4 2586 if (result)
f58944e2 2587 goto out;
f0b50732 2588
2659e57b
CH		 2589 /*
2590 * Keep the controller around but remove all namespaces if we don't have
2591 * any working I/O queue.
2592 */
3cf519b5 2593 if (dev->online_queues < 2) {
1b3c47c1 2594 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2595 nvme_kill_queues(&dev->ctrl);
5bae7f73 2596 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2597 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2598 } else {
25646264 2599 nvme_start_queues(&dev->ctrl);
302ad8cc 2600 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2601 /* hit this only when allocate tagset fails */
2602 if (nvme_dev_add(dev))
2603 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2604 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2605 }
2606
2b1b7e78
JW		 2607 /*
2608 * If only admin queue live, keep it to do further investigation or
2609 * recovery.
2610 */
2611 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2612 dev_warn(dev->ctrl.device,
2613 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2614 goto out;
2615 }
92911a55 2616
d09f2b45 2617 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2618 return;
f0b50732 2619
3cf519b5 2620 out:
f58944e2 2621 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2622}
2623
5c8809e6 2624static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2625{
5c8809e6 2626 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2627 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2628
2629 if (pci_get_drvdata(pdev))
921920ab 2630 device_release_driver(&pdev->dev);
1673f1f0 2631 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2632}
2633
1c63dc66 2634static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2635{
1c63dc66 2636 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2637 return 0;
9ca97374
TH		 2638}
2639
5fd4ce1b 2640static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2641{
5fd4ce1b
CH		 2642 writel(val, to_nvme_dev(ctrl)->bar + off);
2643 return 0;
2644}
4cc06521 2645
7fd8930f
CH		 2646static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2647{
2648 *val = readq(to_nvme_dev(ctrl)->bar + off);
2649 return 0;
4cc06521
KB		 2650}
2651
97c12223
KB		 2652static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2653{
2654 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2655
2656 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2657}
2658
1c63dc66 2659static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2660 .name = "pcie",
e439bb12 2661 .module = THIS_MODULE,
e0596ab2
LG		 2662 .flags = NVME_F_METADATA_SUPPORTED |
2663 NVME_F_PCI_P2PDMA,
1c63dc66 2664 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2665 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2666 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2667 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2668 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2669 .get_address = nvme_pci_get_address,
1c63dc66 2670};
4cc06521 2671
b00a726a
KB		 2672static int nvme_dev_map(struct nvme_dev *dev)
2673{
b00a726a
KB		 2674 struct pci_dev *pdev = to_pci_dev(dev->dev);
2675
a1f447b3 2676 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2677 return -ENODEV;
2678
97f6ef64 2679 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2680 goto release;
2681
9fa196e7 2682 return 0;
b00a726a 2683 release:
9fa196e7
MG		 2684 pci_release_mem_regions(pdev);
2685 return -ENODEV;
b00a726a
KB		 2686}
2687
8427bbc2 2688static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2689{
2690 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2691 /*
2692 * Several Samsung devices seem to drop off the PCIe bus
2693 * randomly when APST is on and uses the deepest sleep state.
2694 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2695 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2696 * 950 PRO 256GB", but it seems to be restricted to two Dell
2697 * laptops.
2698 */
2699 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2700 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2701 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2702 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2703 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2704 /*
2705 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2706 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2707 * within few minutes after bootup on a Coffee Lake board -
2708 * ASUS PRIME Z370-A
8427bbc2
KHF		 2709 */
2710 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2711 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2712 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2713 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2714 }
2715
2716 return 0;
2717}
2718
18119775
KB		 2719static void nvme_async_probe(void *data, async_cookie_t cookie)
2720{
2721 struct nvme_dev *dev = data;
80f513b5 2722
18119775
KB		 2723 nvme_reset_ctrl_sync(&dev->ctrl);
2724 flush_work(&dev->ctrl.scan_work);
80f513b5 2725 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2726}
2727
8d85fce7 2728static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2729{
a4aea562 2730 int node, result = -ENOMEM;
b60503ba 2731 struct nvme_dev *dev;
ff5350a8 2732 unsigned long quirks = id->driver_data;
943e942e 2733 size_t alloc_size;
b60503ba 2734
a4aea562
MB		 2735 node = dev_to_node(&pdev->dev);
2736 if (node == NUMA_NO_NODE)
2fa84351 2737 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2738
2739 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2740 if (!dev)
2741 return -ENOMEM;
147b27e4 2742
3b6592f7
JA		 2743 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2744 GFP_KERNEL, node);
b60503ba
MW		 2745 if (!dev->queues)
2746 goto free;
2747
e75ec752 2748 dev->dev = get_device(&pdev->dev);
9a6b9458 2749 pci_set_drvdata(pdev, dev);
1c63dc66 2750
b00a726a
KB		 2751 result = nvme_dev_map(dev);
2752 if (result)
b00c9b7a 2753 goto put_pci;
b00a726a 2754
d86c4d8e 2755 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2756 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2757 mutex_init(&dev->shutdown_lock);
b60503ba 2758
091b6092
MW		 2759 result = nvme_setup_prp_pools(dev);
2760 if (result)
b00c9b7a 2761 goto unmap;
4cc06521 2762
8427bbc2 2763 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2764
943e942e
JA		 2765 /*
2766 * Double check that our mempool alloc size will cover the biggest
2767 * command we support.
2768 */
2769 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2770 NVME_MAX_SEGS, true);
2771 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2772
2773 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2774 mempool_kfree,
2775 (void *) alloc_size,
2776 GFP_KERNEL, node);
2777 if (!dev->iod_mempool) {
2778 result = -ENOMEM;
2779 goto release_pools;
2780 }
2781
b6e44b4c
KB		 2782 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2783 quirks);
2784 if (result)
2785 goto release_mempool;
2786
1b3c47c1
SG		 2787 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2788
80f513b5 2789 nvme_get_ctrl(&dev->ctrl);
18119775 2790 async_schedule(nvme_async_probe, dev);
4caff8fc 2791
b60503ba
MW		 2792 return 0;
2793
b6e44b4c
KB		 2794 release_mempool:
2795 mempool_destroy(dev->iod_mempool);
0877cb0d 2796 release_pools:
091b6092 2797 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2798 unmap:
2799 nvme_dev_unmap(dev);
a96d4f5c 2800 put_pci:
e75ec752 2801 put_device(dev->dev);
b60503ba
MW		 2802 free:
2803 kfree(dev->queues);
b60503ba
MW		 2804 kfree(dev);
2805 return result;
2806}
2807
775755ed 2808static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2809{
a6739479 2810 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2811 nvme_dev_disable(dev, false);
775755ed 2812}
f0d54a54 2813
775755ed
CH		 2814static void nvme_reset_done(struct pci_dev *pdev)
2815{
f263fbb8 2816 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2817 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2818}
2819
09ece142
KB		 2820static void nvme_shutdown(struct pci_dev *pdev)
2821{
2822 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2823 nvme_dev_disable(dev, true);
09ece142
KB		 2824}
2825
f58944e2
KB		 2826/*
2827 * The driver's remove may be called on a device in a partially initialized
2828 * state. This function must not have any dependencies on the device state in
2829 * order to proceed.
2830 */
8d85fce7 2831static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2832{
2833 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2834
bb8d261e 2835 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2836 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2837
6db28eda 2838 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2839 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2840 nvme_dev_disable(dev, true);
cb4bfda6 2841 nvme_dev_remove_admin(dev);
6db28eda 2842 }
0ff9d4e1 2843
d86c4d8e 2844 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2845 nvme_stop_ctrl(&dev->ctrl);
2846 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2847 nvme_dev_disable(dev, true);
9fe5c59f 2848 nvme_release_cmb(dev);
87ad72a5 2849 nvme_free_host_mem(dev);
a4aea562 2850 nvme_dev_remove_admin(dev);
a1a5ef99 2851 nvme_free_queues(dev, 0);
d09f2b45 2852 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2853 nvme_release_prp_pools(dev);
b00a726a 2854 nvme_dev_unmap(dev);
1673f1f0 2855 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2856}
2857
671a6018 2858#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2859static int nvme_suspend(struct device *dev)
2860{
2861 struct pci_dev *pdev = to_pci_dev(dev);
2862 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2863
a5cdb68c 2864 nvme_dev_disable(ndev, true);
cd638946
KB		 2865 return 0;
2866}
2867
2868static int nvme_resume(struct device *dev)
2869{
2870 struct pci_dev *pdev = to_pci_dev(dev);
2871 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2872
d86c4d8e 2873 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2874 return 0;
cd638946 2875}
671a6018 2876#endif
cd638946
KB		 2877
2878static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2879
a0a3408e
KB		 2880static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2881 pci_channel_state_t state)
2882{
2883 struct nvme_dev *dev = pci_get_drvdata(pdev);
2884
2885 /*
2886 * A frozen channel requires a reset. When detected, this method will
2887 * shutdown the controller to quiesce. The controller will be restarted
2888 * after the slot reset through driver's slot_reset callback.
2889 */
a0a3408e
KB		 2890 switch (state) {
2891 case pci_channel_io_normal:
2892 return PCI_ERS_RESULT_CAN_RECOVER;
2893 case pci_channel_io_frozen:
d011fb31
KB		 2894 dev_warn(dev->ctrl.device,
2895 "frozen state error detected, reset controller\n");
a5cdb68c 2896 nvme_dev_disable(dev, false);
a0a3408e
KB		 2897 return PCI_ERS_RESULT_NEED_RESET;
2898 case pci_channel_io_perm_failure:
d011fb31
KB		 2899 dev_warn(dev->ctrl.device,
2900 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2901 return PCI_ERS_RESULT_DISCONNECT;
2902 }
2903 return PCI_ERS_RESULT_NEED_RESET;
2904}
2905
2906static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2907{
2908 struct nvme_dev *dev = pci_get_drvdata(pdev);
2909
1b3c47c1 2910 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2911 pci_restore_state(pdev);
d86c4d8e 2912 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2913 return PCI_ERS_RESULT_RECOVERED;
2914}
2915
2916static void nvme_error_resume(struct pci_dev *pdev)
2917{
72cd4cc2
KB		 2918 struct nvme_dev *dev = pci_get_drvdata(pdev);
2919
2920 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2921}
2922
1d352035 2923static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2924 .error_detected = nvme_error_detected,
b60503ba
MW		 2925 .slot_reset = nvme_slot_reset,
2926 .resume = nvme_error_resume,
775755ed
CH		 2927 .reset_prepare = nvme_reset_prepare,
2928 .reset_done = nvme_reset_done,
b60503ba
MW		 2929};
2930
6eb0d698 2931static const struct pci_device_id nvme_id_table[] = {
106198ed 2932 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2933 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2934 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2935 { PCI_VDEVICE(INTEL, 0x0a53),
2936 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2937 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2938 { PCI_VDEVICE(INTEL, 0x0a54),
2939 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2940 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2941 { PCI_VDEVICE(INTEL, 0x0a55),
2942 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2943 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2944 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2945 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2946 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2947 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2948 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2949 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2950 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2951 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2952 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2953 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2954 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2955 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2956 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2957 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2958 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2959 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2960 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2961 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2962 .driver_data = NVME_QUIRK_LIGHTNVM, },
2963 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2964 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2965 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2966 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2967 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2968 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2969 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2970 { 0, }
2971};
2972MODULE_DEVICE_TABLE(pci, nvme_id_table);
2973
2974static struct pci_driver nvme_driver = {
2975 .name = "nvme",
2976 .id_table = nvme_id_table,
2977 .probe = nvme_probe,
8d85fce7 2978 .remove = nvme_remove,
09ece142 2979 .shutdown = nvme_shutdown,
cd638946
KB		 2980 .driver = {
2981 .pm = &nvme_dev_pm_ops,
2982 },
74d986ab 2983 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2984 .err_handler = &nvme_err_handler,
2985};
2986
2987static int __init nvme_init(void)
2988{
9a6327d2 2989 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2990}
2991
2992static void __exit nvme_exit(void)
2993{
2994 pci_unregister_driver(&nvme_driver);
03e0f3a6 2995 flush_workqueue(nvme_wq);
21bd78bc 2996 _nvme_check_size();
b60503ba
MW		 2997}
2998
2999MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3000MODULE_LICENSE("GPL");
c78b4713 3001MODULE_VERSION("1.0");
b60503ba
MW		 3002module_init(nvme_init);
3003module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)