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nvme/pci: Remove last_cq_head
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
3b6592f7 71static int write_queues;
483178f3 72module_param(write_queues, int, 0644);
3b6592f7
JA		 73MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
a232ea0e 77static int poll_queues;
483178f3 78module_param(poll_queues, int, 0644);
4b04cc6a
JA		 79MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
1c63dc66
CH		 81struct nvme_dev;
82struct nvme_queue;
b3fffdef 83
a5cdb68c 84static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 85static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 86
1c63dc66
CH		 87/*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90struct nvme_dev {
147b27e4 91 struct nvme_queue *queues;
1c63dc66
CH		 92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
1c63dc66
CH		 98 unsigned online_queues;
99 unsigned max_qid;
e20ba6e1 100 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 101 unsigned int num_vecs;
1c63dc66 102 int q_depth;
c1e0cc7e 103 int io_sqes;
1c63dc66 104 u32 db_stride;
1c63dc66 105 void __iomem *bar;
97f6ef64 106 unsigned long bar_mapped_size;
5c8809e6 107 struct work_struct remove_work;
77bf25ea 108 struct mutex shutdown_lock;
1c63dc66 109 bool subsystem;
1c63dc66 110 u64 cmb_size;
0f238ff5 111 bool cmb_use_sqes;
1c63dc66 112 u32 cmbsz;
202021c1 113 u32 cmbloc;
1c63dc66 114 struct nvme_ctrl ctrl;
d916b1be 115 u32 last_ps;
87ad72a5 116
943e942e
JA		 117 mempool_t *iod_mempool;
118
87ad72a5 119 /* shadow doorbell buffer support: */
f9f38e33
HK		 120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
4033f35d 128 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
4d115420 131};
1fa6aead 132
b27c1e68 133static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134{
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142}
143
f9f38e33
HK		 144static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145{
146 return qid * 2 * stride;
147}
148
149static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150{
151 return (qid * 2 + 1) * stride;
152}
153
1c63dc66
CH		 154static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155{
156 return container_of(ctrl, struct nvme_dev, ctrl);
157}
158
b60503ba
MW		 159/*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163struct nvme_queue {
091b6092 164 struct nvme_dev *dev;
1ab0cd69 165 spinlock_t sq_lock;
c1e0cc7e 166 void *sq_cmds;
3a7afd8e
CH		 167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 169 volatile struct nvme_completion *cqes;
42483228 170 struct blk_mq_tags **tags;
b60503ba
MW		 171 dma_addr_t sq_dma_addr;
172 dma_addr_t cq_dma_addr;
b60503ba
MW		 173 u32 __iomem *q_db;
174 u16 q_depth;
7c349dde 175 u16 cq_vector;
b60503ba 176 u16 sq_tail;
04f3eafd 177 u16 last_sq_tail;
b60503ba 178 u16 cq_head;
c30341dc 179 u16 qid;
e9539f47 180 u8 cq_phase;
c1e0cc7e 181 u8 sqes;
4e224106
CH		 182 unsigned long flags;
183#define NVMEQ_ENABLED 0
63223078 184#define NVMEQ_SQ_CMB 1
d1ed6aa1 185#define NVMEQ_DELETE_ERROR 2
7c349dde 186#define NVMEQ_POLLED 3
f9f38e33
HK		 187 u32 *dbbuf_sq_db;
188 u32 *dbbuf_cq_db;
189 u32 *dbbuf_sq_ei;
190 u32 *dbbuf_cq_ei;
d1ed6aa1 191 struct completion delete_done;
b60503ba
MW		 192};
193
71bd150c 194/*
9b048119
CH		 195 * The nvme_iod describes the data in an I/O.
196 *
197 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
198 * to the actual struct scatterlist.
71bd150c
CH		 199 */
200struct nvme_iod {
d49187e9 201 struct nvme_request req;
f4800d6d 202 struct nvme_queue *nvmeq;
a7a7cbe3 203 bool use_sgl;
f4800d6d 204 int aborted;
71bd150c 205 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 206 int nents; /* Used in scatterlist */
71bd150c 207 dma_addr_t first_dma;
dff824b2 208 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 209 dma_addr_t meta_dma;
f4800d6d 210 struct scatterlist *sg;
b60503ba
MW		 211};
212
3b6592f7
JA		 213static unsigned int max_io_queues(void)
214{
4b04cc6a 215 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 216}
217
218static unsigned int max_queue_count(void)
219{
220 /* IO queues + admin queue */
221 return 1 + max_io_queues();
222}
223
f9f38e33
HK		 224static inline unsigned int nvme_dbbuf_size(u32 stride)
225{
3b6592f7 226 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 227}
228
229static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
230{
231 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
232
233 if (dev->dbbuf_dbs)
234 return 0;
235
236 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
237 &dev->dbbuf_dbs_dma_addr,
238 GFP_KERNEL);
239 if (!dev->dbbuf_dbs)
240 return -ENOMEM;
241 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
242 &dev->dbbuf_eis_dma_addr,
243 GFP_KERNEL);
244 if (!dev->dbbuf_eis) {
245 dma_free_coherent(dev->dev, mem_size,
246 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
247 dev->dbbuf_dbs = NULL;
248 return -ENOMEM;
249 }
250
251 return 0;
252}
253
254static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
255{
256 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
257
258 if (dev->dbbuf_dbs) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
262 }
263 if (dev->dbbuf_eis) {
264 dma_free_coherent(dev->dev, mem_size,
265 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
266 dev->dbbuf_eis = NULL;
267 }
268}
269
270static void nvme_dbbuf_init(struct nvme_dev *dev,
271 struct nvme_queue *nvmeq, int qid)
272{
273 if (!dev->dbbuf_dbs || !qid)
274 return;
275
276 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
279 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
280}
281
282static void nvme_dbbuf_set(struct nvme_dev *dev)
283{
284 struct nvme_command c;
285
286 if (!dev->dbbuf_dbs)
287 return;
288
289 memset(&c, 0, sizeof(c));
290 c.dbbuf.opcode = nvme_admin_dbbuf;
291 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
292 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
293
294 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 295 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 296 /* Free memory and continue on */
297 nvme_dbbuf_dma_free(dev);
298 }
299}
300
301static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
302{
303 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
304}
305
306/* Update dbbuf and return true if an MMIO is required */
307static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
308 volatile u32 *dbbuf_ei)
309{
310 if (dbbuf_db) {
311 u16 old_value;
312
313 /*
314 * Ensure that the queue is written before updating
315 * the doorbell in memory
316 */
317 wmb();
318
319 old_value = *dbbuf_db;
320 *dbbuf_db = value;
321
f1ed3df2
MW		 322 /*
323 * Ensure that the doorbell is updated before reading the event
324 * index from memory. The controller needs to provide similar
325 * ordering to ensure the envent index is updated before reading
326 * the doorbell.
327 */
328 mb();
329
f9f38e33
HK		 330 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
331 return false;
332 }
333
334 return true;
b60503ba
MW		 335}
336
ac3dd5bd
JA		 337/*
338 * Will slightly overestimate the number of pages needed. This is OK
339 * as it only leads to a small amount of wasted memory for the lifetime of
340 * the I/O.
341 */
342static int nvme_npages(unsigned size, struct nvme_dev *dev)
343{
5fd4ce1b
CH		 344 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
345 dev->ctrl.page_size);
ac3dd5bd
JA		 346 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
347}
348
a7a7cbe3
CK		 349/*
350 * Calculates the number of pages needed for the SGL segments. For example a 4k
351 * page can accommodate 256 SGL descriptors.
352 */
353static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 354{
a7a7cbe3 355 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 356}
ac3dd5bd 357
a7a7cbe3
CK		 358static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
359 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 360{
a7a7cbe3
CK		 361 size_t alloc_size;
362
363 if (use_sgl)
364 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
365 else
366 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
367
368 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 369}
ac3dd5bd 370
a4aea562
MB		 371static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
372 unsigned int hctx_idx)
e85248e5 373{
a4aea562 374 struct nvme_dev *dev = data;
147b27e4 375 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 376
42483228
KB		 377 WARN_ON(hctx_idx != 0);
378 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
379 WARN_ON(nvmeq->tags);
380
a4aea562 381 hctx->driver_data = nvmeq;
42483228 382 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 383 return 0;
e85248e5
MW		 384}
385
4af0e21c
KB		 386static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
387{
388 struct nvme_queue *nvmeq = hctx->driver_data;
389
390 nvmeq->tags = NULL;
391}
392
a4aea562
MB		 393static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
394 unsigned int hctx_idx)
b60503ba 395{
a4aea562 396 struct nvme_dev *dev = data;
147b27e4 397 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 398
42483228
KB		 399 if (!nvmeq->tags)
400 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 401
42483228 402 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 403 hctx->driver_data = nvmeq;
404 return 0;
b60503ba
MW		 405}
406
d6296d39
CH		 407static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
408 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 409{
d6296d39 410 struct nvme_dev *dev = set->driver_data;
f4800d6d 411 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 412 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 413 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 414
415 BUG_ON(!nvmeq);
f4800d6d 416 iod->nvmeq = nvmeq;
59e29ce6
SG		 417
418 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 419 return 0;
420}
421
3b6592f7
JA		 422static int queue_irq_offset(struct nvme_dev *dev)
423{
424 /* if we have more than 1 vec, admin queue offsets us by 1 */
425 if (dev->num_vecs > 1)
426 return 1;
427
428 return 0;
429}
430
dca51e78
CH		 431static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
432{
433 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 434 int i, qoff, offset;
435
436 offset = queue_irq_offset(dev);
437 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
438 struct blk_mq_queue_map *map = &set->map[i];
439
440 map->nr_queues = dev->io_queues[i];
441 if (!map->nr_queues) {
e20ba6e1 442 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 443 continue;
3b6592f7
JA		 444 }
445
4b04cc6a
JA		 446 /*
447 * The poll queue(s) doesn't have an IRQ (and hence IRQ
448 * affinity), so use the regular blk-mq cpu mapping
449 */
3b6592f7 450 map->queue_offset = qoff;
cb9e0e50 451 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 452 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
453 else
454 blk_mq_map_queues(map);
3b6592f7
JA		 455 qoff += map->nr_queues;
456 offset += map->nr_queues;
457 }
458
459 return 0;
dca51e78
CH		 460}
461
04f3eafd
JA		 462/*
463 * Write sq tail if we are asked to, or if the next command would wrap.
464 */
465static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
466{
467 if (!write_sq) {
468 u16 next_tail = nvmeq->sq_tail + 1;
469
470 if (next_tail == nvmeq->q_depth)
471 next_tail = 0;
472 if (next_tail != nvmeq->last_sq_tail)
473 return;
474 }
475
476 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
477 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
478 writel(nvmeq->sq_tail, nvmeq->q_db);
479 nvmeq->last_sq_tail = nvmeq->sq_tail;
480}
481
b60503ba 482/**
90ea5ca4 483 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 484 * @nvmeq: The queue to use
485 * @cmd: The command to send
04f3eafd 486 * @write_sq: whether to write to the SQ doorbell
b60503ba 487 */
04f3eafd
JA		 488static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
489 bool write_sq)
b60503ba 490{
90ea5ca4 491 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 492 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
493 cmd, sizeof(*cmd));
90ea5ca4
CH		 494 if (++nvmeq->sq_tail == nvmeq->q_depth)
495 nvmeq->sq_tail = 0;
04f3eafd
JA		 496 nvme_write_sq_db(nvmeq, write_sq);
497 spin_unlock(&nvmeq->sq_lock);
498}
499
500static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
501{
502 struct nvme_queue *nvmeq = hctx->driver_data;
503
504 spin_lock(&nvmeq->sq_lock);
505 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
506 nvme_write_sq_db(nvmeq, true);
90ea5ca4 507 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 508}
509
a7a7cbe3 510static void **nvme_pci_iod_list(struct request *req)
b60503ba 511{
f4800d6d 512 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 513 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 514}
515
955b1b5a
MI		 516static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
517{
518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 519 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 520 unsigned int avg_seg_size;
521
20469a37
KB		 522 if (nseg == 0)
523 return false;
524
525 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 526
527 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
528 return false;
529 if (!iod->nvmeq->qid)
530 return false;
531 if (!sgl_threshold || avg_seg_size < sgl_threshold)
532 return false;
533 return true;
534}
535
7fe07d14 536static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 537{
f4800d6d 538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 539 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
540 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 541 int i;
eca18b23 542
dff824b2 543 if (iod->dma_len) {
f2fa006f
IR		 544 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
545 rq_dma_dir(req));
dff824b2 546 return;
7fe07d14
CH		 547 }
548
dff824b2
CH		 549 WARN_ON_ONCE(!iod->nents);
550
7f73eac3
LG		 551 if (is_pci_p2pdma_page(sg_page(iod->sg)))
552 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
553 rq_dma_dir(req));
554 else
dff824b2
CH		 555 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
556
557
eca18b23 558 if (iod->npages == 0)
a7a7cbe3
CK		 559 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
560 dma_addr);
561
eca18b23 562 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 563 void *addr = nvme_pci_iod_list(req)[i];
564
565 if (iod->use_sgl) {
566 struct nvme_sgl_desc *sg_list = addr;
567
568 next_dma_addr =
569 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
570 } else {
571 __le64 *prp_list = addr;
572
573 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
574 }
575
576 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
577 dma_addr = next_dma_addr;
eca18b23 578 }
ac3dd5bd 579
d43f1ccf 580 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 581}
582
d0877473
KB		 583static void nvme_print_sgl(struct scatterlist *sgl, int nents)
584{
585 int i;
586 struct scatterlist *sg;
587
588 for_each_sg(sgl, sg, nents, i) {
589 dma_addr_t phys = sg_phys(sg);
590 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
591 "dma_address:%pad dma_length:%d\n",
592 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
593 sg_dma_len(sg));
594 }
595}
596
a7a7cbe3
CK		 597static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
598 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 599{
f4800d6d 600 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 601 struct dma_pool *pool;
b131c61d 602 int length = blk_rq_payload_bytes(req);
eca18b23 603 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 604 int dma_len = sg_dma_len(sg);
605 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 606 u32 page_size = dev->ctrl.page_size;
f137e0f1 607 int offset = dma_addr & (page_size - 1);
e025344c 608 __le64 *prp_list;
a7a7cbe3 609 void **list = nvme_pci_iod_list(req);
e025344c 610 dma_addr_t prp_dma;
eca18b23 611 int nprps, i;
ff22b54f 612
1d090624 613 length -= (page_size - offset);
5228b328
JS		 614 if (length <= 0) {
615 iod->first_dma = 0;
a7a7cbe3 616 goto done;
5228b328 617 }
ff22b54f 618
1d090624 619 dma_len -= (page_size - offset);
ff22b54f 620 if (dma_len) {
1d090624 621 dma_addr += (page_size - offset);
ff22b54f
MW		 622 } else {
623 sg = sg_next(sg);
624 dma_addr = sg_dma_address(sg);
625 dma_len = sg_dma_len(sg);
626 }
627
1d090624 628 if (length <= page_size) {
edd10d33 629 iod->first_dma = dma_addr;
a7a7cbe3 630 goto done;
e025344c
SMM		 631 }
632
1d090624 633 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 634 if (nprps <= (256 / 8)) {
635 pool = dev->prp_small_pool;
eca18b23 636 iod->npages = 0;
99802a7a
MW		 637 } else {
638 pool = dev->prp_page_pool;
eca18b23 639 iod->npages = 1;
99802a7a
MW		 640 }
641
69d2b571 642 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 643 if (!prp_list) {
edd10d33 644 iod->first_dma = dma_addr;
eca18b23 645 iod->npages = -1;
86eea289 646 return BLK_STS_RESOURCE;
b77954cb 647 }
eca18b23
MW		 648 list[0] = prp_list;
649 iod->first_dma = prp_dma;
e025344c
SMM		 650 i = 0;
651 for (;;) {
1d090624 652 if (i == page_size >> 3) {
e025344c 653 __le64 *old_prp_list = prp_list;
69d2b571 654 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 655 if (!prp_list)
86eea289 656 return BLK_STS_RESOURCE;
eca18b23 657 list[iod->npages++] = prp_list;
7523d834
MW		 658 prp_list[0] = old_prp_list[i - 1];
659 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
660 i = 1;
e025344c
SMM		 661 }
662 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 663 dma_len -= page_size;
664 dma_addr += page_size;
665 length -= page_size;
e025344c
SMM		 666 if (length <= 0)
667 break;
668 if (dma_len > 0)
669 continue;
86eea289
KB		 670 if (unlikely(dma_len < 0))
671 goto bad_sgl;
e025344c
SMM		 672 sg = sg_next(sg);
673 dma_addr = sg_dma_address(sg);
674 dma_len = sg_dma_len(sg);
ff22b54f
MW		 675 }
676
a7a7cbe3
CK		 677done:
678 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
679 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
680
86eea289
KB		 681 return BLK_STS_OK;
682
683 bad_sgl:
d0877473
KB		 684 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
685 "Invalid SGL for payload:%d nents:%d\n",
686 blk_rq_payload_bytes(req), iod->nents);
86eea289 687 return BLK_STS_IOERR;
ff22b54f
MW		 688}
689
a7a7cbe3
CK		 690static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
691 struct scatterlist *sg)
692{
693 sge->addr = cpu_to_le64(sg_dma_address(sg));
694 sge->length = cpu_to_le32(sg_dma_len(sg));
695 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
696}
697
698static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
699 dma_addr_t dma_addr, int entries)
700{
701 sge->addr = cpu_to_le64(dma_addr);
702 if (entries < SGES_PER_PAGE) {
703 sge->length = cpu_to_le32(entries * sizeof(*sge));
704 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
705 } else {
706 sge->length = cpu_to_le32(PAGE_SIZE);
707 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
708 }
709}
710
711static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 712 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 713{
714 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 715 struct dma_pool *pool;
716 struct nvme_sgl_desc *sg_list;
717 struct scatterlist *sg = iod->sg;
a7a7cbe3 718 dma_addr_t sgl_dma;
b0f2853b 719 int i = 0;
a7a7cbe3 720
a7a7cbe3
CK		 721 /* setting the transfer type as SGL */
722 cmd->flags = NVME_CMD_SGL_METABUF;
723
b0f2853b 724 if (entries == 1) {
a7a7cbe3
CK		 725 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
726 return BLK_STS_OK;
727 }
728
729 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
730 pool = dev->prp_small_pool;
731 iod->npages = 0;
732 } else {
733 pool = dev->prp_page_pool;
734 iod->npages = 1;
735 }
736
737 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
738 if (!sg_list) {
739 iod->npages = -1;
740 return BLK_STS_RESOURCE;
741 }
742
743 nvme_pci_iod_list(req)[0] = sg_list;
744 iod->first_dma = sgl_dma;
745
746 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
747
748 do {
749 if (i == SGES_PER_PAGE) {
750 struct nvme_sgl_desc *old_sg_desc = sg_list;
751 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
752
753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
754 if (!sg_list)
755 return BLK_STS_RESOURCE;
756
757 i = 0;
758 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
759 sg_list[i++] = *link;
760 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
761 }
762
763 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 764 sg = sg_next(sg);
b0f2853b 765 } while (--entries > 0);
a7a7cbe3 766
a7a7cbe3
CK		 767 return BLK_STS_OK;
768}
769
dff824b2
CH		 770static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
771 struct request *req, struct nvme_rw_command *cmnd,
772 struct bio_vec *bv)
773{
774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4f40484
KH		 775 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
776 unsigned int first_prp_len = dev->ctrl.page_size - offset;
dff824b2
CH		 777
778 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
779 if (dma_mapping_error(dev->dev, iod->first_dma))
780 return BLK_STS_RESOURCE;
781 iod->dma_len = bv->bv_len;
782
783 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
784 if (bv->bv_len > first_prp_len)
785 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
786 return 0;
787}
788
29791057
CH		 789static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
790 struct request *req, struct nvme_rw_command *cmnd,
791 struct bio_vec *bv)
792{
793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
794
795 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
796 if (dma_mapping_error(dev->dev, iod->first_dma))
797 return BLK_STS_RESOURCE;
798 iod->dma_len = bv->bv_len;
799
049bf372 800 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 801 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
802 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
803 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
804 return 0;
805}
806
fc17b653 807static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 808 struct nvme_command *cmnd)
d29ec824 809{
f4800d6d 810 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 811 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 812 int nr_mapped;
d29ec824 813
dff824b2
CH		 814 if (blk_rq_nr_phys_segments(req) == 1) {
815 struct bio_vec bv = req_bvec(req);
816
817 if (!is_pci_p2pdma_page(bv.bv_page)) {
818 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
819 return nvme_setup_prp_simple(dev, req,
820 &cmnd->rw, &bv);
29791057
CH		 821
822 if (iod->nvmeq->qid &&
823 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
824 return nvme_setup_sgl_simple(dev, req,
825 &cmnd->rw, &bv);
dff824b2
CH		 826 }
827 }
828
829 iod->dma_len = 0;
d43f1ccf
CH		 830 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
831 if (!iod->sg)
832 return BLK_STS_RESOURCE;
f9d03f96 833 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 834 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 835 if (!iod->nents)
836 goto out;
d29ec824 837
e0596ab2 838 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 839 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
840 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 841 else
842 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 843 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 844 if (!nr_mapped)
ba1ca37e 845 goto out;
d29ec824 846
70479b71 847 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 848 if (iod->use_sgl)
b0f2853b 849 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 850 else
851 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 852out:
86eea289 853 if (ret != BLK_STS_OK)
4aedb705
CH		 854 nvme_unmap_data(dev, req);
855 return ret;
856}
3045c0d0 857
4aedb705
CH		 858static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
859 struct nvme_command *cmnd)
860{
861 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 862
4aedb705
CH		 863 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
864 rq_dma_dir(req), 0);
865 if (dma_mapping_error(dev->dev, iod->meta_dma))
866 return BLK_STS_IOERR;
867 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
868 return 0;
00df5cb4
MW		 869}
870
d29ec824
CH		 871/*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
fc17b653 874static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 875 const struct blk_mq_queue_data *bd)
edd10d33 876{
a4aea562
MB		 877 struct nvme_ns *ns = hctx->queue->queuedata;
878 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 879 struct nvme_dev *dev = nvmeq->dev;
a4aea562 880 struct request *req = bd->rq;
9b048119 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 882 struct nvme_command cmnd;
ebe6d874 883 blk_status_t ret;
e1e5e564 884
9b048119
CH		 885 iod->aborted = 0;
886 iod->npages = -1;
887 iod->nents = 0;
888
d1f06f4a
JA		 889 /*
890 * We should not need to do this, but we're still using this to
891 * ensure we can drain requests on a dying queue.
892 */
4e224106 893 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 894 return BLK_STS_IOERR;
895
f9d03f96 896 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 897 if (ret)
f4800d6d 898 return ret;
a4aea562 899
fc17b653 900 if (blk_rq_nr_phys_segments(req)) {
b131c61d 901 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 902 if (ret)
9b048119 903 goto out_free_cmd;
fc17b653 904 }
a4aea562 905
4aedb705
CH		 906 if (blk_integrity_rq(req)) {
907 ret = nvme_map_metadata(dev, req, &cmnd);
908 if (ret)
909 goto out_unmap_data;
910 }
911
aae239e1 912 blk_mq_start_request(req);
04f3eafd 913 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 914 return BLK_STS_OK;
4aedb705
CH		 915out_unmap_data:
916 nvme_unmap_data(dev, req);
f9d03f96
CH		 917out_free_cmd:
918 nvme_cleanup_cmd(req);
ba1ca37e 919 return ret;
b60503ba 920}
e1e5e564 921
77f02a7a 922static void nvme_pci_complete_rq(struct request *req)
eee417b0 923{
f4800d6d 924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 925 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 926
4aedb705
CH		 927 if (blk_integrity_rq(req))
928 dma_unmap_page(dev->dev, iod->meta_dma,
929 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 930 if (blk_rq_nr_phys_segments(req))
4aedb705 931 nvme_unmap_data(dev, req);
77f02a7a 932 nvme_complete_rq(req);
b60503ba
MW		 933}
934
d783e0bd 935/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 936static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 937{
750dde44
CH		 938 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
939 nvmeq->cq_phase;
d783e0bd
MR		 940}
941
eb281c82 942static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 943{
eb281c82 944 u16 head = nvmeq->cq_head;
adf68f21 945
397c699f
KB		 946 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
947 nvmeq->dbbuf_cq_ei))
948 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 949}
aae239e1 950
5cb525c8 951static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 952{
5cb525c8 953 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 954 struct request *req;
adf68f21 955
83a12fb7
SG		 956 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
957 dev_warn(nvmeq->dev->ctrl.device,
958 "invalid id %d completed on queue %d\n",
959 cqe->command_id, le16_to_cpu(cqe->sq_id));
960 return;
b60503ba
MW		 961 }
962
83a12fb7
SG		 963 /*
964 * AEN requests are special as they don't time out and can
965 * survive any kind of queue freeze and often don't respond to
966 * aborts. We don't even bother to allocate a struct request
967 * for them but rather special case them here.
968 */
58a8df67 969 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 970 nvme_complete_async_event(&nvmeq->dev->ctrl,
971 cqe->status, &cqe->result);
a0fa9647 972 return;
83a12fb7 973 }
b60503ba 974
83a12fb7 975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 977 nvme_end_request(req, cqe->status, cqe->result);
978}
b60503ba 979
5cb525c8 980static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 981{
5cb525c8
JA		 982 while (start != end) {
983 nvme_handle_cqe(nvmeq, start);
984 if (++start == nvmeq->q_depth)
985 start = 0;
986 }
987}
adf68f21 988
5cb525c8
JA		 989static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
990{
dcca1662 991 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 992 nvmeq->cq_head = 0;
993 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 994 } else {
995 nvmeq->cq_head++;
b60503ba 996 }
a0fa9647
JA		 997}
998
1052b8ac
JA		 999static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1000 u16 *end, unsigned int tag)
a0fa9647 1001{
1052b8ac 1002 int found = 0;
b60503ba 1003
5cb525c8 1004 *start = nvmeq->cq_head;
1052b8ac
JA		 1005 while (nvme_cqe_pending(nvmeq)) {
1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1007 found++;
5cb525c8 1008 nvme_update_cq_head(nvmeq);
920d13a8 1009 }
5cb525c8 1010 *end = nvmeq->cq_head;
eb281c82 1011
5cb525c8 1012 if (*start != *end)
920d13a8 1013 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1014 return found;
b60503ba
MW		 1015}
1016
1017static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1018{
58ffacb5 1019 struct nvme_queue *nvmeq = data;
68fa9dbe 1020 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1021 u16 start, end;
1022
3a7afd8e
CH		 1023 /*
1024 * The rmb/wmb pair ensures we see all updates from a previous run of
1025 * the irq handler, even if that was on another CPU.
1026 */
1027 rmb();
5cb525c8 1028 nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1029 wmb();
5cb525c8 1030
68fa9dbe
JA		 1031 if (start != end) {
1032 nvme_complete_cqes(nvmeq, start, end);
1033 return IRQ_HANDLED;
1034 }
1035
1036 return ret;
58ffacb5
MW		 1037}
1038
1039static irqreturn_t nvme_irq_check(int irq, void *data)
1040{
1041 struct nvme_queue *nvmeq = data;
750dde44 1042 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1043 return IRQ_WAKE_THREAD;
1044 return IRQ_NONE;
58ffacb5
MW		 1045}
1046
0b2a8a9f
CH		 1047/*
1048 * Poll for completions any queue, including those not dedicated to polling.
1049 * Can be called from any context.
1050 */
1051static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1052{
3a7afd8e 1053 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1054 u16 start, end;
1052b8ac 1055 int found;
a0fa9647 1056
3a7afd8e
CH		 1057 /*
1058 * For a poll queue we need to protect against the polling thread
1059 * using the CQ lock. For normal interrupt driven threads we have
1060 * to disable the interrupt to avoid racing with it.
1061 */
7c349dde 1062 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
3a7afd8e 1063 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1064 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1065 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1066 } else {
1067 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1068 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1069 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1070 }
442e19b7 1071
5cb525c8 1072 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1073 return found;
a0fa9647
JA		 1074}
1075
9743139c 1076static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1077{
1078 struct nvme_queue *nvmeq = hctx->driver_data;
1079 u16 start, end;
1080 bool found;
1081
1082 if (!nvme_cqe_pending(nvmeq))
1083 return 0;
1084
3a7afd8e 1085 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1086 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1087 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1088
1089 nvme_complete_cqes(nvmeq, start, end);
1090 return found;
1091}
1092
ad22c355 1093static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1094{
f866fc42 1095 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1096 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1097 struct nvme_command c;
b60503ba 1098
a4aea562
MB		 1099 memset(&c, 0, sizeof(c));
1100 c.common.opcode = nvme_admin_async_event;
ad22c355 1101 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1102 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1103}
1104
b60503ba 1105static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1106{
b60503ba
MW		 1107 struct nvme_command c;
1108
1109 memset(&c, 0, sizeof(c));
1110 c.delete_queue.opcode = opcode;
1111 c.delete_queue.qid = cpu_to_le16(id);
1112
1c63dc66 1113 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1114}
1115
b60503ba 1116static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1117 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1118{
b60503ba 1119 struct nvme_command c;
4b04cc6a
JA		 1120 int flags = NVME_QUEUE_PHYS_CONTIG;
1121
7c349dde 1122 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1123 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1124
d29ec824 1125 /*
16772ae6 1126 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1127 * is attached to the request.
1128 */
b60503ba
MW		 1129 memset(&c, 0, sizeof(c));
1130 c.create_cq.opcode = nvme_admin_create_cq;
1131 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1132 c.create_cq.cqid = cpu_to_le16(qid);
1133 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1134 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1135 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1136
1c63dc66 1137 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1138}
1139
1140static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1141 struct nvme_queue *nvmeq)
1142{
9abd68ef 1143 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1144 struct nvme_command c;
81c1cd98 1145 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1146
9abd68ef
JA		 1147 /*
1148 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1149 * set. Since URGENT priority is zeroes, it makes all queues
1150 * URGENT.
1151 */
1152 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1153 flags |= NVME_SQ_PRIO_MEDIUM;
1154
d29ec824 1155 /*
16772ae6 1156 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1157 * is attached to the request.
1158 */
b60503ba
MW		 1159 memset(&c, 0, sizeof(c));
1160 c.create_sq.opcode = nvme_admin_create_sq;
1161 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1162 c.create_sq.sqid = cpu_to_le16(qid);
1163 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_sq.sq_flags = cpu_to_le16(flags);
1165 c.create_sq.cqid = cpu_to_le16(qid);
1166
1c63dc66 1167 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1168}
1169
1170static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1171{
1172 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1173}
1174
1175static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1176{
1177 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1178}
1179
2a842aca 1180static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1181{
f4800d6d
CH		 1182 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1183 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1184
27fa9bc5
CH		 1185 dev_warn(nvmeq->dev->ctrl.device,
1186 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1187 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1188 blk_mq_free_request(req);
bc5fc7e4
MW		 1189}
1190
b2a0eb1a
KB		 1191static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1192{
1193
1194 /* If true, indicates loss of adapter communication, possibly by a
1195 * NVMe Subsystem reset.
1196 */
1197 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1198
ad70062c
JW		 1199 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1200 switch (dev->ctrl.state) {
1201 case NVME_CTRL_RESETTING:
ad6a0a52 1202 case NVME_CTRL_CONNECTING:
b2a0eb1a 1203 return false;
ad70062c
JW		 1204 default:
1205 break;
1206 }
b2a0eb1a
KB		 1207
1208 /* We shouldn't reset unless the controller is on fatal error state
1209 * _or_ if we lost the communication with it.
1210 */
1211 if (!(csts & NVME_CSTS_CFS) && !nssro)
1212 return false;
1213
b2a0eb1a
KB		 1214 return true;
1215}
1216
1217static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1218{
1219 /* Read a config register to help see what died. */
1220 u16 pci_status;
1221 int result;
1222
1223 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1224 &pci_status);
1225 if (result == PCIBIOS_SUCCESSFUL)
1226 dev_warn(dev->ctrl.device,
1227 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1228 csts, pci_status);
1229 else
1230 dev_warn(dev->ctrl.device,
1231 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1232 csts, result);
1233}
1234
31c7c7d2 1235static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1236{
f4800d6d
CH		 1237 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1238 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1239 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1240 struct request *abort_req;
a4aea562 1241 struct nvme_command cmd;
b2a0eb1a
KB		 1242 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1243
651438bb
WX		 1244 /* If PCI error recovery process is happening, we cannot reset or
1245 * the recovery mechanism will surely fail.
1246 */
1247 mb();
1248 if (pci_channel_offline(to_pci_dev(dev->dev)))
1249 return BLK_EH_RESET_TIMER;
1250
b2a0eb1a
KB		 1251 /*
1252 * Reset immediately if the controller is failed
1253 */
1254 if (nvme_should_reset(dev, csts)) {
1255 nvme_warn_reset(dev, csts);
1256 nvme_dev_disable(dev, false);
d86c4d8e 1257 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1258 return BLK_EH_DONE;
b2a0eb1a 1259 }
c30341dc 1260
7776db1c
KB		 1261 /*
1262 * Did we miss an interrupt?
1263 */
0b2a8a9f 1264 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1265 dev_warn(dev->ctrl.device,
1266 "I/O %d QID %d timeout, completion polled\n",
1267 req->tag, nvmeq->qid);
db8c48e4 1268 return BLK_EH_DONE;
7776db1c
KB		 1269 }
1270
31c7c7d2 1271 /*
fd634f41
CH		 1272 * Shutdown immediately if controller times out while starting. The
1273 * reset work will see the pci device disabled when it gets the forced
1274 * cancellation error. All outstanding requests are completed on
db8c48e4 1275 * shutdown, so we return BLK_EH_DONE.
fd634f41 1276 */
4244140d
KB		 1277 switch (dev->ctrl.state) {
1278 case NVME_CTRL_CONNECTING:
2036f726
KB		 1279 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1280 /* fall through */
1281 case NVME_CTRL_DELETING:
b9cac43c 1282 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1283 "I/O %d QID %d timeout, disable controller\n",
1284 req->tag, nvmeq->qid);
2036f726 1285 nvme_dev_disable(dev, true);
27fa9bc5 1286 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1287 return BLK_EH_DONE;
39a9dd81
KB		 1288 case NVME_CTRL_RESETTING:
1289 return BLK_EH_RESET_TIMER;
4244140d
KB		 1290 default:
1291 break;
c30341dc
KB		 1292 }
1293
fd634f41
CH		 1294 /*
1295 * Shutdown the controller immediately and schedule a reset if the
1296 * command was already aborted once before and still hasn't been
1297 * returned to the driver, or if this is the admin queue.
31c7c7d2 1298 */
f4800d6d 1299 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1300 dev_warn(dev->ctrl.device,
e1569a16
KB		 1301 "I/O %d QID %d timeout, reset controller\n",
1302 req->tag, nvmeq->qid);
a5cdb68c 1303 nvme_dev_disable(dev, false);
d86c4d8e 1304 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1305
27fa9bc5 1306 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1307 return BLK_EH_DONE;
c30341dc 1308 }
c30341dc 1309
e7a2a87d 1310 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1311 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1312 return BLK_EH_RESET_TIMER;
6bf25d16 1313 }
7bf7d778 1314 iod->aborted = 1;
a4aea562 1315
c30341dc
KB		 1316 memset(&cmd, 0, sizeof(cmd));
1317 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1318 cmd.abort.cid = req->tag;
c30341dc 1319 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1320
1b3c47c1
SG		 1321 dev_warn(nvmeq->dev->ctrl.device,
1322 "I/O %d QID %d timeout, aborting\n",
1323 req->tag, nvmeq->qid);
e7a2a87d
CH		 1324
1325 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1326 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1327 if (IS_ERR(abort_req)) {
1328 atomic_inc(&dev->ctrl.abort_limit);
1329 return BLK_EH_RESET_TIMER;
1330 }
1331
1332 abort_req->timeout = ADMIN_TIMEOUT;
1333 abort_req->end_io_data = NULL;
1334 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1335
31c7c7d2
CH		 1336 /*
1337 * The aborted req will be completed on receiving the abort req.
1338 * We enable the timer again. If hit twice, it'll cause a device reset,
1339 * as the device then is in a faulty state.
1340 */
1341 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1342}
1343
a4aea562
MB		 1344static void nvme_free_queue(struct nvme_queue *nvmeq)
1345{
8a1d09a6 1346 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1347 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1348 if (!nvmeq->sq_cmds)
1349 return;
0f238ff5 1350
63223078 1351 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1352 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1353 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1354 } else {
8a1d09a6 1355 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1356 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1357 }
9e866774
MW		 1358}
1359
a1a5ef99 1360static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1361{
1362 int i;
1363
d858e5f0 1364 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1365 dev->ctrl.queue_count--;
147b27e4 1366 nvme_free_queue(&dev->queues[i]);
121c7ad4 1367 }
22404274
KB		 1368}
1369
4d115420
KB		 1370/**
1371 * nvme_suspend_queue - put queue into suspended state
40581d1a 1372 * @nvmeq: queue to suspend
4d115420
KB		 1373 */
1374static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1375{
4e224106 1376 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1377 return 1;
a09115b2 1378
4e224106 1379 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1380 mb();
a09115b2 1381
4e224106 1382 nvmeq->dev->online_queues--;
1c63dc66 1383 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1384 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1385 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1386 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1387 return 0;
1388}
b60503ba 1389
8fae268b
KB		 1390static void nvme_suspend_io_queues(struct nvme_dev *dev)
1391{
1392 int i;
1393
1394 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1395 nvme_suspend_queue(&dev->queues[i]);
1396}
1397
a5cdb68c 1398static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1399{
147b27e4 1400 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1401
a5cdb68c
KB		 1402 if (shutdown)
1403 nvme_shutdown_ctrl(&dev->ctrl);
1404 else
b5b05048 1405 nvme_disable_ctrl(&dev->ctrl);
07836e65 1406
0b2a8a9f 1407 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1408}
1409
8ffaadf7
JD		 1410static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1411 int entry_size)
1412{
1413 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1414 unsigned q_size_aligned = roundup(q_depth * entry_size,
1415 dev->ctrl.page_size);
8ffaadf7
JD		 1416
1417 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1418 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1419 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1420 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1421
1422 /*
1423 * Ensure the reduced q_depth is above some threshold where it
1424 * would be better to map queues in system memory with the
1425 * original depth
1426 */
1427 if (q_depth < 64)
1428 return -ENOMEM;
1429 }
1430
1431 return q_depth;
1432}
1433
1434static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1435 int qid)
8ffaadf7 1436{
0f238ff5
LG		 1437 struct pci_dev *pdev = to_pci_dev(dev->dev);
1438
1439 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1440 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1441 if (nvmeq->sq_cmds) {
1442 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1443 nvmeq->sq_cmds);
1444 if (nvmeq->sq_dma_addr) {
1445 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1446 return 0;
1447 }
1448
8a1d09a6 1449 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1450 }
0f238ff5 1451 }
8ffaadf7 1452
8a1d09a6 1453 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1454 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1455 if (!nvmeq->sq_cmds)
1456 return -ENOMEM;
8ffaadf7
JD		 1457 return 0;
1458}
1459
a6ff7262 1460static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1461{
147b27e4 1462 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1463
62314e40
KB		 1464 if (dev->ctrl.queue_count > qid)
1465 return 0;
b60503ba 1466
c1e0cc7e 1467 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1468 nvmeq->q_depth = depth;
1469 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1470 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1471 if (!nvmeq->cqes)
1472 goto free_nvmeq;
b60503ba 1473
8a1d09a6 1474 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1475 goto free_cqdma;
1476
091b6092 1477 nvmeq->dev = dev;
1ab0cd69 1478 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1479 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1480 nvmeq->cq_head = 0;
82123460 1481 nvmeq->cq_phase = 1;
b80d5ccc 1482 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1483 nvmeq->qid = qid;
d858e5f0 1484 dev->ctrl.queue_count++;
36a7e993 1485
147b27e4 1486 return 0;
b60503ba
MW		 1487
1488 free_cqdma:
8a1d09a6
BH		 1489 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1490 nvmeq->cq_dma_addr);
b60503ba 1491 free_nvmeq:
147b27e4 1492 return -ENOMEM;
b60503ba
MW		 1493}
1494
dca51e78 1495static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1496{
0ff199cb
CH		 1497 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1498 int nr = nvmeq->dev->ctrl.instance;
1499
1500 if (use_threaded_interrupts) {
1501 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1502 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1503 } else {
1504 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1505 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1506 }
3001082c
MW		 1507}
1508
22404274 1509static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1510{
22404274 1511 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1512
22404274 1513 nvmeq->sq_tail = 0;
04f3eafd 1514 nvmeq->last_sq_tail = 0;
22404274
KB		 1515 nvmeq->cq_head = 0;
1516 nvmeq->cq_phase = 1;
b80d5ccc 1517 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1518 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1519 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1520 dev->online_queues++;
3a7afd8e 1521 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1522}
1523
4b04cc6a 1524static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1525{
1526 struct nvme_dev *dev = nvmeq->dev;
1527 int result;
7c349dde 1528 u16 vector = 0;
3f85d50b 1529
d1ed6aa1
CH		 1530 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1531
22b55601
KB		 1532 /*
1533 * A queue's vector matches the queue identifier unless the controller
1534 * has only one vector available.
1535 */
4b04cc6a
JA		 1536 if (!polled)
1537 vector = dev->num_vecs == 1 ? 0 : qid;
1538 else
7c349dde 1539 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1540
a8e3e0bb 1541 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1542 if (result)
1543 return result;
b60503ba
MW		 1544
1545 result = adapter_alloc_sq(dev, qid, nvmeq);
1546 if (result < 0)
ded45505 1547 return result;
c80b36cd 1548 if (result)
b60503ba
MW		 1549 goto release_cq;
1550
a8e3e0bb 1551 nvmeq->cq_vector = vector;
161b8be2 1552 nvme_init_queue(nvmeq, qid);
4b04cc6a 1553
7c349dde 1554 if (!polled) {
4b04cc6a
JA		 1555 result = queue_request_irq(nvmeq);
1556 if (result < 0)
1557 goto release_sq;
1558 }
b60503ba 1559
4e224106 1560 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1561 return result;
b60503ba 1562
a8e3e0bb 1563release_sq:
f25a2dfc 1564 dev->online_queues--;
b60503ba 1565 adapter_delete_sq(dev, qid);
a8e3e0bb 1566release_cq:
b60503ba 1567 adapter_delete_cq(dev, qid);
22404274 1568 return result;
b60503ba
MW		 1569}
1570
f363b089 1571static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1572 .queue_rq = nvme_queue_rq,
77f02a7a 1573 .complete = nvme_pci_complete_rq,
a4aea562 1574 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1575 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1576 .init_request = nvme_init_request,
a4aea562
MB		 1577 .timeout = nvme_timeout,
1578};
1579
f363b089 1580static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1581 .queue_rq = nvme_queue_rq,
1582 .complete = nvme_pci_complete_rq,
1583 .commit_rqs = nvme_commit_rqs,
1584 .init_hctx = nvme_init_hctx,
1585 .init_request = nvme_init_request,
1586 .map_queues = nvme_pci_map_queues,
1587 .timeout = nvme_timeout,
1588 .poll = nvme_poll,
dabcefab
JA		 1589};
1590
ea191d2f
KB		 1591static void nvme_dev_remove_admin(struct nvme_dev *dev)
1592{
1c63dc66 1593 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1594 /*
1595 * If the controller was reset during removal, it's possible
1596 * user requests may be waiting on a stopped queue. Start the
1597 * queue to flush these to completion.
1598 */
c81545f9 1599 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1600 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1601 blk_mq_free_tag_set(&dev->admin_tagset);
1602 }
1603}
1604
a4aea562
MB		 1605static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1606{
1c63dc66 1607 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1608 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1609 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1610
38dabe21 1611 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1612 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1613 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1614 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1615 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1616 dev->admin_tagset.driver_data = dev;
1617
1618 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1619 return -ENOMEM;
34b6c231 1620 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1621
1c63dc66
CH		 1622 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1623 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1624 blk_mq_free_tag_set(&dev->admin_tagset);
1625 return -ENOMEM;
1626 }
1c63dc66 1627 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1628 nvme_dev_remove_admin(dev);
1c63dc66 1629 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1630 return -ENODEV;
1631 }
0fb59cbc 1632 } else
c81545f9 1633 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1634
1635 return 0;
1636}
1637
97f6ef64
XY		 1638static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1639{
1640 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1641}
1642
1643static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1644{
1645 struct pci_dev *pdev = to_pci_dev(dev->dev);
1646
1647 if (size <= dev->bar_mapped_size)
1648 return 0;
1649 if (size > pci_resource_len(pdev, 0))
1650 return -ENOMEM;
1651 if (dev->bar)
1652 iounmap(dev->bar);
1653 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1654 if (!dev->bar) {
1655 dev->bar_mapped_size = 0;
1656 return -ENOMEM;
1657 }
1658 dev->bar_mapped_size = size;
1659 dev->dbs = dev->bar + NVME_REG_DBS;
1660
1661 return 0;
1662}
1663
01ad0990 1664static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1665{
ba47e386 1666 int result;
b60503ba
MW		 1667 u32 aqa;
1668 struct nvme_queue *nvmeq;
1669
97f6ef64
XY		 1670 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1671 if (result < 0)
1672 return result;
1673
8ef2074d 1674 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1675 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1676
7a67cbea
CH		 1677 if (dev->subsystem &&
1678 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1679 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1680
b5b05048 1681 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1682 if (result < 0)
1683 return result;
b60503ba 1684
a6ff7262 1685 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1686 if (result)
1687 return result;
b60503ba 1688
147b27e4 1689 nvmeq = &dev->queues[0];
b60503ba
MW		 1690 aqa = nvmeq->q_depth - 1;
1691 aqa |= aqa << 16;
1692
7a67cbea
CH		 1693 writel(aqa, dev->bar + NVME_REG_AQA);
1694 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1695 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1696
c0f2f45b 1697 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1698 if (result)
d4875622 1699 return result;
a4aea562 1700
2b25d981 1701 nvmeq->cq_vector = 0;
161b8be2 1702 nvme_init_queue(nvmeq, 0);
dca51e78 1703 result = queue_request_irq(nvmeq);
758dd7fd 1704 if (result) {
7c349dde 1705 dev->online_queues--;
d4875622 1706 return result;
758dd7fd 1707 }
025c557a 1708
4e224106 1709 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1710 return result;
1711}
1712
749941f2 1713static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1714{
4b04cc6a 1715 unsigned i, max, rw_queues;
749941f2 1716 int ret = 0;
42f61420 1717
d858e5f0 1718 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1719 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1720 ret = -ENOMEM;
42f61420 1721 break;
749941f2
CH		 1722 }
1723 }
42f61420 1724
d858e5f0 1725 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1726 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1727 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1728 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1729 } else {
1730 rw_queues = max;
1731 }
1732
949928c1 1733 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1734 bool polled = i > rw_queues;
1735
1736 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1737 if (ret)
42f61420 1738 break;
27e8166c 1739 }
749941f2
CH		 1740
1741 /*
1742 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1743 * than the desired amount of queues, and even a controller without
1744 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1745 * be useful to upgrade a buggy firmware for example.
1746 */
1747 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1748}
1749
202021c1
SB		 1750static ssize_t nvme_cmb_show(struct device *dev,
1751 struct device_attribute *attr,
1752 char *buf)
1753{
1754 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1755
c965809c 1756 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1757 ndev->cmbloc, ndev->cmbsz);
1758}
1759static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1760
88de4598 1761static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1762{
88de4598
CH		 1763 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1764
1765 return 1ULL << (12 + 4 * szu);
1766}
1767
1768static u32 nvme_cmb_size(struct nvme_dev *dev)
1769{
1770 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1771}
1772
f65efd6d 1773static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1774{
88de4598 1775 u64 size, offset;
8ffaadf7
JD		 1776 resource_size_t bar_size;
1777 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1778 int bar;
8ffaadf7 1779
9fe5c59f
KB		 1780 if (dev->cmb_size)
1781 return;
1782
7a67cbea 1783 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1784 if (!dev->cmbsz)
1785 return;
202021c1 1786 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1787
88de4598
CH		 1788 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1789 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1790 bar = NVME_CMB_BIR(dev->cmbloc);
1791 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1792
1793 if (offset > bar_size)
f65efd6d 1794 return;
8ffaadf7
JD		 1795
1796 /*
1797 * Controllers may support a CMB size larger than their BAR,
1798 * for example, due to being behind a bridge. Reduce the CMB to
1799 * the reported size of the BAR
1800 */
1801 if (size > bar_size - offset)
1802 size = bar_size - offset;
1803
0f238ff5
LG		 1804 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1805 dev_warn(dev->ctrl.device,
1806 "failed to register the CMB\n");
f65efd6d 1807 return;
0f238ff5
LG		 1808 }
1809
8ffaadf7 1810 dev->cmb_size = size;
0f238ff5
LG		 1811 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1812
1813 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1814 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1815 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1816
1817 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1818 &dev_attr_cmb.attr, NULL))
1819 dev_warn(dev->ctrl.device,
1820 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1821}
1822
1823static inline void nvme_release_cmb(struct nvme_dev *dev)
1824{
0f238ff5 1825 if (dev->cmb_size) {
1c78f773
MG		 1826 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1827 &dev_attr_cmb.attr, NULL);
0f238ff5 1828 dev->cmb_size = 0;
8ffaadf7
JD		 1829 }
1830}
1831
87ad72a5
CH		 1832static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1833{
4033f35d 1834 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1835 struct nvme_command c;
87ad72a5
CH		 1836 int ret;
1837
87ad72a5
CH		 1838 memset(&c, 0, sizeof(c));
1839 c.features.opcode = nvme_admin_set_features;
1840 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1841 c.features.dword11 = cpu_to_le32(bits);
1842 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1843 ilog2(dev->ctrl.page_size));
1844 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1845 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1846 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1847
1848 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1849 if (ret) {
1850 dev_warn(dev->ctrl.device,
1851 "failed to set host mem (err %d, flags %#x).\n",
1852 ret, bits);
1853 }
87ad72a5
CH		 1854 return ret;
1855}
1856
1857static void nvme_free_host_mem(struct nvme_dev *dev)
1858{
1859 int i;
1860
1861 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1862 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1863 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1864
cc667f6d
LD		 1865 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1866 le64_to_cpu(desc->addr),
1867 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1868 }
1869
1870 kfree(dev->host_mem_desc_bufs);
1871 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1872 dma_free_coherent(dev->dev,
1873 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1874 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1875 dev->host_mem_descs = NULL;
7e5dd57e 1876 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1877}
1878
92dc6895
CH		 1879static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1880 u32 chunk_size)
9d713c2b 1881{
87ad72a5 1882 struct nvme_host_mem_buf_desc *descs;
92dc6895 1883 u32 max_entries, len;
4033f35d 1884 dma_addr_t descs_dma;
2ee0e4ed 1885 int i = 0;
87ad72a5 1886 void **bufs;
6fbcde66 1887 u64 size, tmp;
87ad72a5 1888
87ad72a5
CH		 1889 tmp = (preferred + chunk_size - 1);
1890 do_div(tmp, chunk_size);
1891 max_entries = tmp;
044a9df1
CH		 1892
1893 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1894 max_entries = dev->ctrl.hmmaxd;
1895
750afb08
LC		 1896 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1897 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1898 if (!descs)
1899 goto out;
1900
1901 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1902 if (!bufs)
1903 goto out_free_descs;
1904
244a8fe4 1905 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1906 dma_addr_t dma_addr;
1907
50cdb7c6 1908 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1909 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1910 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1911 if (!bufs[i])
1912 break;
1913
1914 descs[i].addr = cpu_to_le64(dma_addr);
1915 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1916 i++;
1917 }
1918
92dc6895 1919 if (!size)
87ad72a5 1920 goto out_free_bufs;
87ad72a5 1921
87ad72a5
CH		 1922 dev->nr_host_mem_descs = i;
1923 dev->host_mem_size = size;
1924 dev->host_mem_descs = descs;
4033f35d 1925 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1926 dev->host_mem_desc_bufs = bufs;
1927 return 0;
1928
1929out_free_bufs:
1930 while (--i >= 0) {
1931 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1932
cc667f6d
LD		 1933 dma_free_attrs(dev->dev, size, bufs[i],
1934 le64_to_cpu(descs[i].addr),
1935 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1936 }
1937
1938 kfree(bufs);
1939out_free_descs:
4033f35d
CH		 1940 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1941 descs_dma);
87ad72a5 1942out:
87ad72a5
CH		 1943 dev->host_mem_descs = NULL;
1944 return -ENOMEM;
1945}
1946
92dc6895
CH		 1947static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1948{
1949 u32 chunk_size;
1950
1951 /* start big and work our way down */
30f92d62 1952 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1953 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1954 chunk_size /= 2) {
1955 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1956 if (!min || dev->host_mem_size >= min)
1957 return 0;
1958 nvme_free_host_mem(dev);
1959 }
1960 }
1961
1962 return -ENOMEM;
1963}
1964
9620cfba 1965static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1966{
1967 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1968 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1969 u64 min = (u64)dev->ctrl.hmmin * 4096;
1970 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1971 int ret;
87ad72a5
CH		 1972
1973 preferred = min(preferred, max);
1974 if (min > max) {
1975 dev_warn(dev->ctrl.device,
1976 "min host memory (%lld MiB) above limit (%d MiB).\n",
1977 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1978 nvme_free_host_mem(dev);
9620cfba 1979 return 0;
87ad72a5
CH		 1980 }
1981
1982 /*
1983 * If we already have a buffer allocated check if we can reuse it.
1984 */
1985 if (dev->host_mem_descs) {
1986 if (dev->host_mem_size >= min)
1987 enable_bits |= NVME_HOST_MEM_RETURN;
1988 else
1989 nvme_free_host_mem(dev);
1990 }
1991
1992 if (!dev->host_mem_descs) {
92dc6895
CH		 1993 if (nvme_alloc_host_mem(dev, min, preferred)) {
1994 dev_warn(dev->ctrl.device,
1995 "failed to allocate host memory buffer.\n");
9620cfba 1996 return 0; /* controller must work without HMB */
92dc6895
CH		 1997 }
1998
1999 dev_info(dev->ctrl.device,
2000 "allocated %lld MiB host memory buffer.\n",
2001 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2002 }
2003
9620cfba
CH		 2004 ret = nvme_set_host_mem(dev, enable_bits);
2005 if (ret)
87ad72a5 2006 nvme_free_host_mem(dev);
9620cfba 2007 return ret;
9d713c2b
KB		 2008}
2009
612b7286
ML		 2010/*
2011 * nirqs is the number of interrupts available for write and read
2012 * queues. The core already reserved an interrupt for the admin queue.
2013 */
2014static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2015{
612b7286
ML		 2016 struct nvme_dev *dev = affd->priv;
2017 unsigned int nr_read_queues;
3b6592f7
JA		 2018
2019 /*
612b7286
ML		 2020 * If there is no interupt available for queues, ensure that
2021 * the default queue is set to 1. The affinity set size is
2022 * also set to one, but the irq core ignores it for this case.
2023 *
2024 * If only one interrupt is available or 'write_queue' == 0, combine
2025 * write and read queues.
2026 *
2027 * If 'write_queues' > 0, ensure it leaves room for at least one read
2028 * queue.
3b6592f7 2029 */
612b7286
ML		 2030 if (!nrirqs) {
2031 nrirqs = 1;
2032 nr_read_queues = 0;
2033 } else if (nrirqs == 1 || !write_queues) {
2034 nr_read_queues = 0;
2035 } else if (write_queues >= nrirqs) {
2036 nr_read_queues = 1;
3b6592f7 2037 } else {
612b7286 2038 nr_read_queues = nrirqs - write_queues;
3b6592f7 2039 }
612b7286
ML		 2040
2041 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2042 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2043 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2044 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2045 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2046}
2047
6451fe73 2048static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2049{
2050 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2051 struct irq_affinity affd = {
9cfef55b 2052 .pre_vectors = 1,
612b7286
ML		 2053 .calc_sets = nvme_calc_irq_sets,
2054 .priv = dev,
3b6592f7 2055 };
6451fe73 2056 unsigned int irq_queues, this_p_queues;
dad77d63 2057 unsigned int nr_cpus = num_possible_cpus();
6451fe73
JA		 2058
2059 /*
2060 * Poll queues don't need interrupts, but we need at least one IO
2061 * queue left over for non-polled IO.
2062 */
2063 this_p_queues = poll_queues;
2064 if (this_p_queues >= nr_io_queues) {
2065 this_p_queues = nr_io_queues - 1;
2066 irq_queues = 1;
2067 } else {
dad77d63
MI		 2068 if (nr_cpus < nr_io_queues - this_p_queues)
2069 irq_queues = nr_cpus + 1;
2070 else
2071 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2072 }
2073 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2074
612b7286
ML		 2075 /* Initialize for the single interrupt case */
2076 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2077 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2078
66341331
BH		 2079 /*
2080 * Some Apple controllers require all queues to use the
2081 * first vector.
2082 */
2083 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2084 irq_queues = 1;
2085
612b7286
ML		 2086 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2087 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2088}
2089
8fae268b
KB		 2090static void nvme_disable_io_queues(struct nvme_dev *dev)
2091{
2092 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2093 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2094}
2095
8d85fce7 2096static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2097{
147b27e4 2098 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2099 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2100 int result, nr_io_queues;
2101 unsigned long size;
b60503ba 2102
3b6592f7 2103 nr_io_queues = max_io_queues();
d38e9f04
BH		 2104
2105 /*
2106 * If tags are shared with admin queue (Apple bug), then
2107 * make sure we only use one IO queue.
2108 */
2109 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2110 nr_io_queues = 1;
2111
9a0be7ab
CH		 2112 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2113 if (result < 0)
1b23484b 2114 return result;
9a0be7ab 2115
f5fa90dc 2116 if (nr_io_queues == 0)
a5229050 2117 return 0;
4e224106
CH		 2118
2119 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2120
0f238ff5 2121 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2122 result = nvme_cmb_qdepth(dev, nr_io_queues,
2123 sizeof(struct nvme_command));
2124 if (result > 0)
2125 dev->q_depth = result;
2126 else
0f238ff5 2127 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2128 }
2129
97f6ef64
XY		 2130 do {
2131 size = db_bar_size(dev, nr_io_queues);
2132 result = nvme_remap_bar(dev, size);
2133 if (!result)
2134 break;
2135 if (!--nr_io_queues)
2136 return -ENOMEM;
2137 } while (1);
2138 adminq->q_db = dev->dbs;
f1938f6e 2139
8fae268b 2140 retry:
9d713c2b 2141 /* Deregister the admin queue's interrupt */
0ff199cb 2142 pci_free_irq(pdev, 0, adminq);
9d713c2b 2143
e32efbfc
JA		 2144 /*
2145 * If we enable msix early due to not intx, disable it again before
2146 * setting up the full range we need.
2147 */
dca51e78 2148 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2149
2150 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2151 if (result <= 0)
dca51e78 2152 return -EIO;
3b6592f7 2153
22b55601 2154 dev->num_vecs = result;
4b04cc6a 2155 result = max(result - 1, 1);
e20ba6e1 2156 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2157
063a8096
MW		 2158 /*
2159 * Should investigate if there's a performance win from allocating
2160 * more queues than interrupt vectors; it might allow the submission
2161 * path to scale better, even if the receive path is limited by the
2162 * number of interrupts.
2163 */
dca51e78 2164 result = queue_request_irq(adminq);
7c349dde 2165 if (result)
d4875622 2166 return result;
4e224106 2167 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2168
2169 result = nvme_create_io_queues(dev);
2170 if (result || dev->online_queues < 2)
2171 return result;
2172
2173 if (dev->online_queues - 1 < dev->max_qid) {
2174 nr_io_queues = dev->online_queues - 1;
2175 nvme_disable_io_queues(dev);
2176 nvme_suspend_io_queues(dev);
2177 goto retry;
2178 }
2179 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2180 dev->io_queues[HCTX_TYPE_DEFAULT],
2181 dev->io_queues[HCTX_TYPE_READ],
2182 dev->io_queues[HCTX_TYPE_POLL]);
2183 return 0;
b60503ba
MW		 2184}
2185
2a842aca 2186static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2187{
db3cbfff 2188 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2189
db3cbfff 2190 blk_mq_free_request(req);
d1ed6aa1 2191 complete(&nvmeq->delete_done);
a5768aa8
KB		 2192}
2193
2a842aca 2194static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2195{
db3cbfff 2196 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2197
d1ed6aa1
CH		 2198 if (error)
2199 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2200
2201 nvme_del_queue_end(req, error);
a5768aa8
KB		 2202}
2203
db3cbfff 2204static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2205{
db3cbfff
KB		 2206 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2207 struct request *req;
2208 struct nvme_command cmd;
bda4e0fb 2209
db3cbfff
KB		 2210 memset(&cmd, 0, sizeof(cmd));
2211 cmd.delete_queue.opcode = opcode;
2212 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2213
eb71f435 2214 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2215 if (IS_ERR(req))
2216 return PTR_ERR(req);
bda4e0fb 2217
db3cbfff
KB		 2218 req->timeout = ADMIN_TIMEOUT;
2219 req->end_io_data = nvmeq;
2220
d1ed6aa1 2221 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2222 blk_execute_rq_nowait(q, NULL, req, false,
2223 opcode == nvme_admin_delete_cq ?
2224 nvme_del_cq_end : nvme_del_queue_end);
2225 return 0;
bda4e0fb
KB		 2226}
2227
8fae268b 2228static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2229{
5271edd4 2230 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2231 unsigned long timeout;
a5768aa8 2232
db3cbfff 2233 retry:
5271edd4
CH		 2234 timeout = ADMIN_TIMEOUT;
2235 while (nr_queues > 0) {
2236 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2237 break;
2238 nr_queues--;
2239 sent++;
db3cbfff 2240 }
d1ed6aa1
CH		 2241 while (sent) {
2242 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2243
2244 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2245 timeout);
2246 if (timeout == 0)
2247 return false;
d1ed6aa1
CH		 2248
2249 /* handle any remaining CQEs */
2250 if (opcode == nvme_admin_delete_cq &&
2251 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2252 nvme_poll_irqdisable(nvmeq, -1);
2253
2254 sent--;
5271edd4
CH		 2255 if (nr_queues)
2256 goto retry;
2257 }
2258 return true;
a5768aa8
KB		 2259}
2260
5d02a5c1 2261static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2262{
2b1b7e78
JW		 2263 int ret;
2264
5bae7f73 2265 if (!dev->ctrl.tagset) {
376f7ef8 2266 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2267 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2268 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2269 if (dev->io_queues[HCTX_TYPE_POLL])
2270 dev->tagset.nr_maps++;
ffe7704d
KB		 2271 dev->tagset.timeout = NVME_IO_TIMEOUT;
2272 dev->tagset.numa_node = dev_to_node(dev->dev);
2273 dev->tagset.queue_depth =
a4aea562 2274 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2275 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2276 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2277 dev->tagset.driver_data = dev;
b60503ba 2278
d38e9f04
BH		 2279 /*
2280 * Some Apple controllers requires tags to be unique
2281 * across admin and IO queue, so reserve the first 32
2282 * tags of the IO queue.
2283 */
2284 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2285 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2286
2b1b7e78
JW		 2287 ret = blk_mq_alloc_tag_set(&dev->tagset);
2288 if (ret) {
2289 dev_warn(dev->ctrl.device,
2290 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2291 return;
2b1b7e78 2292 }
5bae7f73 2293 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2294 } else {
2295 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2296
2297 /* Free previously allocated queues that are no longer usable */
2298 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2299 }
949928c1 2300
e8fd41bb 2301 nvme_dbbuf_set(dev);
b60503ba
MW		 2302}
2303
b00a726a 2304static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2305{
b00a726a 2306 int result = -ENOMEM;
e75ec752 2307 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2308
2309 if (pci_enable_device_mem(pdev))
2310 return result;
2311
0877cb0d 2312 pci_set_master(pdev);
0877cb0d 2313
4fe06923 2314 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2315 goto disable;
0877cb0d 2316
7a67cbea 2317 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2318 result = -ENODEV;
b00a726a 2319 goto disable;
0e53d180 2320 }
e32efbfc
JA		 2321
2322 /*
a5229050
KB		 2323 * Some devices and/or platforms don't advertise or work with INTx
2324 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2325 * adjust this later.
e32efbfc 2326 */
dca51e78
CH		 2327 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2328 if (result < 0)
2329 return result;
e32efbfc 2330
20d0dfe6 2331 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2332
20d0dfe6 2333 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2334 io_queue_depth);
aa22c8e6 2335 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2336 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2337 dev->dbs = dev->bar + 4096;
1f390c1f 2338
66341331
BH		 2339 /*
2340 * Some Apple controllers require a non-standard SQE size.
2341 * Interestingly they also seem to ignore the CC:IOSQES register
2342 * so we don't bother updating it here.
2343 */
2344 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2345 dev->io_sqes = 7;
2346 else
2347 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2348
2349 /*
2350 * Temporary fix for the Apple controller found in the MacBook8,1 and
2351 * some MacBook7,1 to avoid controller resets and data loss.
2352 */
2353 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2354 dev->q_depth = 2;
9bdcfb10
CH		 2355 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2356 "set queue depth=%u to work around controller resets\n",
1f390c1f 2357 dev->q_depth);
d554b5e1
MP		 2358 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2359 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2360 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2361 dev->q_depth = 64;
2362 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2363 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2364 }
2365
d38e9f04
BH		 2366 /*
2367 * Controllers with the shared tags quirk need the IO queue to be
2368 * big enough so that we get 32 tags for the admin queue
2369 */
2370 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2371 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2372 dev->q_depth = NVME_AQ_DEPTH + 2;
2373 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2374 dev->q_depth);
2375 }
2376
2377
f65efd6d 2378 nvme_map_cmb(dev);
202021c1 2379
a0a3408e
KB		 2380 pci_enable_pcie_error_reporting(pdev);
2381 pci_save_state(pdev);
0877cb0d
KB		 2382 return 0;
2383
2384 disable:
0877cb0d
KB		 2385 pci_disable_device(pdev);
2386 return result;
2387}
2388
2389static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2390{
2391 if (dev->bar)
2392 iounmap(dev->bar);
a1f447b3 2393 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2394}
2395
2396static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2397{
e75ec752
CH		 2398 struct pci_dev *pdev = to_pci_dev(dev->dev);
2399
dca51e78 2400 pci_free_irq_vectors(pdev);
0877cb0d 2401
a0a3408e
KB		 2402 if (pci_is_enabled(pdev)) {
2403 pci_disable_pcie_error_reporting(pdev);
e75ec752 2404 pci_disable_device(pdev);
4d115420 2405 }
4d115420
KB		 2406}
2407
a5cdb68c 2408static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2409{
e43269e6 2410 bool dead = true, freeze = false;
302ad8cc 2411 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2412
77bf25ea 2413 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2414 if (pci_is_enabled(pdev)) {
2415 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2416
ebef7368 2417 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2418 dev->ctrl.state == NVME_CTRL_RESETTING) {
2419 freeze = true;
302ad8cc 2420 nvme_start_freeze(&dev->ctrl);
e43269e6 2421 }
302ad8cc
KB		 2422 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2423 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2424 }
c21377f8 2425
302ad8cc
KB		 2426 /*
2427 * Give the controller a chance to complete all entered requests if
2428 * doing a safe shutdown.
2429 */
e43269e6
KB		 2430 if (!dead && shutdown && freeze)
2431 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2432
2433 nvme_stop_queues(&dev->ctrl);
87ad72a5 2434
64ee0ac0 2435 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2436 nvme_disable_io_queues(dev);
a5cdb68c 2437 nvme_disable_admin_queue(dev, shutdown);
4d115420 2438 }
8fae268b
KB		 2439 nvme_suspend_io_queues(dev);
2440 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2441 nvme_pci_disable(dev);
07836e65 2442
e1958e65
ML		 2443 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2444 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2445 blk_mq_tagset_wait_completed_request(&dev->tagset);
2446 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2447
2448 /*
2449 * The driver will not be starting up queues again if shutting down so
2450 * must flush all entered requests to their failed completion to avoid
2451 * deadlocking blk-mq hot-cpu notifier.
2452 */
c8e9e9b7 2453 if (shutdown) {
302ad8cc 2454 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2455 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2456 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2457 }
77bf25ea 2458 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2459}
2460
c1ac9a4b
KB		 2461static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2462{
2463 if (!nvme_wait_reset(&dev->ctrl))
2464 return -EBUSY;
2465 nvme_dev_disable(dev, shutdown);
2466 return 0;
2467}
2468
091b6092
MW		 2469static int nvme_setup_prp_pools(struct nvme_dev *dev)
2470{
e75ec752 2471 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2472 PAGE_SIZE, PAGE_SIZE, 0);
2473 if (!dev->prp_page_pool)
2474 return -ENOMEM;
2475
99802a7a 2476 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2477 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2478 256, 256, 0);
2479 if (!dev->prp_small_pool) {
2480 dma_pool_destroy(dev->prp_page_pool);
2481 return -ENOMEM;
2482 }
091b6092
MW		 2483 return 0;
2484}
2485
2486static void nvme_release_prp_pools(struct nvme_dev *dev)
2487{
2488 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2489 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2490}
2491
770597ec
KB		 2492static void nvme_free_tagset(struct nvme_dev *dev)
2493{
2494 if (dev->tagset.tags)
2495 blk_mq_free_tag_set(&dev->tagset);
2496 dev->ctrl.tagset = NULL;
2497}
2498
1673f1f0 2499static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2500{
1673f1f0 2501 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2502
f9f38e33 2503 nvme_dbbuf_dma_free(dev);
e75ec752 2504 put_device(dev->dev);
770597ec 2505 nvme_free_tagset(dev);
1c63dc66
CH		 2506 if (dev->ctrl.admin_q)
2507 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2508 kfree(dev->queues);
e286bcfc 2509 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2510 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2511 kfree(dev);
2512}
2513
7c1ce408 2514static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2515{
c1ac9a4b
KB		 2516 /*
2517 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2518 * may be holding this pci_dev's device lock.
2519 */
2520 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2521 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2522 nvme_dev_disable(dev, false);
9f9cafc1 2523 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2524 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2525 nvme_put_ctrl(&dev->ctrl);
2526}
2527
fd634f41 2528static void nvme_reset_work(struct work_struct *work)
5e82e952 2529{
d86c4d8e
CH		 2530 struct nvme_dev *dev =
2531 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2532 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2533 int result;
5e82e952 2534
e71afda4
CK		 2535 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2536 result = -ENODEV;
fd634f41 2537 goto out;
e71afda4 2538 }
5e82e952 2539
fd634f41
CH		 2540 /*
2541 * If we're called to reset a live controller first shut it down before
2542 * moving on.
2543 */
b00a726a 2544 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2545 nvme_dev_disable(dev, false);
d6135c3a 2546 nvme_sync_queues(&dev->ctrl);
5e82e952 2547
5c959d73 2548 mutex_lock(&dev->shutdown_lock);
b00a726a 2549 result = nvme_pci_enable(dev);
f0b50732 2550 if (result)
4726bcf3 2551 goto out_unlock;
f0b50732 2552
01ad0990 2553 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2554 if (result)
4726bcf3 2555 goto out_unlock;
f0b50732 2556
0fb59cbc
KB		 2557 result = nvme_alloc_admin_tags(dev);
2558 if (result)
4726bcf3 2559 goto out_unlock;
b9afca3e 2560
943e942e
JA		 2561 /*
2562 * Limit the max command size to prevent iod->sg allocations going
2563 * over a single page.
2564 */
7637de31
CH		 2565 dev->ctrl.max_hw_sectors = min_t(u32,
2566 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2567 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2568
2569 /*
2570 * Don't limit the IOMMU merged segment size.
2571 */
2572 dma_set_max_seg_size(dev->dev, 0xffffffff);
2573
5c959d73
KB		 2574 mutex_unlock(&dev->shutdown_lock);
2575
2576 /*
2577 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2578 * initializing procedure here.
2579 */
2580 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2581 dev_warn(dev->ctrl.device,
2582 "failed to mark controller CONNECTING\n");
cee6c269 2583 result = -EBUSY;
5c959d73
KB		 2584 goto out;
2585 }
943e942e 2586
ce4541f4
CH		 2587 result = nvme_init_identify(&dev->ctrl);
2588 if (result)
f58944e2 2589 goto out;
ce4541f4 2590
e286bcfc
SB		 2591 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2592 if (!dev->ctrl.opal_dev)
2593 dev->ctrl.opal_dev =
2594 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2595 else if (was_suspend)
2596 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2597 } else {
2598 free_opal_dev(dev->ctrl.opal_dev);
2599 dev->ctrl.opal_dev = NULL;
4f1244c8 2600 }
a98e58e5 2601
f9f38e33
HK		 2602 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2603 result = nvme_dbbuf_dma_alloc(dev);
2604 if (result)
2605 dev_warn(dev->dev,
2606 "unable to allocate dma for dbbuf\n");
2607 }
2608
9620cfba
CH		 2609 if (dev->ctrl.hmpre) {
2610 result = nvme_setup_host_mem(dev);
2611 if (result < 0)
2612 goto out;
2613 }
87ad72a5 2614
f0b50732 2615 result = nvme_setup_io_queues(dev);
badc34d4 2616 if (result)
f58944e2 2617 goto out;
f0b50732 2618
2659e57b
CH		 2619 /*
2620 * Keep the controller around but remove all namespaces if we don't have
2621 * any working I/O queue.
2622 */
3cf519b5 2623 if (dev->online_queues < 2) {
1b3c47c1 2624 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2625 nvme_kill_queues(&dev->ctrl);
5bae7f73 2626 nvme_remove_namespaces(&dev->ctrl);
770597ec 2627 nvme_free_tagset(dev);
3cf519b5 2628 } else {
25646264 2629 nvme_start_queues(&dev->ctrl);
302ad8cc 2630 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2631 nvme_dev_add(dev);
302ad8cc 2632 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2633 }
2634
2b1b7e78
JW		 2635 /*
2636 * If only admin queue live, keep it to do further investigation or
2637 * recovery.
2638 */
5d02a5c1 2639 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2640 dev_warn(dev->ctrl.device,
5d02a5c1 2641 "failed to mark controller live state\n");
e71afda4 2642 result = -ENODEV;
bb8d261e
CH		 2643 goto out;
2644 }
92911a55 2645
d09f2b45 2646 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2647 return;
f0b50732 2648
4726bcf3
KB		 2649 out_unlock:
2650 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2651 out:
7c1ce408
CK		 2652 if (result)
2653 dev_warn(dev->ctrl.device,
2654 "Removing after probe failure status: %d\n", result);
2655 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2656}
2657
5c8809e6 2658static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2659{
5c8809e6 2660 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2661 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2662
2663 if (pci_get_drvdata(pdev))
921920ab 2664 device_release_driver(&pdev->dev);
1673f1f0 2665 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2666}
2667
1c63dc66 2668static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2669{
1c63dc66 2670 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2671 return 0;
9ca97374
TH		 2672}
2673
5fd4ce1b 2674static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2675{
5fd4ce1b
CH		 2676 writel(val, to_nvme_dev(ctrl)->bar + off);
2677 return 0;
2678}
4cc06521 2679
7fd8930f
CH		 2680static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2681{
3a8ecc93 2682 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2683 return 0;
4cc06521
KB		 2684}
2685
97c12223
KB		 2686static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2687{
2688 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2689
2690 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2691}
2692
1c63dc66 2693static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2694 .name = "pcie",
e439bb12 2695 .module = THIS_MODULE,
e0596ab2
LG		 2696 .flags = NVME_F_METADATA_SUPPORTED |
2697 NVME_F_PCI_P2PDMA,
1c63dc66 2698 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2699 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2700 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2701 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2702 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2703 .get_address = nvme_pci_get_address,
1c63dc66 2704};
4cc06521 2705
b00a726a
KB		 2706static int nvme_dev_map(struct nvme_dev *dev)
2707{
b00a726a
KB		 2708 struct pci_dev *pdev = to_pci_dev(dev->dev);
2709
a1f447b3 2710 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2711 return -ENODEV;
2712
97f6ef64 2713 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2714 goto release;
2715
9fa196e7 2716 return 0;
b00a726a 2717 release:
9fa196e7
MG		 2718 pci_release_mem_regions(pdev);
2719 return -ENODEV;
b00a726a
KB		 2720}
2721
8427bbc2 2722static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2723{
2724 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2725 /*
2726 * Several Samsung devices seem to drop off the PCIe bus
2727 * randomly when APST is on and uses the deepest sleep state.
2728 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2729 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2730 * 950 PRO 256GB", but it seems to be restricted to two Dell
2731 * laptops.
2732 */
2733 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2734 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2735 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2736 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2737 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2738 /*
2739 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2740 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2741 * within few minutes after bootup on a Coffee Lake board -
2742 * ASUS PRIME Z370-A
8427bbc2
KHF		 2743 */
2744 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2745 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2746 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2747 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2748 }
2749
2750 return 0;
2751}
2752
18119775
KB		 2753static void nvme_async_probe(void *data, async_cookie_t cookie)
2754{
2755 struct nvme_dev *dev = data;
80f513b5 2756
bd46a906 2757 flush_work(&dev->ctrl.reset_work);
18119775 2758 flush_work(&dev->ctrl.scan_work);
80f513b5 2759 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2760}
2761
8d85fce7 2762static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2763{
a4aea562 2764 int node, result = -ENOMEM;
b60503ba 2765 struct nvme_dev *dev;
ff5350a8 2766 unsigned long quirks = id->driver_data;
943e942e 2767 size_t alloc_size;
b60503ba 2768
a4aea562
MB		 2769 node = dev_to_node(&pdev->dev);
2770 if (node == NUMA_NO_NODE)
2fa84351 2771 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2772
2773 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2774 if (!dev)
2775 return -ENOMEM;
147b27e4 2776
3b6592f7
JA		 2777 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2778 GFP_KERNEL, node);
b60503ba
MW		 2779 if (!dev->queues)
2780 goto free;
2781
e75ec752 2782 dev->dev = get_device(&pdev->dev);
9a6b9458 2783 pci_set_drvdata(pdev, dev);
1c63dc66 2784
b00a726a
KB		 2785 result = nvme_dev_map(dev);
2786 if (result)
b00c9b7a 2787 goto put_pci;
b00a726a 2788
d86c4d8e 2789 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2790 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2791 mutex_init(&dev->shutdown_lock);
b60503ba 2792
091b6092
MW		 2793 result = nvme_setup_prp_pools(dev);
2794 if (result)
b00c9b7a 2795 goto unmap;
4cc06521 2796
8427bbc2 2797 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2798
943e942e
JA		 2799 /*
2800 * Double check that our mempool alloc size will cover the biggest
2801 * command we support.
2802 */
2803 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2804 NVME_MAX_SEGS, true);
2805 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2806
2807 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2808 mempool_kfree,
2809 (void *) alloc_size,
2810 GFP_KERNEL, node);
2811 if (!dev->iod_mempool) {
2812 result = -ENOMEM;
2813 goto release_pools;
2814 }
2815
b6e44b4c
KB		 2816 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2817 quirks);
2818 if (result)
2819 goto release_mempool;
2820
1b3c47c1
SG		 2821 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2822
bd46a906 2823 nvme_reset_ctrl(&dev->ctrl);
80f513b5 2824 nvme_get_ctrl(&dev->ctrl);
18119775 2825 async_schedule(nvme_async_probe, dev);
4caff8fc 2826
b60503ba
MW		 2827 return 0;
2828
b6e44b4c
KB		 2829 release_mempool:
2830 mempool_destroy(dev->iod_mempool);
0877cb0d 2831 release_pools:
091b6092 2832 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2833 unmap:
2834 nvme_dev_unmap(dev);
a96d4f5c 2835 put_pci:
e75ec752 2836 put_device(dev->dev);
b60503ba
MW		 2837 free:
2838 kfree(dev->queues);
b60503ba
MW		 2839 kfree(dev);
2840 return result;
2841}
2842
775755ed 2843static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2844{
a6739479 2845 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2846
2847 /*
2848 * We don't need to check the return value from waiting for the reset
2849 * state as pci_dev device lock is held, making it impossible to race
2850 * with ->remove().
2851 */
2852 nvme_disable_prepare_reset(dev, false);
2853 nvme_sync_queues(&dev->ctrl);
775755ed 2854}
f0d54a54 2855
775755ed
CH		 2856static void nvme_reset_done(struct pci_dev *pdev)
2857{
f263fbb8 2858 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2859
2860 if (!nvme_try_sched_reset(&dev->ctrl))
2861 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2862}
2863
09ece142
KB		 2864static void nvme_shutdown(struct pci_dev *pdev)
2865{
2866 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b 2867 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2868}
2869
f58944e2
KB		 2870/*
2871 * The driver's remove may be called on a device in a partially initialized
2872 * state. This function must not have any dependencies on the device state in
2873 * order to proceed.
2874 */
8d85fce7 2875static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2876{
2877 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2878
bb8d261e 2879 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2880 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2881
6db28eda 2882 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2883 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2884 nvme_dev_disable(dev, true);
cb4bfda6 2885 nvme_dev_remove_admin(dev);
6db28eda 2886 }
0ff9d4e1 2887
d86c4d8e 2888 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2889 nvme_stop_ctrl(&dev->ctrl);
2890 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2891 nvme_dev_disable(dev, true);
9fe5c59f 2892 nvme_release_cmb(dev);
87ad72a5 2893 nvme_free_host_mem(dev);
a4aea562 2894 nvme_dev_remove_admin(dev);
a1a5ef99 2895 nvme_free_queues(dev, 0);
d09f2b45 2896 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2897 nvme_release_prp_pools(dev);
b00a726a 2898 nvme_dev_unmap(dev);
1673f1f0 2899 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2900}
2901
671a6018 2902#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2903static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2904{
2905 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2906}
2907
2908static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2909{
2910 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2911}
2912
2913static int nvme_resume(struct device *dev)
2914{
2915 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2916 struct nvme_ctrl *ctrl = &ndev->ctrl;
2917
4eaefe8c 2918 if (ndev->last_ps == U32_MAX ||
d916b1be 2919 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2920 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 2921 return 0;
2922}
2923
cd638946
KB		 2924static int nvme_suspend(struct device *dev)
2925{
2926 struct pci_dev *pdev = to_pci_dev(dev);
2927 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2928 struct nvme_ctrl *ctrl = &ndev->ctrl;
2929 int ret = -EBUSY;
2930
4eaefe8c
RW		 2931 ndev->last_ps = U32_MAX;
2932
d916b1be
KB		 2933 /*
2934 * The platform does not remove power for a kernel managed suspend so
2935 * use host managed nvme power settings for lowest idle power if
2936 * possible. This should have quicker resume latency than a full device
2937 * shutdown. But if the firmware is involved after the suspend or the
2938 * device does not support any non-default power states, shut down the
2939 * device fully.
4eaefe8c
RW		 2940 *
2941 * If ASPM is not enabled for the device, shut down the device and allow
2942 * the PCI bus layer to put it into D3 in order to take the PCIe link
2943 * down, so as to allow the platform to achieve its minimum low-power
2944 * state (which may not be possible if the link is up).
d916b1be 2945 */
4eaefe8c 2946 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 2947 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 2948 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2949 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 2950
2951 nvme_start_freeze(ctrl);
2952 nvme_wait_freeze(ctrl);
2953 nvme_sync_queues(ctrl);
2954
5d02a5c1 2955 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 2956 goto unfreeze;
2957
d916b1be
KB		 2958 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2959 if (ret < 0)
2960 goto unfreeze;
2961
7cbb5c6f
ML		 2962 /*
2963 * A saved state prevents pci pm from generically controlling the
2964 * device's power. If we're using protocol specific settings, we don't
2965 * want pci interfering.
2966 */
2967 pci_save_state(pdev);
2968
d916b1be
KB		 2969 ret = nvme_set_power_state(ctrl, ctrl->npss);
2970 if (ret < 0)
2971 goto unfreeze;
2972
2973 if (ret) {
7cbb5c6f
ML		 2974 /* discard the saved state */
2975 pci_load_saved_state(pdev, NULL);
2976
d916b1be
KB		 2977 /*
2978 * Clearing npss forces a controller reset on resume. The
05d3046f 2979 * correct value will be rediscovered then.
d916b1be 2980 */
c1ac9a4b 2981 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 2982 ctrl->npss = 0;
d916b1be 2983 }
d916b1be
KB		 2984unfreeze:
2985 nvme_unfreeze(ctrl);
2986 return ret;
2987}
2988
2989static int nvme_simple_suspend(struct device *dev)
2990{
2991 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
c1ac9a4b 2992 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 2993}
2994
d916b1be 2995static int nvme_simple_resume(struct device *dev)
cd638946
KB		 2996{
2997 struct pci_dev *pdev = to_pci_dev(dev);
2998 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2999
c1ac9a4b 3000 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3001}
3002
21774222 3003static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3004 .suspend = nvme_suspend,
3005 .resume = nvme_resume,
3006 .freeze = nvme_simple_suspend,
3007 .thaw = nvme_simple_resume,
3008 .poweroff = nvme_simple_suspend,
3009 .restore = nvme_simple_resume,
3010};
3011#endif /* CONFIG_PM_SLEEP */
b60503ba 3012
a0a3408e
KB		 3013static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3014 pci_channel_state_t state)
3015{
3016 struct nvme_dev *dev = pci_get_drvdata(pdev);
3017
3018 /*
3019 * A frozen channel requires a reset. When detected, this method will
3020 * shutdown the controller to quiesce. The controller will be restarted
3021 * after the slot reset through driver's slot_reset callback.
3022 */
a0a3408e
KB		 3023 switch (state) {
3024 case pci_channel_io_normal:
3025 return PCI_ERS_RESULT_CAN_RECOVER;
3026 case pci_channel_io_frozen:
d011fb31
KB		 3027 dev_warn(dev->ctrl.device,
3028 "frozen state error detected, reset controller\n");
a5cdb68c 3029 nvme_dev_disable(dev, false);
a0a3408e
KB		 3030 return PCI_ERS_RESULT_NEED_RESET;
3031 case pci_channel_io_perm_failure:
d011fb31
KB		 3032 dev_warn(dev->ctrl.device,
3033 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3034 return PCI_ERS_RESULT_DISCONNECT;
3035 }
3036 return PCI_ERS_RESULT_NEED_RESET;
3037}
3038
3039static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3040{
3041 struct nvme_dev *dev = pci_get_drvdata(pdev);
3042
1b3c47c1 3043 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3044 pci_restore_state(pdev);
d86c4d8e 3045 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3046 return PCI_ERS_RESULT_RECOVERED;
3047}
3048
3049static void nvme_error_resume(struct pci_dev *pdev)
3050{
72cd4cc2
KB		 3051 struct nvme_dev *dev = pci_get_drvdata(pdev);
3052
3053 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3054}
3055
1d352035 3056static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3057 .error_detected = nvme_error_detected,
b60503ba
MW		 3058 .slot_reset = nvme_slot_reset,
3059 .resume = nvme_error_resume,
775755ed
CH		 3060 .reset_prepare = nvme_reset_prepare,
3061 .reset_done = nvme_reset_done,
b60503ba
MW		 3062};
3063
6eb0d698 3064static const struct pci_device_id nvme_id_table[] = {
106198ed 3065 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3066 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3067 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3068 { PCI_VDEVICE(INTEL, 0x0a53),
3069 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3070 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3071 { PCI_VDEVICE(INTEL, 0x0a54),
3072 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3073 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3074 { PCI_VDEVICE(INTEL, 0x0a55),
3075 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3076 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3077 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3078 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2
AM		 3079 NVME_QUIRK_MEDIUM_PRIO_SQ |
3080 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
6299358d
JD		 3081 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3082 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3083 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3084 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3085 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3086 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3087 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3088 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3089 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3090 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3091 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3092 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3093 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3094 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3095 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3096 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3097 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3098 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3099 .driver_data = NVME_QUIRK_LIGHTNVM, },
3100 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3101 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3102 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3103 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3104 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3105 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3106 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3107 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3108 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3109 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3110 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3111 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3112 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3113 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3114 NVME_QUIRK_128_BYTES_SQES |
3115 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3116 { 0, }
3117};
3118MODULE_DEVICE_TABLE(pci, nvme_id_table);
3119
3120static struct pci_driver nvme_driver = {
3121 .name = "nvme",
3122 .id_table = nvme_id_table,
3123 .probe = nvme_probe,
8d85fce7 3124 .remove = nvme_remove,
09ece142 3125 .shutdown = nvme_shutdown,
d916b1be 3126#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3127 .driver = {
3128 .pm = &nvme_dev_pm_ops,
3129 },
d916b1be 3130#endif
74d986ab 3131 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3132 .err_handler = &nvme_err_handler,
3133};
3134
3135static int __init nvme_init(void)
3136{
81101540
CH		 3137 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3138 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3139 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3140 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
9a6327d2 3141 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3142}
3143
3144static void __exit nvme_exit(void)
3145{
3146 pci_unregister_driver(&nvme_driver);
03e0f3a6 3147 flush_workqueue(nvme_wq);
b60503ba
MW		 3148}
3149
3150MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3151MODULE_LICENSE("GPL");
c78b4713 3152MODULE_VERSION("1.0");
b60503ba
MW		 3153module_init(nvme_init);
3154module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)