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nvme-pci: fix some comments issues
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
61f3b896 64 .get = param_get_uint,
b27c1e68 65};
66
61f3b896 67static unsigned int io_queue_depth = 1024;
b27c1e68 68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
9c9e76d5
WZ		 71static int io_queue_count_set(const char *val, const struct kernel_param *kp)
72{
73 unsigned int n;
74 int ret;
75
76 ret = kstrtouint(val, 10, &n);
77 if (ret != 0 || n > num_possible_cpus())
78 return -EINVAL;
79 return param_set_uint(val, kp);
80}
81
82static const struct kernel_param_ops io_queue_count_ops = {
83 .set = io_queue_count_set,
84 .get = param_get_uint,
85};
86
3f68baf7 87static unsigned int write_queues;
9c9e76d5 88module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 89MODULE_PARM_DESC(write_queues,
90 "Number of queues to use for writes. If not set, reads and writes "
91 "will share a queue set.");
92
3f68baf7 93static unsigned int poll_queues;
9c9e76d5 94module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 95MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
96
1c63dc66
CH		 97struct nvme_dev;
98struct nvme_queue;
b3fffdef 99
a5cdb68c 100static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 101static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 102
1c63dc66
CH		 103/*
104 * Represents an NVM Express device. Each nvme_dev is a PCI function.
105 */
106struct nvme_dev {
147b27e4 107 struct nvme_queue *queues;
1c63dc66
CH		 108 struct blk_mq_tag_set tagset;
109 struct blk_mq_tag_set admin_tagset;
110 u32 __iomem *dbs;
111 struct device *dev;
112 struct dma_pool *prp_page_pool;
113 struct dma_pool *prp_small_pool;
1c63dc66
CH		 114 unsigned online_queues;
115 unsigned max_qid;
e20ba6e1 116 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 117 unsigned int num_vecs;
61f3b896 118 u16 q_depth;
c1e0cc7e 119 int io_sqes;
1c63dc66 120 u32 db_stride;
1c63dc66 121 void __iomem *bar;
97f6ef64 122 unsigned long bar_mapped_size;
5c8809e6 123 struct work_struct remove_work;
77bf25ea 124 struct mutex shutdown_lock;
1c63dc66 125 bool subsystem;
1c63dc66 126 u64 cmb_size;
0f238ff5 127 bool cmb_use_sqes;
1c63dc66 128 u32 cmbsz;
202021c1 129 u32 cmbloc;
1c63dc66 130 struct nvme_ctrl ctrl;
d916b1be 131 u32 last_ps;
87ad72a5 132
943e942e
JA		 133 mempool_t *iod_mempool;
134
87ad72a5 135 /* shadow doorbell buffer support: */
f9f38e33
HK		 136 u32 *dbbuf_dbs;
137 dma_addr_t dbbuf_dbs_dma_addr;
138 u32 *dbbuf_eis;
139 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 140
141 /* host memory buffer support: */
142 u64 host_mem_size;
143 u32 nr_host_mem_descs;
4033f35d 144 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 145 struct nvme_host_mem_buf_desc *host_mem_descs;
146 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 147 unsigned int nr_allocated_queues;
148 unsigned int nr_write_queues;
149 unsigned int nr_poll_queues;
4d115420 150};
1fa6aead 151
b27c1e68 152static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
153{
61f3b896
CK		 154 int ret;
155 u16 n;
b27c1e68 156
61f3b896 157 ret = kstrtou16(val, 10, &n);
b27c1e68 158 if (ret != 0 || n < 2)
159 return -EINVAL;
160
61f3b896 161 return param_set_ushort(val, kp);
b27c1e68 162}
163
f9f38e33
HK		 164static inline unsigned int sq_idx(unsigned int qid, u32 stride)
165{
166 return qid * 2 * stride;
167}
168
169static inline unsigned int cq_idx(unsigned int qid, u32 stride)
170{
171 return (qid * 2 + 1) * stride;
172}
173
1c63dc66
CH		 174static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
175{
176 return container_of(ctrl, struct nvme_dev, ctrl);
177}
178
b60503ba
MW		 179/*
180 * An NVM Express queue. Each device has at least two (one for admin
181 * commands and one for I/O commands).
182 */
183struct nvme_queue {
091b6092 184 struct nvme_dev *dev;
1ab0cd69 185 spinlock_t sq_lock;
c1e0cc7e 186 void *sq_cmds;
3a7afd8e
CH		 187 /* only used for poll queues: */
188 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 189 struct nvme_completion *cqes;
b60503ba
MW		 190 dma_addr_t sq_dma_addr;
191 dma_addr_t cq_dma_addr;
b60503ba
MW		 192 u32 __iomem *q_db;
193 u16 q_depth;
7c349dde 194 u16 cq_vector;
b60503ba
MW		 195 u16 sq_tail;
196 u16 cq_head;
c30341dc 197 u16 qid;
e9539f47 198 u8 cq_phase;
c1e0cc7e 199 u8 sqes;
4e224106
CH		 200 unsigned long flags;
201#define NVMEQ_ENABLED 0
63223078 202#define NVMEQ_SQ_CMB 1
d1ed6aa1 203#define NVMEQ_DELETE_ERROR 2
7c349dde 204#define NVMEQ_POLLED 3
f9f38e33
HK		 205 u32 *dbbuf_sq_db;
206 u32 *dbbuf_cq_db;
207 u32 *dbbuf_sq_ei;
208 u32 *dbbuf_cq_ei;
d1ed6aa1 209 struct completion delete_done;
b60503ba
MW		 210};
211
71bd150c 212/*
9b048119
CH		 213 * The nvme_iod describes the data in an I/O.
214 *
215 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
216 * to the actual struct scatterlist.
71bd150c
CH		 217 */
218struct nvme_iod {
d49187e9 219 struct nvme_request req;
f4800d6d 220 struct nvme_queue *nvmeq;
a7a7cbe3 221 bool use_sgl;
f4800d6d 222 int aborted;
71bd150c 223 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 224 int nents; /* Used in scatterlist */
71bd150c 225 dma_addr_t first_dma;
dff824b2 226 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 227 dma_addr_t meta_dma;
f4800d6d 228 struct scatterlist *sg;
b60503ba
MW		 229};
230
2a5bcfdd 231static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 232{
2a5bcfdd 233 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 234}
235
236static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
237{
2a5bcfdd 238 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 239
240 if (dev->dbbuf_dbs)
241 return 0;
242
243 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
244 &dev->dbbuf_dbs_dma_addr,
245 GFP_KERNEL);
246 if (!dev->dbbuf_dbs)
247 return -ENOMEM;
248 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
249 &dev->dbbuf_eis_dma_addr,
250 GFP_KERNEL);
251 if (!dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
254 dev->dbbuf_dbs = NULL;
255 return -ENOMEM;
256 }
257
258 return 0;
259}
260
261static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
262{
2a5bcfdd 263 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 264
265 if (dev->dbbuf_dbs) {
266 dma_free_coherent(dev->dev, mem_size,
267 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
268 dev->dbbuf_dbs = NULL;
269 }
270 if (dev->dbbuf_eis) {
271 dma_free_coherent(dev->dev, mem_size,
272 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
273 dev->dbbuf_eis = NULL;
274 }
275}
276
277static void nvme_dbbuf_init(struct nvme_dev *dev,
278 struct nvme_queue *nvmeq, int qid)
279{
280 if (!dev->dbbuf_dbs || !qid)
281 return;
282
283 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
284 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
285 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
286 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
287}
288
289static void nvme_dbbuf_set(struct nvme_dev *dev)
290{
291 struct nvme_command c;
292
293 if (!dev->dbbuf_dbs)
294 return;
295
296 memset(&c, 0, sizeof(c));
297 c.dbbuf.opcode = nvme_admin_dbbuf;
298 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
299 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
300
301 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 302 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 303 /* Free memory and continue on */
304 nvme_dbbuf_dma_free(dev);
305 }
306}
307
308static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
309{
310 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
311}
312
313/* Update dbbuf and return true if an MMIO is required */
314static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
315 volatile u32 *dbbuf_ei)
316{
317 if (dbbuf_db) {
318 u16 old_value;
319
320 /*
321 * Ensure that the queue is written before updating
322 * the doorbell in memory
323 */
324 wmb();
325
326 old_value = *dbbuf_db;
327 *dbbuf_db = value;
328
f1ed3df2
MW		 329 /*
330 * Ensure that the doorbell is updated before reading the event
331 * index from memory. The controller needs to provide similar
332 * ordering to ensure the envent index is updated before reading
333 * the doorbell.
334 */
335 mb();
336
f9f38e33
HK		 337 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
338 return false;
339 }
340
341 return true;
b60503ba
MW		 342}
343
ac3dd5bd
JA		 344/*
345 * Will slightly overestimate the number of pages needed. This is OK
346 * as it only leads to a small amount of wasted memory for the lifetime of
347 * the I/O.
348 */
349static int nvme_npages(unsigned size, struct nvme_dev *dev)
350{
5fd4ce1b
CH		 351 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
352 dev->ctrl.page_size);
ac3dd5bd
JA		 353 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
354}
355
a7a7cbe3
CK		 356/*
357 * Calculates the number of pages needed for the SGL segments. For example a 4k
358 * page can accommodate 256 SGL descriptors.
359 */
360static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 361{
a7a7cbe3 362 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 363}
ac3dd5bd 364
a7a7cbe3
CK		 365static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
366 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 367{
a7a7cbe3
CK		 368 size_t alloc_size;
369
370 if (use_sgl)
371 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
372 else
373 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
374
375 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 376}
ac3dd5bd 377
a4aea562
MB		 378static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
379 unsigned int hctx_idx)
e85248e5 380{
a4aea562 381 struct nvme_dev *dev = data;
147b27e4 382 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 383
42483228
KB		 384 WARN_ON(hctx_idx != 0);
385 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 386
a4aea562
MB		 387 hctx->driver_data = nvmeq;
388 return 0;
e85248e5
MW		 389}
390
a4aea562
MB		 391static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
392 unsigned int hctx_idx)
b60503ba 393{
a4aea562 394 struct nvme_dev *dev = data;
147b27e4 395 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 396
42483228 397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 398 hctx->driver_data = nvmeq;
399 return 0;
b60503ba
MW		 400}
401
d6296d39
CH		 402static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 404{
d6296d39 405 struct nvme_dev *dev = set->driver_data;
f4800d6d 406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 409
410 BUG_ON(!nvmeq);
f4800d6d 411 iod->nvmeq = nvmeq;
59e29ce6
SG		 412
413 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 414 return 0;
415}
416
3b6592f7
JA		 417static int queue_irq_offset(struct nvme_dev *dev)
418{
419 /* if we have more than 1 vec, admin queue offsets us by 1 */
420 if (dev->num_vecs > 1)
421 return 1;
422
423 return 0;
424}
425
dca51e78
CH		 426static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
427{
428 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 429 int i, qoff, offset;
430
431 offset = queue_irq_offset(dev);
432 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
433 struct blk_mq_queue_map *map = &set->map[i];
434
435 map->nr_queues = dev->io_queues[i];
436 if (!map->nr_queues) {
e20ba6e1 437 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 438 continue;
3b6592f7
JA		 439 }
440
4b04cc6a
JA		 441 /*
442 * The poll queue(s) doesn't have an IRQ (and hence IRQ
443 * affinity), so use the regular blk-mq cpu mapping
444 */
3b6592f7 445 map->queue_offset = qoff;
cb9e0e50 446 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 447 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
448 else
449 blk_mq_map_queues(map);
3b6592f7
JA		 450 qoff += map->nr_queues;
451 offset += map->nr_queues;
452 }
453
454 return 0;
dca51e78
CH		 455}
456
54b2fcee 457static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
04f3eafd 458{
04f3eafd
JA		 459 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
460 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
461 writel(nvmeq->sq_tail, nvmeq->q_db);
04f3eafd
JA		 462}
463
b60503ba 464/**
90ea5ca4 465 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 466 * @nvmeq: The queue to use
467 * @cmd: The command to send
04f3eafd 468 * @write_sq: whether to write to the SQ doorbell
b60503ba 469 */
04f3eafd
JA		 470static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
471 bool write_sq)
b60503ba 472{
90ea5ca4 473 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 474 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
475 cmd, sizeof(*cmd));
90ea5ca4
CH		 476 if (++nvmeq->sq_tail == nvmeq->q_depth)
477 nvmeq->sq_tail = 0;
54b2fcee
KB		 478 if (write_sq)
479 nvme_write_sq_db(nvmeq);
04f3eafd
JA		 480 spin_unlock(&nvmeq->sq_lock);
481}
482
483static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
484{
485 struct nvme_queue *nvmeq = hctx->driver_data;
486
487 spin_lock(&nvmeq->sq_lock);
54b2fcee 488 nvme_write_sq_db(nvmeq);
90ea5ca4 489 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 490}
491
a7a7cbe3 492static void **nvme_pci_iod_list(struct request *req)
b60503ba 493{
f4800d6d 494 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 495 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 496}
497
955b1b5a
MI		 498static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
499{
500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 501 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 502 unsigned int avg_seg_size;
503
20469a37 504 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 505
506 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
507 return false;
508 if (!iod->nvmeq->qid)
509 return false;
510 if (!sgl_threshold || avg_seg_size < sgl_threshold)
511 return false;
512 return true;
513}
514
7fe07d14 515static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 516{
f4800d6d 517 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 518 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
519 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 520 int i;
eca18b23 521
dff824b2 522 if (iod->dma_len) {
f2fa006f
IR		 523 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
524 rq_dma_dir(req));
dff824b2 525 return;
7fe07d14
CH		 526 }
527
dff824b2
CH		 528 WARN_ON_ONCE(!iod->nents);
529
7f73eac3
LG		 530 if (is_pci_p2pdma_page(sg_page(iod->sg)))
531 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
532 rq_dma_dir(req));
533 else
dff824b2
CH		 534 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
535
536
eca18b23 537 if (iod->npages == 0)
a7a7cbe3
CK		 538 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
539 dma_addr);
540
eca18b23 541 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 542 void *addr = nvme_pci_iod_list(req)[i];
543
544 if (iod->use_sgl) {
545 struct nvme_sgl_desc *sg_list = addr;
546
547 next_dma_addr =
548 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
549 } else {
550 __le64 *prp_list = addr;
551
552 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
553 }
554
555 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
556 dma_addr = next_dma_addr;
eca18b23 557 }
ac3dd5bd 558
d43f1ccf 559 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 560}
561
d0877473
KB		 562static void nvme_print_sgl(struct scatterlist *sgl, int nents)
563{
564 int i;
565 struct scatterlist *sg;
566
567 for_each_sg(sgl, sg, nents, i) {
568 dma_addr_t phys = sg_phys(sg);
569 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
570 "dma_address:%pad dma_length:%d\n",
571 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
572 sg_dma_len(sg));
573 }
574}
575
a7a7cbe3
CK		 576static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
577 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 578{
f4800d6d 579 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 580 struct dma_pool *pool;
b131c61d 581 int length = blk_rq_payload_bytes(req);
eca18b23 582 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 583 int dma_len = sg_dma_len(sg);
584 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 585 u32 page_size = dev->ctrl.page_size;
f137e0f1 586 int offset = dma_addr & (page_size - 1);
e025344c 587 __le64 *prp_list;
a7a7cbe3 588 void **list = nvme_pci_iod_list(req);
e025344c 589 dma_addr_t prp_dma;
eca18b23 590 int nprps, i;
ff22b54f 591
1d090624 592 length -= (page_size - offset);
5228b328
JS		 593 if (length <= 0) {
594 iod->first_dma = 0;
a7a7cbe3 595 goto done;
5228b328 596 }
ff22b54f 597
1d090624 598 dma_len -= (page_size - offset);
ff22b54f 599 if (dma_len) {
1d090624 600 dma_addr += (page_size - offset);
ff22b54f
MW		 601 } else {
602 sg = sg_next(sg);
603 dma_addr = sg_dma_address(sg);
604 dma_len = sg_dma_len(sg);
605 }
606
1d090624 607 if (length <= page_size) {
edd10d33 608 iod->first_dma = dma_addr;
a7a7cbe3 609 goto done;
e025344c
SMM		 610 }
611
1d090624 612 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 613 if (nprps <= (256 / 8)) {
614 pool = dev->prp_small_pool;
eca18b23 615 iod->npages = 0;
99802a7a
MW		 616 } else {
617 pool = dev->prp_page_pool;
eca18b23 618 iod->npages = 1;
99802a7a
MW		 619 }
620
69d2b571 621 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 622 if (!prp_list) {
edd10d33 623 iod->first_dma = dma_addr;
eca18b23 624 iod->npages = -1;
86eea289 625 return BLK_STS_RESOURCE;
b77954cb 626 }
eca18b23
MW		 627 list[0] = prp_list;
628 iod->first_dma = prp_dma;
e025344c
SMM		 629 i = 0;
630 for (;;) {
1d090624 631 if (i == page_size >> 3) {
e025344c 632 __le64 *old_prp_list = prp_list;
69d2b571 633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 634 if (!prp_list)
86eea289 635 return BLK_STS_RESOURCE;
eca18b23 636 list[iod->npages++] = prp_list;
7523d834
MW		 637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
e025344c
SMM		 640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 642 dma_len -= page_size;
643 dma_addr += page_size;
644 length -= page_size;
e025344c
SMM		 645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
86eea289
KB		 649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
e025344c
SMM		 651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
ff22b54f
MW		 654 }
655
a7a7cbe3
CK		 656done:
657 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
658 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
659
86eea289
KB		 660 return BLK_STS_OK;
661
662 bad_sgl:
d0877473
KB		 663 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->nents);
86eea289 666 return BLK_STS_IOERR;
ff22b54f
MW		 667}
668
a7a7cbe3
CK		 669static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671{
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675}
676
677static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679{
680 sge->addr = cpu_to_le64(dma_addr);
681 if (entries < SGES_PER_PAGE) {
682 sge->length = cpu_to_le32(entries * sizeof(*sge));
683 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
684 } else {
685 sge->length = cpu_to_le32(PAGE_SIZE);
686 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
687 }
688}
689
690static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 691 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 692{
693 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 694 struct dma_pool *pool;
695 struct nvme_sgl_desc *sg_list;
696 struct scatterlist *sg = iod->sg;
a7a7cbe3 697 dma_addr_t sgl_dma;
b0f2853b 698 int i = 0;
a7a7cbe3 699
a7a7cbe3
CK		 700 /* setting the transfer type as SGL */
701 cmd->flags = NVME_CMD_SGL_METABUF;
702
b0f2853b 703 if (entries == 1) {
a7a7cbe3
CK		 704 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
705 return BLK_STS_OK;
706 }
707
708 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
709 pool = dev->prp_small_pool;
710 iod->npages = 0;
711 } else {
712 pool = dev->prp_page_pool;
713 iod->npages = 1;
714 }
715
716 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
717 if (!sg_list) {
718 iod->npages = -1;
719 return BLK_STS_RESOURCE;
720 }
721
722 nvme_pci_iod_list(req)[0] = sg_list;
723 iod->first_dma = sgl_dma;
724
725 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
726
727 do {
728 if (i == SGES_PER_PAGE) {
729 struct nvme_sgl_desc *old_sg_desc = sg_list;
730 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
731
732 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
733 if (!sg_list)
734 return BLK_STS_RESOURCE;
735
736 i = 0;
737 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
738 sg_list[i++] = *link;
739 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
740 }
741
742 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 743 sg = sg_next(sg);
b0f2853b 744 } while (--entries > 0);
a7a7cbe3 745
a7a7cbe3
CK		 746 return BLK_STS_OK;
747}
748
dff824b2
CH		 749static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
750 struct request *req, struct nvme_rw_command *cmnd,
751 struct bio_vec *bv)
752{
753 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4f40484
KH		 754 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
755 unsigned int first_prp_len = dev->ctrl.page_size - offset;
dff824b2
CH		 756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
762 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
763 if (bv->bv_len > first_prp_len)
764 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
765 return 0;
766}
767
29791057
CH		 768static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
769 struct request *req, struct nvme_rw_command *cmnd,
770 struct bio_vec *bv)
771{
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
773
774 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
775 if (dma_mapping_error(dev->dev, iod->first_dma))
776 return BLK_STS_RESOURCE;
777 iod->dma_len = bv->bv_len;
778
049bf372 779 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 780 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
781 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
782 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
783 return 0;
784}
785
fc17b653 786static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 787 struct nvme_command *cmnd)
d29ec824 788{
f4800d6d 789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 790 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 791 int nr_mapped;
d29ec824 792
dff824b2
CH		 793 if (blk_rq_nr_phys_segments(req) == 1) {
794 struct bio_vec bv = req_bvec(req);
795
796 if (!is_pci_p2pdma_page(bv.bv_page)) {
797 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
798 return nvme_setup_prp_simple(dev, req,
799 &cmnd->rw, &bv);
29791057
CH		 800
801 if (iod->nvmeq->qid &&
802 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
803 return nvme_setup_sgl_simple(dev, req,
804 &cmnd->rw, &bv);
dff824b2
CH		 805 }
806 }
807
808 iod->dma_len = 0;
d43f1ccf
CH		 809 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
810 if (!iod->sg)
811 return BLK_STS_RESOURCE;
f9d03f96 812 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 813 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 814 if (!iod->nents)
815 goto out;
d29ec824 816
e0596ab2 817 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 818 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
819 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 820 else
821 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 822 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 823 if (!nr_mapped)
ba1ca37e 824 goto out;
d29ec824 825
70479b71 826 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 827 if (iod->use_sgl)
b0f2853b 828 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 829 else
830 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 831out:
86eea289 832 if (ret != BLK_STS_OK)
4aedb705
CH		 833 nvme_unmap_data(dev, req);
834 return ret;
835}
3045c0d0 836
4aedb705
CH		 837static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
838 struct nvme_command *cmnd)
839{
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 841
4aedb705
CH		 842 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
843 rq_dma_dir(req), 0);
844 if (dma_mapping_error(dev->dev, iod->meta_dma))
845 return BLK_STS_IOERR;
846 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
847 return 0;
00df5cb4
MW		 848}
849
d29ec824
CH		 850/*
851 * NOTE: ns is NULL when called on the admin queue.
852 */
fc17b653 853static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 854 const struct blk_mq_queue_data *bd)
edd10d33 855{
a4aea562
MB		 856 struct nvme_ns *ns = hctx->queue->queuedata;
857 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 858 struct nvme_dev *dev = nvmeq->dev;
a4aea562 859 struct request *req = bd->rq;
9b048119 860 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 861 struct nvme_command cmnd;
ebe6d874 862 blk_status_t ret;
e1e5e564 863
9b048119
CH		 864 iod->aborted = 0;
865 iod->npages = -1;
866 iod->nents = 0;
867
d1f06f4a
JA		 868 /*
869 * We should not need to do this, but we're still using this to
870 * ensure we can drain requests on a dying queue.
871 */
4e224106 872 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 873 return BLK_STS_IOERR;
874
f9d03f96 875 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 876 if (ret)
f4800d6d 877 return ret;
a4aea562 878
fc17b653 879 if (blk_rq_nr_phys_segments(req)) {
b131c61d 880 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 881 if (ret)
9b048119 882 goto out_free_cmd;
fc17b653 883 }
a4aea562 884
4aedb705
CH		 885 if (blk_integrity_rq(req)) {
886 ret = nvme_map_metadata(dev, req, &cmnd);
887 if (ret)
888 goto out_unmap_data;
889 }
890
aae239e1 891 blk_mq_start_request(req);
04f3eafd 892 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 893 return BLK_STS_OK;
4aedb705
CH		 894out_unmap_data:
895 nvme_unmap_data(dev, req);
f9d03f96
CH		 896out_free_cmd:
897 nvme_cleanup_cmd(req);
ba1ca37e 898 return ret;
b60503ba 899}
e1e5e564 900
77f02a7a 901static void nvme_pci_complete_rq(struct request *req)
eee417b0 902{
f4800d6d 903 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 904 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 905
4aedb705
CH		 906 if (blk_integrity_rq(req))
907 dma_unmap_page(dev->dev, iod->meta_dma,
908 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 909 if (blk_rq_nr_phys_segments(req))
4aedb705 910 nvme_unmap_data(dev, req);
77f02a7a 911 nvme_complete_rq(req);
b60503ba
MW		 912}
913
d783e0bd 914/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 915static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 916{
74943d45
KB		 917 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
918
919 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 920}
921
eb281c82 922static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 923{
eb281c82 924 u16 head = nvmeq->cq_head;
adf68f21 925
397c699f
KB		 926 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
927 nvmeq->dbbuf_cq_ei))
928 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 929}
aae239e1 930
cfa27356
CH		 931static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
932{
933 if (!nvmeq->qid)
934 return nvmeq->dev->admin_tagset.tags[0];
935 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
936}
937
5cb525c8 938static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 939{
74943d45 940 struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 941 struct request *req;
adf68f21 942
83a12fb7
SG		 943 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
944 dev_warn(nvmeq->dev->ctrl.device,
945 "invalid id %d completed on queue %d\n",
946 cqe->command_id, le16_to_cpu(cqe->sq_id));
947 return;
b60503ba
MW		 948 }
949
83a12fb7
SG		 950 /*
951 * AEN requests are special as they don't time out and can
952 * survive any kind of queue freeze and often don't respond to
953 * aborts. We don't even bother to allocate a struct request
954 * for them but rather special case them here.
955 */
58a8df67 956 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 957 nvme_complete_async_event(&nvmeq->dev->ctrl,
958 cqe->status, &cqe->result);
a0fa9647 959 return;
83a12fb7 960 }
b60503ba 961
cfa27356 962 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
604c01d5 963 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
ff029451
CH		 964 if (!nvme_end_request(req, cqe->status, cqe->result))
965 nvme_pci_complete_rq(req);
83a12fb7 966}
b60503ba 967
5cb525c8
JA		 968static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
969{
a8de6639
AD		 970 u16 tmp = nvmeq->cq_head + 1;
971
972 if (tmp == nvmeq->q_depth) {
5cb525c8 973 nvmeq->cq_head = 0;
e2a366a4 974 nvmeq->cq_phase ^= 1;
a8de6639
AD		 975 } else {
976 nvmeq->cq_head = tmp;
b60503ba 977 }
a0fa9647
JA		 978}
979
324b494c 980static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 981{
1052b8ac 982 int found = 0;
b60503ba 983
1052b8ac 984 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 985 found++;
b69e2ef2
KB		 986 /*
987 * load-load control dependency between phase and the rest of
988 * the cqe requires a full read memory barrier
989 */
990 dma_rmb();
324b494c 991 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 992 nvme_update_cq_head(nvmeq);
920d13a8 993 }
eb281c82 994
324b494c 995 if (found)
920d13a8 996 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 997 return found;
b60503ba
MW		 998}
999
1000static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1001{
58ffacb5 1002 struct nvme_queue *nvmeq = data;
68fa9dbe 1003 irqreturn_t ret = IRQ_NONE;
5cb525c8 1004
3a7afd8e
CH		 1005 /*
1006 * The rmb/wmb pair ensures we see all updates from a previous run of
1007 * the irq handler, even if that was on another CPU.
1008 */
1009 rmb();
324b494c
KB		 1010 if (nvme_process_cq(nvmeq))
1011 ret = IRQ_HANDLED;
3a7afd8e 1012 wmb();
5cb525c8 1013
68fa9dbe 1014 return ret;
58ffacb5
MW		 1015}
1016
1017static irqreturn_t nvme_irq_check(int irq, void *data)
1018{
1019 struct nvme_queue *nvmeq = data;
750dde44 1020 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1021 return IRQ_WAKE_THREAD;
1022 return IRQ_NONE;
58ffacb5
MW		 1023}
1024
0b2a8a9f 1025/*
fa059b85 1026 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1027 * Can be called from any context.
1028 */
fa059b85 1029static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1030{
3a7afd8e 1031 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1032
fa059b85 1033 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1034
fa059b85
KB		 1035 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1036 nvme_process_cq(nvmeq);
1037 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1038}
1039
9743139c 1040static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1041{
1042 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1043 bool found;
1044
1045 if (!nvme_cqe_pending(nvmeq))
1046 return 0;
1047
3a7afd8e 1048 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1049 found = nvme_process_cq(nvmeq);
3a7afd8e 1050 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1051
dabcefab
JA		 1052 return found;
1053}
1054
ad22c355 1055static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1056{
f866fc42 1057 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1058 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1059 struct nvme_command c;
b60503ba 1060
a4aea562
MB		 1061 memset(&c, 0, sizeof(c));
1062 c.common.opcode = nvme_admin_async_event;
ad22c355 1063 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1064 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1065}
1066
b60503ba 1067static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1068{
b60503ba
MW		 1069 struct nvme_command c;
1070
1071 memset(&c, 0, sizeof(c));
1072 c.delete_queue.opcode = opcode;
1073 c.delete_queue.qid = cpu_to_le16(id);
1074
1c63dc66 1075 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1076}
1077
b60503ba 1078static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1079 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1080{
b60503ba 1081 struct nvme_command c;
4b04cc6a
JA		 1082 int flags = NVME_QUEUE_PHYS_CONTIG;
1083
7c349dde 1084 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1085 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1086
d29ec824 1087 /*
16772ae6 1088 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1089 * is attached to the request.
1090 */
b60503ba
MW		 1091 memset(&c, 0, sizeof(c));
1092 c.create_cq.opcode = nvme_admin_create_cq;
1093 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1094 c.create_cq.cqid = cpu_to_le16(qid);
1095 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1096 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1097 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1098
1c63dc66 1099 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1100}
1101
1102static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1103 struct nvme_queue *nvmeq)
1104{
9abd68ef 1105 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1106 struct nvme_command c;
81c1cd98 1107 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1108
9abd68ef
JA		 1109 /*
1110 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1111 * set. Since URGENT priority is zeroes, it makes all queues
1112 * URGENT.
1113 */
1114 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1115 flags |= NVME_SQ_PRIO_MEDIUM;
1116
d29ec824 1117 /*
16772ae6 1118 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1119 * is attached to the request.
1120 */
b60503ba
MW		 1121 memset(&c, 0, sizeof(c));
1122 c.create_sq.opcode = nvme_admin_create_sq;
1123 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1124 c.create_sq.sqid = cpu_to_le16(qid);
1125 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1126 c.create_sq.sq_flags = cpu_to_le16(flags);
1127 c.create_sq.cqid = cpu_to_le16(qid);
1128
1c63dc66 1129 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1130}
1131
1132static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1133{
1134 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1135}
1136
1137static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1138{
1139 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1140}
1141
2a842aca 1142static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1143{
f4800d6d
CH		 1144 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1145 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1146
27fa9bc5
CH		 1147 dev_warn(nvmeq->dev->ctrl.device,
1148 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1149 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1150 blk_mq_free_request(req);
bc5fc7e4
MW		 1151}
1152
b2a0eb1a
KB		 1153static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1154{
b2a0eb1a
KB		 1155 /* If true, indicates loss of adapter communication, possibly by a
1156 * NVMe Subsystem reset.
1157 */
1158 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1159
ad70062c
JW		 1160 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1161 switch (dev->ctrl.state) {
1162 case NVME_CTRL_RESETTING:
ad6a0a52 1163 case NVME_CTRL_CONNECTING:
b2a0eb1a 1164 return false;
ad70062c
JW		 1165 default:
1166 break;
1167 }
b2a0eb1a
KB		 1168
1169 /* We shouldn't reset unless the controller is on fatal error state
1170 * _or_ if we lost the communication with it.
1171 */
1172 if (!(csts & NVME_CSTS_CFS) && !nssro)
1173 return false;
1174
b2a0eb1a
KB		 1175 return true;
1176}
1177
1178static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1179{
1180 /* Read a config register to help see what died. */
1181 u16 pci_status;
1182 int result;
1183
1184 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1185 &pci_status);
1186 if (result == PCIBIOS_SUCCESSFUL)
1187 dev_warn(dev->ctrl.device,
1188 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1189 csts, pci_status);
1190 else
1191 dev_warn(dev->ctrl.device,
1192 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1193 csts, result);
1194}
1195
31c7c7d2 1196static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1197{
f4800d6d
CH		 1198 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1199 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1200 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1201 struct request *abort_req;
a4aea562 1202 struct nvme_command cmd;
b2a0eb1a
KB		 1203 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1204
651438bb
WX		 1205 /* If PCI error recovery process is happening, we cannot reset or
1206 * the recovery mechanism will surely fail.
1207 */
1208 mb();
1209 if (pci_channel_offline(to_pci_dev(dev->dev)))
1210 return BLK_EH_RESET_TIMER;
1211
b2a0eb1a
KB		 1212 /*
1213 * Reset immediately if the controller is failed
1214 */
1215 if (nvme_should_reset(dev, csts)) {
1216 nvme_warn_reset(dev, csts);
1217 nvme_dev_disable(dev, false);
d86c4d8e 1218 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1219 return BLK_EH_DONE;
b2a0eb1a 1220 }
c30341dc 1221
7776db1c
KB		 1222 /*
1223 * Did we miss an interrupt?
1224 */
fa059b85
KB		 1225 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1226 nvme_poll(req->mq_hctx);
1227 else
1228 nvme_poll_irqdisable(nvmeq);
1229
bf392a5d 1230 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1231 dev_warn(dev->ctrl.device,
1232 "I/O %d QID %d timeout, completion polled\n",
1233 req->tag, nvmeq->qid);
db8c48e4 1234 return BLK_EH_DONE;
7776db1c
KB		 1235 }
1236
31c7c7d2 1237 /*
fd634f41
CH		 1238 * Shutdown immediately if controller times out while starting. The
1239 * reset work will see the pci device disabled when it gets the forced
1240 * cancellation error. All outstanding requests are completed on
db8c48e4 1241 * shutdown, so we return BLK_EH_DONE.
fd634f41 1242 */
4244140d
KB		 1243 switch (dev->ctrl.state) {
1244 case NVME_CTRL_CONNECTING:
2036f726
KB		 1245 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1246 /* fall through */
1247 case NVME_CTRL_DELETING:
b9cac43c 1248 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1249 "I/O %d QID %d timeout, disable controller\n",
1250 req->tag, nvmeq->qid);
2036f726 1251 nvme_dev_disable(dev, true);
27fa9bc5 1252 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1253 return BLK_EH_DONE;
39a9dd81
KB		 1254 case NVME_CTRL_RESETTING:
1255 return BLK_EH_RESET_TIMER;
4244140d
KB		 1256 default:
1257 break;
c30341dc
KB		 1258 }
1259
fd634f41 1260 /*
ee0d96d3
BW		 1261 * Shutdown the controller immediately and schedule a reset if the
1262 * command was already aborted once before and still hasn't been
1263 * returned to the driver, or if this is the admin queue.
31c7c7d2 1264 */
f4800d6d 1265 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1266 dev_warn(dev->ctrl.device,
e1569a16
KB		 1267 "I/O %d QID %d timeout, reset controller\n",
1268 req->tag, nvmeq->qid);
a5cdb68c 1269 nvme_dev_disable(dev, false);
d86c4d8e 1270 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1271
27fa9bc5 1272 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1273 return BLK_EH_DONE;
c30341dc 1274 }
c30341dc 1275
e7a2a87d 1276 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1277 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1278 return BLK_EH_RESET_TIMER;
6bf25d16 1279 }
7bf7d778 1280 iod->aborted = 1;
a4aea562 1281
c30341dc
KB		 1282 memset(&cmd, 0, sizeof(cmd));
1283 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1284 cmd.abort.cid = req->tag;
c30341dc 1285 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1286
1b3c47c1
SG		 1287 dev_warn(nvmeq->dev->ctrl.device,
1288 "I/O %d QID %d timeout, aborting\n",
1289 req->tag, nvmeq->qid);
e7a2a87d
CH		 1290
1291 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1292 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1293 if (IS_ERR(abort_req)) {
1294 atomic_inc(&dev->ctrl.abort_limit);
1295 return BLK_EH_RESET_TIMER;
1296 }
1297
1298 abort_req->timeout = ADMIN_TIMEOUT;
1299 abort_req->end_io_data = NULL;
1300 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1301
31c7c7d2
CH		 1302 /*
1303 * The aborted req will be completed on receiving the abort req.
1304 * We enable the timer again. If hit twice, it'll cause a device reset,
1305 * as the device then is in a faulty state.
1306 */
1307 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1308}
1309
a4aea562
MB		 1310static void nvme_free_queue(struct nvme_queue *nvmeq)
1311{
8a1d09a6 1312 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1313 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1314 if (!nvmeq->sq_cmds)
1315 return;
0f238ff5 1316
63223078 1317 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1318 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1319 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1320 } else {
8a1d09a6 1321 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1322 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1323 }
9e866774
MW		 1324}
1325
a1a5ef99 1326static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1327{
1328 int i;
1329
d858e5f0 1330 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1331 dev->ctrl.queue_count--;
147b27e4 1332 nvme_free_queue(&dev->queues[i]);
121c7ad4 1333 }
22404274
KB		 1334}
1335
4d115420
KB		 1336/**
1337 * nvme_suspend_queue - put queue into suspended state
40581d1a 1338 * @nvmeq: queue to suspend
4d115420
KB		 1339 */
1340static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1341{
4e224106 1342 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1343 return 1;
a09115b2 1344
4e224106 1345 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1346 mb();
a09115b2 1347
4e224106 1348 nvmeq->dev->online_queues--;
1c63dc66 1349 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1350 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1351 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1352 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1353 return 0;
1354}
b60503ba 1355
8fae268b
KB		 1356static void nvme_suspend_io_queues(struct nvme_dev *dev)
1357{
1358 int i;
1359
1360 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1361 nvme_suspend_queue(&dev->queues[i]);
1362}
1363
a5cdb68c 1364static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1365{
147b27e4 1366 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1367
a5cdb68c
KB		 1368 if (shutdown)
1369 nvme_shutdown_ctrl(&dev->ctrl);
1370 else
b5b05048 1371 nvme_disable_ctrl(&dev->ctrl);
07836e65 1372
bf392a5d 1373 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1374}
1375
fa46c6fb
KB		 1376/*
1377 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1378 * that can check this device's completion queues have synced, except
1379 * nvme_poll(). This is the last chance for the driver to see a natural
1380 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1381 */
1382static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1383{
fa46c6fb
KB		 1384 int i;
1385
9210c075
DZ		 1386 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1387 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1388 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1389 spin_unlock(&dev->queues[i].cq_poll_lock);
1390 }
fa46c6fb
KB		 1391}
1392
8ffaadf7
JD		 1393static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1394 int entry_size)
1395{
1396 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1397 unsigned q_size_aligned = roundup(q_depth * entry_size,
1398 dev->ctrl.page_size);
8ffaadf7
JD		 1399
1400 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1401 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1402 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1403 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1404
1405 /*
1406 * Ensure the reduced q_depth is above some threshold where it
1407 * would be better to map queues in system memory with the
1408 * original depth
1409 */
1410 if (q_depth < 64)
1411 return -ENOMEM;
1412 }
1413
1414 return q_depth;
1415}
1416
1417static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1418 int qid)
8ffaadf7 1419{
0f238ff5
LG		 1420 struct pci_dev *pdev = to_pci_dev(dev->dev);
1421
1422 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1423 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1424 if (nvmeq->sq_cmds) {
1425 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1426 nvmeq->sq_cmds);
1427 if (nvmeq->sq_dma_addr) {
1428 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1429 return 0;
1430 }
1431
8a1d09a6 1432 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1433 }
0f238ff5 1434 }
8ffaadf7 1435
8a1d09a6 1436 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1437 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1438 if (!nvmeq->sq_cmds)
1439 return -ENOMEM;
8ffaadf7
JD		 1440 return 0;
1441}
1442
a6ff7262 1443static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1444{
147b27e4 1445 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1446
62314e40
KB		 1447 if (dev->ctrl.queue_count > qid)
1448 return 0;
b60503ba 1449
c1e0cc7e 1450 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1451 nvmeq->q_depth = depth;
1452 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1453 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1454 if (!nvmeq->cqes)
1455 goto free_nvmeq;
b60503ba 1456
8a1d09a6 1457 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1458 goto free_cqdma;
1459
091b6092 1460 nvmeq->dev = dev;
1ab0cd69 1461 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1462 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1463 nvmeq->cq_head = 0;
82123460 1464 nvmeq->cq_phase = 1;
b80d5ccc 1465 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1466 nvmeq->qid = qid;
d858e5f0 1467 dev->ctrl.queue_count++;
36a7e993 1468
147b27e4 1469 return 0;
b60503ba
MW		 1470
1471 free_cqdma:
8a1d09a6
BH		 1472 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1473 nvmeq->cq_dma_addr);
b60503ba 1474 free_nvmeq:
147b27e4 1475 return -ENOMEM;
b60503ba
MW		 1476}
1477
dca51e78 1478static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1479{
0ff199cb
CH		 1480 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1481 int nr = nvmeq->dev->ctrl.instance;
1482
1483 if (use_threaded_interrupts) {
1484 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1485 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1486 } else {
1487 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1488 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1489 }
3001082c
MW		 1490}
1491
22404274 1492static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1493{
22404274 1494 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1495
22404274
KB		 1496 nvmeq->sq_tail = 0;
1497 nvmeq->cq_head = 0;
1498 nvmeq->cq_phase = 1;
b80d5ccc 1499 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1500 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1501 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1502 dev->online_queues++;
3a7afd8e 1503 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1504}
1505
4b04cc6a 1506static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1507{
1508 struct nvme_dev *dev = nvmeq->dev;
1509 int result;
7c349dde 1510 u16 vector = 0;
3f85d50b 1511
d1ed6aa1
CH		 1512 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1513
22b55601
KB		 1514 /*
1515 * A queue's vector matches the queue identifier unless the controller
1516 * has only one vector available.
1517 */
4b04cc6a
JA		 1518 if (!polled)
1519 vector = dev->num_vecs == 1 ? 0 : qid;
1520 else
7c349dde 1521 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1522
a8e3e0bb 1523 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1524 if (result)
1525 return result;
b60503ba
MW		 1526
1527 result = adapter_alloc_sq(dev, qid, nvmeq);
1528 if (result < 0)
ded45505 1529 return result;
c80b36cd 1530 if (result)
b60503ba
MW		 1531 goto release_cq;
1532
a8e3e0bb 1533 nvmeq->cq_vector = vector;
161b8be2 1534 nvme_init_queue(nvmeq, qid);
4b04cc6a 1535
7c349dde 1536 if (!polled) {
4b04cc6a
JA		 1537 result = queue_request_irq(nvmeq);
1538 if (result < 0)
1539 goto release_sq;
1540 }
b60503ba 1541
4e224106 1542 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1543 return result;
b60503ba 1544
a8e3e0bb 1545release_sq:
f25a2dfc 1546 dev->online_queues--;
b60503ba 1547 adapter_delete_sq(dev, qid);
a8e3e0bb 1548release_cq:
b60503ba 1549 adapter_delete_cq(dev, qid);
22404274 1550 return result;
b60503ba
MW		 1551}
1552
f363b089 1553static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1554 .queue_rq = nvme_queue_rq,
77f02a7a 1555 .complete = nvme_pci_complete_rq,
a4aea562 1556 .init_hctx = nvme_admin_init_hctx,
0350815a 1557 .init_request = nvme_init_request,
a4aea562
MB		 1558 .timeout = nvme_timeout,
1559};
1560
f363b089 1561static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1562 .queue_rq = nvme_queue_rq,
1563 .complete = nvme_pci_complete_rq,
1564 .commit_rqs = nvme_commit_rqs,
1565 .init_hctx = nvme_init_hctx,
1566 .init_request = nvme_init_request,
1567 .map_queues = nvme_pci_map_queues,
1568 .timeout = nvme_timeout,
1569 .poll = nvme_poll,
dabcefab
JA		 1570};
1571
ea191d2f
KB		 1572static void nvme_dev_remove_admin(struct nvme_dev *dev)
1573{
1c63dc66 1574 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1575 /*
1576 * If the controller was reset during removal, it's possible
1577 * user requests may be waiting on a stopped queue. Start the
1578 * queue to flush these to completion.
1579 */
c81545f9 1580 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1581 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1582 blk_mq_free_tag_set(&dev->admin_tagset);
1583 }
1584}
1585
a4aea562
MB		 1586static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1587{
1c63dc66 1588 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1589 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1590 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1591
38dabe21 1592 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1593 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
d4ec47f1 1594 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1595 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1596 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1597 dev->admin_tagset.driver_data = dev;
1598
1599 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1600 return -ENOMEM;
34b6c231 1601 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1602
1c63dc66
CH		 1603 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1604 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1605 blk_mq_free_tag_set(&dev->admin_tagset);
1606 return -ENOMEM;
1607 }
1c63dc66 1608 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1609 nvme_dev_remove_admin(dev);
1c63dc66 1610 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1611 return -ENODEV;
1612 }
0fb59cbc 1613 } else
c81545f9 1614 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1615
1616 return 0;
1617}
1618
97f6ef64
XY		 1619static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1620{
1621 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1622}
1623
1624static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1625{
1626 struct pci_dev *pdev = to_pci_dev(dev->dev);
1627
1628 if (size <= dev->bar_mapped_size)
1629 return 0;
1630 if (size > pci_resource_len(pdev, 0))
1631 return -ENOMEM;
1632 if (dev->bar)
1633 iounmap(dev->bar);
1634 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1635 if (!dev->bar) {
1636 dev->bar_mapped_size = 0;
1637 return -ENOMEM;
1638 }
1639 dev->bar_mapped_size = size;
1640 dev->dbs = dev->bar + NVME_REG_DBS;
1641
1642 return 0;
1643}
1644
01ad0990 1645static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1646{
ba47e386 1647 int result;
b60503ba
MW		 1648 u32 aqa;
1649 struct nvme_queue *nvmeq;
1650
97f6ef64
XY		 1651 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1652 if (result < 0)
1653 return result;
1654
8ef2074d 1655 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1656 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1657
7a67cbea
CH		 1658 if (dev->subsystem &&
1659 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1660 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1661
b5b05048 1662 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1663 if (result < 0)
1664 return result;
b60503ba 1665
a6ff7262 1666 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1667 if (result)
1668 return result;
b60503ba 1669
635333e4
MG		 1670 dev->ctrl.numa_node = dev_to_node(dev->dev);
1671
147b27e4 1672 nvmeq = &dev->queues[0];
b60503ba
MW		 1673 aqa = nvmeq->q_depth - 1;
1674 aqa |= aqa << 16;
1675
7a67cbea
CH		 1676 writel(aqa, dev->bar + NVME_REG_AQA);
1677 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1678 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1679
c0f2f45b 1680 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1681 if (result)
d4875622 1682 return result;
a4aea562 1683
2b25d981 1684 nvmeq->cq_vector = 0;
161b8be2 1685 nvme_init_queue(nvmeq, 0);
dca51e78 1686 result = queue_request_irq(nvmeq);
758dd7fd 1687 if (result) {
7c349dde 1688 dev->online_queues--;
d4875622 1689 return result;
758dd7fd 1690 }
025c557a 1691
4e224106 1692 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1693 return result;
1694}
1695
749941f2 1696static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1697{
4b04cc6a 1698 unsigned i, max, rw_queues;
749941f2 1699 int ret = 0;
42f61420 1700
d858e5f0 1701 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1702 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1703 ret = -ENOMEM;
42f61420 1704 break;
749941f2
CH		 1705 }
1706 }
42f61420 1707
d858e5f0 1708 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1709 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1710 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1711 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1712 } else {
1713 rw_queues = max;
1714 }
1715
949928c1 1716 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1717 bool polled = i > rw_queues;
1718
1719 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1720 if (ret)
42f61420 1721 break;
27e8166c 1722 }
749941f2
CH		 1723
1724 /*
1725 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1726 * than the desired amount of queues, and even a controller without
1727 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1728 * be useful to upgrade a buggy firmware for example.
1729 */
1730 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1731}
1732
202021c1
SB		 1733static ssize_t nvme_cmb_show(struct device *dev,
1734 struct device_attribute *attr,
1735 char *buf)
1736{
1737 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1738
c965809c 1739 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1740 ndev->cmbloc, ndev->cmbsz);
1741}
1742static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1743
88de4598 1744static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1745{
88de4598
CH		 1746 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1747
1748 return 1ULL << (12 + 4 * szu);
1749}
1750
1751static u32 nvme_cmb_size(struct nvme_dev *dev)
1752{
1753 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1754}
1755
f65efd6d 1756static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1757{
88de4598 1758 u64 size, offset;
8ffaadf7
JD		 1759 resource_size_t bar_size;
1760 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1761 int bar;
8ffaadf7 1762
9fe5c59f
KB		 1763 if (dev->cmb_size)
1764 return;
1765
7a67cbea 1766 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1767 if (!dev->cmbsz)
1768 return;
202021c1 1769 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1770
88de4598
CH		 1771 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1772 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1773 bar = NVME_CMB_BIR(dev->cmbloc);
1774 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1775
1776 if (offset > bar_size)
f65efd6d 1777 return;
8ffaadf7
JD		 1778
1779 /*
1780 * Controllers may support a CMB size larger than their BAR,
1781 * for example, due to being behind a bridge. Reduce the CMB to
1782 * the reported size of the BAR
1783 */
1784 if (size > bar_size - offset)
1785 size = bar_size - offset;
1786
0f238ff5
LG		 1787 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1788 dev_warn(dev->ctrl.device,
1789 "failed to register the CMB\n");
f65efd6d 1790 return;
0f238ff5
LG		 1791 }
1792
8ffaadf7 1793 dev->cmb_size = size;
0f238ff5
LG		 1794 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1795
1796 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1797 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1798 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1799
1800 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1801 &dev_attr_cmb.attr, NULL))
1802 dev_warn(dev->ctrl.device,
1803 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1804}
1805
1806static inline void nvme_release_cmb(struct nvme_dev *dev)
1807{
0f238ff5 1808 if (dev->cmb_size) {
1c78f773
MG		 1809 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1810 &dev_attr_cmb.attr, NULL);
0f238ff5 1811 dev->cmb_size = 0;
8ffaadf7
JD		 1812 }
1813}
1814
87ad72a5
CH		 1815static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1816{
4033f35d 1817 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1818 struct nvme_command c;
87ad72a5
CH		 1819 int ret;
1820
87ad72a5
CH		 1821 memset(&c, 0, sizeof(c));
1822 c.features.opcode = nvme_admin_set_features;
1823 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1824 c.features.dword11 = cpu_to_le32(bits);
1825 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1826 ilog2(dev->ctrl.page_size));
1827 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1828 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1829 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1830
1831 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1832 if (ret) {
1833 dev_warn(dev->ctrl.device,
1834 "failed to set host mem (err %d, flags %#x).\n",
1835 ret, bits);
1836 }
87ad72a5
CH		 1837 return ret;
1838}
1839
1840static void nvme_free_host_mem(struct nvme_dev *dev)
1841{
1842 int i;
1843
1844 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1845 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1846 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1847
cc667f6d
LD		 1848 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1849 le64_to_cpu(desc->addr),
1850 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1851 }
1852
1853 kfree(dev->host_mem_desc_bufs);
1854 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1855 dma_free_coherent(dev->dev,
1856 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1857 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1858 dev->host_mem_descs = NULL;
7e5dd57e 1859 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1860}
1861
92dc6895
CH		 1862static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1863 u32 chunk_size)
9d713c2b 1864{
87ad72a5 1865 struct nvme_host_mem_buf_desc *descs;
92dc6895 1866 u32 max_entries, len;
4033f35d 1867 dma_addr_t descs_dma;
2ee0e4ed 1868 int i = 0;
87ad72a5 1869 void **bufs;
6fbcde66 1870 u64 size, tmp;
87ad72a5 1871
87ad72a5
CH		 1872 tmp = (preferred + chunk_size - 1);
1873 do_div(tmp, chunk_size);
1874 max_entries = tmp;
044a9df1
CH		 1875
1876 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1877 max_entries = dev->ctrl.hmmaxd;
1878
750afb08
LC		 1879 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1880 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1881 if (!descs)
1882 goto out;
1883
1884 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1885 if (!bufs)
1886 goto out_free_descs;
1887
244a8fe4 1888 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1889 dma_addr_t dma_addr;
1890
50cdb7c6 1891 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1892 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1893 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1894 if (!bufs[i])
1895 break;
1896
1897 descs[i].addr = cpu_to_le64(dma_addr);
1898 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1899 i++;
1900 }
1901
92dc6895 1902 if (!size)
87ad72a5 1903 goto out_free_bufs;
87ad72a5 1904
87ad72a5
CH		 1905 dev->nr_host_mem_descs = i;
1906 dev->host_mem_size = size;
1907 dev->host_mem_descs = descs;
4033f35d 1908 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1909 dev->host_mem_desc_bufs = bufs;
1910 return 0;
1911
1912out_free_bufs:
1913 while (--i >= 0) {
1914 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1915
cc667f6d
LD		 1916 dma_free_attrs(dev->dev, size, bufs[i],
1917 le64_to_cpu(descs[i].addr),
1918 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1919 }
1920
1921 kfree(bufs);
1922out_free_descs:
4033f35d
CH		 1923 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1924 descs_dma);
87ad72a5 1925out:
87ad72a5
CH		 1926 dev->host_mem_descs = NULL;
1927 return -ENOMEM;
1928}
1929
92dc6895
CH		 1930static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1931{
9dc54a0d
CK		 1932 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1933 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1934 u64 chunk_size;
92dc6895
CH		 1935
1936 /* start big and work our way down */
9dc54a0d 1937 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 1938 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1939 if (!min || dev->host_mem_size >= min)
1940 return 0;
1941 nvme_free_host_mem(dev);
1942 }
1943 }
1944
1945 return -ENOMEM;
1946}
1947
9620cfba 1948static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1949{
1950 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1951 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1952 u64 min = (u64)dev->ctrl.hmmin * 4096;
1953 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1954 int ret;
87ad72a5
CH		 1955
1956 preferred = min(preferred, max);
1957 if (min > max) {
1958 dev_warn(dev->ctrl.device,
1959 "min host memory (%lld MiB) above limit (%d MiB).\n",
1960 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1961 nvme_free_host_mem(dev);
9620cfba 1962 return 0;
87ad72a5
CH		 1963 }
1964
1965 /*
1966 * If we already have a buffer allocated check if we can reuse it.
1967 */
1968 if (dev->host_mem_descs) {
1969 if (dev->host_mem_size >= min)
1970 enable_bits |= NVME_HOST_MEM_RETURN;
1971 else
1972 nvme_free_host_mem(dev);
1973 }
1974
1975 if (!dev->host_mem_descs) {
92dc6895
CH		 1976 if (nvme_alloc_host_mem(dev, min, preferred)) {
1977 dev_warn(dev->ctrl.device,
1978 "failed to allocate host memory buffer.\n");
9620cfba 1979 return 0; /* controller must work without HMB */
92dc6895
CH		 1980 }
1981
1982 dev_info(dev->ctrl.device,
1983 "allocated %lld MiB host memory buffer.\n",
1984 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1985 }
1986
9620cfba
CH		 1987 ret = nvme_set_host_mem(dev, enable_bits);
1988 if (ret)
87ad72a5 1989 nvme_free_host_mem(dev);
9620cfba 1990 return ret;
9d713c2b
KB		 1991}
1992
612b7286
ML		 1993/*
1994 * nirqs is the number of interrupts available for write and read
1995 * queues. The core already reserved an interrupt for the admin queue.
1996 */
1997static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 1998{
612b7286 1999 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2000 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2001
2002 /*
ee0d96d3 2003 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2004 * the default queue is set to 1. The affinity set size is
2005 * also set to one, but the irq core ignores it for this case.
2006 *
2007 * If only one interrupt is available or 'write_queue' == 0, combine
2008 * write and read queues.
2009 *
2010 * If 'write_queues' > 0, ensure it leaves room for at least one read
2011 * queue.
3b6592f7 2012 */
612b7286
ML		 2013 if (!nrirqs) {
2014 nrirqs = 1;
2015 nr_read_queues = 0;
2a5bcfdd 2016 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2017 nr_read_queues = 0;
2a5bcfdd 2018 } else if (nr_write_queues >= nrirqs) {
612b7286 2019 nr_read_queues = 1;
3b6592f7 2020 } else {
2a5bcfdd 2021 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2022 }
612b7286
ML		 2023
2024 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2025 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2026 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2027 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2028 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2029}
2030
6451fe73 2031static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2032{
2033 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2034 struct irq_affinity affd = {
9cfef55b 2035 .pre_vectors = 1,
612b7286
ML		 2036 .calc_sets = nvme_calc_irq_sets,
2037 .priv = dev,
3b6592f7 2038 };
6451fe73
JA		 2039 unsigned int irq_queues, this_p_queues;
2040
2041 /*
2042 * Poll queues don't need interrupts, but we need at least one IO
2043 * queue left over for non-polled IO.
2044 */
2a5bcfdd 2045 this_p_queues = dev->nr_poll_queues;
6451fe73
JA		 2046 if (this_p_queues >= nr_io_queues) {
2047 this_p_queues = nr_io_queues - 1;
2048 irq_queues = 1;
2049 } else {
7e4c6b9a 2050 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2051 }
2052 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2053
612b7286
ML		 2054 /* Initialize for the single interrupt case */
2055 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2056 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2057
66341331
BH		 2058 /*
2059 * Some Apple controllers require all queues to use the
2060 * first vector.
2061 */
2062 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2063 irq_queues = 1;
2064
612b7286
ML		 2065 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2066 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2067}
2068
8fae268b
KB		 2069static void nvme_disable_io_queues(struct nvme_dev *dev)
2070{
2071 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2072 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2073}
2074
2a5bcfdd
WZ		 2075static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2076{
2077 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2078}
2079
8d85fce7 2080static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2081{
147b27e4 2082 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2083 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2084 unsigned int nr_io_queues;
97f6ef64 2085 unsigned long size;
2a5bcfdd 2086 int result;
b60503ba 2087
2a5bcfdd
WZ		 2088 /*
2089 * Sample the module parameters once at reset time so that we have
2090 * stable values to work with.
2091 */
2092 dev->nr_write_queues = write_queues;
2093 dev->nr_poll_queues = poll_queues;
d38e9f04
BH		 2094
2095 /*
2096 * If tags are shared with admin queue (Apple bug), then
2097 * make sure we only use one IO queue.
2098 */
2099 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2100 nr_io_queues = 1;
2a5bcfdd
WZ		 2101 else
2102 nr_io_queues = min(nvme_max_io_queues(dev),
2103 dev->nr_allocated_queues - 1);
d38e9f04 2104
9a0be7ab
CH		 2105 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2106 if (result < 0)
1b23484b 2107 return result;
9a0be7ab 2108
f5fa90dc 2109 if (nr_io_queues == 0)
a5229050 2110 return 0;
4e224106
CH		 2111
2112 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2113
0f238ff5 2114 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2115 result = nvme_cmb_qdepth(dev, nr_io_queues,
2116 sizeof(struct nvme_command));
2117 if (result > 0)
2118 dev->q_depth = result;
2119 else
0f238ff5 2120 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2121 }
2122
97f6ef64
XY		 2123 do {
2124 size = db_bar_size(dev, nr_io_queues);
2125 result = nvme_remap_bar(dev, size);
2126 if (!result)
2127 break;
2128 if (!--nr_io_queues)
2129 return -ENOMEM;
2130 } while (1);
2131 adminq->q_db = dev->dbs;
f1938f6e 2132
8fae268b 2133 retry:
9d713c2b 2134 /* Deregister the admin queue's interrupt */
0ff199cb 2135 pci_free_irq(pdev, 0, adminq);
9d713c2b 2136
e32efbfc
JA		 2137 /*
2138 * If we enable msix early due to not intx, disable it again before
2139 * setting up the full range we need.
2140 */
dca51e78 2141 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2142
2143 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2144 if (result <= 0)
dca51e78 2145 return -EIO;
3b6592f7 2146
22b55601 2147 dev->num_vecs = result;
4b04cc6a 2148 result = max(result - 1, 1);
e20ba6e1 2149 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2150
063a8096
MW		 2151 /*
2152 * Should investigate if there's a performance win from allocating
2153 * more queues than interrupt vectors; it might allow the submission
2154 * path to scale better, even if the receive path is limited by the
2155 * number of interrupts.
2156 */
dca51e78 2157 result = queue_request_irq(adminq);
7c349dde 2158 if (result)
d4875622 2159 return result;
4e224106 2160 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2161
2162 result = nvme_create_io_queues(dev);
2163 if (result || dev->online_queues < 2)
2164 return result;
2165
2166 if (dev->online_queues - 1 < dev->max_qid) {
2167 nr_io_queues = dev->online_queues - 1;
2168 nvme_disable_io_queues(dev);
2169 nvme_suspend_io_queues(dev);
2170 goto retry;
2171 }
2172 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2173 dev->io_queues[HCTX_TYPE_DEFAULT],
2174 dev->io_queues[HCTX_TYPE_READ],
2175 dev->io_queues[HCTX_TYPE_POLL]);
2176 return 0;
b60503ba
MW		 2177}
2178
2a842aca 2179static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2180{
db3cbfff 2181 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2182
db3cbfff 2183 blk_mq_free_request(req);
d1ed6aa1 2184 complete(&nvmeq->delete_done);
a5768aa8
KB		 2185}
2186
2a842aca 2187static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2188{
db3cbfff 2189 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2190
d1ed6aa1
CH		 2191 if (error)
2192 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2193
2194 nvme_del_queue_end(req, error);
a5768aa8
KB		 2195}
2196
db3cbfff 2197static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2198{
db3cbfff
KB		 2199 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2200 struct request *req;
2201 struct nvme_command cmd;
bda4e0fb 2202
db3cbfff
KB		 2203 memset(&cmd, 0, sizeof(cmd));
2204 cmd.delete_queue.opcode = opcode;
2205 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2206
eb71f435 2207 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2208 if (IS_ERR(req))
2209 return PTR_ERR(req);
bda4e0fb 2210
db3cbfff
KB		 2211 req->timeout = ADMIN_TIMEOUT;
2212 req->end_io_data = nvmeq;
2213
d1ed6aa1 2214 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2215 blk_execute_rq_nowait(q, NULL, req, false,
2216 opcode == nvme_admin_delete_cq ?
2217 nvme_del_cq_end : nvme_del_queue_end);
2218 return 0;
bda4e0fb
KB		 2219}
2220
8fae268b 2221static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2222{
5271edd4 2223 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2224 unsigned long timeout;
a5768aa8 2225
db3cbfff 2226 retry:
5271edd4
CH		 2227 timeout = ADMIN_TIMEOUT;
2228 while (nr_queues > 0) {
2229 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2230 break;
2231 nr_queues--;
2232 sent++;
db3cbfff 2233 }
d1ed6aa1
CH		 2234 while (sent) {
2235 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2236
2237 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2238 timeout);
2239 if (timeout == 0)
2240 return false;
d1ed6aa1 2241
d1ed6aa1 2242 sent--;
5271edd4
CH		 2243 if (nr_queues)
2244 goto retry;
2245 }
2246 return true;
a5768aa8
KB		 2247}
2248
5d02a5c1 2249static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2250{
2b1b7e78
JW		 2251 int ret;
2252
5bae7f73 2253 if (!dev->ctrl.tagset) {
376f7ef8 2254 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2255 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2256 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2257 if (dev->io_queues[HCTX_TYPE_POLL])
2258 dev->tagset.nr_maps++;
ffe7704d 2259 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2260 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2261 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2262 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2263 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2264 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2265 dev->tagset.driver_data = dev;
b60503ba 2266
d38e9f04
BH		 2267 /*
2268 * Some Apple controllers requires tags to be unique
2269 * across admin and IO queue, so reserve the first 32
2270 * tags of the IO queue.
2271 */
2272 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2273 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2274
2b1b7e78
JW		 2275 ret = blk_mq_alloc_tag_set(&dev->tagset);
2276 if (ret) {
2277 dev_warn(dev->ctrl.device,
2278 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2279 return;
2b1b7e78 2280 }
5bae7f73 2281 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2282 } else {
2283 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2284
2285 /* Free previously allocated queues that are no longer usable */
2286 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2287 }
949928c1 2288
e8fd41bb 2289 nvme_dbbuf_set(dev);
b60503ba
MW		 2290}
2291
b00a726a 2292static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2293{
b00a726a 2294 int result = -ENOMEM;
e75ec752 2295 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2296
2297 if (pci_enable_device_mem(pdev))
2298 return result;
2299
0877cb0d 2300 pci_set_master(pdev);
0877cb0d 2301
4fe06923 2302 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2303 goto disable;
0877cb0d 2304
7a67cbea 2305 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2306 result = -ENODEV;
b00a726a 2307 goto disable;
0e53d180 2308 }
e32efbfc
JA		 2309
2310 /*
a5229050
KB		 2311 * Some devices and/or platforms don't advertise or work with INTx
2312 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2313 * adjust this later.
e32efbfc 2314 */
dca51e78
CH		 2315 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2316 if (result < 0)
2317 return result;
e32efbfc 2318
20d0dfe6 2319 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2320
61f3b896 2321 dev->q_depth = min_t(u16, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2322 io_queue_depth);
aa22c8e6 2323 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2324 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2325 dev->dbs = dev->bar + 4096;
1f390c1f 2326
66341331
BH		 2327 /*
2328 * Some Apple controllers require a non-standard SQE size.
2329 * Interestingly they also seem to ignore the CC:IOSQES register
2330 * so we don't bother updating it here.
2331 */
2332 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2333 dev->io_sqes = 7;
2334 else
2335 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2336
2337 /*
2338 * Temporary fix for the Apple controller found in the MacBook8,1 and
2339 * some MacBook7,1 to avoid controller resets and data loss.
2340 */
2341 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2342 dev->q_depth = 2;
9bdcfb10
CH		 2343 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2344 "set queue depth=%u to work around controller resets\n",
1f390c1f 2345 dev->q_depth);
d554b5e1
MP		 2346 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2347 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2348 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2349 dev->q_depth = 64;
2350 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2351 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2352 }
2353
d38e9f04
BH		 2354 /*
2355 * Controllers with the shared tags quirk need the IO queue to be
2356 * big enough so that we get 32 tags for the admin queue
2357 */
2358 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2359 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2360 dev->q_depth = NVME_AQ_DEPTH + 2;
2361 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2362 dev->q_depth);
2363 }
2364
2365
f65efd6d 2366 nvme_map_cmb(dev);
202021c1 2367
a0a3408e
KB		 2368 pci_enable_pcie_error_reporting(pdev);
2369 pci_save_state(pdev);
0877cb0d
KB		 2370 return 0;
2371
2372 disable:
0877cb0d
KB		 2373 pci_disable_device(pdev);
2374 return result;
2375}
2376
2377static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2378{
2379 if (dev->bar)
2380 iounmap(dev->bar);
a1f447b3 2381 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2382}
2383
2384static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2385{
e75ec752
CH		 2386 struct pci_dev *pdev = to_pci_dev(dev->dev);
2387
dca51e78 2388 pci_free_irq_vectors(pdev);
0877cb0d 2389
a0a3408e
KB		 2390 if (pci_is_enabled(pdev)) {
2391 pci_disable_pcie_error_reporting(pdev);
e75ec752 2392 pci_disable_device(pdev);
4d115420 2393 }
4d115420
KB		 2394}
2395
a5cdb68c 2396static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2397{
e43269e6 2398 bool dead = true, freeze = false;
302ad8cc 2399 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2400
77bf25ea 2401 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2402 if (pci_is_enabled(pdev)) {
2403 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2404
ebef7368 2405 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2406 dev->ctrl.state == NVME_CTRL_RESETTING) {
2407 freeze = true;
302ad8cc 2408 nvme_start_freeze(&dev->ctrl);
e43269e6 2409 }
302ad8cc
KB		 2410 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2411 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2412 }
c21377f8 2413
302ad8cc
KB		 2414 /*
2415 * Give the controller a chance to complete all entered requests if
2416 * doing a safe shutdown.
2417 */
e43269e6
KB		 2418 if (!dead && shutdown && freeze)
2419 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2420
2421 nvme_stop_queues(&dev->ctrl);
87ad72a5 2422
64ee0ac0 2423 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2424 nvme_disable_io_queues(dev);
a5cdb68c 2425 nvme_disable_admin_queue(dev, shutdown);
4d115420 2426 }
8fae268b
KB		 2427 nvme_suspend_io_queues(dev);
2428 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2429 nvme_pci_disable(dev);
fa46c6fb 2430 nvme_reap_pending_cqes(dev);
07836e65 2431
e1958e65
ML		 2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2434 blk_mq_tagset_wait_completed_request(&dev->tagset);
2435 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2436
2437 /*
2438 * The driver will not be starting up queues again if shutting down so
2439 * must flush all entered requests to their failed completion to avoid
2440 * deadlocking blk-mq hot-cpu notifier.
2441 */
c8e9e9b7 2442 if (shutdown) {
302ad8cc 2443 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2444 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2445 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2446 }
77bf25ea 2447 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2448}
2449
c1ac9a4b
KB		 2450static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2451{
2452 if (!nvme_wait_reset(&dev->ctrl))
2453 return -EBUSY;
2454 nvme_dev_disable(dev, shutdown);
2455 return 0;
2456}
2457
091b6092
MW		 2458static int nvme_setup_prp_pools(struct nvme_dev *dev)
2459{
e75ec752 2460 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2461 PAGE_SIZE, PAGE_SIZE, 0);
2462 if (!dev->prp_page_pool)
2463 return -ENOMEM;
2464
99802a7a 2465 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2466 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2467 256, 256, 0);
2468 if (!dev->prp_small_pool) {
2469 dma_pool_destroy(dev->prp_page_pool);
2470 return -ENOMEM;
2471 }
091b6092
MW		 2472 return 0;
2473}
2474
2475static void nvme_release_prp_pools(struct nvme_dev *dev)
2476{
2477 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2478 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2479}
2480
770597ec
KB		 2481static void nvme_free_tagset(struct nvme_dev *dev)
2482{
2483 if (dev->tagset.tags)
2484 blk_mq_free_tag_set(&dev->tagset);
2485 dev->ctrl.tagset = NULL;
2486}
2487
1673f1f0 2488static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2489{
1673f1f0 2490 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2491
f9f38e33 2492 nvme_dbbuf_dma_free(dev);
770597ec 2493 nvme_free_tagset(dev);
1c63dc66
CH		 2494 if (dev->ctrl.admin_q)
2495 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2496 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2497 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2498 put_device(dev->dev);
2499 kfree(dev->queues);
5e82e952
KB		 2500 kfree(dev);
2501}
2502
7c1ce408 2503static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2504{
c1ac9a4b
KB		 2505 /*
2506 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2507 * may be holding this pci_dev's device lock.
2508 */
2509 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2510 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2511 nvme_dev_disable(dev, false);
9f9cafc1 2512 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2513 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2514 nvme_put_ctrl(&dev->ctrl);
2515}
2516
fd634f41 2517static void nvme_reset_work(struct work_struct *work)
5e82e952 2518{
d86c4d8e
CH		 2519 struct nvme_dev *dev =
2520 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2521 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2522 int result;
5e82e952 2523
e71afda4
CK		 2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2525 result = -ENODEV;
fd634f41 2526 goto out;
e71afda4 2527 }
5e82e952 2528
fd634f41
CH		 2529 /*
2530 * If we're called to reset a live controller first shut it down before
2531 * moving on.
2532 */
b00a726a 2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2534 nvme_dev_disable(dev, false);
d6135c3a 2535 nvme_sync_queues(&dev->ctrl);
5e82e952 2536
5c959d73 2537 mutex_lock(&dev->shutdown_lock);
b00a726a 2538 result = nvme_pci_enable(dev);
f0b50732 2539 if (result)
4726bcf3 2540 goto out_unlock;
f0b50732 2541
01ad0990 2542 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2543 if (result)
4726bcf3 2544 goto out_unlock;
f0b50732 2545
0fb59cbc
KB		 2546 result = nvme_alloc_admin_tags(dev);
2547 if (result)
4726bcf3 2548 goto out_unlock;
b9afca3e 2549
943e942e
JA		 2550 /*
2551 * Limit the max command size to prevent iod->sg allocations going
2552 * over a single page.
2553 */
7637de31
CH		 2554 dev->ctrl.max_hw_sectors = min_t(u32,
2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2556 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2557
2558 /*
2559 * Don't limit the IOMMU merged segment size.
2560 */
2561 dma_set_max_seg_size(dev->dev, 0xffffffff);
2562
5c959d73
KB		 2563 mutex_unlock(&dev->shutdown_lock);
2564
2565 /*
2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2567 * initializing procedure here.
2568 */
2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2570 dev_warn(dev->ctrl.device,
2571 "failed to mark controller CONNECTING\n");
cee6c269 2572 result = -EBUSY;
5c959d73
KB		 2573 goto out;
2574 }
943e942e 2575
95093350
MG		 2576 /*
2577 * We do not support an SGL for metadata (yet), so we are limited to a
2578 * single integrity segment for the separate metadata pointer.
2579 */
2580 dev->ctrl.max_integrity_segments = 1;
2581
ce4541f4
CH		 2582 result = nvme_init_identify(&dev->ctrl);
2583 if (result)
f58944e2 2584 goto out;
ce4541f4 2585
e286bcfc
SB		 2586 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2587 if (!dev->ctrl.opal_dev)
2588 dev->ctrl.opal_dev =
2589 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2590 else if (was_suspend)
2591 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2592 } else {
2593 free_opal_dev(dev->ctrl.opal_dev);
2594 dev->ctrl.opal_dev = NULL;
4f1244c8 2595 }
a98e58e5 2596
f9f38e33
HK		 2597 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2598 result = nvme_dbbuf_dma_alloc(dev);
2599 if (result)
2600 dev_warn(dev->dev,
2601 "unable to allocate dma for dbbuf\n");
2602 }
2603
9620cfba
CH		 2604 if (dev->ctrl.hmpre) {
2605 result = nvme_setup_host_mem(dev);
2606 if (result < 0)
2607 goto out;
2608 }
87ad72a5 2609
f0b50732 2610 result = nvme_setup_io_queues(dev);
badc34d4 2611 if (result)
f58944e2 2612 goto out;
f0b50732 2613
2659e57b
CH		 2614 /*
2615 * Keep the controller around but remove all namespaces if we don't have
2616 * any working I/O queue.
2617 */
3cf519b5 2618 if (dev->online_queues < 2) {
1b3c47c1 2619 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2620 nvme_kill_queues(&dev->ctrl);
5bae7f73 2621 nvme_remove_namespaces(&dev->ctrl);
770597ec 2622 nvme_free_tagset(dev);
3cf519b5 2623 } else {
25646264 2624 nvme_start_queues(&dev->ctrl);
302ad8cc 2625 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2626 nvme_dev_add(dev);
302ad8cc 2627 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2628 }
2629
2b1b7e78
JW		 2630 /*
2631 * If only admin queue live, keep it to do further investigation or
2632 * recovery.
2633 */
5d02a5c1 2634 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2635 dev_warn(dev->ctrl.device,
5d02a5c1 2636 "failed to mark controller live state\n");
e71afda4 2637 result = -ENODEV;
bb8d261e
CH		 2638 goto out;
2639 }
92911a55 2640
d09f2b45 2641 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2642 return;
f0b50732 2643
4726bcf3
KB		 2644 out_unlock:
2645 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2646 out:
7c1ce408
CK		 2647 if (result)
2648 dev_warn(dev->ctrl.device,
2649 "Removing after probe failure status: %d\n", result);
2650 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2651}
2652
5c8809e6 2653static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2654{
5c8809e6 2655 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2656 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2657
2658 if (pci_get_drvdata(pdev))
921920ab 2659 device_release_driver(&pdev->dev);
1673f1f0 2660 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2661}
2662
1c63dc66 2663static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2664{
1c63dc66 2665 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2666 return 0;
9ca97374
TH		 2667}
2668
5fd4ce1b 2669static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2670{
5fd4ce1b
CH		 2671 writel(val, to_nvme_dev(ctrl)->bar + off);
2672 return 0;
2673}
4cc06521 2674
7fd8930f
CH		 2675static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2676{
3a8ecc93 2677 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2678 return 0;
4cc06521
KB		 2679}
2680
97c12223
KB		 2681static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2682{
2683 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2684
2db24e4a 2685 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2686}
2687
1c63dc66 2688static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2689 .name = "pcie",
e439bb12 2690 .module = THIS_MODULE,
e0596ab2
LG		 2691 .flags = NVME_F_METADATA_SUPPORTED |
2692 NVME_F_PCI_P2PDMA,
1c63dc66 2693 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2694 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2695 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2696 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2697 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2698 .get_address = nvme_pci_get_address,
1c63dc66 2699};
4cc06521 2700
b00a726a
KB		 2701static int nvme_dev_map(struct nvme_dev *dev)
2702{
b00a726a
KB		 2703 struct pci_dev *pdev = to_pci_dev(dev->dev);
2704
a1f447b3 2705 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2706 return -ENODEV;
2707
97f6ef64 2708 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2709 goto release;
2710
9fa196e7 2711 return 0;
b00a726a 2712 release:
9fa196e7
MG		 2713 pci_release_mem_regions(pdev);
2714 return -ENODEV;
b00a726a
KB		 2715}
2716
8427bbc2 2717static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2718{
2719 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2720 /*
2721 * Several Samsung devices seem to drop off the PCIe bus
2722 * randomly when APST is on and uses the deepest sleep state.
2723 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2724 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2725 * 950 PRO 256GB", but it seems to be restricted to two Dell
2726 * laptops.
2727 */
2728 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2729 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2730 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2731 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2732 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2733 /*
2734 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2735 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2736 * within few minutes after bootup on a Coffee Lake board -
2737 * ASUS PRIME Z370-A
8427bbc2
KHF		 2738 */
2739 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2740 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2741 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2742 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2743 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2744 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2745 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2746 /*
2747 * Forcing to use host managed nvme power settings for
2748 * lowest idle power with quick resume latency on
2749 * Samsung and Toshiba SSDs based on suspend behavior
2750 * on Coffee Lake board for LENOVO C640
2751 */
2752 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2753 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2754 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2755 }
2756
2757 return 0;
2758}
2759
18119775
KB		 2760static void nvme_async_probe(void *data, async_cookie_t cookie)
2761{
2762 struct nvme_dev *dev = data;
80f513b5 2763
bd46a906 2764 flush_work(&dev->ctrl.reset_work);
18119775 2765 flush_work(&dev->ctrl.scan_work);
80f513b5 2766 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2767}
2768
8d85fce7 2769static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2770{
a4aea562 2771 int node, result = -ENOMEM;
b60503ba 2772 struct nvme_dev *dev;
ff5350a8 2773 unsigned long quirks = id->driver_data;
943e942e 2774 size_t alloc_size;
b60503ba 2775
a4aea562
MB		 2776 node = dev_to_node(&pdev->dev);
2777 if (node == NUMA_NO_NODE)
2fa84351 2778 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2779
2780 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2781 if (!dev)
2782 return -ENOMEM;
147b27e4 2783
2a5bcfdd
WZ		 2784 dev->nr_write_queues = write_queues;
2785 dev->nr_poll_queues = poll_queues;
2786 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2787 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2788 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2789 if (!dev->queues)
2790 goto free;
2791
e75ec752 2792 dev->dev = get_device(&pdev->dev);
9a6b9458 2793 pci_set_drvdata(pdev, dev);
1c63dc66 2794
b00a726a
KB		 2795 result = nvme_dev_map(dev);
2796 if (result)
b00c9b7a 2797 goto put_pci;
b00a726a 2798
d86c4d8e 2799 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2800 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2801 mutex_init(&dev->shutdown_lock);
b60503ba 2802
091b6092
MW		 2803 result = nvme_setup_prp_pools(dev);
2804 if (result)
b00c9b7a 2805 goto unmap;
4cc06521 2806
8427bbc2 2807 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2808
943e942e
JA		 2809 /*
2810 * Double check that our mempool alloc size will cover the biggest
2811 * command we support.
2812 */
2813 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2814 NVME_MAX_SEGS, true);
2815 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2816
2817 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2818 mempool_kfree,
2819 (void *) alloc_size,
2820 GFP_KERNEL, node);
2821 if (!dev->iod_mempool) {
2822 result = -ENOMEM;
2823 goto release_pools;
2824 }
2825
b6e44b4c
KB		 2826 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2827 quirks);
2828 if (result)
2829 goto release_mempool;
2830
1b3c47c1
SG		 2831 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2832
bd46a906 2833 nvme_reset_ctrl(&dev->ctrl);
18119775 2834 async_schedule(nvme_async_probe, dev);
4caff8fc 2835
b60503ba
MW		 2836 return 0;
2837
b6e44b4c
KB		 2838 release_mempool:
2839 mempool_destroy(dev->iod_mempool);
0877cb0d 2840 release_pools:
091b6092 2841 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2842 unmap:
2843 nvme_dev_unmap(dev);
a96d4f5c 2844 put_pci:
e75ec752 2845 put_device(dev->dev);
b60503ba
MW		 2846 free:
2847 kfree(dev->queues);
b60503ba
MW		 2848 kfree(dev);
2849 return result;
2850}
2851
775755ed 2852static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2853{
a6739479 2854 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2855
2856 /*
2857 * We don't need to check the return value from waiting for the reset
2858 * state as pci_dev device lock is held, making it impossible to race
2859 * with ->remove().
2860 */
2861 nvme_disable_prepare_reset(dev, false);
2862 nvme_sync_queues(&dev->ctrl);
775755ed 2863}
f0d54a54 2864
775755ed
CH		 2865static void nvme_reset_done(struct pci_dev *pdev)
2866{
f263fbb8 2867 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2868
2869 if (!nvme_try_sched_reset(&dev->ctrl))
2870 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2871}
2872
09ece142
KB		 2873static void nvme_shutdown(struct pci_dev *pdev)
2874{
2875 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b 2876 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2877}
2878
f58944e2
KB		 2879/*
2880 * The driver's remove may be called on a device in a partially initialized
2881 * state. This function must not have any dependencies on the device state in
2882 * order to proceed.
2883 */
8d85fce7 2884static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2885{
2886 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2887
bb8d261e 2888 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2889 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2890
6db28eda 2891 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2892 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2893 nvme_dev_disable(dev, true);
cb4bfda6 2894 nvme_dev_remove_admin(dev);
6db28eda 2895 }
0ff9d4e1 2896
d86c4d8e 2897 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2898 nvme_stop_ctrl(&dev->ctrl);
2899 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2900 nvme_dev_disable(dev, true);
9fe5c59f 2901 nvme_release_cmb(dev);
87ad72a5 2902 nvme_free_host_mem(dev);
a4aea562 2903 nvme_dev_remove_admin(dev);
a1a5ef99 2904 nvme_free_queues(dev, 0);
9a6b9458 2905 nvme_release_prp_pools(dev);
b00a726a 2906 nvme_dev_unmap(dev);
726612b6 2907 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2908}
2909
671a6018 2910#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2911static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2912{
2913 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2914}
2915
2916static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2917{
2918 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2919}
2920
2921static int nvme_resume(struct device *dev)
2922{
2923 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2924 struct nvme_ctrl *ctrl = &ndev->ctrl;
2925
4eaefe8c 2926 if (ndev->last_ps == U32_MAX ||
d916b1be 2927 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2928 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 2929 return 0;
2930}
2931
cd638946
KB		 2932static int nvme_suspend(struct device *dev)
2933{
2934 struct pci_dev *pdev = to_pci_dev(dev);
2935 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2936 struct nvme_ctrl *ctrl = &ndev->ctrl;
2937 int ret = -EBUSY;
2938
4eaefe8c
RW		 2939 ndev->last_ps = U32_MAX;
2940
d916b1be
KB		 2941 /*
2942 * The platform does not remove power for a kernel managed suspend so
2943 * use host managed nvme power settings for lowest idle power if
2944 * possible. This should have quicker resume latency than a full device
2945 * shutdown. But if the firmware is involved after the suspend or the
2946 * device does not support any non-default power states, shut down the
2947 * device fully.
4eaefe8c
RW		 2948 *
2949 * If ASPM is not enabled for the device, shut down the device and allow
2950 * the PCI bus layer to put it into D3 in order to take the PCIe link
2951 * down, so as to allow the platform to achieve its minimum low-power
2952 * state (which may not be possible if the link is up).
b97120b1
CH		 2953 *
2954 * If a host memory buffer is enabled, shut down the device as the NVMe
2955 * specification allows the device to access the host memory buffer in
2956 * host DRAM from all power states, but hosts will fail access to DRAM
2957 * during S3.
d916b1be 2958 */
4eaefe8c 2959 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 2960 !pcie_aspm_enabled(pdev) ||
b97120b1 2961 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 2962 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2963 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 2964
2965 nvme_start_freeze(ctrl);
2966 nvme_wait_freeze(ctrl);
2967 nvme_sync_queues(ctrl);
2968
5d02a5c1 2969 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 2970 goto unfreeze;
2971
d916b1be
KB		 2972 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2973 if (ret < 0)
2974 goto unfreeze;
2975
7cbb5c6f
ML		 2976 /*
2977 * A saved state prevents pci pm from generically controlling the
2978 * device's power. If we're using protocol specific settings, we don't
2979 * want pci interfering.
2980 */
2981 pci_save_state(pdev);
2982
d916b1be
KB		 2983 ret = nvme_set_power_state(ctrl, ctrl->npss);
2984 if (ret < 0)
2985 goto unfreeze;
2986
2987 if (ret) {
7cbb5c6f
ML		 2988 /* discard the saved state */
2989 pci_load_saved_state(pdev, NULL);
2990
d916b1be
KB		 2991 /*
2992 * Clearing npss forces a controller reset on resume. The
05d3046f 2993 * correct value will be rediscovered then.
d916b1be 2994 */
c1ac9a4b 2995 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 2996 ctrl->npss = 0;
d916b1be 2997 }
d916b1be
KB		 2998unfreeze:
2999 nvme_unfreeze(ctrl);
3000 return ret;
3001}
3002
3003static int nvme_simple_suspend(struct device *dev)
3004{
3005 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
c1ac9a4b 3006 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3007}
3008
d916b1be 3009static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3010{
3011 struct pci_dev *pdev = to_pci_dev(dev);
3012 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3013
c1ac9a4b 3014 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3015}
3016
21774222 3017static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3018 .suspend = nvme_suspend,
3019 .resume = nvme_resume,
3020 .freeze = nvme_simple_suspend,
3021 .thaw = nvme_simple_resume,
3022 .poweroff = nvme_simple_suspend,
3023 .restore = nvme_simple_resume,
3024};
3025#endif /* CONFIG_PM_SLEEP */
b60503ba 3026
a0a3408e
KB		 3027static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3028 pci_channel_state_t state)
3029{
3030 struct nvme_dev *dev = pci_get_drvdata(pdev);
3031
3032 /*
3033 * A frozen channel requires a reset. When detected, this method will
3034 * shutdown the controller to quiesce. The controller will be restarted
3035 * after the slot reset through driver's slot_reset callback.
3036 */
a0a3408e
KB		 3037 switch (state) {
3038 case pci_channel_io_normal:
3039 return PCI_ERS_RESULT_CAN_RECOVER;
3040 case pci_channel_io_frozen:
d011fb31
KB		 3041 dev_warn(dev->ctrl.device,
3042 "frozen state error detected, reset controller\n");
a5cdb68c 3043 nvme_dev_disable(dev, false);
a0a3408e
KB		 3044 return PCI_ERS_RESULT_NEED_RESET;
3045 case pci_channel_io_perm_failure:
d011fb31
KB		 3046 dev_warn(dev->ctrl.device,
3047 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3048 return PCI_ERS_RESULT_DISCONNECT;
3049 }
3050 return PCI_ERS_RESULT_NEED_RESET;
3051}
3052
3053static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3054{
3055 struct nvme_dev *dev = pci_get_drvdata(pdev);
3056
1b3c47c1 3057 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3058 pci_restore_state(pdev);
d86c4d8e 3059 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3060 return PCI_ERS_RESULT_RECOVERED;
3061}
3062
3063static void nvme_error_resume(struct pci_dev *pdev)
3064{
72cd4cc2
KB		 3065 struct nvme_dev *dev = pci_get_drvdata(pdev);
3066
3067 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3068}
3069
1d352035 3070static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3071 .error_detected = nvme_error_detected,
b60503ba
MW		 3072 .slot_reset = nvme_slot_reset,
3073 .resume = nvme_error_resume,
775755ed
CH		 3074 .reset_prepare = nvme_reset_prepare,
3075 .reset_done = nvme_reset_done,
b60503ba
MW		 3076};
3077
6eb0d698 3078static const struct pci_device_id nvme_id_table[] = {
972b13e2 3079 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3080 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3081 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3082 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3083 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3084 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3085 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3086 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3087 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3088 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3089 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3090 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3091 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3092 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2
AM		 3093 NVME_QUIRK_MEDIUM_PRIO_SQ |
3094 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
6299358d
JD		 3095 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3096 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3097 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3098 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3099 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3100 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3101 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3102 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3103 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3104 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3105 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3106 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3107 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3108 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3109 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3110 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3111 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3112 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3113 .driver_data = NVME_QUIRK_LIGHTNVM, },
3114 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3115 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3116 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3117 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3118 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3119 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3120 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3121 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3122 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3123 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
98f7b86a
AS		 3124 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3125 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3127 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3128 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3129 NVME_QUIRK_128_BYTES_SQES |
3130 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3131 { 0, }
3132};
3133MODULE_DEVICE_TABLE(pci, nvme_id_table);
3134
3135static struct pci_driver nvme_driver = {
3136 .name = "nvme",
3137 .id_table = nvme_id_table,
3138 .probe = nvme_probe,
8d85fce7 3139 .remove = nvme_remove,
09ece142 3140 .shutdown = nvme_shutdown,
d916b1be 3141#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3142 .driver = {
3143 .pm = &nvme_dev_pm_ops,
3144 },
d916b1be 3145#endif
74d986ab 3146 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3147 .err_handler = &nvme_err_handler,
3148};
3149
3150static int __init nvme_init(void)
3151{
81101540
CH		 3152 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3153 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3154 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3155 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3156
9a6327d2 3157 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3158}
3159
3160static void __exit nvme_exit(void)
3161{
3162 pci_unregister_driver(&nvme_driver);
03e0f3a6 3163 flush_workqueue(nvme_wq);
b60503ba
MW		 3164}
3165
3166MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3167MODULE_LICENSE("GPL");
c78b4713 3168MODULE_VERSION("1.0");
b60503ba
MW		 3169module_init(nvme_init);
3170module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)